Revert "drm/amd/display: Add 3DLUT DMA broadcast support"

+1 -1

drivers/gpu/drm/amd/display/dc/core/dc.c

··· 4671 4671 srf_updates[i].cm->flags.bits.lut3d_enable && 4672 4672 srf_updates[i].cm->flags.bits.lut3d_dma_enable && 4673 4673 dc->hwss.trigger_3dlut_dma_load) 4674 - dc->hwss.trigger_3dlut_dma_load(pipe_ctx); 4674 + dc->hwss.trigger_3dlut_dma_load(dc, pipe_ctx); 4675 4675 4676 4676 /*program triple buffer after lock based on flip type*/ 4677 4677 if (dc->hwss.program_triplebuffer != NULL && dc->debug.enable_tri_buf) {

+44 -63

drivers/gpu/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

··· 374 374 } 375 375 } 376 376 377 - void dcn401_trigger_3dlut_dma_load(struct pipe_ctx *pipe_ctx) 377 + void dcn401_trigger_3dlut_dma_load(struct dc *dc, struct pipe_ctx *pipe_ctx) 378 378 { 379 - const struct pipe_ctx *primary_dpp_pipe_ctx = resource_get_primary_dpp_pipe(pipe_ctx); 380 - struct hubp *primary_hubp = primary_dpp_pipe_ctx ? 381 - primary_dpp_pipe_ctx->plane_res.hubp : NULL; 379 + (void)dc; 380 + struct hubp *hubp = pipe_ctx->plane_res.hubp; 382 381 383 - if (primary_hubp && primary_hubp->funcs->hubp_enable_3dlut_fl) { 384 - primary_hubp->funcs->hubp_enable_3dlut_fl(primary_hubp, true); 382 + if (hubp->funcs->hubp_enable_3dlut_fl) { 383 + hubp->funcs->hubp_enable_3dlut_fl(hubp, true); 385 384 } 386 385 } 387 386 ··· 388 389 const struct dc_plane_state *plane_state) 389 390 { 390 391 struct dc *dc = pipe_ctx->plane_res.hubp->ctx->dc; 391 - const struct pipe_ctx *primary_dpp_pipe_ctx = resource_get_primary_dpp_pipe(pipe_ctx); 392 392 struct dpp *dpp_base = pipe_ctx->plane_res.dpp; 393 393 struct hubp *hubp = pipe_ctx->plane_res.hubp; 394 - struct hubp *primary_hubp = primary_dpp_pipe_ctx ? 395 - primary_dpp_pipe_ctx->plane_res.hubp : NULL; 396 394 const struct dc_plane_cm *cm = &plane_state->cm; 397 395 int mpcc_id = hubp->inst; 398 396 struct mpc *mpc = dc->res_pool->mpc; ··· 487 491 mpc->funcs->program_lut_read_write_control(mpc, MCM_LUT_3DLUT, lut_bank_a, 12, mpcc_id); 488 492 489 493 if (mpc->funcs->update_3dlut_fast_load_select) 490 - mpc->funcs->update_3dlut_fast_load_select(mpc, mpcc_id, primary_hubp->inst); 494 + mpc->funcs->update_3dlut_fast_load_select(mpc, mpcc_id, hubp->inst); 491 495 492 496 /* HUBP */ 493 - if (primary_hubp->inst == hubp->inst) { 494 - /* only program if this is the primary dpp pipe for the given plane */ 495 - if (hubp->funcs->hubp_program_3dlut_fl_config) 496 - hubp->funcs->hubp_program_3dlut_fl_config(hubp, &cm->lut3d_dma); 497 + if (hubp->funcs->hubp_program_3dlut_fl_config) 498 + hubp->funcs->hubp_program_3dlut_fl_config(hubp, &cm->lut3d_dma); 497 499 498 - if (hubp->funcs->hubp_program_3dlut_fl_crossbar) 499 - hubp->funcs->hubp_program_3dlut_fl_crossbar(hubp, cm->lut3d_dma.format); 500 + if (hubp->funcs->hubp_program_3dlut_fl_crossbar) 501 + hubp->funcs->hubp_program_3dlut_fl_crossbar(hubp, cm->lut3d_dma.format); 500 502 501 - if (hubp->funcs->hubp_program_3dlut_fl_addr) 502 - hubp->funcs->hubp_program_3dlut_fl_addr(hubp, &cm->lut3d_dma.addr); 503 + if (hubp->funcs->hubp_program_3dlut_fl_addr) 504 + hubp->funcs->hubp_program_3dlut_fl_addr(hubp, &cm->lut3d_dma.addr); 503 505 504 - if (hubp->funcs->hubp_enable_3dlut_fl) { 505 - hubp->funcs->hubp_enable_3dlut_fl(hubp, true); 506 - } else { 507 - /* GPU memory only supports fast load path */ 508 - BREAK_TO_DEBUGGER(); 509 - lut_enable = false; 510 - result = false; 511 - } 506 + if (hubp->funcs->hubp_enable_3dlut_fl) { 507 + hubp->funcs->hubp_enable_3dlut_fl(hubp, true); 512 508 } else { 513 - /* re-trigger priamry HUBP to load 3DLUT */ 514 - if (primary_hubp->funcs->hubp_enable_3dlut_fl) { 515 - primary_hubp->funcs->hubp_enable_3dlut_fl(primary_hubp, true); 516 - } 517 - 518 - /* clear FL setup on this pipe's HUBP */ 519 - memset(&lut3d_dma, 0, sizeof(lut3d_dma)); 520 - if (hubp->funcs->hubp_program_3dlut_fl_config) 521 - hubp->funcs->hubp_program_3dlut_fl_config(hubp, &lut3d_dma); 522 - 523 - if (hubp->funcs->hubp_enable_3dlut_fl) 524 - hubp->funcs->hubp_enable_3dlut_fl(hubp, false); 509 + /* GPU memory only supports fast load path */ 510 + BREAK_TO_DEBUGGER(); 511 + lut_enable = false; 512 + result = false; 525 513 } 526 514 } else { 527 515 /* Legacy (Host) Load Mode */ ··· 1815 1835 * This is meant to work around a known HW issue where VREADY will cancel the pending 3DLUT_ENABLE signal regardless 1816 1836 * of whether OTG lock is currently being held or not. 1817 1837 */ 1818 - const struct pipe_ctx *otg_master_pipe_ctx = resource_get_otg_master(pipe_ctx); 1819 - struct timing_generator *tg = otg_master_pipe_ctx ? 1820 - otg_master_pipe_ctx->stream_res.tg : NULL; 1821 - const struct pipe_ctx *primary_dpp_pipe_ctx = resource_is_pipe_type(pipe_ctx, DPP_PIPE) ? 1822 - resource_get_primary_dpp_pipe(pipe_ctx) : pipe_ctx; 1823 - struct hubp *primary_hubp = primary_dpp_pipe_ctx ? 1824 - primary_dpp_pipe_ctx->plane_res.hubp : NULL; 1838 + struct pipe_ctx *wa_pipes[MAX_PIPES] = { NULL }; 1839 + struct pipe_ctx *odm_pipe, *mpc_pipe; 1840 + int i, wa_pipe_ct = 0; 1825 1841 1826 - if (!otg_master_pipe_ctx && !tg) { 1827 - return; 1842 + for (odm_pipe = pipe_ctx; odm_pipe != NULL; odm_pipe = odm_pipe->next_odm_pipe) { 1843 + for (mpc_pipe = odm_pipe; mpc_pipe != NULL; mpc_pipe = mpc_pipe->bottom_pipe) { 1844 + if (mpc_pipe->plane_state && 1845 + mpc_pipe->plane_state->cm.flags.bits.lut3d_enable && 1846 + mpc_pipe->plane_state->cm.flags.bits.lut3d_dma_enable) { 1847 + wa_pipes[wa_pipe_ct++] = mpc_pipe; 1848 + } 1849 + } 1828 1850 } 1829 1851 1830 - if (primary_dpp_pipe_ctx && 1831 - primary_dpp_pipe_ctx->plane_state && 1832 - primary_dpp_pipe_ctx->plane_state->cm.flags.bits.lut3d_enable && 1833 - primary_dpp_pipe_ctx->plane_state->cm.flags.bits.lut3d_dma_enable) { 1834 - if (tg->funcs->set_vupdate_keepout) 1835 - tg->funcs->set_vupdate_keepout(tg, true); 1852 + if (wa_pipe_ct > 0) { 1853 + if (pipe_ctx->stream_res.tg->funcs->set_vupdate_keepout) 1854 + pipe_ctx->stream_res.tg->funcs->set_vupdate_keepout(pipe_ctx->stream_res.tg, true); 1836 1855 1837 - if (primary_hubp->funcs->hubp_enable_3dlut_fl) { 1838 - primary_hubp->funcs->hubp_enable_3dlut_fl(primary_hubp, true); 1856 + for (i = 0; i < wa_pipe_ct; ++i) { 1857 + if (wa_pipes[i]->plane_res.hubp->funcs->hubp_enable_3dlut_fl) 1858 + wa_pipes[i]->plane_res.hubp->funcs->hubp_enable_3dlut_fl(wa_pipes[i]->plane_res.hubp, true); 1839 1859 } 1840 1860 1841 - tg->funcs->unlock(tg); 1842 - if (tg->funcs->wait_update_lock_status) 1843 - tg->funcs->wait_update_lock_status(tg, false); 1861 + pipe_ctx->stream_res.tg->funcs->unlock(pipe_ctx->stream_res.tg); 1862 + if (pipe_ctx->stream_res.tg->funcs->wait_update_lock_status) 1863 + pipe_ctx->stream_res.tg->funcs->wait_update_lock_status(pipe_ctx->stream_res.tg, false); 1844 1864 1845 - if (primary_hubp->funcs->hubp_enable_3dlut_fl) { 1846 - primary_hubp->funcs->hubp_enable_3dlut_fl(primary_hubp, true); 1865 + for (i = 0; i < wa_pipe_ct; ++i) { 1866 + if (wa_pipes[i]->plane_res.hubp->funcs->hubp_enable_3dlut_fl) 1867 + wa_pipes[i]->plane_res.hubp->funcs->hubp_enable_3dlut_fl(wa_pipes[i]->plane_res.hubp, true); 1847 1868 } 1848 1869 1849 - if (tg->funcs->set_vupdate_keepout) 1850 - tg->funcs->set_vupdate_keepout(tg, false); 1870 + if (pipe_ctx->stream_res.tg->funcs->set_vupdate_keepout) 1871 + pipe_ctx->stream_res.tg->funcs->set_vupdate_keepout(pipe_ctx->stream_res.tg, false); 1851 1872 } else { 1852 - tg->funcs->unlock(tg); 1873 + pipe_ctx->stream_res.tg->funcs->unlock(pipe_ctx->stream_res.tg); 1853 1874 } 1854 1875 } 1855 1876

+2 -1

drivers/gpu/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.h

··· 41 41 bool dcn401_set_output_transfer_func(struct dc *dc, 42 42 struct pipe_ctx *pipe_ctx, 43 43 const struct dc_stream_state *stream); 44 - void dcn401_trigger_3dlut_dma_load(struct pipe_ctx *pipe_ctx); 44 + void dcn401_trigger_3dlut_dma_load(struct dc *dc, 45 + struct pipe_ctx *pipe_ctx); 45 46 void dcn401_calculate_dccg_tmds_div_value(struct pipe_ctx *pipe_ctx, 46 47 unsigned int *tmds_div); 47 48 enum dc_status dcn401_enable_stream_timing(

+1 -1

drivers/gpu/drm/amd/display/dc/hwss/hw_sequencer.h

··· 1120 1120 void (*program_output_csc)(struct dc *dc, struct pipe_ctx *pipe_ctx, 1121 1121 enum dc_color_space colorspace, 1122 1122 uint16_t *matrix, int opp_id); 1123 - void (*trigger_3dlut_dma_load)(struct pipe_ctx *pipe_ctx); 1123 + void (*trigger_3dlut_dma_load)(struct dc *dc, struct pipe_ctx *pipe_ctx); 1124 1124 1125 1125 /* VM Related */ 1126 1126 int (*init_sys_ctx)(struct dce_hwseq *hws,

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