Merge branch 'bnxt_en-updates-for-net-next'

+2 -2

drivers/infiniband/hw/bnxt_re/main.c

··· 595 595 bnxt_re_init_hwrm_hdr((void *)&req, HWRM_VNIC_CFG); 596 596 597 597 req.flags = cpu_to_le32(VNIC_CFG_REQ_FLAGS_ROCE_ONLY_VNIC_MODE); 598 - req.enables = cpu_to_le32(VNIC_CFG_REQ_ENABLES_RAW_QP_ID | 598 + req.enables = cpu_to_le32(VNIC_CFG_REQ_ENABLES_QP_ID | 599 599 VNIC_CFG_REQ_ENABLES_MRU); 600 600 req.vnic_id = cpu_to_le16(rdev->mirror_vnic_id); 601 - req.raw_qp_id = cpu_to_le32(qp_id); 601 + req.qp_id = cpu_to_le32(qp_id); 602 602 req.mru = cpu_to_le16(rdev->netdev->mtu + VLAN_ETH_HLEN); 603 603 604 604 bnxt_re_fill_fw_msg(&fw_msg, (void *)&req, sizeof(req), NULL,

+38 -1

drivers/net/ethernet/broadcom/bnxt/bnxt.c

··· 6567 6567 if (bp->flags & BNXT_FLAG_CHIP_P5_PLUS) { 6568 6568 if (!rx_rings) 6569 6569 return 0; 6570 + if (bp->rss_cap & BNXT_RSS_CAP_LARGE_RSS_CTX) 6571 + return BNXT_RSS_TABLE_MAX_TBL_P5; 6572 + 6570 6573 return bnxt_calc_nr_ring_pages(rx_rings - 1, 6571 6574 BNXT_RSS_TABLE_ENTRIES_P5); 6572 6575 } ··· 8080 8077 bp->rx_nr_rings = rx_rings; 8081 8078 bp->cp_nr_rings = hwr.cp; 8082 8079 8080 + /* Fall back if we cannot reserve enough HW RSS contexts */ 8081 + if ((bp->rss_cap & BNXT_RSS_CAP_LARGE_RSS_CTX) && 8082 + hwr.rss_ctx < bnxt_get_total_rss_ctxs(bp, &hwr)) 8083 + bp->rss_cap &= ~BNXT_RSS_CAP_LARGE_RSS_CTX; 8084 + 8083 8085 if (!bnxt_rings_ok(bp, &hwr)) 8084 8086 return -ENOMEM; 8085 8087 ··· 9575 9567 hw_resc->min_stat_ctxs = le16_to_cpu(resp->min_stat_ctx); 9576 9568 hw_resc->max_stat_ctxs = le16_to_cpu(resp->max_stat_ctx); 9577 9569 9570 + if (hw_resc->max_rsscos_ctxs >= 9571 + hw_resc->max_vnics * BNXT_LARGE_RSS_TO_VNIC_RATIO) 9572 + bp->rss_cap |= BNXT_RSS_CAP_LARGE_RSS_CTX; 9573 + 9578 9574 if (bp->flags & BNXT_FLAG_CHIP_P5_PLUS) { 9579 9575 u16 max_msix = le16_to_cpu(resp->max_msix); 9580 9576 ··· 9712 9700 bp->fw_cap |= BNXT_FW_CAP_EXT_HW_STATS_SUPPORTED; 9713 9701 if (BNXT_PF(bp) && (flags_ext & FUNC_QCAPS_RESP_FLAGS_EXT_PTP_PPS_SUPPORTED)) 9714 9702 bp->fw_cap |= BNXT_FW_CAP_PTP_PPS; 9703 + if (flags_ext & FUNC_QCAPS_RESP_FLAGS_EXT_PTP_PTM_SUPPORTED) 9704 + bp->fw_cap |= BNXT_FW_CAP_PTP_PTM; 9715 9705 if (flags_ext & FUNC_QCAPS_RESP_FLAGS_EXT_PTP_64BIT_RTC_SUPPORTED) 9716 9706 bp->fw_cap |= BNXT_FW_CAP_PTP_RTC; 9717 9707 if (BNXT_PF(bp) && (flags_ext & FUNC_QCAPS_RESP_FLAGS_EXT_HOT_RESET_IF_SUPPORT)) ··· 11915 11901 } 11916 11902 } 11917 11903 11904 + static char *bnxt_link_down_reason(struct bnxt_link_info *link_info) 11905 + { 11906 + u8 reason = link_info->link_down_reason; 11907 + 11908 + /* Multiple bits can be set, we report 1 bit only in order of 11909 + * priority. 11910 + */ 11911 + if (reason & PORT_PHY_QCFG_RESP_LINK_DOWN_REASON_RF) 11912 + return "(Remote fault)"; 11913 + if (reason & PORT_PHY_QCFG_RESP_LINK_DOWN_REASON_OTP_SPEED_VIOLATION) 11914 + return "(OTP Speed limit violation)"; 11915 + if (reason & PORT_PHY_QCFG_RESP_LINK_DOWN_REASON_CABLE_REMOVED) 11916 + return "(Cable removed)"; 11917 + if (reason & PORT_PHY_QCFG_RESP_LINK_DOWN_REASON_MODULE_FAULT) 11918 + return "(Module fault)"; 11919 + if (reason & PORT_PHY_QCFG_RESP_LINK_DOWN_REASON_BMC_REQUEST) 11920 + return "(BMC request down)"; 11921 + return ""; 11922 + } 11923 + 11918 11924 void bnxt_report_link(struct bnxt *bp) 11919 11925 { 11920 11926 if (BNXT_LINK_IS_UP(bp)) { ··· 11992 11958 (fec & BNXT_FEC_AUTONEG) ? "on" : "off", 11993 11959 bnxt_report_fec(&bp->link_info)); 11994 11960 } else { 11961 + char *str = bnxt_link_down_reason(&bp->link_info); 11962 + 11995 11963 netif_carrier_off(bp->dev); 11996 - netdev_err(bp->dev, "NIC Link is Down\n"); 11964 + netdev_err(bp->dev, "NIC Link is Down %s\n", str); 11997 11965 } 11998 11966 } 11999 11967 ··· 12195 12159 link_info->phy_addr = resp->eee_config_phy_addr & 12196 12160 PORT_PHY_QCFG_RESP_PHY_ADDR_MASK; 12197 12161 link_info->module_status = resp->module_status; 12162 + link_info->link_down_reason = resp->link_down_reason; 12198 12163 12199 12164 if (bp->phy_flags & BNXT_PHY_FL_EEE_CAP) { 12200 12165 struct ethtool_keee *eee = &bp->eee;

+6

drivers/net/ethernet/broadcom/bnxt/bnxt.h

··· 1367 1367 u32 max_rx_wm_flows; 1368 1368 }; 1369 1369 1370 + #define BNXT_LARGE_RSS_TO_VNIC_RATIO 7 1371 + 1370 1372 #if defined(CONFIG_BNXT_SRIOV) 1371 1373 struct bnxt_vf_info { 1372 1374 u16 fw_fid; ··· 1553 1551 #define BNXT_LINK_STATE_DOWN 1 1554 1552 #define BNXT_LINK_STATE_UP 2 1555 1553 #define BNXT_LINK_IS_UP(bp) ((bp)->link_info.link_state == BNXT_LINK_STATE_UP) 1554 + u8 link_down_reason; 1556 1555 u8 active_lanes; 1557 1556 u8 duplex; 1558 1557 #define BNXT_LINK_DUPLEX_HALF PORT_PHY_QCFG_RESP_DUPLEX_STATE_HALF ··· 2413 2410 #define BNXT_RSS_CAP_ESP_V6_RSS_CAP BIT(7) 2414 2411 #define BNXT_RSS_CAP_MULTI_RSS_CTX BIT(8) 2415 2412 #define BNXT_RSS_CAP_IPV6_FLOW_LABEL_RSS_CAP BIT(9) 2413 + #define BNXT_RSS_CAP_LARGE_RSS_CTX BIT(10) 2416 2414 2417 2415 u8 rss_hash_key[HW_HASH_KEY_SIZE]; 2418 2416 u8 rss_hash_key_valid:1; ··· 2520 2516 #define BNXT_FW_CAP_SW_MAX_RESOURCE_LIMITS BIT_ULL(41) 2521 2517 #define BNXT_FW_CAP_NPAR_1_2 BIT_ULL(42) 2522 2518 #define BNXT_FW_CAP_MIRROR_ON_ROCE BIT_ULL(43) 2519 + #define BNXT_FW_CAP_PTP_PTM BIT_ULL(44) 2523 2520 2524 2521 u32 fw_dbg_cap; 2525 2522 ··· 2706 2701 #define BNXT_PHY_FL_NO_PFC (PORT_PHY_QCAPS_RESP_FLAGS2_PFC_UNSUPPORTED << 8) 2707 2702 #define BNXT_PHY_FL_BANK_SEL (PORT_PHY_QCAPS_RESP_FLAGS2_BANK_ADDR_SUPPORTED << 8) 2708 2703 #define BNXT_PHY_FL_SPEEDS2 (PORT_PHY_QCAPS_RESP_FLAGS2_SPEEDS2_SUPPORTED << 8) 2704 + #define BNXT_PHY_FL_FDRSTATS (PORT_PHY_QCAPS_RESP_FLAGS2_FDRSTAT_CMD_SUPPORTED << 8) 2709 2705 2710 2706 /* copied from flags in hwrm_port_mac_qcaps_output */ 2711 2707 u8 mac_flags;

+115 -3

drivers/net/ethernet/broadcom/bnxt/bnxt_ethtool.c

··· 3216 3216 return 0; 3217 3217 } 3218 3218 3219 + static const struct ethtool_fec_hist_range bnxt_fec_ranges[] = { 3220 + { 0, 0}, 3221 + { 1, 1}, 3222 + { 2, 2}, 3223 + { 3, 3}, 3224 + { 4, 4}, 3225 + { 5, 5}, 3226 + { 6, 6}, 3227 + { 7, 7}, 3228 + { 8, 8}, 3229 + { 9, 9}, 3230 + { 10, 10}, 3231 + { 11, 11}, 3232 + { 12, 12}, 3233 + { 13, 13}, 3234 + { 14, 14}, 3235 + { 15, 15}, 3236 + { 0, 0}, 3237 + }; 3238 + 3239 + static void bnxt_hwrm_port_phy_fdrstat(struct bnxt *bp, 3240 + struct ethtool_fec_hist *hist) 3241 + { 3242 + struct ethtool_fec_hist_value *values = hist->values; 3243 + struct hwrm_port_phy_fdrstat_output *resp; 3244 + struct hwrm_port_phy_fdrstat_input *req; 3245 + int rc, i; 3246 + 3247 + if (!(bp->phy_flags & BNXT_PHY_FL_FDRSTATS)) 3248 + return; 3249 + 3250 + rc = hwrm_req_init(bp, req, HWRM_PORT_PHY_FDRSTAT); 3251 + if (rc) 3252 + return; 3253 + 3254 + req->port_id = cpu_to_le16(bp->pf.port_id); 3255 + req->ops = cpu_to_le16(PORT_PHY_FDRSTAT_REQ_OPS_COUNTER); 3256 + resp = hwrm_req_hold(bp, req); 3257 + rc = hwrm_req_send(bp, req); 3258 + if (!rc) { 3259 + hist->ranges = bnxt_fec_ranges; 3260 + for (i = 0; i <= 15; i++) { 3261 + __le64 sum = resp->accumulated_codewords_err_s[i]; 3262 + 3263 + values[i].sum = le64_to_cpu(sum); 3264 + } 3265 + } 3266 + hwrm_req_drop(bp, req); 3267 + } 3268 + 3219 3269 static void bnxt_get_fec_stats(struct net_device *dev, 3220 3270 struct ethtool_fec_stats *fec_stats, 3221 3271 struct ethtool_fec_hist *hist) ··· 3287 3237 *(rx + BNXT_RX_STATS_EXT_OFFSET(rx_fec_corrected_blocks)); 3288 3238 fec_stats->uncorrectable_blocks.total = 3289 3239 *(rx + BNXT_RX_STATS_EXT_OFFSET(rx_fec_uncorrectable_blocks)); 3240 + bnxt_hwrm_port_phy_fdrstat(bp, hist); 3290 3241 } 3291 3242 3292 3243 static u32 bnxt_ethtool_forced_fec_to_fw(struct bnxt_link_info *link_info, ··· 3430 3379 3431 3380 /* TODO: handle MF, VF, driver close case */ 3432 3381 return BNXT_LINK_IS_UP(bp); 3382 + } 3383 + 3384 + static int bnxt_get_link_ext_state(struct net_device *dev, 3385 + struct ethtool_link_ext_state_info *info) 3386 + { 3387 + struct bnxt *bp = netdev_priv(dev); 3388 + u8 reason; 3389 + 3390 + if (BNXT_LINK_IS_UP(bp)) 3391 + return -ENODATA; 3392 + 3393 + reason = bp->link_info.link_down_reason; 3394 + if (reason & PORT_PHY_QCFG_RESP_LINK_DOWN_REASON_RF) { 3395 + info->link_ext_state = ETHTOOL_LINK_EXT_STATE_LINK_TRAINING_FAILURE; 3396 + info->link_training = ETHTOOL_LINK_EXT_SUBSTATE_LT_REMOTE_FAULT; 3397 + return 0; 3398 + } 3399 + if (reason & PORT_PHY_QCFG_RESP_LINK_DOWN_REASON_CABLE_REMOVED) { 3400 + info->link_ext_state = ETHTOOL_LINK_EXT_STATE_NO_CABLE; 3401 + return 0; 3402 + } 3403 + if (reason & PORT_PHY_QCFG_RESP_LINK_DOWN_REASON_OTP_SPEED_VIOLATION) { 3404 + info->link_ext_state = ETHTOOL_LINK_EXT_STATE_OTP_SPEED_VIOLATION; 3405 + return 0; 3406 + } 3407 + if (reason & PORT_PHY_QCFG_RESP_LINK_DOWN_REASON_MODULE_FAULT) { 3408 + info->link_ext_state = ETHTOOL_LINK_EXT_STATE_MODULE; 3409 + return 0; 3410 + } 3411 + if (reason & PORT_PHY_QCFG_RESP_LINK_DOWN_REASON_BMC_REQUEST) { 3412 + info->link_ext_state = ETHTOOL_LINK_EXT_STATE_BMC_REQUEST_DOWN; 3413 + return 0; 3414 + } 3415 + return -ENODATA; 3433 3416 } 3434 3417 3435 3418 int bnxt_hwrm_nvm_get_dev_info(struct bnxt *bp, ··· 3882 3797 #define BNXT_NVM_MORE_FLAG (cpu_to_le16(NVM_MODIFY_REQ_FLAGS_BATCH_MODE)) 3883 3798 #define BNXT_NVM_LAST_FLAG (cpu_to_le16(NVM_MODIFY_REQ_FLAGS_BATCH_LAST)) 3884 3799 3800 + static int bnxt_hwrm_nvm_defrag(struct bnxt *bp) 3801 + { 3802 + struct hwrm_nvm_defrag_input *req; 3803 + int rc; 3804 + 3805 + rc = hwrm_req_init(bp, req, HWRM_NVM_DEFRAG); 3806 + if (rc) 3807 + return rc; 3808 + req->flags = cpu_to_le32(NVM_DEFRAG_REQ_FLAGS_DEFRAG); 3809 + hwrm_req_timeout(bp, req, bp->hwrm_cmd_max_timeout); 3810 + 3811 + return hwrm_req_send(bp, req); 3812 + } 3813 + 3885 3814 static int bnxt_resize_update_entry(struct net_device *dev, size_t fw_size, 3886 3815 struct netlink_ext_ack *extack) 3887 3816 { 3817 + struct bnxt *bp = netdev_priv(dev); 3818 + bool retry = false; 3888 3819 u32 item_len; 3889 3820 int rc; 3890 3821 ··· 3913 3812 } 3914 3813 3915 3814 if (fw_size > item_len) { 3916 - rc = bnxt_flash_nvram(dev, BNX_DIR_TYPE_UPDATE, 3917 - BNX_DIR_ORDINAL_FIRST, 0, 1, 3918 - round_up(fw_size, 4096), NULL, 0); 3815 + do { 3816 + rc = bnxt_flash_nvram(dev, BNX_DIR_TYPE_UPDATE, 3817 + BNX_DIR_ORDINAL_FIRST, 0, 1, 3818 + round_up(fw_size, 4096), NULL, 3819 + 0); 3820 + 3821 + if (rc == -ENOSPC) { 3822 + if (retry || bnxt_hwrm_nvm_defrag(bp)) 3823 + break; 3824 + retry = true; 3825 + } 3826 + } while (rc == -ENOSPC); 3827 + 3919 3828 if (rc) { 3920 3829 BNXT_NVM_ERR_MSG(dev, extack, MSG_RESIZE_UPDATE_ERR); 3921 3830 return rc; ··· 5745 5634 .get_eeprom = bnxt_get_eeprom, 5746 5635 .set_eeprom = bnxt_set_eeprom, 5747 5636 .get_link = bnxt_get_link, 5637 + .get_link_ext_state = bnxt_get_link_ext_state, 5748 5638 .get_link_ext_stats = bnxt_get_link_ext_stats, 5749 5639 .get_eee = bnxt_get_eee, 5750 5640 .set_eee = bnxt_set_eee,

+47

drivers/net/ethernet/broadcom/bnxt/bnxt_ptp.c

··· 882 882 } 883 883 } 884 884 885 + static int bnxt_phc_get_syncdevicetime(ktime_t *device, 886 + struct system_counterval_t *system, 887 + void *ctx) 888 + { 889 + struct bnxt_ptp_cfg *ptp = (struct bnxt_ptp_cfg *)ctx; 890 + struct hwrm_func_ptp_ts_query_output *resp; 891 + struct hwrm_func_ptp_ts_query_input *req; 892 + struct bnxt *bp = ptp->bp; 893 + u64 ptm_local_ts; 894 + int rc; 895 + 896 + rc = hwrm_req_init(bp, req, HWRM_FUNC_PTP_TS_QUERY); 897 + if (rc) 898 + return rc; 899 + req->flags = cpu_to_le32(FUNC_PTP_TS_QUERY_REQ_FLAGS_PTM_TIME); 900 + resp = hwrm_req_hold(bp, req); 901 + rc = hwrm_req_send(bp, req); 902 + if (rc) { 903 + hwrm_req_drop(bp, req); 904 + return rc; 905 + } 906 + ptm_local_ts = le64_to_cpu(resp->ptm_local_ts); 907 + *device = ns_to_ktime(bnxt_timecounter_cyc2time(ptp, ptm_local_ts)); 908 + /* ptm_system_ts is 64-bit */ 909 + system->cycles = le64_to_cpu(resp->ptm_system_ts); 910 + system->cs_id = CSID_X86_ART; 911 + system->use_nsecs = true; 912 + 913 + hwrm_req_drop(bp, req); 914 + 915 + return 0; 916 + } 917 + 918 + static int bnxt_ptp_getcrosststamp(struct ptp_clock_info *ptp_info, 919 + struct system_device_crosststamp *xtstamp) 920 + { 921 + struct bnxt_ptp_cfg *ptp = container_of(ptp_info, struct bnxt_ptp_cfg, 922 + ptp_info); 923 + 924 + return get_device_system_crosststamp(bnxt_phc_get_syncdevicetime, 925 + ptp, NULL, xtstamp); 926 + } 927 + 885 928 static const struct ptp_clock_info bnxt_ptp_caps = { 886 929 .owner = THIS_MODULE, 887 930 .name = "bnxt clock", ··· 1137 1094 if (bnxt_ptp_pps_init(bp)) 1138 1095 netdev_err(bp->dev, "1pps not initialized, continuing without 1pps support\n"); 1139 1096 } 1097 + if ((bp->fw_cap & BNXT_FW_CAP_PTP_PTM) && pcie_ptm_enabled(bp->pdev) && 1098 + boot_cpu_has(X86_FEATURE_ART)) 1099 + ptp->ptp_info.getcrosststamp = bnxt_ptp_getcrosststamp; 1100 + 1140 1101 ptp->ptp_clock = ptp_clock_register(&ptp->ptp_info, &bp->pdev->dev); 1141 1102 if (IS_ERR(ptp->ptp_clock)) { 1142 1103 int err = PTR_ERR(ptp->ptp_clock);

+151 -16

include/linux/bnxt/hsi.h

··· 187 187 #define HWRM_RING_QCFG 0x63UL 188 188 #define HWRM_RESERVED5 0x64UL 189 189 #define HWRM_RESERVED6 0x65UL 190 + #define HWRM_PORT_ADSM_QSTATES 0x66UL 191 + #define HWRM_PORT_EVENTS_LOG 0x67UL 190 192 #define HWRM_VNIC_RSS_COS_LB_CTX_ALLOC 0x70UL 191 193 #define HWRM_VNIC_RSS_COS_LB_CTX_FREE 0x71UL 192 194 #define HWRM_QUEUE_MPLS_QCAPS 0x80UL ··· 237 235 #define HWRM_PORT_PHY_MDIO_BUS_ACQUIRE 0xb7UL 238 236 #define HWRM_PORT_PHY_MDIO_BUS_RELEASE 0xb8UL 239 237 #define HWRM_PORT_QSTATS_EXT_PFC_WD 0xb9UL 240 - #define HWRM_RESERVED7 0xbaUL 238 + #define HWRM_PORT_QSTATS_EXT_PFC_ADV 0xbaUL 241 239 #define HWRM_PORT_TX_FIR_CFG 0xbbUL 242 240 #define HWRM_PORT_TX_FIR_QCFG 0xbcUL 243 241 #define HWRM_PORT_ECN_QSTATS 0xbdUL ··· 273 271 #define HWRM_PORT_EP_TX_CFG 0xdbUL 274 272 #define HWRM_PORT_CFG 0xdcUL 275 273 #define HWRM_PORT_QCFG 0xddUL 274 + #define HWRM_PORT_DSC_COLLECTION 0xdeUL 276 275 #define HWRM_PORT_MAC_QCAPS 0xdfUL 277 276 #define HWRM_TEMP_MONITOR_QUERY 0xe0UL 278 277 #define HWRM_REG_POWER_QUERY 0xe1UL ··· 283 280 #define HWRM_MONITOR_PAX_HISTOGRAM_COLLECT 0xe5UL 284 281 #define HWRM_STAT_QUERY_ROCE_STATS 0xe6UL 285 282 #define HWRM_STAT_QUERY_ROCE_STATS_EXT 0xe7UL 283 + #define HWRM_MONITOR_DEVICE_HEALTH 0xe8UL 286 284 #define HWRM_WOL_FILTER_ALLOC 0xf0UL 287 285 #define HWRM_WOL_FILTER_FREE 0xf1UL 288 286 #define HWRM_WOL_FILTER_QCFG 0xf2UL ··· 644 640 #define HWRM_VERSION_MAJOR 1 645 641 #define HWRM_VERSION_MINOR 10 646 642 #define HWRM_VERSION_UPDATE 3 647 - #define HWRM_VERSION_RSVD 133 648 - #define HWRM_VERSION_STR "1.10.3.133" 643 + #define HWRM_VERSION_RSVD 151 644 + #define HWRM_VERSION_STR "1.10.3.151" 649 645 650 646 /* hwrm_ver_get_input (size:192b/24B) */ 651 647 struct hwrm_ver_get_input { ··· 1420 1416 #define ASYNC_EVENT_CMPL_ERROR_REPORT_BASE_EVENT_DATA1_ERROR_TYPE_DB_DROP 0x8UL 1421 1417 #define ASYNC_EVENT_CMPL_ERROR_REPORT_BASE_EVENT_DATA1_ERROR_TYPE_MD_TEMP 0x9UL 1422 1418 #define ASYNC_EVENT_CMPL_ERROR_REPORT_BASE_EVENT_DATA1_ERROR_TYPE_VNIC_ERR 0xaUL 1423 - #define ASYNC_EVENT_CMPL_ERROR_REPORT_BASE_EVENT_DATA1_ERROR_TYPE_LAST ASYNC_EVENT_CMPL_ERROR_REPORT_BASE_EVENT_DATA1_ERROR_TYPE_VNIC_ERR 1419 + #define ASYNC_EVENT_CMPL_ERROR_REPORT_BASE_EVENT_DATA1_ERROR_TYPE_L2_TX_RING 0xbUL 1420 + #define ASYNC_EVENT_CMPL_ERROR_REPORT_BASE_EVENT_DATA1_ERROR_TYPE_LAST ASYNC_EVENT_CMPL_ERROR_REPORT_BASE_EVENT_DATA1_ERROR_TYPE_L2_TX_RING 1424 1421 }; 1425 1422 1426 1423 /* hwrm_async_event_cmpl_error_report_pause_storm (size:128b/16B) */ ··· 1939 1934 #define FUNC_QCAPS_RESP_FLAGS_EXT3_PCIE_COMPLIANCE_SUPPORTED 0x100UL 1940 1935 #define FUNC_QCAPS_RESP_FLAGS_EXT3_MULTI_L2_DB_SUPPORTED 0x200UL 1941 1936 #define FUNC_QCAPS_RESP_FLAGS_EXT3_PCIE_SECURE_ATS_SUPPORTED 0x400UL 1942 - #define FUNC_QCAPS_RESP_FLAGS_EXT3_MBUF_STATS_SUPPORTED 0x800UL 1937 + #define FUNC_QCAPS_RESP_FLAGS_EXT3_MBUF_DATA_SUPPORTED 0x800UL 1938 + #define FUNC_QCAPS_RESP_FLAGS_EXT3_ROCE_CMPL_TS_SUPPORTED 0x1000UL 1939 + #define FUNC_QCAPS_RESP_FLAGS_EXT3_ROCE_ST_SUPPORTED 0x2000UL 1943 1940 __le16 max_roce_vfs; 1944 1941 __le16 max_crypto_rx_flow_filters; 1945 1942 u8 unused_3[3]; ··· 4448 4441 #define PORT_PHY_CFG_REQ_FORCE_LINK_SPEEDS2_200GB_PAM4_112 0x7d2UL 4449 4442 #define PORT_PHY_CFG_REQ_FORCE_LINK_SPEEDS2_400GB_PAM4_112 0xfa2UL 4450 4443 #define PORT_PHY_CFG_REQ_FORCE_LINK_SPEEDS2_800GB_PAM4_112 0x1f42UL 4451 - #define PORT_PHY_CFG_REQ_FORCE_LINK_SPEEDS2_LAST PORT_PHY_CFG_REQ_FORCE_LINK_SPEEDS2_800GB_PAM4_112 4444 + #define PORT_PHY_CFG_REQ_FORCE_LINK_SPEEDS2_200GB_PAM4_224 0x7d3UL 4445 + #define PORT_PHY_CFG_REQ_FORCE_LINK_SPEEDS2_400GB_PAM4_224 0xfa3UL 4446 + #define PORT_PHY_CFG_REQ_FORCE_LINK_SPEEDS2_800GB_PAM4_224 0x1f43UL 4447 + #define PORT_PHY_CFG_REQ_FORCE_LINK_SPEEDS2_LAST PORT_PHY_CFG_REQ_FORCE_LINK_SPEEDS2_800GB_PAM4_224 4452 4448 __le16 auto_link_speeds2_mask; 4453 4449 #define PORT_PHY_CFG_REQ_AUTO_LINK_SPEEDS2_MASK_1GB 0x1UL 4454 4450 #define PORT_PHY_CFG_REQ_AUTO_LINK_SPEEDS2_MASK_10GB 0x2UL ··· 4467 4457 #define PORT_PHY_CFG_REQ_AUTO_LINK_SPEEDS2_MASK_200GB_PAM4_112 0x800UL 4468 4458 #define PORT_PHY_CFG_REQ_AUTO_LINK_SPEEDS2_MASK_400GB_PAM4_112 0x1000UL 4469 4459 #define PORT_PHY_CFG_REQ_AUTO_LINK_SPEEDS2_MASK_800GB_PAM4_112 0x2000UL 4470 - u8 unused_2[6]; 4460 + __le16 auto_link_speeds2_ext_mask; 4461 + #define PORT_PHY_CFG_REQ_AUTO_LINK_SPEEDS2_EXT_MASK_200GB_PAM4_224 0x1UL 4462 + #define PORT_PHY_CFG_REQ_AUTO_LINK_SPEEDS2_EXT_MASK_400GB_PAM4_224 0x2UL 4463 + #define PORT_PHY_CFG_REQ_AUTO_LINK_SPEEDS2_EXT_MASK_800GB_PAM4_224 0x4UL 4464 + u8 unused_2[4]; 4471 4465 }; 4472 4466 4473 4467 /* hwrm_port_phy_cfg_output (size:128b/16B) */ ··· 4505 4491 u8 unused_0[6]; 4506 4492 }; 4507 4493 4508 - /* hwrm_port_phy_qcfg_output (size:832b/104B) */ 4494 + /* hwrm_port_phy_qcfg_output (size:896b/112B) */ 4509 4495 struct hwrm_port_phy_qcfg_output { 4510 4496 __le16 error_code; 4511 4497 __le16 req_type; ··· 4515 4501 #define PORT_PHY_QCFG_RESP_LINK_NO_LINK 0x0UL 4516 4502 #define PORT_PHY_QCFG_RESP_LINK_SIGNAL 0x1UL 4517 4503 #define PORT_PHY_QCFG_RESP_LINK_LINK 0x2UL 4518 - #define PORT_PHY_QCFG_RESP_LINK_LAST PORT_PHY_QCFG_RESP_LINK_LINK 4504 + #define PORT_PHY_QCFG_RESP_LINK_NO_SD 0x3UL 4505 + #define PORT_PHY_QCFG_RESP_LINK_NO_LOCK 0x4UL 4506 + #define PORT_PHY_QCFG_RESP_LINK_LAST PORT_PHY_QCFG_RESP_LINK_NO_LOCK 4519 4507 u8 active_fec_signal_mode; 4520 4508 #define PORT_PHY_QCFG_RESP_SIGNAL_MODE_MASK 0xfUL 4521 4509 #define PORT_PHY_QCFG_RESP_SIGNAL_MODE_SFT 0 4522 4510 #define PORT_PHY_QCFG_RESP_SIGNAL_MODE_NRZ 0x0UL 4523 4511 #define PORT_PHY_QCFG_RESP_SIGNAL_MODE_PAM4 0x1UL 4524 4512 #define PORT_PHY_QCFG_RESP_SIGNAL_MODE_PAM4_112 0x2UL 4525 - #define PORT_PHY_QCFG_RESP_SIGNAL_MODE_LAST PORT_PHY_QCFG_RESP_SIGNAL_MODE_PAM4_112 4513 + #define PORT_PHY_QCFG_RESP_SIGNAL_MODE_PAM4_224 0x3UL 4514 + #define PORT_PHY_QCFG_RESP_SIGNAL_MODE_LAST PORT_PHY_QCFG_RESP_SIGNAL_MODE_PAM4_224 4526 4515 #define PORT_PHY_QCFG_RESP_ACTIVE_FEC_MASK 0xf0UL 4527 4516 #define PORT_PHY_QCFG_RESP_ACTIVE_FEC_SFT 4 4528 4517 #define PORT_PHY_QCFG_RESP_ACTIVE_FEC_FEC_NONE_ACTIVE (0x0UL << 4) ··· 4716 4699 #define PORT_PHY_QCFG_RESP_PHY_TYPE_800G_BASEER8 0x3bUL 4717 4700 #define PORT_PHY_QCFG_RESP_PHY_TYPE_800G_BASEFR8 0x3cUL 4718 4701 #define PORT_PHY_QCFG_RESP_PHY_TYPE_800G_BASEDR8 0x3dUL 4719 - #define PORT_PHY_QCFG_RESP_PHY_TYPE_LAST PORT_PHY_QCFG_RESP_PHY_TYPE_800G_BASEDR8 4702 + #define PORT_PHY_QCFG_RESP_PHY_TYPE_400G_BASEDR4 0x3eUL 4703 + #define PORT_PHY_QCFG_RESP_PHY_TYPE_400G_BASEFR4 0x3fUL 4704 + #define PORT_PHY_QCFG_RESP_PHY_TYPE_LAST PORT_PHY_QCFG_RESP_PHY_TYPE_400G_BASEFR4 4720 4705 u8 media_type; 4721 4706 #define PORT_PHY_QCFG_RESP_MEDIA_TYPE_UNKNOWN 0x0UL 4722 4707 #define PORT_PHY_QCFG_RESP_MEDIA_TYPE_TP 0x1UL ··· 4878 4859 #define PORT_PHY_QCFG_RESP_FORCE_LINK_SPEEDS2_200GB_PAM4_112 0x7d2UL 4879 4860 #define PORT_PHY_QCFG_RESP_FORCE_LINK_SPEEDS2_400GB_PAM4_112 0xfa2UL 4880 4861 #define PORT_PHY_QCFG_RESP_FORCE_LINK_SPEEDS2_800GB_PAM4_112 0x1f42UL 4881 - #define PORT_PHY_QCFG_RESP_FORCE_LINK_SPEEDS2_LAST PORT_PHY_QCFG_RESP_FORCE_LINK_SPEEDS2_800GB_PAM4_112 4862 + #define PORT_PHY_QCFG_RESP_FORCE_LINK_SPEEDS2_200GB_PAM4_224 0x7d3UL 4863 + #define PORT_PHY_QCFG_RESP_FORCE_LINK_SPEEDS2_400GB_PAM4_224 0xfa3UL 4864 + #define PORT_PHY_QCFG_RESP_FORCE_LINK_SPEEDS2_800GB_PAM4_224 0x1f43UL 4865 + #define PORT_PHY_QCFG_RESP_FORCE_LINK_SPEEDS2_LAST PORT_PHY_QCFG_RESP_FORCE_LINK_SPEEDS2_800GB_PAM4_224 4882 4866 __le16 auto_link_speeds2; 4883 4867 #define PORT_PHY_QCFG_RESP_AUTO_LINK_SPEEDS2_1GB 0x1UL 4884 4868 #define PORT_PHY_QCFG_RESP_AUTO_LINK_SPEEDS2_10GB 0x2UL ··· 4898 4876 #define PORT_PHY_QCFG_RESP_AUTO_LINK_SPEEDS2_400GB_PAM4_112 0x1000UL 4899 4877 #define PORT_PHY_QCFG_RESP_AUTO_LINK_SPEEDS2_800GB_PAM4_112 0x2000UL 4900 4878 u8 active_lanes; 4879 + u8 rsvd1; 4880 + __le16 support_speeds2_ext; 4881 + #define PORT_PHY_QCFG_RESP_SUPPORT_SPEEDS2_EXT_200GB_PAM4_224 0x1UL 4882 + #define PORT_PHY_QCFG_RESP_SUPPORT_SPEEDS2_EXT_400GB_PAM4_224 0x2UL 4883 + #define PORT_PHY_QCFG_RESP_SUPPORT_SPEEDS2_EXT_800GB_PAM4_224 0x4UL 4884 + __le16 auto_link_speeds2_ext; 4885 + #define PORT_PHY_QCFG_RESP_AUTO_LINK_SPEEDS2_EXT_200GB_PAM4_224 0x1UL 4886 + #define PORT_PHY_QCFG_RESP_AUTO_LINK_SPEEDS2_EXT_400GB_PAM4_224 0x2UL 4887 + #define PORT_PHY_QCFG_RESP_AUTO_LINK_SPEEDS2_EXT_800GB_PAM4_224 0x4UL 4888 + u8 rsvd2[3]; 4901 4889 u8 valid; 4902 4890 }; 4903 4891 ··· 5510 5478 u8 unused_0[6]; 5511 5479 }; 5512 5480 5513 - /* hwrm_port_phy_qcaps_output (size:320b/40B) */ 5481 + /* hwrm_port_phy_qcaps_output (size:384b/48B) */ 5514 5482 struct hwrm_port_phy_qcaps_output { 5515 5483 __le16 error_code; 5516 5484 __le16 req_type; ··· 5595 5563 #define PORT_PHY_QCAPS_RESP_FLAGS2_BANK_ADDR_SUPPORTED 0x4UL 5596 5564 #define PORT_PHY_QCAPS_RESP_FLAGS2_SPEEDS2_SUPPORTED 0x8UL 5597 5565 #define PORT_PHY_QCAPS_RESP_FLAGS2_REMOTE_LPBK_UNSUPPORTED 0x10UL 5566 + #define PORT_PHY_QCAPS_RESP_FLAGS2_PFC_ADV_STATS_SUPPORTED 0x20UL 5567 + #define PORT_PHY_QCAPS_RESP_FLAGS2_ADSM_REPORT_SUPPORTED 0x40UL 5568 + #define PORT_PHY_QCAPS_RESP_FLAGS2_PM_EVENT_LOG_SUPPORTED 0x80UL 5569 + #define PORT_PHY_QCAPS_RESP_FLAGS2_FDRSTAT_CMD_SUPPORTED 0x100UL 5598 5570 u8 internal_port_cnt; 5599 5571 u8 unused_0; 5600 5572 __le16 supported_speeds2_force_mode; ··· 5631 5595 #define PORT_PHY_QCAPS_RESP_SUPPORTED_SPEEDS2_AUTO_MODE_200GB_PAM4_112 0x800UL 5632 5596 #define PORT_PHY_QCAPS_RESP_SUPPORTED_SPEEDS2_AUTO_MODE_400GB_PAM4_112 0x1000UL 5633 5597 #define PORT_PHY_QCAPS_RESP_SUPPORTED_SPEEDS2_AUTO_MODE_800GB_PAM4_112 0x2000UL 5634 - u8 unused_1[3]; 5598 + __le16 supported_speeds2_ext_force_mode; 5599 + #define PORT_PHY_QCAPS_RESP_SUPPORTED_SPEEDS2_EXT_FORCE_MODE_200GB_PAM4_224 0x1UL 5600 + #define PORT_PHY_QCAPS_RESP_SUPPORTED_SPEEDS2_EXT_FORCE_MODE_400GB_PAM4_224 0x2UL 5601 + #define PORT_PHY_QCAPS_RESP_SUPPORTED_SPEEDS2_EXT_FORCE_MODE_800GB_PAM4_224 0x4UL 5602 + __le16 supported_speeds2_ext_auto_mode; 5603 + #define PORT_PHY_QCAPS_RESP_SUPPORTED_SPEEDS2_EXT_AUTO_MODE_200GB_PAM4_224 0x1UL 5604 + #define PORT_PHY_QCAPS_RESP_SUPPORTED_SPEEDS2_EXT_AUTO_MODE_400GB_PAM4_224 0x2UL 5605 + #define PORT_PHY_QCAPS_RESP_SUPPORTED_SPEEDS2_EXT_AUTO_MODE_800GB_PAM4_224 0x4UL 5606 + u8 unused_1[7]; 5635 5607 u8 valid; 5636 5608 }; 5637 5609 ··· 6093 6049 #define PORT_LED_QCAPS_RESP_LED3_COLOR_CAPS_GRNAMB_SUPPORTED 0x8UL 6094 6050 u8 unused_4[3]; 6095 6051 u8 valid; 6052 + }; 6053 + 6054 + /* hwrm_port_phy_fdrstat_input (size:192b/24B) */ 6055 + struct hwrm_port_phy_fdrstat_input { 6056 + __le16 req_type; 6057 + __le16 cmpl_ring; 6058 + __le16 seq_id; 6059 + __le16 target_id; 6060 + __le64 resp_addr; 6061 + __le16 port_id; 6062 + __le16 rsvd[2]; 6063 + __le16 ops; 6064 + #define PORT_PHY_FDRSTAT_REQ_OPS_START 0x0UL 6065 + #define PORT_PHY_FDRSTAT_REQ_OPS_STOP 0x1UL 6066 + #define PORT_PHY_FDRSTAT_REQ_OPS_CLEAR 0x2UL 6067 + #define PORT_PHY_FDRSTAT_REQ_OPS_COUNTER 0x3UL 6068 + #define PORT_PHY_FDRSTAT_REQ_OPS_LAST PORT_PHY_FDRSTAT_REQ_OPS_COUNTER 6069 + }; 6070 + 6071 + /* hwrm_port_phy_fdrstat_output (size:3072b/384B) */ 6072 + struct hwrm_port_phy_fdrstat_output { 6073 + __le16 error_code; 6074 + __le16 req_type; 6075 + __le16 seq_id; 6076 + __le16 resp_len; 6077 + __le64 start_time; 6078 + __le64 end_time; 6079 + __le64 cmic_start_time; 6080 + __le64 cmic_end_time; 6081 + __le64 accumulated_uncorrected_codewords; 6082 + __le64 accumulated_corrected_codewords; 6083 + __le64 accumulated_total_codewords; 6084 + __le64 accumulated_symbol_errors; 6085 + __le64 accumulated_codewords_err_s[17]; 6086 + __le64 uncorrected_codewords; 6087 + __le64 corrected_codewords; 6088 + __le64 total_codewords; 6089 + __le64 symbol_errors; 6090 + __le64 codewords_err_s[17]; 6091 + __le32 window_size; 6092 + __le16 unused_0[1]; 6093 + u8 unused_1; 6094 + u8 valid; 6095 + }; 6096 + 6097 + /* hwrm_port_phy_fdrstat_cmd_err (size:64b/8B) */ 6098 + struct hwrm_port_phy_fdrstat_cmd_err { 6099 + u8 code; 6100 + #define PORT_PHY_FDRSTAT_CMD_ERR_CODE_UNKNOWN 0x0UL 6101 + #define PORT_PHY_FDRSTAT_CMD_ERR_CODE_NOT_STARTED 0x1UL 6102 + #define PORT_PHY_FDRSTAT_CMD_ERR_CODE_LAST PORT_PHY_FDRSTAT_CMD_ERR_CODE_NOT_STARTED 6103 + u8 unused_0[7]; 6096 6104 }; 6097 6105 6098 6106 /* hwrm_port_mac_qcaps_input (size:192b/24B) */ ··· 7008 6912 #define VNIC_CFG_REQ_FLAGS_RSS_DFLT_CR_MODE 0x20UL 7009 6913 #define VNIC_CFG_REQ_FLAGS_ROCE_MIRRORING_CAPABLE_VNIC_MODE 0x40UL 7010 6914 #define VNIC_CFG_REQ_FLAGS_PORTCOS_MAPPING_MODE 0x80UL 6915 + #define VNIC_CFG_REQ_FLAGS_DEST_QP 0x100UL 7011 6916 __le32 enables; 7012 6917 #define VNIC_CFG_REQ_ENABLES_DFLT_RING_GRP 0x1UL 7013 6918 #define VNIC_CFG_REQ_ENABLES_RSS_RULE 0x2UL ··· 7020 6923 #define VNIC_CFG_REQ_ENABLES_QUEUE_ID 0x80UL 7021 6924 #define VNIC_CFG_REQ_ENABLES_RX_CSUM_V2_MODE 0x100UL 7022 6925 #define VNIC_CFG_REQ_ENABLES_L2_CQE_MODE 0x200UL 7023 - #define VNIC_CFG_REQ_ENABLES_RAW_QP_ID 0x400UL 6926 + #define VNIC_CFG_REQ_ENABLES_QP_ID 0x400UL 7024 6927 __le16 vnic_id; 7025 6928 __le16 dflt_ring_grp; 7026 6929 __le16 rss_rule; ··· 7040 6943 #define VNIC_CFG_REQ_L2_CQE_MODE_COMPRESSED 0x1UL 7041 6944 #define VNIC_CFG_REQ_L2_CQE_MODE_MIXED 0x2UL 7042 6945 #define VNIC_CFG_REQ_L2_CQE_MODE_LAST VNIC_CFG_REQ_L2_CQE_MODE_MIXED 7043 - __le32 raw_qp_id; 6946 + __le32 qp_id; 7044 6947 }; 7045 6948 7046 6949 /* hwrm_vnic_cfg_output (size:128b/16B) */ ··· 7506 7409 #define RING_ALLOC_REQ_FLAGS_DISABLE_CQ_OVERFLOW_DETECTION 0x2UL 7507 7410 #define RING_ALLOC_REQ_FLAGS_NQ_DBR_PACING 0x4UL 7508 7411 #define RING_ALLOC_REQ_FLAGS_TX_PKT_TS_CMPL_ENABLE 0x8UL 7412 + #define RING_ALLOC_REQ_FLAGS_DPI_ROCE_MANAGED 0x10UL 7413 + #define RING_ALLOC_REQ_FLAGS_TIMER_RESET 0x20UL 7509 7414 __le64 page_tbl_addr; 7510 7415 __le32 fbo; 7511 7416 u8 page_size; ··· 7682 7583 #define RING_AGGINT_QCAPS_RESP_CMPL_PARAMS_CMPL_AGGR_DMA_TMR 0x40UL 7683 7584 #define RING_AGGINT_QCAPS_RESP_CMPL_PARAMS_CMPL_AGGR_DMA_TMR_DURING_INT 0x80UL 7684 7585 #define RING_AGGINT_QCAPS_RESP_CMPL_PARAMS_NUM_CMPL_AGGR_INT 0x100UL 7586 + #define RING_AGGINT_QCAPS_RESP_CMPL_PARAMS_TMR_RESET_ON_ALLOC 0x200UL 7685 7587 __le32 nq_params; 7686 7588 #define RING_AGGINT_QCAPS_RESP_NQ_PARAMS_INT_LAT_TMR_MIN 0x1UL 7687 7589 __le16 num_cmpl_dma_aggr_min; ··· 10425 10325 __le16 instance; 10426 10326 __le16 unused_1; 10427 10327 u8 seg_flags; 10328 + #define DBG_COREDUMP_RETRIEVE_REQ_SFLAG_LIVE_DATA 0x1UL 10329 + #define DBG_COREDUMP_RETRIEVE_REQ_SFLAG_CRASHED_DATA 0x2UL 10330 + #define DBG_COREDUMP_RETRIEVE_REQ_SFLAG_NO_COMPRESS 0x4UL 10428 10331 u8 unused_2; 10429 10332 __le16 unused_3; 10430 10333 __le32 unused_4; ··· 11026 10923 #define NVM_SET_VARIABLE_CMD_ERR_CODE_INVALID_DATA_LEN 0x8UL 11027 10924 #define NVM_SET_VARIABLE_CMD_ERR_CODE_NO_MEM 0x9UL 11028 10925 #define NVM_SET_VARIABLE_CMD_ERR_CODE_LAST NVM_SET_VARIABLE_CMD_ERR_CODE_NO_MEM 10926 + u8 unused_0[7]; 10927 + }; 10928 + 10929 + /* hwrm_nvm_defrag_input (size:192b/24B) */ 10930 + struct hwrm_nvm_defrag_input { 10931 + __le16 req_type; 10932 + __le16 cmpl_ring; 10933 + __le16 seq_id; 10934 + __le16 target_id; 10935 + __le64 resp_addr; 10936 + __le32 flags; 10937 + #define NVM_DEFRAG_REQ_FLAGS_DEFRAG 0x1UL 10938 + u8 unused_0[4]; 10939 + }; 10940 + 10941 + /* hwrm_nvm_defrag_output (size:128b/16B) */ 10942 + struct hwrm_nvm_defrag_output { 10943 + __le16 error_code; 10944 + __le16 req_type; 10945 + __le16 seq_id; 10946 + __le16 resp_len; 10947 + u8 unused_0[7]; 10948 + u8 valid; 10949 + }; 10950 + 10951 + /* hwrm_nvm_defrag_cmd_err (size:64b/8B) */ 10952 + struct hwrm_nvm_defrag_cmd_err { 10953 + u8 code; 10954 + #define NVM_DEFRAG_CMD_ERR_CODE_UNKNOWN 0x0UL 10955 + #define NVM_DEFRAG_CMD_ERR_CODE_FAIL 0x1UL 10956 + #define NVM_DEFRAG_CMD_ERR_CODE_CHECK_FAIL 0x2UL 10957 + #define NVM_DEFRAG_CMD_ERR_CODE_LAST NVM_DEFRAG_CMD_ERR_CODE_CHECK_FAIL 11029 10958 u8 unused_0[7]; 11030 10959 }; 11031 10960

+2

include/uapi/linux/ethtool.h

··· 603 603 ETHTOOL_LINK_EXT_STATE_POWER_BUDGET_EXCEEDED, 604 604 ETHTOOL_LINK_EXT_STATE_OVERHEAT, 605 605 ETHTOOL_LINK_EXT_STATE_MODULE, 606 + ETHTOOL_LINK_EXT_STATE_OTP_SPEED_VIOLATION, 607 + ETHTOOL_LINK_EXT_STATE_BMC_REQUEST_DOWN, 606 608 }; 607 609 608 610 /* More information in addition to ETHTOOL_LINK_EXT_STATE_AUTONEG. */

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