tjh.dev / kernel
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Merge tag 'drm-fixes-2026-04-03' of https://gitlab.freedesktop.org/drm/kernel

Pull drm fixes from Dave Airlie:
"Hopefully no Easter eggs in this bunch of fixes. Usual stuff across
the amd/intel with some misc bits. Thanks to Thorsten and Alex for
making sure a regression fix that was hanging around in process land
finally made it in, that is probably the biggest change in here.

core:
- revert unplug/framebuffer fix as it caused problems
- compat ioctl speculation fix

bridge:
- refcounting fix

sysfb:
- error handling fix

amdgpu:
- fix renoir audio regression
- UserQ fixes
- PASID handling fix
- S4 fix for smu11 chips
- Misc small fixes

amdkfd:
- Non-4K page fixes

i915:
- Fix for #12045: Huawei Matebook E (DRR-WXX): Persistent Black
Screen on Boot with i915 and Gen11: Modesetting and Backlight
Control Malfunction
- Fix for #15826: i915: Raptor Lake-P [UHD Graphics] display
flicker/corruption on eDP panel
- Use crtc_state->enhanced_framing properly on ivb/hsw CPU eDP

xe:
- uapi: Accept canonical GPU addresses in xe_vm_madvise_ioctl
- Disallow writes to read-only VMAs
- PXP fixes
- Disable garbage collector work item on SVM close
- void memory allocations in xe_device_declare_wedged

qaic:
- hang fix

ast:
- initialisation fix"

* tag 'drm-fixes-2026-04-03' of https://gitlab.freedesktop.org/drm/kernel: (28 commits)
drm/amd/display: Wire up dcn10_dio_construct() for all pre-DCN401 generations
drm/ioc32: stop speculation on the drm_compat_ioctl path
drm/sysfb: Fix efidrm error handling and memory type mismatch
drm/i915/dp: Use crtc_state->enhanced_framing properly on ivb/hsw CPU eDP
drm/i915/cdclk: Do the full CDCLK dance for min_voltage_level changes
drm/amdkfd: Fix queue preemption/eviction failures by aligning control stack size to GPU page size
drm/amdgpu: Fix wait after reset sequence in S4
drm/amd/display: Fix NULL pointer dereference in dcn401_init_hw()
drm/amdgpu: Change AMDGPU_VA_RESERVED_TRAP_SIZE to 64KB
drm/amdgpu/userq: fix memory leak in MQD creation error paths
drm/amd: Fix MQD and control stack alignment for non-4K
drm/amdkfd: Align expected_queue_size to PAGE_SIZE
drm/amdgpu: fix the idr allocation flags
drm/amdgpu: validate doorbell_offset in user queue creation
drm/amdgpu/pm: drop SMU driver if version not matched messages
drm/xe: Avoid memory allocations in xe_device_declare_wedged()
drm/xe: Disable garbage collector work item on SVM close
drm/xe/pxp: Don't allow PXP on older PTL GSC FWs
drm/xe/pxp: Clear restart flag in pxp_start after jumping back
drm/xe/pxp: Remove incorrect handling of impossible state during suspend
...

Linus Torvalds 60d9212c d8a9a4b1

+1013 -108
+45 -2
drivers/accel/qaic/qaic_control.c
··· 914 914 */ 915 915 return -ENODEV; 916 916 917 - if (status) { 917 + if (usr && status) { 918 918 /* 919 919 * Releasing resources failed on the device side, which puts 920 920 * us in a bind since they may still be in use, so enable the ··· 1109 1109 mutex_lock(&qdev->cntl_mutex); 1110 1110 if (!list_empty(&elem.list)) 1111 1111 list_del(&elem.list); 1112 + /* resp_worker() processed the response but the wait was interrupted */ 1113 + else if (ret == -ERESTARTSYS) 1114 + ret = 0; 1112 1115 if (!ret && !elem.buf) 1113 1116 ret = -ETIMEDOUT; 1114 1117 else if (ret > 0 && !elem.buf) ··· 1422 1419 } 1423 1420 mutex_unlock(&qdev->cntl_mutex); 1424 1421 1425 - if (!found) 1422 + if (!found) { 1423 + /* 1424 + * The user might have gone away at this point without waiting 1425 + * for QAIC_TRANS_DEACTIVATE_FROM_DEV transaction coming from 1426 + * the device. If this is not handled correctly, the host will 1427 + * not know that the DBC[n] has been freed on the device. 1428 + * Due to this failure in synchronization between the device and 1429 + * the host, if another user requests to activate a network, and 1430 + * the device assigns DBC[n] again, save_dbc_buf() will hang, 1431 + * waiting for dbc[n]->in_use to be set to false, which will not 1432 + * happen unless the qaic_dev_reset_clean_local_state() gets 1433 + * called by resetting the device (or re-inserting the module). 1434 + * 1435 + * As a solution, we look for QAIC_TRANS_DEACTIVATE_FROM_DEV 1436 + * transactions in the message before disposing of it, then 1437 + * handle releasing the DBC resources. 1438 + * 1439 + * Since the user has gone away, if the device could not 1440 + * deactivate the network (status != 0), there is no way to 1441 + * enable and reassign the DBC to the user. We can put trust in 1442 + * the device that it will release all the active DBCs in 1443 + * response to the QAIC_TRANS_TERMINATE_TO_DEV transaction, 1444 + * otherwise, the user can issue an soc_reset to the device. 1445 + */ 1446 + u32 msg_count = le32_to_cpu(msg->hdr.count); 1447 + u32 msg_len = le32_to_cpu(msg->hdr.len); 1448 + u32 len = 0; 1449 + int j; 1450 + 1451 + for (j = 0; j < msg_count && len < msg_len; ++j) { 1452 + struct wire_trans_hdr *trans_hdr; 1453 + 1454 + trans_hdr = (struct wire_trans_hdr *)(msg->data + len); 1455 + if (le32_to_cpu(trans_hdr->type) == QAIC_TRANS_DEACTIVATE_FROM_DEV) { 1456 + if (decode_deactivate(qdev, trans_hdr, &len, NULL)) 1457 + len += le32_to_cpu(trans_hdr->len); 1458 + } else { 1459 + len += le32_to_cpu(trans_hdr->len); 1460 + } 1461 + } 1426 1462 /* request must have timed out, drop packet */ 1427 1463 kfree(msg); 1464 + } 1428 1465 1429 1466 kfree(resp); 1430 1467 }
+6 -2
drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c
··· 2703 2703 if (r) 2704 2704 return r; 2705 2705 2706 - if (amdgpu_acpi_should_gpu_reset(adev)) 2707 - return amdgpu_asic_reset(adev); 2706 + if (amdgpu_acpi_should_gpu_reset(adev)) { 2707 + amdgpu_device_lock_reset_domain(adev->reset_domain); 2708 + r = amdgpu_asic_reset(adev); 2709 + amdgpu_device_unlock_reset_domain(adev->reset_domain); 2710 + return r; 2711 + } 2708 2712 return 0; 2709 2713 } 2710 2714
+44
drivers/gpu/drm/amd/amdgpu/amdgpu_gart.c
··· 404 404 } 405 405 406 406 /** 407 + * amdgpu_gart_map_gfx9_mqd - map mqd and ctrl_stack dma_addresses into GART entries 408 + * 409 + * @adev: amdgpu_device pointer 410 + * @offset: offset into the GPU's gart aperture 411 + * @pages: number of pages to bind 412 + * @dma_addr: DMA addresses of pages 413 + * @flags: page table entry flags 414 + * 415 + * Map the MQD and control stack addresses into GART entries with the correct 416 + * memory types on gfxv9. The MQD occupies the first 4KB and is followed by 417 + * the control stack. The MQD uses UC (uncached) memory, while the control stack 418 + * uses NC (non-coherent) memory. 419 + */ 420 + void amdgpu_gart_map_gfx9_mqd(struct amdgpu_device *adev, uint64_t offset, 421 + int pages, dma_addr_t *dma_addr, uint64_t flags) 422 + { 423 + uint64_t page_base; 424 + unsigned int i, j, t; 425 + int idx; 426 + uint64_t ctrl_flags = AMDGPU_PTE_MTYPE_VG10(flags, AMDGPU_MTYPE_NC); 427 + void *dst; 428 + 429 + if (!adev->gart.ptr) 430 + return; 431 + 432 + if (!drm_dev_enter(adev_to_drm(adev), &idx)) 433 + return; 434 + 435 + t = offset / AMDGPU_GPU_PAGE_SIZE; 436 + dst = adev->gart.ptr; 437 + for (i = 0; i < pages; i++) { 438 + page_base = dma_addr[i]; 439 + for (j = 0; j < AMDGPU_GPU_PAGES_IN_CPU_PAGE; j++, t++) { 440 + if ((i == 0) && (j == 0)) 441 + amdgpu_gmc_set_pte_pde(adev, dst, t, page_base, flags); 442 + else 443 + amdgpu_gmc_set_pte_pde(adev, dst, t, page_base, ctrl_flags); 444 + page_base += AMDGPU_GPU_PAGE_SIZE; 445 + } 446 + } 447 + drm_dev_exit(idx); 448 + } 449 + 450 + /** 407 451 * amdgpu_gart_bind - bind pages into the gart page table 408 452 * 409 453 * @adev: amdgpu_device pointer
+2
drivers/gpu/drm/amd/amdgpu/amdgpu_gart.h
··· 62 62 void amdgpu_gart_map(struct amdgpu_device *adev, uint64_t offset, 63 63 int pages, dma_addr_t *dma_addr, uint64_t flags, 64 64 void *dst); 65 + void amdgpu_gart_map_gfx9_mqd(struct amdgpu_device *adev, uint64_t offset, 66 + int pages, dma_addr_t *dma_addr, uint64_t flags); 65 67 void amdgpu_gart_bind(struct amdgpu_device *adev, uint64_t offset, 66 68 int pages, dma_addr_t *dma_addr, uint64_t flags); 67 69 void amdgpu_gart_map_vram_range(struct amdgpu_device *adev, uint64_t pa,
+4 -1
drivers/gpu/drm/amd/amdgpu/amdgpu_ids.c
··· 68 68 return -EINVAL; 69 69 70 70 spin_lock(&amdgpu_pasid_idr_lock); 71 + /* TODO: Need to replace the idr with an xarry, and then 72 + * handle the internal locking with ATOMIC safe paths. 73 + */ 71 74 pasid = idr_alloc_cyclic(&amdgpu_pasid_idr, NULL, 1, 72 - 1U << bits, GFP_KERNEL); 75 + 1U << bits, GFP_ATOMIC); 73 76 spin_unlock(&amdgpu_pasid_idr_lock); 74 77 75 78 if (pasid >= 0)
+3 -13
drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.c
··· 853 853 int num_xcc = max(1U, adev->gfx.num_xcc_per_xcp); 854 854 uint64_t page_idx, pages_per_xcc; 855 855 int i; 856 - uint64_t ctrl_flags = AMDGPU_PTE_MTYPE_VG10(flags, AMDGPU_MTYPE_NC); 857 856 858 857 pages_per_xcc = total_pages; 859 858 do_div(pages_per_xcc, num_xcc); 860 859 861 860 for (i = 0, page_idx = 0; i < num_xcc; i++, page_idx += pages_per_xcc) { 862 - /* MQD page: use default flags */ 863 - amdgpu_gart_bind(adev, 861 + amdgpu_gart_map_gfx9_mqd(adev, 864 862 gtt->offset + (page_idx << PAGE_SHIFT), 865 - 1, &gtt->ttm.dma_address[page_idx], flags); 866 - /* 867 - * Ctrl pages - modify the memory type to NC (ctrl_flags) from 868 - * the second page of the BO onward. 869 - */ 870 - amdgpu_gart_bind(adev, 871 - gtt->offset + ((page_idx + 1) << PAGE_SHIFT), 872 - pages_per_xcc - 1, 873 - &gtt->ttm.dma_address[page_idx + 1], 874 - ctrl_flags); 863 + pages_per_xcc, &gtt->ttm.dma_address[page_idx], 864 + flags); 875 865 } 876 866 } 877 867
+7
drivers/gpu/drm/amd/amdgpu/amdgpu_userq.c
··· 600 600 goto unpin_bo; 601 601 } 602 602 603 + /* Validate doorbell_offset is within the doorbell BO */ 604 + if ((u64)db_info->doorbell_offset * db_size + db_size > 605 + amdgpu_bo_size(db_obj->obj)) { 606 + r = -EINVAL; 607 + goto unpin_bo; 608 + } 609 + 603 610 index = amdgpu_doorbell_index_on_bar(uq_mgr->adev, db_obj->obj, 604 611 db_info->doorbell_offset, db_size); 605 612 drm_dbg_driver(adev_to_drm(uq_mgr->adev),
+1 -1
drivers/gpu/drm/amd/amdgpu/amdgpu_vm.h
··· 173 173 #define AMDGPU_VA_RESERVED_SEQ64_SIZE (2ULL << 20) 174 174 #define AMDGPU_VA_RESERVED_SEQ64_START(adev) (AMDGPU_VA_RESERVED_CSA_START(adev) \ 175 175 - AMDGPU_VA_RESERVED_SEQ64_SIZE) 176 - #define AMDGPU_VA_RESERVED_TRAP_SIZE (2ULL << 12) 176 + #define AMDGPU_VA_RESERVED_TRAP_SIZE (1ULL << 16) 177 177 #define AMDGPU_VA_RESERVED_TRAP_START(adev) (AMDGPU_VA_RESERVED_SEQ64_START(adev) \ 178 178 - AMDGPU_VA_RESERVED_TRAP_SIZE) 179 179 #define AMDGPU_VA_RESERVED_BOTTOM (1ULL << 16)
+12 -4
drivers/gpu/drm/amd/amdgpu/mes_userqueue.c
··· 324 324 325 325 r = amdgpu_userq_input_va_validate(adev, queue, compute_mqd->eop_va, 326 326 2048); 327 - if (r) 327 + if (r) { 328 + kfree(compute_mqd); 328 329 goto free_mqd; 330 + } 329 331 330 332 userq_props->eop_gpu_addr = compute_mqd->eop_va; 331 333 userq_props->hqd_pipe_priority = AMDGPU_GFX_PIPE_PRIO_NORMAL; ··· 367 365 368 366 r = amdgpu_userq_input_va_validate(adev, queue, mqd_gfx_v11->shadow_va, 369 367 shadow_info.shadow_size); 370 - if (r) 368 + if (r) { 369 + kfree(mqd_gfx_v11); 371 370 goto free_mqd; 371 + } 372 372 r = amdgpu_userq_input_va_validate(adev, queue, mqd_gfx_v11->csa_va, 373 373 shadow_info.csa_size); 374 - if (r) 374 + if (r) { 375 + kfree(mqd_gfx_v11); 375 376 goto free_mqd; 377 + } 376 378 377 379 kfree(mqd_gfx_v11); 378 380 } else if (queue->queue_type == AMDGPU_HW_IP_DMA) { ··· 396 390 } 397 391 r = amdgpu_userq_input_va_validate(adev, queue, mqd_sdma_v11->csa_va, 398 392 32); 399 - if (r) 393 + if (r) { 394 + kfree(mqd_sdma_v11); 400 395 goto free_mqd; 396 + } 401 397 402 398 userq_props->csa_addr = mqd_sdma_v11->csa_va; 403 399 kfree(mqd_sdma_v11);
+2 -1
drivers/gpu/drm/amd/amdgpu/psp_v11_0.c
··· 170 170 int retry_loop; 171 171 172 172 /* For a reset done at the end of S3, only wait for TOS to be unloaded */ 173 - if (adev->in_s3 && !(adev->flags & AMD_IS_APU) && amdgpu_in_reset(adev)) 173 + if ((adev->in_s4 || adev->in_s3) && !(adev->flags & AMD_IS_APU) && 174 + amdgpu_in_reset(adev)) 174 175 return psp_v11_wait_for_tos_unload(psp); 175 176 176 177 for (retry_loop = 0; retry_loop < 20; retry_loop++) {
+15 -8
drivers/gpu/drm/amd/amdkfd/kfd_mqd_manager_v9.c
··· 42 42 struct queue_properties *q) 43 43 { 44 44 if (mm->dev->kfd->cwsr_enabled && 45 - q->type == KFD_QUEUE_TYPE_COMPUTE) 46 - return ALIGN(q->ctl_stack_size, PAGE_SIZE) + 47 - ALIGN(sizeof(struct v9_mqd), PAGE_SIZE); 45 + q->type == KFD_QUEUE_TYPE_COMPUTE) { 46 + 47 + /* On gfxv9, the MQD resides in the first 4K page, 48 + * followed by the control stack. Align both to 49 + * AMDGPU_GPU_PAGE_SIZE to maintain the required 4K boundary. 50 + */ 51 + 52 + return ALIGN(ALIGN(q->ctl_stack_size, AMDGPU_GPU_PAGE_SIZE) + 53 + ALIGN(sizeof(struct v9_mqd), AMDGPU_GPU_PAGE_SIZE), PAGE_SIZE); 54 + } 48 55 49 56 return mm->mqd_size; 50 57 } ··· 158 151 if (!mqd_mem_obj) 159 152 return NULL; 160 153 retval = amdgpu_amdkfd_alloc_kernel_mem(node->adev, 161 - (ALIGN(q->ctl_stack_size, PAGE_SIZE) + 162 - ALIGN(sizeof(struct v9_mqd), PAGE_SIZE)) * 154 + (ALIGN(ALIGN(q->ctl_stack_size, AMDGPU_GPU_PAGE_SIZE) + 155 + ALIGN(sizeof(struct v9_mqd), AMDGPU_GPU_PAGE_SIZE), PAGE_SIZE)) * 163 156 NUM_XCC(node->xcc_mask), 164 157 mqd_on_vram(node->adev) ? AMDGPU_GEM_DOMAIN_VRAM : 165 158 AMDGPU_GEM_DOMAIN_GTT, ··· 367 360 struct kfd_context_save_area_header header; 368 361 369 362 /* Control stack is located one page after MQD. */ 370 - void *mqd_ctl_stack = (void *)((uintptr_t)mqd + PAGE_SIZE); 363 + void *mqd_ctl_stack = (void *)((uintptr_t)mqd + AMDGPU_GPU_PAGE_SIZE); 371 364 372 365 m = get_mqd(mqd); 373 366 ··· 404 397 { 405 398 struct v9_mqd *m; 406 399 /* Control stack is located one page after MQD. */ 407 - void *ctl_stack = (void *)((uintptr_t)mqd + PAGE_SIZE); 400 + void *ctl_stack = (void *)((uintptr_t)mqd + AMDGPU_GPU_PAGE_SIZE); 408 401 409 402 m = get_mqd(mqd); 410 403 ··· 450 443 *gart_addr = addr; 451 444 452 445 /* Control stack is located one page after MQD. */ 453 - ctl_stack = (void *)((uintptr_t)*mqd + PAGE_SIZE); 446 + ctl_stack = (void *)((uintptr_t)*mqd + AMDGPU_GPU_PAGE_SIZE); 454 447 memcpy(ctl_stack, ctl_stack_src, ctl_stack_size); 455 448 456 449 m->cp_hqd_pq_doorbell_control =
+2 -2
drivers/gpu/drm/amd/amdkfd/kfd_priv.h
··· 102 102 * The first chunk is the TBA used for the CWSR ISA code. The second 103 103 * chunk is used as TMA for user-mode trap handler setup in daisy-chain mode. 104 104 */ 105 - #define KFD_CWSR_TBA_TMA_SIZE (PAGE_SIZE * 2) 106 - #define KFD_CWSR_TMA_OFFSET (PAGE_SIZE + 2048) 105 + #define KFD_CWSR_TBA_TMA_SIZE (AMDGPU_GPU_PAGE_SIZE * 2) 106 + #define KFD_CWSR_TMA_OFFSET (AMDGPU_GPU_PAGE_SIZE + 2048) 107 107 108 108 #define KFD_MAX_NUM_OF_QUEUES_PER_DEVICE \ 109 109 (KFD_MAX_NUM_OF_PROCESSES * \
+6 -5
drivers/gpu/drm/amd/amdkfd/kfd_queue.c
··· 249 249 topo_dev->node_props.gfx_target_version < 90000) 250 250 /* metadata_queue_size not supported on GFX7/GFX8 */ 251 251 expected_queue_size = 252 - properties->queue_size / 2; 252 + PAGE_ALIGN(properties->queue_size / 2); 253 253 else 254 254 expected_queue_size = 255 - properties->queue_size + properties->metadata_queue_size; 255 + PAGE_ALIGN(properties->queue_size + properties->metadata_queue_size); 256 256 257 257 vm = drm_priv_to_vm(pdd->drm_priv); 258 258 err = amdgpu_bo_reserve(vm->root.bo, false); ··· 492 492 cu_num = props->simd_count / props->simd_per_cu / NUM_XCC(dev->gpu->xcc_mask); 493 493 wave_num = get_num_waves(props, gfxv, cu_num); 494 494 495 - wg_data_size = ALIGN(cu_num * WG_CONTEXT_DATA_SIZE_PER_CU(gfxv, props), PAGE_SIZE); 495 + wg_data_size = ALIGN(cu_num * WG_CONTEXT_DATA_SIZE_PER_CU(gfxv, props), 496 + AMDGPU_GPU_PAGE_SIZE); 496 497 ctl_stack_size = wave_num * CNTL_STACK_BYTES_PER_WAVE(gfxv) + 8; 497 498 ctl_stack_size = ALIGN(SIZEOF_HSA_USER_CONTEXT_SAVE_AREA_HEADER + ctl_stack_size, 498 - PAGE_SIZE); 499 + AMDGPU_GPU_PAGE_SIZE); 499 500 500 501 if ((gfxv / 10000 * 10000) == 100000) { 501 502 /* HW design limits control stack size to 0x7000. ··· 508 507 509 508 props->ctl_stack_size = ctl_stack_size; 510 509 props->debug_memory_size = ALIGN(wave_num * DEBUGGER_BYTES_PER_WAVE, DEBUGGER_BYTES_ALIGN); 511 - props->cwsr_size = ctl_stack_size + wg_data_size; 510 + props->cwsr_size = ALIGN(ctl_stack_size + wg_data_size, PAGE_SIZE); 512 511 513 512 if (gfxv == 80002) /* GFX_VERSION_TONGA */ 514 513 props->eop_buffer_size = 0x8000;
+11 -6
drivers/gpu/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c
··· 147 147 int edp_num; 148 148 uint32_t backlight = MAX_BACKLIGHT_LEVEL; 149 149 uint32_t user_level = MAX_BACKLIGHT_LEVEL; 150 + bool dchub_ref_freq_changed; 150 151 int current_dchub_ref_freq = 0; 151 152 152 153 if (dc->clk_mgr && dc->clk_mgr->funcs && dc->clk_mgr->funcs->init_clocks) { ··· 361 360 dc->caps.dmub_caps.psr = dc->ctx->dmub_srv->dmub->feature_caps.psr; 362 361 dc->caps.dmub_caps.mclk_sw = dc->ctx->dmub_srv->dmub->feature_caps.fw_assisted_mclk_switch_ver > 0; 363 362 dc->caps.dmub_caps.fams_ver = dc->ctx->dmub_srv->dmub->feature_caps.fw_assisted_mclk_switch_ver; 363 + 364 + /* sw and fw FAMS versions must match for support */ 364 365 dc->debug.fams2_config.bits.enable &= 365 - dc->caps.dmub_caps.fams_ver == dc->debug.fams_version.ver; // sw & fw fams versions must match for support 366 - if ((!dc->debug.fams2_config.bits.enable && dc->res_pool->funcs->update_bw_bounding_box) 367 - || res_pool->ref_clocks.dchub_ref_clock_inKhz / 1000 != current_dchub_ref_freq) { 366 + dc->caps.dmub_caps.fams_ver == dc->debug.fams_version.ver; 367 + dchub_ref_freq_changed = 368 + res_pool->ref_clocks.dchub_ref_clock_inKhz / 1000 != current_dchub_ref_freq; 369 + if ((!dc->debug.fams2_config.bits.enable || dchub_ref_freq_changed) && 370 + dc->res_pool->funcs->update_bw_bounding_box && 371 + dc->clk_mgr && dc->clk_mgr->bw_params) { 368 372 /* update bounding box if FAMS2 disabled, or if dchub clk has changed */ 369 - if (dc->clk_mgr) 370 - dc->res_pool->funcs->update_bw_bounding_box(dc, 371 - dc->clk_mgr->bw_params); 373 + dc->res_pool->funcs->update_bw_bounding_box(dc, 374 + dc->clk_mgr->bw_params); 372 375 } 373 376 } 374 377 }
+41
drivers/gpu/drm/amd/display/dc/resource/dcn10/dcn10_resource.c
··· 71 71 #include "dce/dce_dmcu.h" 72 72 #include "dce/dce_aux.h" 73 73 #include "dce/dce_i2c.h" 74 + #include "dio/dcn10/dcn10_dio.h" 74 75 75 76 #ifndef mmDP0_DP_DPHY_INTERNAL_CTRL 76 77 #define mmDP0_DP_DPHY_INTERNAL_CTRL 0x210f ··· 444 443 static const struct dcn_hubbub_mask hubbub_mask = { 445 444 HUBBUB_MASK_SH_LIST_DCN10(_MASK) 446 445 }; 446 + 447 + static const struct dcn_dio_registers dio_regs = { 448 + DIO_REG_LIST_DCN10() 449 + }; 450 + 451 + #define DIO_MASK_SH_LIST(mask_sh)\ 452 + HWS_SF(, DIO_MEM_PWR_CTRL, I2C_LIGHT_SLEEP_FORCE, mask_sh) 453 + 454 + static const struct dcn_dio_shift dio_shift = { 455 + DIO_MASK_SH_LIST(__SHIFT) 456 + }; 457 + 458 + static const struct dcn_dio_mask dio_mask = { 459 + DIO_MASK_SH_LIST(_MASK) 460 + }; 461 + 462 + static struct dio *dcn10_dio_create(struct dc_context *ctx) 463 + { 464 + struct dcn10_dio *dio10 = kzalloc_obj(struct dcn10_dio); 465 + 466 + if (!dio10) 467 + return NULL; 468 + 469 + dcn10_dio_construct(dio10, ctx, &dio_regs, &dio_shift, &dio_mask); 470 + 471 + return &dio10->base; 472 + } 447 473 448 474 static int map_transmitter_id_to_phy_instance( 449 475 enum transmitter transmitter) ··· 944 916 945 917 kfree(pool->base.hubbub); 946 918 pool->base.hubbub = NULL; 919 + 920 + if (pool->base.dio != NULL) { 921 + kfree(TO_DCN10_DIO(pool->base.dio)); 922 + pool->base.dio = NULL; 923 + } 947 924 948 925 for (i = 0; i < pool->base.pipe_count; i++) { 949 926 if (pool->base.opps[i] != NULL) ··· 1683 1650 if (pool->base.hubbub == NULL) { 1684 1651 BREAK_TO_DEBUGGER(); 1685 1652 dm_error("DC: failed to create hubbub!\n"); 1653 + goto fail; 1654 + } 1655 + 1656 + /* DIO */ 1657 + pool->base.dio = dcn10_dio_create(ctx); 1658 + if (pool->base.dio == NULL) { 1659 + BREAK_TO_DEBUGGER(); 1660 + dm_error("DC: failed to create dio!\n"); 1686 1661 goto fail; 1687 1662 } 1688 1663
+42
drivers/gpu/drm/amd/display/dc/resource/dcn20/dcn20_resource.c
··· 82 82 #include "dce/dce_dmcu.h" 83 83 #include "dce/dce_aux.h" 84 84 #include "dce/dce_i2c.h" 85 + #include "dio/dcn10/dcn10_dio.h" 85 86 #include "vm_helper.h" 86 87 87 88 #include "link_enc_cfg.h" ··· 550 549 static const struct dcn_hubbub_mask hubbub_mask = { 551 550 HUBBUB_MASK_SH_LIST_DCN20(_MASK) 552 551 }; 552 + 553 + static const struct dcn_dio_registers dio_regs = { 554 + DIO_REG_LIST_DCN10() 555 + }; 556 + 557 + #define DIO_MASK_SH_LIST(mask_sh)\ 558 + HWS_SF(, DIO_MEM_PWR_CTRL, I2C_LIGHT_SLEEP_FORCE, mask_sh) 559 + 560 + static const struct dcn_dio_shift dio_shift = { 561 + DIO_MASK_SH_LIST(__SHIFT) 562 + }; 563 + 564 + static const struct dcn_dio_mask dio_mask = { 565 + DIO_MASK_SH_LIST(_MASK) 566 + }; 567 + 568 + static struct dio *dcn20_dio_create(struct dc_context *ctx) 569 + { 570 + struct dcn10_dio *dio10 = kzalloc_obj(struct dcn10_dio); 571 + 572 + if (!dio10) 573 + return NULL; 574 + 575 + dcn10_dio_construct(dio10, ctx, &dio_regs, &dio_shift, &dio_mask); 576 + 577 + return &dio10->base; 578 + } 553 579 554 580 #define vmid_regs(id)\ 555 581 [id] = {\ ··· 1132 1104 kfree(pool->base.hubbub); 1133 1105 pool->base.hubbub = NULL; 1134 1106 } 1107 + 1108 + if (pool->base.dio != NULL) { 1109 + kfree(TO_DCN10_DIO(pool->base.dio)); 1110 + pool->base.dio = NULL; 1111 + } 1112 + 1135 1113 for (i = 0; i < pool->base.pipe_count; i++) { 1136 1114 if (pool->base.dpps[i] != NULL) 1137 1115 dcn20_dpp_destroy(&pool->base.dpps[i]); ··· 2723 2689 if (pool->base.hubbub == NULL) { 2724 2690 BREAK_TO_DEBUGGER(); 2725 2691 dm_error("DC: failed to create hubbub!\n"); 2692 + goto create_fail; 2693 + } 2694 + 2695 + /* DIO */ 2696 + pool->base.dio = dcn20_dio_create(ctx); 2697 + if (pool->base.dio == NULL) { 2698 + BREAK_TO_DEBUGGER(); 2699 + dm_error("DC: failed to create dio!\n"); 2726 2700 goto create_fail; 2727 2701 } 2728 2702
+41
drivers/gpu/drm/amd/display/dc/resource/dcn201/dcn201_resource.c
··· 56 56 #include "dce/dce_aux.h" 57 57 #include "dce/dce_i2c.h" 58 58 #include "dcn10/dcn10_resource.h" 59 + #include "dio/dcn10/dcn10_dio.h" 59 60 60 61 #include "cyan_skillfish_ip_offset.h" 61 62 ··· 756 755 return &hubbub->base; 757 756 } 758 757 758 + static const struct dcn_dio_registers dio_regs = { 759 + DIO_REG_LIST_DCN10() 760 + }; 761 + 762 + #define DIO_MASK_SH_LIST(mask_sh)\ 763 + HWS_SF(, DIO_MEM_PWR_CTRL, I2C_LIGHT_SLEEP_FORCE, mask_sh) 764 + 765 + static const struct dcn_dio_shift dio_shift = { 766 + DIO_MASK_SH_LIST(__SHIFT) 767 + }; 768 + 769 + static const struct dcn_dio_mask dio_mask = { 770 + DIO_MASK_SH_LIST(_MASK) 771 + }; 772 + 773 + static struct dio *dcn201_dio_create(struct dc_context *ctx) 774 + { 775 + struct dcn10_dio *dio10 = kzalloc_obj(struct dcn10_dio); 776 + 777 + if (!dio10) 778 + return NULL; 779 + 780 + dcn10_dio_construct(dio10, ctx, &dio_regs, &dio_shift, &dio_mask); 781 + 782 + return &dio10->base; 783 + } 784 + 759 785 static struct timing_generator *dcn201_timing_generator_create( 760 786 struct dc_context *ctx, 761 787 uint32_t instance) ··· 956 928 if (pool->base.hubbub != NULL) { 957 929 kfree(pool->base.hubbub); 958 930 pool->base.hubbub = NULL; 931 + } 932 + 933 + if (pool->base.dio != NULL) { 934 + kfree(TO_DCN10_DIO(pool->base.dio)); 935 + pool->base.dio = NULL; 959 936 } 960 937 961 938 for (i = 0; i < pool->base.pipe_count; i++) { ··· 1306 1273 pool->base.hubbub = dcn201_hubbub_create(ctx); 1307 1274 if (pool->base.hubbub == NULL) { 1308 1275 dm_error("DC: failed to create hubbub!\n"); 1276 + goto create_fail; 1277 + } 1278 + 1279 + /* DIO */ 1280 + pool->base.dio = dcn201_dio_create(ctx); 1281 + if (pool->base.dio == NULL) { 1282 + BREAK_TO_DEBUGGER(); 1283 + dm_error("DC: failed to create dio!\n"); 1309 1284 goto create_fail; 1310 1285 } 1311 1286
+34
drivers/gpu/drm/amd/display/dc/resource/dcn21/dcn21_resource.c
··· 84 84 #include "dce/dce_dmcu.h" 85 85 #include "dce/dce_aux.h" 86 86 #include "dce/dce_i2c.h" 87 + #include "dio/dcn10/dcn10_dio.h" 87 88 #include "dcn21_resource.h" 88 89 #include "vm_helper.h" 89 90 #include "dcn20/dcn20_vmid.h" ··· 330 329 HUBBUB_MASK_SH_LIST_DCN21(_MASK) 331 330 }; 332 331 332 + static const struct dcn_dio_registers dio_regs = { 333 + DIO_REG_LIST_DCN10() 334 + }; 335 + 336 + static const struct dcn_dio_shift dio_shift = { 0 }; 337 + 338 + static const struct dcn_dio_mask dio_mask = { 0 }; 339 + 340 + static struct dio *dcn21_dio_create(struct dc_context *ctx) 341 + { 342 + struct dcn10_dio *dio10 = kzalloc_obj(struct dcn10_dio); 343 + 344 + if (!dio10) 345 + return NULL; 346 + 347 + dcn10_dio_construct(dio10, ctx, &dio_regs, &dio_shift, &dio_mask); 348 + 349 + return &dio10->base; 350 + } 333 351 334 352 #define vmid_regs(id)\ 335 353 [id] = {\ ··· 697 677 kfree(pool->base.hubbub); 698 678 pool->base.hubbub = NULL; 699 679 } 680 + 681 + if (pool->base.dio != NULL) { 682 + kfree(TO_DCN10_DIO(pool->base.dio)); 683 + pool->base.dio = NULL; 684 + } 685 + 700 686 for (i = 0; i < pool->base.pipe_count; i++) { 701 687 if (pool->base.dpps[i] != NULL) 702 688 dcn20_dpp_destroy(&pool->base.dpps[i]); ··· 1677 1651 if (pool->base.hubbub == NULL) { 1678 1652 BREAK_TO_DEBUGGER(); 1679 1653 dm_error("DC: failed to create hubbub!\n"); 1654 + goto create_fail; 1655 + } 1656 + 1657 + /* DIO */ 1658 + pool->base.dio = dcn21_dio_create(ctx); 1659 + if (pool->base.dio == NULL) { 1660 + BREAK_TO_DEBUGGER(); 1661 + dm_error("DC: failed to create dio!\n"); 1680 1662 goto create_fail; 1681 1663 } 1682 1664
+42
drivers/gpu/drm/amd/display/dc/resource/dcn30/dcn30_resource.c
··· 60 60 #include "dml/display_mode_vba.h" 61 61 #include "dcn30/dcn30_dccg.h" 62 62 #include "dcn10/dcn10_resource.h" 63 + #include "dio/dcn10/dcn10_dio.h" 63 64 #include "link_service.h" 64 65 #include "dce/dce_panel_cntl.h" 65 66 ··· 887 886 return &hubbub3->base; 888 887 } 889 888 889 + static const struct dcn_dio_registers dio_regs = { 890 + DIO_REG_LIST_DCN10() 891 + }; 892 + 893 + #define DIO_MASK_SH_LIST(mask_sh)\ 894 + HWS_SF(, DIO_MEM_PWR_CTRL, I2C_LIGHT_SLEEP_FORCE, mask_sh) 895 + 896 + static const struct dcn_dio_shift dio_shift = { 897 + DIO_MASK_SH_LIST(__SHIFT) 898 + }; 899 + 900 + static const struct dcn_dio_mask dio_mask = { 901 + DIO_MASK_SH_LIST(_MASK) 902 + }; 903 + 904 + static struct dio *dcn30_dio_create(struct dc_context *ctx) 905 + { 906 + struct dcn10_dio *dio10 = kzalloc_obj(struct dcn10_dio); 907 + 908 + if (!dio10) 909 + return NULL; 910 + 911 + dcn10_dio_construct(dio10, ctx, &dio_regs, &dio_shift, &dio_mask); 912 + 913 + return &dio10->base; 914 + } 915 + 890 916 static struct timing_generator *dcn30_timing_generator_create( 891 917 struct dc_context *ctx, 892 918 uint32_t instance) ··· 1123 1095 kfree(pool->base.hubbub); 1124 1096 pool->base.hubbub = NULL; 1125 1097 } 1098 + 1099 + if (pool->base.dio != NULL) { 1100 + kfree(TO_DCN10_DIO(pool->base.dio)); 1101 + pool->base.dio = NULL; 1102 + } 1103 + 1126 1104 for (i = 0; i < pool->base.pipe_count; i++) { 1127 1105 if (pool->base.dpps[i] != NULL) 1128 1106 dcn30_dpp_destroy(&pool->base.dpps[i]); ··· 2495 2461 if (pool->base.hubbub == NULL) { 2496 2462 BREAK_TO_DEBUGGER(); 2497 2463 dm_error("DC: failed to create hubbub!\n"); 2464 + goto create_fail; 2465 + } 2466 + 2467 + /* DIO */ 2468 + pool->base.dio = dcn30_dio_create(ctx); 2469 + if (pool->base.dio == NULL) { 2470 + BREAK_TO_DEBUGGER(); 2471 + dm_error("DC: failed to create dio!\n"); 2498 2472 goto create_fail; 2499 2473 } 2500 2474
+42
drivers/gpu/drm/amd/display/dc/resource/dcn301/dcn301_resource.c
··· 59 59 #include "dml/display_mode_vba.h" 60 60 #include "dcn301/dcn301_dccg.h" 61 61 #include "dcn10/dcn10_resource.h" 62 + #include "dio/dcn10/dcn10_dio.h" 62 63 #include "dcn30/dcn30_dio_stream_encoder.h" 63 64 #include "dcn301/dcn301_dio_link_encoder.h" 64 65 #include "dcn301/dcn301_panel_cntl.h" ··· 844 843 return &hubbub3->base; 845 844 } 846 845 846 + static const struct dcn_dio_registers dio_regs = { 847 + DIO_REG_LIST_DCN10() 848 + }; 849 + 850 + #define DIO_MASK_SH_LIST(mask_sh)\ 851 + HWS_SF(, DIO_MEM_PWR_CTRL, I2C_LIGHT_SLEEP_FORCE, mask_sh) 852 + 853 + static const struct dcn_dio_shift dio_shift = { 854 + DIO_MASK_SH_LIST(__SHIFT) 855 + }; 856 + 857 + static const struct dcn_dio_mask dio_mask = { 858 + DIO_MASK_SH_LIST(_MASK) 859 + }; 860 + 861 + static struct dio *dcn301_dio_create(struct dc_context *ctx) 862 + { 863 + struct dcn10_dio *dio10 = kzalloc_obj(struct dcn10_dio); 864 + 865 + if (!dio10) 866 + return NULL; 867 + 868 + dcn10_dio_construct(dio10, ctx, &dio_regs, &dio_shift, &dio_mask); 869 + 870 + return &dio10->base; 871 + } 872 + 847 873 static struct timing_generator *dcn301_timing_generator_create( 848 874 struct dc_context *ctx, uint32_t instance) 849 875 { ··· 1094 1066 kfree(pool->base.hubbub); 1095 1067 pool->base.hubbub = NULL; 1096 1068 } 1069 + 1070 + if (pool->base.dio != NULL) { 1071 + kfree(TO_DCN10_DIO(pool->base.dio)); 1072 + pool->base.dio = NULL; 1073 + } 1074 + 1097 1075 for (i = 0; i < pool->base.pipe_count; i++) { 1098 1076 if (pool->base.dpps[i] != NULL) 1099 1077 dcn301_dpp_destroy(&pool->base.dpps[i]); ··· 1613 1579 if (pool->base.hubbub == NULL) { 1614 1580 BREAK_TO_DEBUGGER(); 1615 1581 dm_error("DC: failed to create hubbub!\n"); 1582 + goto create_fail; 1583 + } 1584 + 1585 + /* DIO */ 1586 + pool->base.dio = dcn301_dio_create(ctx); 1587 + if (pool->base.dio == NULL) { 1588 + BREAK_TO_DEBUGGER(); 1589 + dm_error("DC: failed to create dio!\n"); 1616 1590 goto create_fail; 1617 1591 } 1618 1592
+41
drivers/gpu/drm/amd/display/dc/resource/dcn302/dcn302_resource.c
··· 46 46 #include "dml/dcn30/dcn30_fpu.h" 47 47 48 48 #include "dcn10/dcn10_resource.h" 49 + #include "dio/dcn10/dcn10_dio.h" 49 50 50 51 #include "link_service.h" 51 52 ··· 253 252 static const struct dcn20_vmid_mask vmid_masks = { 254 253 DCN20_VMID_MASK_SH_LIST(_MASK) 255 254 }; 255 + 256 + static const struct dcn_dio_registers dio_regs = { 257 + DIO_REG_LIST_DCN10() 258 + }; 259 + 260 + #define DIO_MASK_SH_LIST(mask_sh)\ 261 + HWS_SF(, DIO_MEM_PWR_CTRL, I2C_LIGHT_SLEEP_FORCE, mask_sh) 262 + 263 + static const struct dcn_dio_shift dio_shift = { 264 + DIO_MASK_SH_LIST(__SHIFT) 265 + }; 266 + 267 + static const struct dcn_dio_mask dio_mask = { 268 + DIO_MASK_SH_LIST(_MASK) 269 + }; 270 + 271 + static struct dio *dcn302_dio_create(struct dc_context *ctx) 272 + { 273 + struct dcn10_dio *dio10 = kzalloc_obj(struct dcn10_dio); 274 + 275 + if (!dio10) 276 + return NULL; 277 + 278 + dcn10_dio_construct(dio10, ctx, &dio_regs, &dio_shift, &dio_mask); 279 + 280 + return &dio10->base; 281 + } 256 282 257 283 static struct hubbub *dcn302_hubbub_create(struct dc_context *ctx) 258 284 { ··· 1050 1022 pool->hubbub = NULL; 1051 1023 } 1052 1024 1025 + if (pool->dio != NULL) { 1026 + kfree(TO_DCN10_DIO(pool->dio)); 1027 + pool->dio = NULL; 1028 + } 1029 + 1053 1030 for (i = 0; i < pool->pipe_count; i++) { 1054 1031 if (pool->dpps[i] != NULL) { 1055 1032 kfree(TO_DCN20_DPP(pool->dpps[i])); ··· 1402 1369 if (pool->hubbub == NULL) { 1403 1370 BREAK_TO_DEBUGGER(); 1404 1371 dm_error("DC: failed to create hubbub!\n"); 1372 + goto create_fail; 1373 + } 1374 + 1375 + /* DIO */ 1376 + pool->dio = dcn302_dio_create(ctx); 1377 + if (pool->dio == NULL) { 1378 + BREAK_TO_DEBUGGER(); 1379 + dm_error("DC: failed to create dio!\n"); 1405 1380 goto create_fail; 1406 1381 } 1407 1382
+41
drivers/gpu/drm/amd/display/dc/resource/dcn303/dcn303_resource.c
··· 46 46 #include "dml/dcn30/dcn30_fpu.h" 47 47 48 48 #include "dcn10/dcn10_resource.h" 49 + #include "dio/dcn10/dcn10_dio.h" 49 50 50 51 #include "link_service.h" 51 52 ··· 249 248 static const struct dcn20_vmid_mask vmid_masks = { 250 249 DCN20_VMID_MASK_SH_LIST(_MASK) 251 250 }; 251 + 252 + static const struct dcn_dio_registers dio_regs = { 253 + DIO_REG_LIST_DCN10() 254 + }; 255 + 256 + #define DIO_MASK_SH_LIST(mask_sh)\ 257 + HWS_SF(, DIO_MEM_PWR_CTRL, I2C_LIGHT_SLEEP_FORCE, mask_sh) 258 + 259 + static const struct dcn_dio_shift dio_shift = { 260 + DIO_MASK_SH_LIST(__SHIFT) 261 + }; 262 + 263 + static const struct dcn_dio_mask dio_mask = { 264 + DIO_MASK_SH_LIST(_MASK) 265 + }; 266 + 267 + static struct dio *dcn303_dio_create(struct dc_context *ctx) 268 + { 269 + struct dcn10_dio *dio10 = kzalloc_obj(struct dcn10_dio); 270 + 271 + if (!dio10) 272 + return NULL; 273 + 274 + dcn10_dio_construct(dio10, ctx, &dio_regs, &dio_shift, &dio_mask); 275 + 276 + return &dio10->base; 277 + } 252 278 253 279 static struct hubbub *dcn303_hubbub_create(struct dc_context *ctx) 254 280 { ··· 994 966 pool->hubbub = NULL; 995 967 } 996 968 969 + if (pool->dio != NULL) { 970 + kfree(TO_DCN10_DIO(pool->dio)); 971 + pool->dio = NULL; 972 + } 973 + 997 974 for (i = 0; i < pool->pipe_count; i++) { 998 975 if (pool->dpps[i] != NULL) { 999 976 kfree(TO_DCN20_DPP(pool->dpps[i])); ··· 1334 1301 if (pool->hubbub == NULL) { 1335 1302 BREAK_TO_DEBUGGER(); 1336 1303 dm_error("DC: failed to create hubbub!\n"); 1304 + goto create_fail; 1305 + } 1306 + 1307 + /* DIO */ 1308 + pool->dio = dcn303_dio_create(ctx); 1309 + if (pool->dio == NULL) { 1310 + BREAK_TO_DEBUGGER(); 1311 + dm_error("DC: failed to create dio!\n"); 1337 1312 goto create_fail; 1338 1313 } 1339 1314
+40
drivers/gpu/drm/amd/display/dc/resource/dcn31/dcn31_resource.c
··· 64 64 #include "dce/dce_audio.h" 65 65 #include "dce/dce_hwseq.h" 66 66 #include "clk_mgr.h" 67 + #include "dio/dcn10/dcn10_dio.h" 67 68 #include "dio/virtual/virtual_stream_encoder.h" 68 69 #include "dce110/dce110_resource.h" 69 70 #include "dml/display_mode_vba.h" ··· 811 810 DCN20_VMID_MASK_SH_LIST(_MASK) 812 811 }; 813 812 813 + static const struct dcn_dio_registers dio_regs = { 814 + DIO_REG_LIST_DCN10() 815 + }; 816 + 817 + #define DIO_MASK_SH_LIST(mask_sh)\ 818 + HWS_SF(, DIO_MEM_PWR_CTRL, I2C_LIGHT_SLEEP_FORCE, mask_sh) 819 + 820 + static const struct dcn_dio_shift dio_shift = { 821 + DIO_MASK_SH_LIST(__SHIFT) 822 + }; 823 + 824 + static const struct dcn_dio_mask dio_mask = { 825 + DIO_MASK_SH_LIST(_MASK) 826 + }; 827 + 814 828 static const struct resource_caps res_cap_dcn31 = { 815 829 .num_timing_generator = 4, 816 830 .num_opp = 4, ··· 1035 1019 num_rmu); 1036 1020 1037 1021 return &mpc30->base; 1022 + } 1023 + 1024 + static struct dio *dcn31_dio_create(struct dc_context *ctx) 1025 + { 1026 + struct dcn10_dio *dio10 = kzalloc_obj(struct dcn10_dio); 1027 + 1028 + if (!dio10) 1029 + return NULL; 1030 + 1031 + dcn10_dio_construct(dio10, ctx, &dio_regs, &dio_shift, &dio_mask); 1032 + 1033 + return &dio10->base; 1038 1034 } 1039 1035 1040 1036 static struct hubbub *dcn31_hubbub_create(struct dc_context *ctx) ··· 1423 1395 if (pool->base.hubbub != NULL) { 1424 1396 kfree(pool->base.hubbub); 1425 1397 pool->base.hubbub = NULL; 1398 + } 1399 + if (pool->base.dio != NULL) { 1400 + kfree(TO_DCN10_DIO(pool->base.dio)); 1401 + pool->base.dio = NULL; 1426 1402 } 1427 1403 for (i = 0; i < pool->base.pipe_count; i++) { 1428 1404 if (pool->base.dpps[i] != NULL) ··· 2092 2060 if (pool->base.hubbub == NULL) { 2093 2061 BREAK_TO_DEBUGGER(); 2094 2062 dm_error("DC: failed to create hubbub!\n"); 2063 + goto create_fail; 2064 + } 2065 + 2066 + /* DIO */ 2067 + pool->base.dio = dcn31_dio_create(ctx); 2068 + if (pool->base.dio == NULL) { 2069 + BREAK_TO_DEBUGGER(); 2070 + dm_error("DC: failed to create dio!\n"); 2095 2071 goto create_fail; 2096 2072 } 2097 2073
+40
drivers/gpu/drm/amd/display/dc/resource/dcn314/dcn314_resource.c
··· 66 66 #include "dce/dce_audio.h" 67 67 #include "dce/dce_hwseq.h" 68 68 #include "clk_mgr.h" 69 + #include "dio/dcn10/dcn10_dio.h" 69 70 #include "dio/virtual/virtual_stream_encoder.h" 70 71 #include "dce110/dce110_resource.h" 71 72 #include "dml/display_mode_vba.h" ··· 823 822 DCN20_VMID_MASK_SH_LIST(_MASK) 824 823 }; 825 824 825 + static const struct dcn_dio_registers dio_regs = { 826 + DIO_REG_LIST_DCN10() 827 + }; 828 + 829 + #define DIO_MASK_SH_LIST(mask_sh)\ 830 + HWS_SF(, DIO_MEM_PWR_CTRL, I2C_LIGHT_SLEEP_FORCE, mask_sh) 831 + 832 + static const struct dcn_dio_shift dio_shift = { 833 + DIO_MASK_SH_LIST(__SHIFT) 834 + }; 835 + 836 + static const struct dcn_dio_mask dio_mask = { 837 + DIO_MASK_SH_LIST(_MASK) 838 + }; 839 + 826 840 static const struct resource_caps res_cap_dcn314 = { 827 841 .num_timing_generator = 4, 828 842 .num_opp = 4, ··· 1093 1077 num_rmu); 1094 1078 1095 1079 return &mpc30->base; 1080 + } 1081 + 1082 + static struct dio *dcn314_dio_create(struct dc_context *ctx) 1083 + { 1084 + struct dcn10_dio *dio10 = kzalloc_obj(struct dcn10_dio); 1085 + 1086 + if (!dio10) 1087 + return NULL; 1088 + 1089 + dcn10_dio_construct(dio10, ctx, &dio_regs, &dio_shift, &dio_mask); 1090 + 1091 + return &dio10->base; 1096 1092 } 1097 1093 1098 1094 static struct hubbub *dcn31_hubbub_create(struct dc_context *ctx) ··· 1482 1454 if (pool->base.hubbub != NULL) { 1483 1455 kfree(pool->base.hubbub); 1484 1456 pool->base.hubbub = NULL; 1457 + } 1458 + if (pool->base.dio != NULL) { 1459 + kfree(TO_DCN10_DIO(pool->base.dio)); 1460 + pool->base.dio = NULL; 1485 1461 } 1486 1462 for (i = 0; i < pool->base.pipe_count; i++) { 1487 1463 if (pool->base.dpps[i] != NULL) ··· 2016 1984 if (pool->base.hubbub == NULL) { 2017 1985 BREAK_TO_DEBUGGER(); 2018 1986 dm_error("DC: failed to create hubbub!\n"); 1987 + goto create_fail; 1988 + } 1989 + 1990 + /* DIO */ 1991 + pool->base.dio = dcn314_dio_create(ctx); 1992 + if (pool->base.dio == NULL) { 1993 + BREAK_TO_DEBUGGER(); 1994 + dm_error("DC: failed to create dio!\n"); 2019 1995 goto create_fail; 2020 1996 } 2021 1997
+40
drivers/gpu/drm/amd/display/dc/resource/dcn315/dcn315_resource.c
··· 63 63 #include "dce/dce_audio.h" 64 64 #include "dce/dce_hwseq.h" 65 65 #include "clk_mgr.h" 66 + #include "dio/dcn10/dcn10_dio.h" 66 67 #include "dio/virtual/virtual_stream_encoder.h" 67 68 #include "dce110/dce110_resource.h" 68 69 #include "dml/display_mode_vba.h" ··· 810 809 DCN20_VMID_MASK_SH_LIST(_MASK) 811 810 }; 812 811 812 + static const struct dcn_dio_registers dio_regs = { 813 + DIO_REG_LIST_DCN10() 814 + }; 815 + 816 + #define DIO_MASK_SH_LIST(mask_sh)\ 817 + HWS_SF(, DIO_MEM_PWR_CTRL, I2C_LIGHT_SLEEP_FORCE, mask_sh) 818 + 819 + static const struct dcn_dio_shift dio_shift = { 820 + DIO_MASK_SH_LIST(__SHIFT) 821 + }; 822 + 823 + static const struct dcn_dio_mask dio_mask = { 824 + DIO_MASK_SH_LIST(_MASK) 825 + }; 826 + 813 827 static const struct resource_caps res_cap_dcn31 = { 814 828 .num_timing_generator = 4, 815 829 .num_opp = 4, ··· 1034 1018 num_rmu); 1035 1019 1036 1020 return &mpc30->base; 1021 + } 1022 + 1023 + static struct dio *dcn315_dio_create(struct dc_context *ctx) 1024 + { 1025 + struct dcn10_dio *dio10 = kzalloc_obj(struct dcn10_dio); 1026 + 1027 + if (!dio10) 1028 + return NULL; 1029 + 1030 + dcn10_dio_construct(dio10, ctx, &dio_regs, &dio_shift, &dio_mask); 1031 + 1032 + return &dio10->base; 1037 1033 } 1038 1034 1039 1035 static struct hubbub *dcn31_hubbub_create(struct dc_context *ctx) ··· 1424 1396 if (pool->base.hubbub != NULL) { 1425 1397 kfree(pool->base.hubbub); 1426 1398 pool->base.hubbub = NULL; 1399 + } 1400 + if (pool->base.dio != NULL) { 1401 + kfree(TO_DCN10_DIO(pool->base.dio)); 1402 + pool->base.dio = NULL; 1427 1403 } 1428 1404 for (i = 0; i < pool->base.pipe_count; i++) { 1429 1405 if (pool->base.dpps[i] != NULL) ··· 2041 2009 if (pool->base.hubbub == NULL) { 2042 2010 BREAK_TO_DEBUGGER(); 2043 2011 dm_error("DC: failed to create hubbub!\n"); 2012 + goto create_fail; 2013 + } 2014 + 2015 + /* DIO */ 2016 + pool->base.dio = dcn315_dio_create(ctx); 2017 + if (pool->base.dio == NULL) { 2018 + BREAK_TO_DEBUGGER(); 2019 + dm_error("DC: failed to create dio!\n"); 2044 2020 goto create_fail; 2045 2021 } 2046 2022
+40
drivers/gpu/drm/amd/display/dc/resource/dcn316/dcn316_resource.c
··· 63 63 #include "dce/dce_audio.h" 64 64 #include "dce/dce_hwseq.h" 65 65 #include "clk_mgr.h" 66 + #include "dio/dcn10/dcn10_dio.h" 66 67 #include "dio/virtual/virtual_stream_encoder.h" 67 68 #include "dce110/dce110_resource.h" 68 69 #include "dml/display_mode_vba.h" ··· 805 804 DCN20_VMID_MASK_SH_LIST(_MASK) 806 805 }; 807 806 807 + static const struct dcn_dio_registers dio_regs = { 808 + DIO_REG_LIST_DCN10() 809 + }; 810 + 811 + #define DIO_MASK_SH_LIST(mask_sh)\ 812 + HWS_SF(, DIO_MEM_PWR_CTRL, I2C_LIGHT_SLEEP_FORCE, mask_sh) 813 + 814 + static const struct dcn_dio_shift dio_shift = { 815 + DIO_MASK_SH_LIST(__SHIFT) 816 + }; 817 + 818 + static const struct dcn_dio_mask dio_mask = { 819 + DIO_MASK_SH_LIST(_MASK) 820 + }; 821 + 808 822 static const struct resource_caps res_cap_dcn31 = { 809 823 .num_timing_generator = 4, 810 824 .num_opp = 4, ··· 1027 1011 num_rmu); 1028 1012 1029 1013 return &mpc30->base; 1014 + } 1015 + 1016 + static struct dio *dcn316_dio_create(struct dc_context *ctx) 1017 + { 1018 + struct dcn10_dio *dio10 = kzalloc_obj(struct dcn10_dio); 1019 + 1020 + if (!dio10) 1021 + return NULL; 1022 + 1023 + dcn10_dio_construct(dio10, ctx, &dio_regs, &dio_shift, &dio_mask); 1024 + 1025 + return &dio10->base; 1030 1026 } 1031 1027 1032 1028 static struct hubbub *dcn31_hubbub_create(struct dc_context *ctx) ··· 1419 1391 if (pool->base.hubbub != NULL) { 1420 1392 kfree(pool->base.hubbub); 1421 1393 pool->base.hubbub = NULL; 1394 + } 1395 + if (pool->base.dio != NULL) { 1396 + kfree(TO_DCN10_DIO(pool->base.dio)); 1397 + pool->base.dio = NULL; 1422 1398 } 1423 1399 for (i = 0; i < pool->base.pipe_count; i++) { 1424 1400 if (pool->base.dpps[i] != NULL) ··· 1916 1884 if (pool->base.hubbub == NULL) { 1917 1885 BREAK_TO_DEBUGGER(); 1918 1886 dm_error("DC: failed to create hubbub!\n"); 1887 + goto create_fail; 1888 + } 1889 + 1890 + /* DIO */ 1891 + pool->base.dio = dcn316_dio_create(ctx); 1892 + if (pool->base.dio == NULL) { 1893 + BREAK_TO_DEBUGGER(); 1894 + dm_error("DC: failed to create dio!\n"); 1919 1895 goto create_fail; 1920 1896 } 1921 1897
+43
drivers/gpu/drm/amd/display/dc/resource/dcn32/dcn32_resource.c
··· 66 66 #include "dce/dce_hwseq.h" 67 67 #include "clk_mgr.h" 68 68 #include "dio/virtual/virtual_stream_encoder.h" 69 + #include "dio/dcn10/dcn10_dio.h" 69 70 #include "dml/display_mode_vba.h" 70 71 #include "dcn32/dcn32_dccg.h" 71 72 #include "dcn10/dcn10_resource.h" ··· 644 643 DCN20_VMID_MASK_SH_LIST(_MASK) 645 644 }; 646 645 646 + static struct dcn_dio_registers dio_regs; 647 + 648 + #define DIO_MASK_SH_LIST(mask_sh)\ 649 + HWS_SF(, DIO_MEM_PWR_CTRL, I2C_LIGHT_SLEEP_FORCE, mask_sh) 650 + 651 + static const struct dcn_dio_shift dio_shift = { 652 + DIO_MASK_SH_LIST(__SHIFT) 653 + }; 654 + 655 + static const struct dcn_dio_mask dio_mask = { 656 + DIO_MASK_SH_LIST(_MASK) 657 + }; 658 + 647 659 static const struct resource_caps res_cap_dcn32 = { 648 660 .num_timing_generator = 4, 649 661 .num_opp = 4, ··· 845 831 kfree(clk_src); 846 832 BREAK_TO_DEBUGGER(); 847 833 return NULL; 834 + } 835 + 836 + static struct dio *dcn32_dio_create(struct dc_context *ctx) 837 + { 838 + struct dcn10_dio *dio10 = kzalloc_obj(struct dcn10_dio); 839 + 840 + if (!dio10) 841 + return NULL; 842 + 843 + #undef REG_STRUCT 844 + #define REG_STRUCT dio_regs 845 + DIO_REG_LIST_DCN10(); 846 + 847 + dcn10_dio_construct(dio10, ctx, &dio_regs, &dio_shift, &dio_mask); 848 + 849 + return &dio10->base; 848 850 } 849 851 850 852 static struct hubbub *dcn32_hubbub_create(struct dc_context *ctx) ··· 1523 1493 1524 1494 if (pool->base.dccg != NULL) 1525 1495 dcn_dccg_destroy(&pool->base.dccg); 1496 + 1497 + if (pool->base.dio != NULL) { 1498 + kfree(TO_DCN10_DIO(pool->base.dio)); 1499 + pool->base.dio = NULL; 1500 + } 1526 1501 1527 1502 if (pool->base.oem_device != NULL) { 1528 1503 struct dc *dc = pool->base.oem_device->ctx->dc; ··· 2405 2370 if (pool->base.hubbub == NULL) { 2406 2371 BREAK_TO_DEBUGGER(); 2407 2372 dm_error("DC: failed to create hubbub!\n"); 2373 + goto create_fail; 2374 + } 2375 + 2376 + /* DIO */ 2377 + pool->base.dio = dcn32_dio_create(ctx); 2378 + if (pool->base.dio == NULL) { 2379 + BREAK_TO_DEBUGGER(); 2380 + dm_error("DC: failed to create dio!\n"); 2408 2381 goto create_fail; 2409 2382 } 2410 2383
+43
drivers/gpu/drm/amd/display/dc/resource/dcn321/dcn321_resource.c
··· 69 69 #include "dce/dce_hwseq.h" 70 70 #include "clk_mgr.h" 71 71 #include "dio/virtual/virtual_stream_encoder.h" 72 + #include "dio/dcn10/dcn10_dio.h" 72 73 #include "dml/display_mode_vba.h" 73 74 #include "dcn32/dcn32_dccg.h" 74 75 #include "dcn10/dcn10_resource.h" ··· 640 639 DCN20_VMID_MASK_SH_LIST(_MASK) 641 640 }; 642 641 642 + static struct dcn_dio_registers dio_regs; 643 + 644 + #define DIO_MASK_SH_LIST(mask_sh)\ 645 + HWS_SF(, DIO_MEM_PWR_CTRL, I2C_LIGHT_SLEEP_FORCE, mask_sh) 646 + 647 + static const struct dcn_dio_shift dio_shift = { 648 + DIO_MASK_SH_LIST(__SHIFT) 649 + }; 650 + 651 + static const struct dcn_dio_mask dio_mask = { 652 + DIO_MASK_SH_LIST(_MASK) 653 + }; 654 + 643 655 static const struct resource_caps res_cap_dcn321 = { 644 656 .num_timing_generator = 4, 645 657 .num_opp = 4, ··· 839 825 kfree(clk_src); 840 826 BREAK_TO_DEBUGGER(); 841 827 return NULL; 828 + } 829 + 830 + static struct dio *dcn321_dio_create(struct dc_context *ctx) 831 + { 832 + struct dcn10_dio *dio10 = kzalloc_obj(struct dcn10_dio); 833 + 834 + if (!dio10) 835 + return NULL; 836 + 837 + #undef REG_STRUCT 838 + #define REG_STRUCT dio_regs 839 + DIO_REG_LIST_DCN10(); 840 + 841 + dcn10_dio_construct(dio10, ctx, &dio_regs, &dio_shift, &dio_mask); 842 + 843 + return &dio10->base; 842 844 } 843 845 844 846 static struct hubbub *dcn321_hubbub_create(struct dc_context *ctx) ··· 1504 1474 if (pool->base.dccg != NULL) 1505 1475 dcn_dccg_destroy(&pool->base.dccg); 1506 1476 1477 + if (pool->base.dio != NULL) { 1478 + kfree(TO_DCN10_DIO(pool->base.dio)); 1479 + pool->base.dio = NULL; 1480 + } 1481 + 1507 1482 if (pool->base.oem_device != NULL) { 1508 1483 struct dc *dc = pool->base.oem_device->ctx->dc; 1509 1484 ··· 1904 1869 if (pool->base.hubbub == NULL) { 1905 1870 BREAK_TO_DEBUGGER(); 1906 1871 dm_error("DC: failed to create hubbub!\n"); 1872 + goto create_fail; 1873 + } 1874 + 1875 + /* DIO */ 1876 + pool->base.dio = dcn321_dio_create(ctx); 1877 + if (pool->base.dio == NULL) { 1878 + BREAK_TO_DEBUGGER(); 1879 + dm_error("DC: failed to create dio!\n"); 1907 1880 goto create_fail; 1908 1881 } 1909 1882
+43
drivers/gpu/drm/amd/display/dc/resource/dcn35/dcn35_resource.c
··· 71 71 #include "dce/dce_hwseq.h" 72 72 #include "clk_mgr.h" 73 73 #include "dio/virtual/virtual_stream_encoder.h" 74 + #include "dio/dcn10/dcn10_dio.h" 74 75 #include "dce110/dce110_resource.h" 75 76 #include "dml/display_mode_vba.h" 76 77 #include "dcn35/dcn35_dccg.h" ··· 665 664 DCN20_VMID_MASK_SH_LIST(_MASK) 666 665 }; 667 666 667 + static struct dcn_dio_registers dio_regs; 668 + 669 + #define DIO_MASK_SH_LIST(mask_sh)\ 670 + HWS_SF(, DIO_MEM_PWR_CTRL, I2C_LIGHT_SLEEP_FORCE, mask_sh) 671 + 672 + static const struct dcn_dio_shift dio_shift = { 673 + DIO_MASK_SH_LIST(__SHIFT) 674 + }; 675 + 676 + static const struct dcn_dio_mask dio_mask = { 677 + DIO_MASK_SH_LIST(_MASK) 678 + }; 679 + 668 680 static const struct resource_caps res_cap_dcn35 = { 669 681 .num_timing_generator = 4, 670 682 .num_opp = 4, ··· 985 971 num_rmu); 986 972 987 973 return &mpc30->base; 974 + } 975 + 976 + static struct dio *dcn35_dio_create(struct dc_context *ctx) 977 + { 978 + struct dcn10_dio *dio10 = kzalloc_obj(struct dcn10_dio); 979 + 980 + if (!dio10) 981 + return NULL; 982 + 983 + #undef REG_STRUCT 984 + #define REG_STRUCT dio_regs 985 + DIO_REG_LIST_DCN10(); 986 + 987 + dcn10_dio_construct(dio10, ctx, &dio_regs, &dio_shift, &dio_mask); 988 + 989 + return &dio10->base; 988 990 } 989 991 990 992 static struct hubbub *dcn35_hubbub_create(struct dc_context *ctx) ··· 1593 1563 1594 1564 if (pool->base.dccg != NULL) 1595 1565 dcn_dccg_destroy(&pool->base.dccg); 1566 + 1567 + if (pool->base.dio != NULL) { 1568 + kfree(TO_DCN10_DIO(pool->base.dio)); 1569 + pool->base.dio = NULL; 1570 + } 1596 1571 } 1597 1572 1598 1573 static struct hubp *dcn35_hubp_create( ··· 2065 2030 if (pool->base.hubbub == NULL) { 2066 2031 BREAK_TO_DEBUGGER(); 2067 2032 dm_error("DC: failed to create hubbub!\n"); 2033 + goto create_fail; 2034 + } 2035 + 2036 + /* DIO */ 2037 + pool->base.dio = dcn35_dio_create(ctx); 2038 + if (pool->base.dio == NULL) { 2039 + BREAK_TO_DEBUGGER(); 2040 + dm_error("DC: failed to create dio!\n"); 2068 2041 goto create_fail; 2069 2042 } 2070 2043
+43
drivers/gpu/drm/amd/display/dc/resource/dcn351/dcn351_resource.c
··· 50 50 #include "dce/dce_hwseq.h" 51 51 #include "clk_mgr.h" 52 52 #include "dio/virtual/virtual_stream_encoder.h" 53 + #include "dio/dcn10/dcn10_dio.h" 53 54 #include "dce110/dce110_resource.h" 54 55 #include "dml/display_mode_vba.h" 55 56 #include "dcn35/dcn35_dccg.h" ··· 645 644 DCN20_VMID_MASK_SH_LIST(_MASK) 646 645 }; 647 646 647 + static struct dcn_dio_registers dio_regs; 648 + 649 + #define DIO_MASK_SH_LIST(mask_sh)\ 650 + HWS_SF(, DIO_MEM_PWR_CTRL, I2C_LIGHT_SLEEP_FORCE, mask_sh) 651 + 652 + static const struct dcn_dio_shift dio_shift = { 653 + DIO_MASK_SH_LIST(__SHIFT) 654 + }; 655 + 656 + static const struct dcn_dio_mask dio_mask = { 657 + DIO_MASK_SH_LIST(_MASK) 658 + }; 659 + 648 660 static const struct resource_caps res_cap_dcn351 = { 649 661 .num_timing_generator = 4, 650 662 .num_opp = 4, ··· 965 951 num_rmu); 966 952 967 953 return &mpc30->base; 954 + } 955 + 956 + static struct dio *dcn351_dio_create(struct dc_context *ctx) 957 + { 958 + struct dcn10_dio *dio10 = kzalloc_obj(struct dcn10_dio); 959 + 960 + if (!dio10) 961 + return NULL; 962 + 963 + #undef REG_STRUCT 964 + #define REG_STRUCT dio_regs 965 + DIO_REG_LIST_DCN10(); 966 + 967 + dcn10_dio_construct(dio10, ctx, &dio_regs, &dio_shift, &dio_mask); 968 + 969 + return &dio10->base; 968 970 } 969 971 970 972 static struct hubbub *dcn35_hubbub_create(struct dc_context *ctx) ··· 1573 1543 1574 1544 if (pool->base.dccg != NULL) 1575 1545 dcn_dccg_destroy(&pool->base.dccg); 1546 + 1547 + if (pool->base.dio != NULL) { 1548 + kfree(TO_DCN10_DIO(pool->base.dio)); 1549 + pool->base.dio = NULL; 1550 + } 1576 1551 } 1577 1552 1578 1553 static struct hubp *dcn35_hubp_create( ··· 2037 2002 if (pool->base.hubbub == NULL) { 2038 2003 BREAK_TO_DEBUGGER(); 2039 2004 dm_error("DC: failed to create hubbub!\n"); 2005 + goto create_fail; 2006 + } 2007 + 2008 + /* DIO */ 2009 + pool->base.dio = dcn351_dio_create(ctx); 2010 + if (pool->base.dio == NULL) { 2011 + BREAK_TO_DEBUGGER(); 2012 + dm_error("DC: failed to create dio!\n"); 2040 2013 goto create_fail; 2041 2014 } 2042 2015
+43
drivers/gpu/drm/amd/display/dc/resource/dcn36/dcn36_resource.c
··· 50 50 #include "dce/dce_hwseq.h" 51 51 #include "clk_mgr.h" 52 52 #include "dio/virtual/virtual_stream_encoder.h" 53 + #include "dio/dcn10/dcn10_dio.h" 53 54 #include "dce110/dce110_resource.h" 54 55 #include "dml/display_mode_vba.h" 55 56 #include "dcn35/dcn35_dccg.h" ··· 652 651 DCN20_VMID_MASK_SH_LIST(_MASK) 653 652 }; 654 653 654 + static struct dcn_dio_registers dio_regs; 655 + 656 + #define DIO_MASK_SH_LIST(mask_sh)\ 657 + HWS_SF(, DIO_MEM_PWR_CTRL, I2C_LIGHT_SLEEP_FORCE, mask_sh) 658 + 659 + static const struct dcn_dio_shift dio_shift = { 660 + DIO_MASK_SH_LIST(__SHIFT) 661 + }; 662 + 663 + static const struct dcn_dio_mask dio_mask = { 664 + DIO_MASK_SH_LIST(_MASK) 665 + }; 666 + 655 667 static const struct resource_caps res_cap_dcn36 = { 656 668 .num_timing_generator = 4, 657 669 .num_opp = 4, ··· 972 958 num_rmu); 973 959 974 960 return &mpc30->base; 961 + } 962 + 963 + static struct dio *dcn36_dio_create(struct dc_context *ctx) 964 + { 965 + struct dcn10_dio *dio10 = kzalloc_obj(struct dcn10_dio); 966 + 967 + if (!dio10) 968 + return NULL; 969 + 970 + #undef REG_STRUCT 971 + #define REG_STRUCT dio_regs 972 + DIO_REG_LIST_DCN10(); 973 + 974 + dcn10_dio_construct(dio10, ctx, &dio_regs, &dio_shift, &dio_mask); 975 + 976 + return &dio10->base; 975 977 } 976 978 977 979 static struct hubbub *dcn35_hubbub_create(struct dc_context *ctx) ··· 1580 1550 1581 1551 if (pool->base.dccg != NULL) 1582 1552 dcn_dccg_destroy(&pool->base.dccg); 1553 + 1554 + if (pool->base.dio != NULL) { 1555 + kfree(TO_DCN10_DIO(pool->base.dio)); 1556 + pool->base.dio = NULL; 1557 + } 1583 1558 } 1584 1559 1585 1560 static struct hubp *dcn35_hubp_create( ··· 2044 2009 if (pool->base.hubbub == NULL) { 2045 2010 BREAK_TO_DEBUGGER(); 2046 2011 dm_error("DC: failed to create hubbub!\n"); 2012 + goto create_fail; 2013 + } 2014 + 2015 + /* DIO */ 2016 + pool->base.dio = dcn36_dio_create(ctx); 2017 + if (pool->base.dio == NULL) { 2018 + BREAK_TO_DEBUGGER(); 2019 + dm_error("DC: failed to create dio!\n"); 2047 2020 goto create_fail; 2048 2021 } 2049 2022
-1
drivers/gpu/drm/amd/pm/swsmu/smu11/smu_v11_0.c
··· 262 262 "smu fw program = %d, version = 0x%08x (%d.%d.%d)\n", 263 263 smu->smc_driver_if_version, if_version, 264 264 smu_program, smu_version, smu_major, smu_minor, smu_debug); 265 - dev_info(smu->adev->dev, "SMU driver if version not matched\n"); 266 265 } 267 266 268 267 return ret;
-1
drivers/gpu/drm/amd/pm/swsmu/smu12/smu_v12_0.c
··· 101 101 "smu fw program = %d, smu fw version = 0x%08x (%d.%d.%d)\n", 102 102 smu->smc_driver_if_version, if_version, 103 103 smu_program, smu_version, smu_major, smu_minor, smu_debug); 104 - dev_info(smu->adev->dev, "SMU driver if version not matched\n"); 105 104 } 106 105 107 106 return ret;
-1
drivers/gpu/drm/amd/pm/swsmu/smu14/smu_v14_0.c
··· 284 284 "smu fw program = %d, smu fw version = 0x%08x (%d.%d.%d)\n", 285 285 smu->smc_driver_if_version, if_version, 286 286 smu_program, smu_version, smu_major, smu_minor, smu_debug); 287 - dev_info(adev->dev, "SMU driver if version not matched\n"); 288 287 } 289 288 290 289 return ret;
+1 -1
drivers/gpu/drm/ast/ast_dp501.c
··· 436 436 /* Finally, clear bits [17:16] of SCU2c */ 437 437 data = ast_read32(ast, 0x1202c); 438 438 data &= 0xfffcffff; 439 - ast_write32(ast, 0, data); 439 + ast_write32(ast, 0x1202c, data); 440 440 441 441 /* Disable DVO */ 442 442 ast_set_index_reg_mask(ast, AST_IO_VGACRI, 0xa3, 0xcf, 0x00);
+11 -5
drivers/gpu/drm/drm_bridge.c
··· 1569 1569 static void drm_bridge_debugfs_show_bridge(struct drm_printer *p, 1570 1570 struct drm_bridge *bridge, 1571 1571 unsigned int idx, 1572 - bool lingering) 1572 + bool lingering, 1573 + bool scoped) 1573 1574 { 1575 + unsigned int refcount = kref_read(&bridge->refcount); 1576 + 1577 + if (scoped) 1578 + refcount--; 1579 + 1574 1580 drm_printf(p, "bridge[%u]: %ps\n", idx, bridge->funcs); 1575 1581 1576 - drm_printf(p, "\trefcount: %u%s\n", kref_read(&bridge->refcount), 1582 + drm_printf(p, "\trefcount: %u%s\n", refcount, 1577 1583 lingering ? " [lingering]" : ""); 1578 1584 1579 1585 drm_printf(p, "\ttype: [%d] %s\n", ··· 1613 1607 mutex_lock(&bridge_lock); 1614 1608 1615 1609 list_for_each_entry(bridge, &bridge_list, list) 1616 - drm_bridge_debugfs_show_bridge(&p, bridge, idx++, false); 1610 + drm_bridge_debugfs_show_bridge(&p, bridge, idx++, false, false); 1617 1611 1618 1612 list_for_each_entry(bridge, &bridge_lingering_list, list) 1619 - drm_bridge_debugfs_show_bridge(&p, bridge, idx++, true); 1613 + drm_bridge_debugfs_show_bridge(&p, bridge, idx++, true, false); 1620 1614 1621 1615 mutex_unlock(&bridge_lock); 1622 1616 ··· 1631 1625 unsigned int idx = 0; 1632 1626 1633 1627 drm_for_each_bridge_in_chain_scoped(encoder, bridge) 1634 - drm_bridge_debugfs_show_bridge(&p, bridge, idx++, false); 1628 + drm_bridge_debugfs_show_bridge(&p, bridge, idx++, false, true); 1635 1629 1636 1630 return 0; 1637 1631 }
+1 -4
drivers/gpu/drm/drm_file.c
··· 233 233 void drm_file_free(struct drm_file *file) 234 234 { 235 235 struct drm_device *dev; 236 - int idx; 237 236 238 237 if (!file) 239 238 return; ··· 249 250 250 251 drm_events_release(file); 251 252 252 - if (drm_core_check_feature(dev, DRIVER_MODESET) && 253 - drm_dev_enter(dev, &idx)) { 253 + if (drm_core_check_feature(dev, DRIVER_MODESET)) { 254 254 drm_fb_release(file); 255 255 drm_property_destroy_user_blobs(dev, file); 256 - drm_dev_exit(idx); 257 256 } 258 257 259 258 if (drm_core_check_feature(dev, DRIVER_SYNCOBJ))
+2
drivers/gpu/drm/drm_ioc32.c
··· 28 28 * IN THE SOFTWARE. 29 29 */ 30 30 #include <linux/compat.h> 31 + #include <linux/nospec.h> 31 32 #include <linux/ratelimit.h> 32 33 #include <linux/export.h> 33 34 ··· 375 374 if (nr >= ARRAY_SIZE(drm_compat_ioctls)) 376 375 return drm_ioctl(filp, cmd, arg); 377 376 377 + nr = array_index_nospec(nr, ARRAY_SIZE(drm_compat_ioctls)); 378 378 fn = drm_compat_ioctls[nr].fn; 379 379 if (!fn) 380 380 return drm_ioctl(filp, cmd, arg);
+3 -6
drivers/gpu/drm/drm_mode_config.c
··· 577 577 */ 578 578 WARN_ON(!list_empty(&dev->mode_config.fb_list)); 579 579 list_for_each_entry_safe(fb, fbt, &dev->mode_config.fb_list, head) { 580 - if (list_empty(&fb->filp_head) || drm_framebuffer_read_refcount(fb) > 1) { 581 - struct drm_printer p = drm_dbg_printer(dev, DRM_UT_KMS, "[leaked fb]"); 580 + struct drm_printer p = drm_dbg_printer(dev, DRM_UT_KMS, "[leaked fb]"); 582 581 583 - drm_printf(&p, "framebuffer[%u]:\n", fb->base.id); 584 - drm_framebuffer_print_info(&p, 1, fb); 585 - } 586 - list_del_init(&fb->filp_head); 582 + drm_printf(&p, "framebuffer[%u]:\n", fb->base.id); 583 + drm_framebuffer_print_info(&p, 1, fb); 587 584 drm_framebuffer_free(&fb->base.refcount); 588 585 } 589 586
+1 -1
drivers/gpu/drm/i915/display/g4x_dp.c
··· 137 137 intel_dp->DP |= DP_SYNC_VS_HIGH; 138 138 intel_dp->DP |= DP_LINK_TRAIN_OFF_CPT; 139 139 140 - if (drm_dp_enhanced_frame_cap(intel_dp->dpcd)) 140 + if (pipe_config->enhanced_framing) 141 141 intel_dp->DP |= DP_ENHANCED_FRAMING; 142 142 143 143 intel_dp->DP |= DP_PIPE_SEL_IVB(crtc->pipe);
+2 -2
drivers/gpu/drm/i915/display/icl_dsi.c
··· 889 889 * non-compressed link speeds, and simplifies down to the ratio between 890 890 * compressed and non-compressed bpp. 891 891 */ 892 - if (crtc_state->dsc.compression_enable) { 892 + if (is_vid_mode(intel_dsi) && crtc_state->dsc.compression_enable) { 893 893 mul = fxp_q4_to_int(crtc_state->dsc.compressed_bpp_x16); 894 894 div = mipi_dsi_pixel_format_to_bpp(intel_dsi->pixel_format); 895 895 } ··· 1503 1503 struct drm_display_mode *adjusted_mode = 1504 1504 &pipe_config->hw.adjusted_mode; 1505 1505 1506 - if (pipe_config->dsc.compressed_bpp_x16) { 1506 + if (is_vid_mode(intel_dsi) && pipe_config->dsc.compressed_bpp_x16) { 1507 1507 int div = fxp_q4_to_int(pipe_config->dsc.compressed_bpp_x16); 1508 1508 int mul = mipi_dsi_pixel_format_to_bpp(intel_dsi->pixel_format); 1509 1509
+54
drivers/gpu/drm/i915/display/intel_cdclk.c
··· 2971 2971 return 0; 2972 2972 } 2973 2973 2974 + static int intel_cdclk_update_crtc_min_voltage_level(struct intel_atomic_state *state, 2975 + struct intel_crtc *crtc, 2976 + u8 old_min_voltage_level, 2977 + u8 new_min_voltage_level, 2978 + bool *need_cdclk_calc) 2979 + { 2980 + struct intel_display *display = to_intel_display(state); 2981 + struct intel_cdclk_state *cdclk_state; 2982 + bool allow_voltage_level_decrease = intel_any_crtc_needs_modeset(state); 2983 + int ret; 2984 + 2985 + if (new_min_voltage_level == old_min_voltage_level) 2986 + return 0; 2987 + 2988 + if (!allow_voltage_level_decrease && 2989 + new_min_voltage_level < old_min_voltage_level) 2990 + return 0; 2991 + 2992 + cdclk_state = intel_atomic_get_cdclk_state(state); 2993 + if (IS_ERR(cdclk_state)) 2994 + return PTR_ERR(cdclk_state); 2995 + 2996 + old_min_voltage_level = cdclk_state->min_voltage_level[crtc->pipe]; 2997 + 2998 + if (new_min_voltage_level == old_min_voltage_level) 2999 + return 0; 3000 + 3001 + if (!allow_voltage_level_decrease && 3002 + new_min_voltage_level < old_min_voltage_level) 3003 + return 0; 3004 + 3005 + cdclk_state->min_voltage_level[crtc->pipe] = new_min_voltage_level; 3006 + 3007 + ret = intel_atomic_lock_global_state(&cdclk_state->base); 3008 + if (ret) 3009 + return ret; 3010 + 3011 + *need_cdclk_calc = true; 3012 + 3013 + drm_dbg_kms(display->drm, 3014 + "[CRTC:%d:%s] min voltage level: %d -> %d\n", 3015 + crtc->base.base.id, crtc->base.name, 3016 + old_min_voltage_level, new_min_voltage_level); 3017 + 3018 + return 0; 3019 + } 3020 + 2974 3021 int intel_cdclk_update_dbuf_bw_min_cdclk(struct intel_atomic_state *state, 2975 3022 int old_min_cdclk, int new_min_cdclk, 2976 3023 bool *need_cdclk_calc) ··· 3431 3384 old_crtc_state->min_cdclk, 3432 3385 new_crtc_state->min_cdclk, 3433 3386 need_cdclk_calc); 3387 + if (ret) 3388 + return ret; 3389 + 3390 + ret = intel_cdclk_update_crtc_min_voltage_level(state, crtc, 3391 + old_crtc_state->min_voltage_level, 3392 + new_crtc_state->min_voltage_level, 3393 + need_cdclk_calc); 3434 3394 if (ret) 3435 3395 return ret; 3436 3396 }
+31 -15
drivers/gpu/drm/sysfb/efidrm.c
··· 151 151 struct drm_sysfb_device *sysfb; 152 152 struct drm_device *dev; 153 153 struct resource *mem = NULL; 154 - void __iomem *screen_base = NULL; 155 154 struct drm_plane *primary_plane; 156 155 struct drm_crtc *crtc; 157 156 struct drm_encoder *encoder; ··· 237 238 238 239 mem_flags = efidrm_get_mem_flags(dev, res->start, vsize); 239 240 240 - if (mem_flags & EFI_MEMORY_WC) 241 - screen_base = devm_ioremap_wc(&pdev->dev, mem->start, resource_size(mem)); 242 - else if (mem_flags & EFI_MEMORY_UC) 243 - screen_base = devm_ioremap(&pdev->dev, mem->start, resource_size(mem)); 244 - else if (mem_flags & EFI_MEMORY_WT) 245 - screen_base = devm_memremap(&pdev->dev, mem->start, resource_size(mem), 246 - MEMREMAP_WT); 247 - else if (mem_flags & EFI_MEMORY_WB) 248 - screen_base = devm_memremap(&pdev->dev, mem->start, resource_size(mem), 249 - MEMREMAP_WB); 250 - else 241 + if (mem_flags & EFI_MEMORY_WC) { 242 + void __iomem *screen_base = devm_ioremap_wc(&pdev->dev, mem->start, 243 + resource_size(mem)); 244 + 245 + if (!screen_base) 246 + return ERR_PTR(-ENXIO); 247 + iosys_map_set_vaddr_iomem(&sysfb->fb_addr, screen_base); 248 + } else if (mem_flags & EFI_MEMORY_UC) { 249 + void __iomem *screen_base = devm_ioremap(&pdev->dev, mem->start, 250 + resource_size(mem)); 251 + 252 + if (!screen_base) 253 + return ERR_PTR(-ENXIO); 254 + iosys_map_set_vaddr_iomem(&sysfb->fb_addr, screen_base); 255 + } else if (mem_flags & EFI_MEMORY_WT) { 256 + void *screen_base = devm_memremap(&pdev->dev, mem->start, 257 + resource_size(mem), MEMREMAP_WT); 258 + 259 + if (IS_ERR(screen_base)) 260 + return ERR_CAST(screen_base); 261 + iosys_map_set_vaddr(&sysfb->fb_addr, screen_base); 262 + } else if (mem_flags & EFI_MEMORY_WB) { 263 + void *screen_base = devm_memremap(&pdev->dev, mem->start, 264 + resource_size(mem), MEMREMAP_WB); 265 + 266 + if (IS_ERR(screen_base)) 267 + return ERR_CAST(screen_base); 268 + iosys_map_set_vaddr(&sysfb->fb_addr, screen_base); 269 + } else { 251 270 drm_err(dev, "invalid mem_flags: 0x%llx\n", mem_flags); 252 - if (!screen_base) 253 - return ERR_PTR(-ENOMEM); 254 - iosys_map_set_vaddr_iomem(&sysfb->fb_addr, screen_base); 271 + return ERR_PTR(-EINVAL); 272 + } 255 273 256 274 /* 257 275 * Modesetting
+13 -14
drivers/gpu/drm/xe/xe_device.c
··· 837 837 } 838 838 } 839 839 840 + static void xe_device_wedged_fini(struct drm_device *drm, void *arg) 841 + { 842 + struct xe_device *xe = arg; 843 + 844 + if (atomic_read(&xe->wedged.flag)) 845 + xe_pm_runtime_put(xe); 846 + } 847 + 840 848 int xe_device_probe(struct xe_device *xe) 841 849 { 842 850 struct xe_tile *tile; ··· 1020 1012 goto err_unregister_display; 1021 1013 1022 1014 detect_preproduction_hw(xe); 1015 + 1016 + err = drmm_add_action_or_reset(&xe->drm, xe_device_wedged_fini, xe); 1017 + if (err) 1018 + goto err_unregister_display; 1023 1019 1024 1020 return devm_add_action_or_reset(xe->drm.dev, xe_device_sanitize, xe); 1025 1021 ··· 1228 1216 return address & GENMASK_ULL(xe->info.va_bits - 1, 0); 1229 1217 } 1230 1218 1231 - static void xe_device_wedged_fini(struct drm_device *drm, void *arg) 1232 - { 1233 - struct xe_device *xe = arg; 1234 - 1235 - xe_pm_runtime_put(xe); 1236 - } 1237 - 1238 1219 /** 1239 1220 * DOC: Xe Device Wedging 1240 1221 * ··· 1305 1300 return; 1306 1301 } 1307 1302 1308 - xe_pm_runtime_get_noresume(xe); 1309 - 1310 - if (drmm_add_action_or_reset(&xe->drm, xe_device_wedged_fini, xe)) { 1311 - drm_err(&xe->drm, "Failed to register xe_device_wedged_fini clean-up. Although device is wedged.\n"); 1312 - return; 1313 - } 1314 - 1315 1303 if (!atomic_xchg(&xe->wedged.flag, 1)) { 1316 1304 xe->needs_flr_on_fini = true; 1305 + xe_pm_runtime_get_noresume(xe); 1317 1306 drm_err(&xe->drm, 1318 1307 "CRITICAL: Xe has declared device %s as wedged.\n" 1319 1308 "IOCTLs and executions are blocked. Only a rebind may clear the failure\n"
+6
drivers/gpu/drm/xe/xe_pagefault.c
··· 187 187 goto unlock_vm; 188 188 } 189 189 190 + if (xe_vma_read_only(vma) && 191 + pf->consumer.access_type != XE_PAGEFAULT_ACCESS_TYPE_READ) { 192 + err = -EPERM; 193 + goto unlock_vm; 194 + } 195 + 190 196 atomic = xe_pagefault_access_is_atomic(pf->consumer.access_type); 191 197 192 198 if (xe_vma_is_cpu_addr_mirror(vma))
+16 -7
drivers/gpu/drm/xe/xe_pxp.c
··· 380 380 return 0; 381 381 } 382 382 383 + /* 384 + * On PTL, older GSC FWs have a bug that can cause them to crash during 385 + * PXP invalidation events, which leads to a complete loss of power 386 + * management on the media GT. Therefore, we can't use PXP on FWs that 387 + * have this bug, which was fixed in PTL GSC build 1396. 388 + */ 389 + if (xe->info.platform == XE_PANTHERLAKE && 390 + gt->uc.gsc.fw.versions.found[XE_UC_FW_VER_RELEASE].build < 1396) { 391 + drm_info(&xe->drm, "PXP requires PTL GSC build 1396 or newer\n"); 392 + return 0; 393 + } 394 + 383 395 pxp = drmm_kzalloc(&xe->drm, sizeof(struct xe_pxp), GFP_KERNEL); 384 396 if (!pxp) { 385 397 err = -ENOMEM; ··· 524 512 static int pxp_start(struct xe_pxp *pxp, u8 type) 525 513 { 526 514 int ret = 0; 527 - bool restart = false; 515 + bool restart; 528 516 529 517 if (!xe_pxp_is_enabled(pxp)) 530 518 return -ENODEV; ··· 552 540 if (!wait_for_completion_timeout(&pxp->activation, 553 541 msecs_to_jiffies(PXP_ACTIVATION_TIMEOUT_MS))) 554 542 return -ETIMEDOUT; 543 + 544 + restart = false; 555 545 556 546 mutex_lock(&pxp->mutex); 557 547 ··· 597 583 drm_err(&pxp->xe->drm, "PXP termination failed before start\n"); 598 584 mutex_lock(&pxp->mutex); 599 585 pxp->status = XE_PXP_ERROR; 586 + complete_all(&pxp->termination); 600 587 601 588 goto out_unlock; 602 589 } ··· 885 870 pxp->key_instance++; 886 871 needs_queue_inval = true; 887 872 break; 888 - default: 889 - drm_err(&pxp->xe->drm, "unexpected state during PXP suspend: %u", 890 - pxp->status); 891 - ret = -EIO; 892 - goto out; 893 873 } 894 874 895 875 /* ··· 909 899 910 900 pxp->last_suspend_key_instance = pxp->key_instance; 911 901 912 - out: 913 902 return ret; 914 903 } 915 904
+1 -1
drivers/gpu/drm/xe/xe_svm.c
··· 903 903 void xe_svm_close(struct xe_vm *vm) 904 904 { 905 905 xe_assert(vm->xe, xe_vm_is_closed(vm)); 906 - flush_work(&vm->svm.garbage_collector.work); 906 + disable_work_sync(&vm->svm.garbage_collector.work); 907 907 xe_svm_put_pagemaps(vm); 908 908 drm_pagemap_release_owner(&vm->svm.peer); 909 909 }
+12 -4
drivers/gpu/drm/xe/xe_vm_madvise.c
··· 408 408 struct xe_device *xe = to_xe_device(dev); 409 409 struct xe_file *xef = to_xe_file(file); 410 410 struct drm_xe_madvise *args = data; 411 - struct xe_vmas_in_madvise_range madvise_range = {.addr = args->start, 412 - .range = args->range, }; 411 + struct xe_vmas_in_madvise_range madvise_range = { 412 + /* 413 + * Userspace may pass canonical (sign-extended) addresses. 414 + * Strip the sign extension to get the internal non-canonical 415 + * form used by the GPUVM, matching xe_vm_bind_ioctl() behavior. 416 + */ 417 + .addr = xe_device_uncanonicalize_addr(xe, args->start), 418 + .range = args->range, 419 + }; 413 420 struct xe_madvise_details details; 414 421 struct xe_vm *vm; 415 422 struct drm_exec exec; ··· 446 439 if (err) 447 440 goto unlock_vm; 448 441 449 - err = xe_vm_alloc_madvise_vma(vm, args->start, args->range); 442 + err = xe_vm_alloc_madvise_vma(vm, madvise_range.addr, args->range); 450 443 if (err) 451 444 goto madv_fini; 452 445 ··· 489 482 madvise_funcs[attr_type](xe, vm, madvise_range.vmas, madvise_range.num_vmas, args, 490 483 &details); 491 484 492 - err = xe_vm_invalidate_madvise_range(vm, args->start, args->start + args->range); 485 + err = xe_vm_invalidate_madvise_range(vm, madvise_range.addr, 486 + madvise_range.addr + args->range); 493 487 494 488 if (madvise_range.has_svm_userptr_vmas) 495 489 xe_svm_notifier_unlock(vm);