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linux
ASoC: dt-bindings: mt8192-afe-pcm: Fix clocks and clock-names
Both clocks and clock-names are missing (a lot of) entries: add
all the used audio clocks and their description and also fix the
example node.
Signed-off-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com>
Fixes: c861af7861aa ("ASoC: dt-bindings: mediatek: mt8192: re-add audio afe document")
Link: https://patch.msgid.link/20260115125624.73598-3-angelogioacchino.delregno@collabora.com
Signed-off-by: Mark Brown <broonie@kernel.org>
authored by
AngeloGioacchino Del Regno
and committed by
Mark Brown
60e8451b
4711b292
+162
-14
+162
-14
Documentation/devicetree/bindings/sound/mt8192-afe-pcm.yaml
+162
-14
Documentation/devicetree/bindings/sound/mt8192-afe-pcm.yaml
···
47
47
- description: AFE clock
48
48
- description: ADDA DAC clock
49
49
- description: ADDA DAC pre-distortion clock
50
-
- description: audio infra sys clock
51
-
- description: audio infra 26M clock
50
+
- description: ADDA ADC clock
51
+
- description: ADDA6 ADC clock
52
+
- description: Audio low-jitter 22.5792m clock
53
+
- description: Audio low-jitter 24.576m clock
54
+
- description: Audio PLL1 tuner clock
55
+
- description: Audio PLL2 tuner clock
56
+
- description: Audio Time-Division Multiplexing interface clock
57
+
- description: ADDA ADC Sine Generator clock
58
+
- description: audio Non-LE clock
59
+
- description: Audio DAC High-Resolution clock
60
+
- description: Audio High-Resolution ADC clock
61
+
- description: Audio High-Resolution ADC SineGen clock
62
+
- description: Audio ADDA6 High-Resolution ADC clock
63
+
- description: Tertiary ADDA DAC clock
64
+
- description: Tertiary ADDA DAC pre-distortion clock
65
+
- description: Tertiary ADDA DAC Sine Generator clock
66
+
- description: Tertiary ADDA DAC High-Resolution clock
67
+
- description: Audio infra sys clock
68
+
- description: Audio infra 26M clock
69
+
- description: Mux for audio clock
70
+
- description: Mux for audio internal bus clock
71
+
- description: Mux main divider by 4
72
+
- description: Primary audio mux
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+
- description: Primary audio PLL
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+
- description: Secondary audio mux
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+
- description: Secondary audio PLL
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+
- description: Primary audio en-generator clock
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+
- description: Primary PLL divider by 4 for IEC
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+
- description: Secondary audio en-generator clock
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+
- description: Secondary PLL divider by 4 for IEC
80
+
- description: Mux selector for I2S port 0
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+
- description: Mux selector for I2S port 1
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+
- description: Mux selector for I2S port 2
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+
- description: Mux selector for I2S port 3
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+
- description: Mux selector for I2S port 4
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+
- description: Mux selector for I2S port 5
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+
- description: Mux selector for I2S port 6
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+
- description: Mux selector for I2S port 7
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+
- description: Mux selector for I2S port 8
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+
- description: Mux selector for I2S port 9
90
+
- description: APLL1 and APLL2 divider for I2S port 0
91
+
- description: APLL1 and APLL2 divider for I2S port 1
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+
- description: APLL1 and APLL2 divider for I2S port 2
93
+
- description: APLL1 and APLL2 divider for I2S port 3
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+
- description: APLL1 and APLL2 divider for I2S port 4
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+
- description: APLL1 and APLL2 divider for IEC
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+
- description: APLL1 and APLL2 divider for I2S port 5
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+
- description: APLL1 and APLL2 divider for I2S port 6
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+
- description: APLL1 and APLL2 divider for I2S port 7
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+
- description: APLL1 and APLL2 divider for I2S port 8
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+
- description: APLL1 and APLL2 divider for I2S port 9
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+
- description: Top mux for audio subsystem
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+
- description: 26MHz clock for audio subsystem
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clock-names:
54
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items:
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- const: aud_afe_clk
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- const: aud_dac_clk
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- const: aud_dac_predis_clk
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+
- const: aud_adc_clk
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+
- const: aud_adda6_adc_clk
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+
- const: aud_apll22m_clk
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+
- const: aud_apll24m_clk
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+
- const: aud_apll1_tuner_clk
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+
- const: aud_apll2_tuner_clk
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+
- const: aud_tdm_clk
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+
- const: aud_tml_clk
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+
- const: aud_nle
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+
- const: aud_dac_hires_clk
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+
- const: aud_adc_hires_clk
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+
- const: aud_adc_hires_tml
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+
- const: aud_adda6_adc_hires_clk
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+
- const: aud_3rd_dac_clk
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+
- const: aud_3rd_dac_predis_clk
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+
- const: aud_3rd_dac_tml
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+
- const: aud_3rd_dac_hires_clk
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- const: aud_infra_clk
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127
- const: aud_infra_26m_clk
128
+
- const: top_mux_audio
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+
- const: top_mux_audio_int
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+
- const: top_mainpll_d4_d4
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+
- const: top_mux_aud_1
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+
- const: top_apll1_ck
133
+
- const: top_mux_aud_2
134
+
- const: top_apll2_ck
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+
- const: top_mux_aud_eng1
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+
- const: top_apll1_d4
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+
- const: top_mux_aud_eng2
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+
- const: top_apll2_d4
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+
- const: top_i2s0_m_sel
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+
- const: top_i2s1_m_sel
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+
- const: top_i2s2_m_sel
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+
- const: top_i2s3_m_sel
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+
- const: top_i2s4_m_sel
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+
- const: top_i2s5_m_sel
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+
- const: top_i2s6_m_sel
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+
- const: top_i2s7_m_sel
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+
- const: top_i2s8_m_sel
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+
- const: top_i2s9_m_sel
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+
- const: top_apll12_div0
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+
- const: top_apll12_div1
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+
- const: top_apll12_div2
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+
- const: top_apll12_div3
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+
- const: top_apll12_div4
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+
- const: top_apll12_divb
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+
- const: top_apll12_div5
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+
- const: top_apll12_div6
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+
- const: top_apll12_div7
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+
- const: top_apll12_div8
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+
- const: top_apll12_div9
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+
- const: top_mux_audio_h
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+
- const: top_clk26m_clk
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required:
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- compatible
···
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afe: mt8192-afe-pcm {
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compatible = "mediatek,mt8192-audio";
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interrupts = <GIC_SPI 202 IRQ_TYPE_LEVEL_HIGH>;
86
+
clocks = <&audsys CLK_AUD_AFE>, <&audsys CLK_AUD_DAC>,
87
+
<&audsys CLK_AUD_DAC_PREDIS>, <&audsys CLK_AUD_ADC>,
88
+
<&audsys CLK_AUD_ADDA6_ADC>, <&audsys CLK_AUD_22M>,
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+
<&audsys CLK_AUD_24M>, <&audsys CLK_AUD_APLL_TUNER>,
90
+
<&audsys CLK_AUD_APLL2_TUNER>, <&audsys CLK_AUD_TDM>,
91
+
<&audsys CLK_AUD_TML>, <&audsys CLK_AUD_NLE>,
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+
<&audsys CLK_AUD_DAC_HIRES>, <&audsys CLK_AUD_ADC_HIRES>,
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+
<&audsys CLK_AUD_ADC_HIRES_TML>, <&audsys CLK_AUD_ADDA6_ADC_HIRES>,
94
+
<&audsys CLK_AUD_3RD_DAC>, <&audsys CLK_AUD_3RD_DAC_PREDIS>,
95
+
<&audsys CLK_AUD_3RD_DAC_TML>, <&audsys CLK_AUD_3RD_DAC_HIRES>,
96
+
<&infracfg CLK_INFRA_AUDIO>, <&infracfg CLK_INFRA_AUDIO_26M_B>,
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+
<&topckgen CLK_TOP_AUDIO_SEL>, <&topckgen CLK_TOP_AUD_INTBUS_SEL>,
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+
<&topckgen CLK_TOP_MAINPLL_D4_D4>, <&topckgen CLK_TOP_AUD_1_SEL>,
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+
<&topckgen CLK_TOP_APLL1>, <&topckgen CLK_TOP_AUD_2_SEL>,
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+
<&topckgen CLK_TOP_APLL2>, <&topckgen CLK_TOP_AUD_ENGEN1_SEL>,
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<&topckgen CLK_TOP_APLL1_D4>, <&topckgen CLK_TOP_AUD_ENGEN2_SEL>,
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+
<&topckgen CLK_TOP_APLL2_D4>, <&topckgen CLK_TOP_APLL_I2S0_M_SEL>,
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<&topckgen CLK_TOP_APLL_I2S1_M_SEL>, <&topckgen CLK_TOP_APLL_I2S2_M_SEL>,
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+
<&topckgen CLK_TOP_APLL_I2S3_M_SEL>, <&topckgen CLK_TOP_APLL_I2S4_M_SEL>,
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+
<&topckgen CLK_TOP_APLL_I2S5_M_SEL>, <&topckgen CLK_TOP_APLL_I2S6_M_SEL>,
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+
<&topckgen CLK_TOP_APLL_I2S7_M_SEL>, <&topckgen CLK_TOP_APLL_I2S8_M_SEL>,
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+
<&topckgen CLK_TOP_APLL_I2S9_M_SEL>, <&topckgen CLK_TOP_APLL12_DIV0>,
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<&topckgen CLK_TOP_APLL12_DIV1>, <&topckgen CLK_TOP_APLL12_DIV2>,
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<&topckgen CLK_TOP_APLL12_DIV3>, <&topckgen CLK_TOP_APLL12_DIV4>,
110
+
<&topckgen CLK_TOP_APLL12_DIVB>, <&topckgen CLK_TOP_APLL12_DIV5>,
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+
<&topckgen CLK_TOP_APLL12_DIV6>, <&topckgen CLK_TOP_APLL12_DIV7>,
112
+
<&topckgen CLK_TOP_APLL12_DIV8>, <&topckgen CLK_TOP_APLL12_DIV9>,
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+
<&topckgen CLK_TOP_AUDIO_H_SEL>, <&clk26m>;
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+
clock-names = "aud_afe_clk", "aud_dac_clk",
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+
"aud_dac_predis_clk", "aud_adc_clk",
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+
"aud_adda6_adc_clk", "aud_apll22m_clk",
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+
"aud_apll24m_clk", "aud_apll1_tuner_clk",
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+
"aud_apll2_tuner_clk", "aud_tdm_clk",
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+
"aud_tml_clk", "aud_nle",
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+
"aud_dac_hires_clk", "aud_adc_hires_clk",
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+
"aud_adc_hires_tml", "aud_adda6_adc_hires_clk",
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+
"aud_3rd_dac_clk", "aud_3rd_dac_predis_clk",
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+
"aud_3rd_dac_tml", "aud_3rd_dac_hires_clk",
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+
"aud_infra_clk", "aud_infra_26m_clk",
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+
"top_mux_audio", "top_mux_audio_int",
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+
"top_mainpll_d4_d4", "top_mux_aud_1",
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+
"top_apll1_ck", "top_mux_aud_2",
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+
"top_apll2_ck", "top_mux_aud_eng1",
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+
"top_apll1_d4", "top_mux_aud_eng2",
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+
"top_apll2_d4", "top_i2s0_m_sel",
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+
"top_i2s1_m_sel", "top_i2s2_m_sel",
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+
"top_i2s3_m_sel", "top_i2s4_m_sel",
133
+
"top_i2s5_m_sel", "top_i2s6_m_sel",
134
+
"top_i2s7_m_sel", "top_i2s8_m_sel",
135
+
"top_i2s9_m_sel", "top_apll12_div0",
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+
"top_apll12_div1", "top_apll12_div2",
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+
"top_apll12_div3", "top_apll12_div4",
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+
"top_apll12_divb", "top_apll12_div5",
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+
"top_apll12_div6", "top_apll12_div7",
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+
"top_apll12_div8", "top_apll12_div9",
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+
"top_mux_audio_h", "top_clk26m_clk";
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+
memory-region = <&afe_dma_mem>;
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+
power-domains = <&scpsys MT8192_POWER_DOMAIN_AUDIO>;
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resets = <&watchdog MT8192_TOPRGU_AUDIO_SW_RST>;
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reset-names = "audiosys";
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mediatek,apmixedsys = <&apmixedsys>;
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mediatek,infracfg = <&infracfg>;
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mediatek,topckgen = <&topckgen>;
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-
power-domains = <&scpsys MT8192_POWER_DOMAIN_AUDIO>;
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-
clocks = <&audsys CLK_AUD_AFE>,
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-
<&audsys CLK_AUD_DAC>,
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-
<&audsys CLK_AUD_DAC_PREDIS>,
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-
<&infracfg CLK_INFRA_AUDIO>,
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-
<&infracfg CLK_INFRA_AUDIO_26M_B>;
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-
clock-names = "aud_afe_clk",
200
-
"aud_dac_clk",
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-
"aud_dac_predis_clk",
202
-
"aud_infra_clk",
203
-
"aud_infra_26m_clk";
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-
memory-region = <&afe_dma_mem>;
205
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};
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151
...