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git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git
kernel
os
linux
drm/amd/display: update dcn315 clock table read
[Why & How]
Make dcn315 base its clock table off dcfclk rather than fclk.
This change also adds some sanity checking to make sure an
empty pmfw table does not result in invalid dal clocks.
Reviewed-by: Charlene Liu <Charlene.Liu@amd.com>
Acked-by: Qingqing Zhuo <qingqing.zhuo@amd.com>
Signed-off-by: Dmytro Laktyushkin <Dmytro.Laktyushkin@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
authored by
Dmytro Laktyushkin
and committed by
Alex Deucher
60f6fe66
d1826081
+67
-40
+67
-40
drivers/gpu/drm/amd/display/dc/clk_mgr/dcn315/dcn315_clk_mgr.c
+67
-40
drivers/gpu/drm/amd/display/dc/clk_mgr/dcn315/dcn315_clk_mgr.c
···
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struct integrated_info *bios_info,
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const DpmClocks_315_t *clock_table)
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{
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-
int i, j;
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int i;
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struct clk_bw_params *bw_params = clk_mgr->base.bw_params;
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-
uint32_t max_dispclk = 0, max_dppclk = 0;
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uint32_t max_dispclk, max_dppclk, max_pstate, max_socclk, max_fclk = 0, min_pstate = 0;
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struct clk_limit_table_entry def_max = bw_params->clk_table.entries[bw_params->clk_table.num_entries - 1];
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j = -1;
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max_dispclk = find_max_clk_value(clock_table->DispClocks, clock_table->NumDispClkLevelsEnabled);
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+
max_dppclk = find_max_clk_value(clock_table->DppClocks, clock_table->NumDispClkLevelsEnabled);
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max_socclk = find_max_clk_value(clock_table->SocClocks, clock_table->NumSocClkLevelsEnabled);
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ASSERT(NUM_DF_PSTATE_LEVELS <= MAX_NUM_DPM_LVL);
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-
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/* Find lowest DPM, FCLK is filled in reverse order*/
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for (i = NUM_DF_PSTATE_LEVELS - 1; i >= 0; i--) {
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if (clock_table->DfPstateTable[i].FClk != 0) {
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j = i;
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break;
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/* Find highest fclk pstate */
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for (i = 0; i < clock_table->NumDfPstatesEnabled; i++) {
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if (clock_table->DfPstateTable[i].FClk > max_fclk) {
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max_fclk = clock_table->DfPstateTable[i].FClk;
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max_pstate = i;
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}
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}
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if (j == -1) {
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/* clock table is all 0s, just use our own hardcode */
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ASSERT(0);
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return;
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}
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/* For 315 we want to base clock table on dcfclk, need at least one entry regardless of pmfw table */
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for (i = 0; i < clock_table->NumDcfClkLevelsEnabled; i++) {
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int j;
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uint32_t min_fclk = clock_table->DfPstateTable[0].FClk;
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bw_params->clk_table.num_entries = j + 1;
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for (j = 1; j < clock_table->NumDfPstatesEnabled; j++) {
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if (clock_table->DfPstateTable[j].Voltage <= clock_table->SocVoltage[i]
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&& clock_table->DfPstateTable[j].FClk < min_fclk) {
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min_fclk = clock_table->DfPstateTable[j].FClk;
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min_pstate = j;
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}
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}
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/* dispclk and dppclk can be max at any voltage, same number of levels for both */
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if (clock_table->NumDispClkLevelsEnabled <= NUM_DISPCLK_DPM_LEVELS &&
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clock_table->NumDispClkLevelsEnabled <= NUM_DPPCLK_DPM_LEVELS) {
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max_dispclk = find_max_clk_value(clock_table->DispClocks, clock_table->NumDispClkLevelsEnabled);
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max_dppclk = find_max_clk_value(clock_table->DppClocks, clock_table->NumDispClkLevelsEnabled);
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} else {
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ASSERT(0);
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}
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for (i = 0; i < bw_params->clk_table.num_entries; i++, j--) {
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int temp;
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bw_params->clk_table.entries[i].fclk_mhz = clock_table->DfPstateTable[j].FClk;
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bw_params->clk_table.entries[i].memclk_mhz = clock_table->DfPstateTable[j].MemClk;
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bw_params->clk_table.entries[i].voltage = clock_table->DfPstateTable[j].Voltage;
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bw_params->clk_table.entries[i].wck_ratio = 1;
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temp = find_clk_for_voltage(clock_table, clock_table->DcfClocks, clock_table->DfPstateTable[j].Voltage);
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if (temp)
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bw_params->clk_table.entries[i].dcfclk_mhz = temp;
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temp = find_clk_for_voltage(clock_table, clock_table->SocClocks, clock_table->DfPstateTable[j].Voltage);
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-
if (temp)
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bw_params->clk_table.entries[i].socclk_mhz = temp;
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bw_params->clk_table.entries[i].fclk_mhz = min_fclk;
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bw_params->clk_table.entries[i].memclk_mhz = clock_table->DfPstateTable[min_pstate].MemClk;
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bw_params->clk_table.entries[i].voltage = clock_table->DfPstateTable[min_pstate].Voltage;
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bw_params->clk_table.entries[i].dcfclk_mhz = clock_table->DcfClocks[i];
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bw_params->clk_table.entries[i].socclk_mhz = clock_table->SocClocks[i];
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bw_params->clk_table.entries[i].dispclk_mhz = max_dispclk;
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bw_params->clk_table.entries[i].dppclk_mhz = max_dppclk;
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-
}
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bw_params->clk_table.entries[i].wck_ratio = 1;
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};
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/* Make sure to include at least one entry and highest pstate */
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if (max_pstate != min_pstate) {
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bw_params->clk_table.entries[i].fclk_mhz = max_fclk;
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bw_params->clk_table.entries[i].memclk_mhz = clock_table->DfPstateTable[max_pstate].MemClk;
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bw_params->clk_table.entries[i].voltage = clock_table->DfPstateTable[max_pstate].Voltage;
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bw_params->clk_table.entries[i].dcfclk_mhz = find_clk_for_voltage(
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clock_table, clock_table->DcfClocks, clock_table->DfPstateTable[max_pstate].Voltage);
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bw_params->clk_table.entries[i].socclk_mhz = find_clk_for_voltage(
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clock_table, clock_table->SocClocks, clock_table->DfPstateTable[max_pstate].Voltage);
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bw_params->clk_table.entries[i].dispclk_mhz = max_dispclk;
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bw_params->clk_table.entries[i].dppclk_mhz = max_dppclk;
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bw_params->clk_table.entries[i].wck_ratio = 1;
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i++;
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}
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bw_params->clk_table.num_entries = i;
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+
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/* Include highest socclk */
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if (bw_params->clk_table.entries[i-1].socclk_mhz < max_socclk)
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bw_params->clk_table.entries[i-1].socclk_mhz = max_socclk;
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+
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/* Set any 0 clocks to max default setting. Not an issue for
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* power since we aren't doing switching in such case anyway
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*/
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for (i = 0; i < bw_params->clk_table.num_entries; i++) {
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if (!bw_params->clk_table.entries[i].fclk_mhz) {
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bw_params->clk_table.entries[i].fclk_mhz = def_max.fclk_mhz;
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bw_params->clk_table.entries[i].memclk_mhz = def_max.memclk_mhz;
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bw_params->clk_table.entries[i].voltage = def_max.voltage;
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}
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if (!bw_params->clk_table.entries[i].dcfclk_mhz)
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bw_params->clk_table.entries[i].dcfclk_mhz = def_max.dcfclk_mhz;
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if (!bw_params->clk_table.entries[i].socclk_mhz)
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bw_params->clk_table.entries[i].socclk_mhz = def_max.socclk_mhz;
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if (!bw_params->clk_table.entries[i].dispclk_mhz)
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bw_params->clk_table.entries[i].dispclk_mhz = def_max.dispclk_mhz;
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if (!bw_params->clk_table.entries[i].dppclk_mhz)
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bw_params->clk_table.entries[i].dppclk_mhz = def_max.dppclk_mhz;
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}
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bw_params->vram_type = bios_info->memory_type;
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bw_params->num_channels = bios_info->ma_channel_number;
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