tjh.dev / kernel
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Merge tag 'pinctrl-v5.19-3' of git://git.kernel.org/pub/scm/linux/kernel/git/linusw/linux-pinctrl

Pull pin control fixes from Linus Walleij:
"Only driver fixes:

- NULL check for the ralink and sunplus drivers

- Add Jacky Bai as maintainer for the Freescale pin controllers

- Fix pin config ops for the Ocelot LAN966x and SparX5

- Disallow AMD pin control to be a module: the GPIO lines need to be
active in early boot, so no can do

- Fix the Armada 37xx to use raw spinlocks in the interrupt handler
path to avoid wait context"

* tag 'pinctrl-v5.19-3' of git://git.kernel.org/pub/scm/linux/kernel/git/linusw/linux-pinctrl:
pinctrl: armada-37xx: use raw spinlocks for regmap to avoid invalid wait context
pinctrl: armada-37xx: make irq_lock a raw spinlock to avoid invalid wait context
pinctrl: Don't allow PINCTRL_AMD to be a module
pinctrl: ocelot: Fix pincfg
pinctrl: ocelot: Fix pincfg for lan966x
MAINTAINERS: Update freescale pin controllers maintainer
pinctrl: sunplus: Add check for kcalloc
pinctrl: ralink: Check for null return of devm_kcalloc

Linus Torvalds 61471911 8f636c6a

+184 -104
+1 -1
MAINTAINERS
··· 15849 15849 M: Dong Aisheng <aisheng.dong@nxp.com> 15850 15850 M: Fabio Estevam <festevam@gmail.com> 15851 15851 M: Shawn Guo <shawnguo@kernel.org> 15852 - M: Stefan Agner <stefan@agner.ch> 15852 + M: Jacky Bai <ping.bai@nxp.com> 15853 15853 R: Pengutronix Kernel Team <kernel@pengutronix.de> 15854 15854 L: linux-gpio@vger.kernel.org 15855 15855 S: Maintained
+1 -1
drivers/pinctrl/Kconfig
··· 32 32 Say Y here to add some extra checks and diagnostics to PINCTRL calls. 33 33 34 34 config PINCTRL_AMD 35 - tristate "AMD GPIO pin control" 35 + bool "AMD GPIO pin control" 36 36 depends on HAS_IOMEM 37 37 depends on ACPI || COMPILE_TEST 38 38 select GPIOLIB
+40 -25
drivers/pinctrl/mvebu/pinctrl-armada-37xx.c
··· 102 102 struct device *dev; 103 103 struct gpio_chip gpio_chip; 104 104 struct irq_chip irq_chip; 105 - spinlock_t irq_lock; 105 + raw_spinlock_t irq_lock; 106 106 struct pinctrl_desc pctl; 107 107 struct pinctrl_dev *pctl_dev; 108 108 struct armada_37xx_pin_group *groups; ··· 523 523 unsigned long flags; 524 524 525 525 armada_37xx_irq_update_reg(&reg, d); 526 - spin_lock_irqsave(&info->irq_lock, flags); 526 + raw_spin_lock_irqsave(&info->irq_lock, flags); 527 527 writel(d->mask, info->base + reg); 528 - spin_unlock_irqrestore(&info->irq_lock, flags); 528 + raw_spin_unlock_irqrestore(&info->irq_lock, flags); 529 529 } 530 530 531 531 static void armada_37xx_irq_mask(struct irq_data *d) ··· 536 536 unsigned long flags; 537 537 538 538 armada_37xx_irq_update_reg(&reg, d); 539 - spin_lock_irqsave(&info->irq_lock, flags); 539 + raw_spin_lock_irqsave(&info->irq_lock, flags); 540 540 val = readl(info->base + reg); 541 541 writel(val & ~d->mask, info->base + reg); 542 - spin_unlock_irqrestore(&info->irq_lock, flags); 542 + raw_spin_unlock_irqrestore(&info->irq_lock, flags); 543 543 } 544 544 545 545 static void armada_37xx_irq_unmask(struct irq_data *d) ··· 550 550 unsigned long flags; 551 551 552 552 armada_37xx_irq_update_reg(&reg, d); 553 - spin_lock_irqsave(&info->irq_lock, flags); 553 + raw_spin_lock_irqsave(&info->irq_lock, flags); 554 554 val = readl(info->base + reg); 555 555 writel(val | d->mask, info->base + reg); 556 - spin_unlock_irqrestore(&info->irq_lock, flags); 556 + raw_spin_unlock_irqrestore(&info->irq_lock, flags); 557 557 } 558 558 559 559 static int armada_37xx_irq_set_wake(struct irq_data *d, unsigned int on) ··· 564 564 unsigned long flags; 565 565 566 566 armada_37xx_irq_update_reg(&reg, d); 567 - spin_lock_irqsave(&info->irq_lock, flags); 567 + raw_spin_lock_irqsave(&info->irq_lock, flags); 568 568 val = readl(info->base + reg); 569 569 if (on) 570 570 val |= (BIT(d->hwirq % GPIO_PER_REG)); 571 571 else 572 572 val &= ~(BIT(d->hwirq % GPIO_PER_REG)); 573 573 writel(val, info->base + reg); 574 - spin_unlock_irqrestore(&info->irq_lock, flags); 574 + raw_spin_unlock_irqrestore(&info->irq_lock, flags); 575 575 576 576 return 0; 577 577 } ··· 583 583 u32 val, reg = IRQ_POL; 584 584 unsigned long flags; 585 585 586 - spin_lock_irqsave(&info->irq_lock, flags); 586 + raw_spin_lock_irqsave(&info->irq_lock, flags); 587 587 armada_37xx_irq_update_reg(&reg, d); 588 588 val = readl(info->base + reg); 589 589 switch (type) { ··· 607 607 break; 608 608 } 609 609 default: 610 - spin_unlock_irqrestore(&info->irq_lock, flags); 610 + raw_spin_unlock_irqrestore(&info->irq_lock, flags); 611 611 return -EINVAL; 612 612 } 613 613 writel(val, info->base + reg); 614 - spin_unlock_irqrestore(&info->irq_lock, flags); 614 + raw_spin_unlock_irqrestore(&info->irq_lock, flags); 615 615 616 616 return 0; 617 617 } ··· 626 626 627 627 regmap_read(info->regmap, INPUT_VAL + 4*reg_idx, &l); 628 628 629 - spin_lock_irqsave(&info->irq_lock, flags); 629 + raw_spin_lock_irqsave(&info->irq_lock, flags); 630 630 p = readl(info->base + IRQ_POL + 4 * reg_idx); 631 631 if ((p ^ l) & (1 << bit_num)) { 632 632 /* ··· 647 647 ret = -1; 648 648 } 649 649 650 - spin_unlock_irqrestore(&info->irq_lock, flags); 650 + raw_spin_unlock_irqrestore(&info->irq_lock, flags); 651 651 return ret; 652 652 } 653 653 ··· 664 664 u32 status; 665 665 unsigned long flags; 666 666 667 - spin_lock_irqsave(&info->irq_lock, flags); 667 + raw_spin_lock_irqsave(&info->irq_lock, flags); 668 668 status = readl_relaxed(info->base + IRQ_STATUS + 4 * i); 669 669 /* Manage only the interrupt that was enabled */ 670 670 status &= readl_relaxed(info->base + IRQ_EN + 4 * i); 671 - spin_unlock_irqrestore(&info->irq_lock, flags); 671 + raw_spin_unlock_irqrestore(&info->irq_lock, flags); 672 672 while (status) { 673 673 u32 hwirq = ffs(status) - 1; 674 674 u32 virq = irq_find_mapping(d, hwirq + ··· 695 695 696 696 update_status: 697 697 /* Update status in case a new IRQ appears */ 698 - spin_lock_irqsave(&info->irq_lock, flags); 698 + raw_spin_lock_irqsave(&info->irq_lock, flags); 699 699 status = readl_relaxed(info->base + 700 700 IRQ_STATUS + 4 * i); 701 701 /* Manage only the interrupt that was enabled */ 702 702 status &= readl_relaxed(info->base + IRQ_EN + 4 * i); 703 - spin_unlock_irqrestore(&info->irq_lock, flags); 703 + raw_spin_unlock_irqrestore(&info->irq_lock, flags); 704 704 } 705 705 } 706 706 chained_irq_exit(chip, desc); ··· 731 731 struct device *dev = &pdev->dev; 732 732 unsigned int i, nr_irq_parent; 733 733 734 - spin_lock_init(&info->irq_lock); 734 + raw_spin_lock_init(&info->irq_lock); 735 735 736 736 nr_irq_parent = of_irq_count(np); 737 737 if (!nr_irq_parent) { ··· 1107 1107 { }, 1108 1108 }; 1109 1109 1110 + static const struct regmap_config armada_37xx_pinctrl_regmap_config = { 1111 + .reg_bits = 32, 1112 + .val_bits = 32, 1113 + .reg_stride = 4, 1114 + .use_raw_spinlock = true, 1115 + }; 1116 + 1110 1117 static int __init armada_37xx_pinctrl_probe(struct platform_device *pdev) 1111 1118 { 1112 1119 struct armada_37xx_pinctrl *info; 1113 1120 struct device *dev = &pdev->dev; 1114 - struct device_node *np = dev->of_node; 1115 1121 struct regmap *regmap; 1122 + void __iomem *base; 1116 1123 int ret; 1124 + 1125 + base = devm_platform_get_and_ioremap_resource(pdev, 0, NULL); 1126 + if (IS_ERR(base)) { 1127 + dev_err(dev, "failed to ioremap base address: %pe\n", base); 1128 + return PTR_ERR(base); 1129 + } 1130 + 1131 + regmap = devm_regmap_init_mmio(dev, base, 1132 + &armada_37xx_pinctrl_regmap_config); 1133 + if (IS_ERR(regmap)) { 1134 + dev_err(dev, "failed to create regmap: %pe\n", regmap); 1135 + return PTR_ERR(regmap); 1136 + } 1117 1137 1118 1138 info = devm_kzalloc(dev, sizeof(*info), GFP_KERNEL); 1119 1139 if (!info) 1120 1140 return -ENOMEM; 1121 1141 1122 1142 info->dev = dev; 1123 - 1124 - regmap = syscon_node_to_regmap(np); 1125 - if (IS_ERR(regmap)) 1126 - return dev_err_probe(dev, PTR_ERR(regmap), "cannot get regmap\n"); 1127 1143 info->regmap = regmap; 1128 - 1129 1144 info->data = of_device_get_match_data(dev); 1130 1145 1131 1146 ret = armada_37xx_pinctrl_register(pdev, info);
+137 -77
drivers/pinctrl/pinctrl-ocelot.c
··· 29 29 #define ocelot_clrsetbits(addr, clear, set) \ 30 30 writel((readl(addr) & ~(clear)) | (set), (addr)) 31 31 32 - /* PINCONFIG bits (sparx5 only) */ 33 32 enum { 34 33 PINCONF_BIAS, 35 34 PINCONF_SCHMITT, 36 35 PINCONF_DRIVE_STRENGTH, 37 36 }; 38 - 39 - #define BIAS_PD_BIT BIT(4) 40 - #define BIAS_PU_BIT BIT(3) 41 - #define BIAS_BITS (BIAS_PD_BIT|BIAS_PU_BIT) 42 - #define SCHMITT_BIT BIT(2) 43 - #define DRIVE_BITS GENMASK(1, 0) 44 37 45 38 /* GPIO standard registers */ 46 39 #define OCELOT_GPIO_OUT_SET 0x0 ··· 314 321 unsigned char a_functions[OCELOT_FUNC_PER_PIN]; /* Additional functions */ 315 322 }; 316 323 324 + struct ocelot_pincfg_data { 325 + u8 pd_bit; 326 + u8 pu_bit; 327 + u8 drive_bits; 328 + u8 schmitt_bit; 329 + }; 330 + 317 331 struct ocelot_pinctrl { 318 332 struct device *dev; 319 333 struct pinctrl_dev *pctl; ··· 328 328 struct regmap *map; 329 329 struct regmap *pincfg; 330 330 struct pinctrl_desc *desc; 331 + const struct ocelot_pincfg_data *pincfg_data; 331 332 struct ocelot_pmx_func func[FUNC_MAX]; 332 333 u8 stride; 334 + }; 335 + 336 + struct ocelot_match_data { 337 + struct pinctrl_desc desc; 338 + struct ocelot_pincfg_data pincfg_data; 333 339 }; 334 340 335 341 #define LUTON_P(p, f0, f1) \ ··· 1331 1325 int ret = -EOPNOTSUPP; 1332 1326 1333 1327 if (info->pincfg) { 1328 + const struct ocelot_pincfg_data *opd = info->pincfg_data; 1334 1329 u32 regcfg; 1335 1330 1336 - ret = regmap_read(info->pincfg, pin, &regcfg); 1331 + ret = regmap_read(info->pincfg, 1332 + pin * regmap_get_reg_stride(info->pincfg), 1333 + &regcfg); 1337 1334 if (ret) 1338 1335 return ret; 1339 1336 1340 1337 ret = 0; 1341 1338 switch (reg) { 1342 1339 case PINCONF_BIAS: 1343 - *val = regcfg & BIAS_BITS; 1340 + *val = regcfg & (opd->pd_bit | opd->pu_bit); 1344 1341 break; 1345 1342 1346 1343 case PINCONF_SCHMITT: 1347 - *val = regcfg & SCHMITT_BIT; 1344 + *val = regcfg & opd->schmitt_bit; 1348 1345 break; 1349 1346 1350 1347 case PINCONF_DRIVE_STRENGTH: 1351 - *val = regcfg & DRIVE_BITS; 1348 + *val = regcfg & opd->drive_bits; 1352 1349 break; 1353 1350 1354 1351 default: ··· 1368 1359 u32 val; 1369 1360 int ret; 1370 1361 1371 - ret = regmap_read(info->pincfg, regaddr, &val); 1362 + ret = regmap_read(info->pincfg, 1363 + regaddr * regmap_get_reg_stride(info->pincfg), 1364 + &val); 1372 1365 if (ret) 1373 1366 return ret; 1374 1367 1375 1368 val &= ~clrbits; 1376 1369 val |= setbits; 1377 1370 1378 - ret = regmap_write(info->pincfg, regaddr, val); 1371 + ret = regmap_write(info->pincfg, 1372 + regaddr * regmap_get_reg_stride(info->pincfg), 1373 + val); 1379 1374 1380 1375 return ret; 1381 1376 } ··· 1392 1379 int ret = -EOPNOTSUPP; 1393 1380 1394 1381 if (info->pincfg) { 1382 + const struct ocelot_pincfg_data *opd = info->pincfg_data; 1395 1383 1396 1384 ret = 0; 1397 1385 switch (reg) { 1398 1386 case PINCONF_BIAS: 1399 - ret = ocelot_pincfg_clrsetbits(info, pin, BIAS_BITS, 1387 + ret = ocelot_pincfg_clrsetbits(info, pin, 1388 + opd->pd_bit | opd->pu_bit, 1400 1389 val); 1401 1390 break; 1402 1391 1403 1392 case PINCONF_SCHMITT: 1404 - ret = ocelot_pincfg_clrsetbits(info, pin, SCHMITT_BIT, 1393 + ret = ocelot_pincfg_clrsetbits(info, pin, 1394 + opd->schmitt_bit, 1405 1395 val); 1406 1396 break; 1407 1397 1408 1398 case PINCONF_DRIVE_STRENGTH: 1409 1399 if (val <= 3) 1410 1400 ret = ocelot_pincfg_clrsetbits(info, pin, 1411 - DRIVE_BITS, val); 1401 + opd->drive_bits, 1402 + val); 1412 1403 else 1413 1404 ret = -EINVAL; 1414 1405 break; ··· 1442 1425 if (param == PIN_CONFIG_BIAS_DISABLE) 1443 1426 val = (val == 0); 1444 1427 else if (param == PIN_CONFIG_BIAS_PULL_DOWN) 1445 - val = (val & BIAS_PD_BIT ? true : false); 1428 + val = !!(val & info->pincfg_data->pd_bit); 1446 1429 else /* PIN_CONFIG_BIAS_PULL_UP */ 1447 - val = (val & BIAS_PU_BIT ? true : false); 1430 + val = !!(val & info->pincfg_data->pu_bit); 1448 1431 break; 1449 1432 1450 1433 case PIN_CONFIG_INPUT_SCHMITT_ENABLE: 1434 + if (!info->pincfg_data->schmitt_bit) 1435 + return -EOPNOTSUPP; 1436 + 1451 1437 err = ocelot_hw_get_value(info, pin, PINCONF_SCHMITT, &val); 1452 1438 if (err) 1453 1439 return err; 1454 1440 1455 - val = (val & SCHMITT_BIT ? true : false); 1441 + val = !!(val & info->pincfg_data->schmitt_bit); 1456 1442 break; 1457 1443 1458 1444 case PIN_CONFIG_DRIVE_STRENGTH: ··· 1499 1479 unsigned long *configs, unsigned int num_configs) 1500 1480 { 1501 1481 struct ocelot_pinctrl *info = pinctrl_dev_get_drvdata(pctldev); 1482 + const struct ocelot_pincfg_data *opd = info->pincfg_data; 1502 1483 u32 param, arg, p; 1503 1484 int cfg, err = 0; 1504 1485 ··· 1512 1491 case PIN_CONFIG_BIAS_PULL_UP: 1513 1492 case PIN_CONFIG_BIAS_PULL_DOWN: 1514 1493 arg = (param == PIN_CONFIG_BIAS_DISABLE) ? 0 : 1515 - (param == PIN_CONFIG_BIAS_PULL_UP) ? BIAS_PU_BIT : 1516 - BIAS_PD_BIT; 1494 + (param == PIN_CONFIG_BIAS_PULL_UP) ? 1495 + opd->pu_bit : opd->pd_bit; 1517 1496 1518 1497 err = ocelot_hw_set_value(info, pin, PINCONF_BIAS, arg); 1519 1498 if (err) ··· 1522 1501 break; 1523 1502 1524 1503 case PIN_CONFIG_INPUT_SCHMITT_ENABLE: 1525 - arg = arg ? SCHMITT_BIT : 0; 1504 + if (!opd->schmitt_bit) 1505 + return -EOPNOTSUPP; 1506 + 1507 + arg = arg ? opd->schmitt_bit : 0; 1526 1508 err = ocelot_hw_set_value(info, pin, PINCONF_SCHMITT, 1527 1509 arg); 1528 1510 if (err) ··· 1586 1562 .dt_free_map = pinconf_generic_dt_free_map, 1587 1563 }; 1588 1564 1589 - static struct pinctrl_desc luton_desc = { 1590 - .name = "luton-pinctrl", 1591 - .pins = luton_pins, 1592 - .npins = ARRAY_SIZE(luton_pins), 1593 - .pctlops = &ocelot_pctl_ops, 1594 - .pmxops = &ocelot_pmx_ops, 1595 - .owner = THIS_MODULE, 1565 + static struct ocelot_match_data luton_desc = { 1566 + .desc = { 1567 + .name = "luton-pinctrl", 1568 + .pins = luton_pins, 1569 + .npins = ARRAY_SIZE(luton_pins), 1570 + .pctlops = &ocelot_pctl_ops, 1571 + .pmxops = &ocelot_pmx_ops, 1572 + .owner = THIS_MODULE, 1573 + }, 1596 1574 }; 1597 1575 1598 - static struct pinctrl_desc serval_desc = { 1599 - .name = "serval-pinctrl", 1600 - .pins = serval_pins, 1601 - .npins = ARRAY_SIZE(serval_pins), 1602 - .pctlops = &ocelot_pctl_ops, 1603 - .pmxops = &ocelot_pmx_ops, 1604 - .owner = THIS_MODULE, 1576 + static struct ocelot_match_data serval_desc = { 1577 + .desc = { 1578 + .name = "serval-pinctrl", 1579 + .pins = serval_pins, 1580 + .npins = ARRAY_SIZE(serval_pins), 1581 + .pctlops = &ocelot_pctl_ops, 1582 + .pmxops = &ocelot_pmx_ops, 1583 + .owner = THIS_MODULE, 1584 + }, 1605 1585 }; 1606 1586 1607 - static struct pinctrl_desc ocelot_desc = { 1608 - .name = "ocelot-pinctrl", 1609 - .pins = ocelot_pins, 1610 - .npins = ARRAY_SIZE(ocelot_pins), 1611 - .pctlops = &ocelot_pctl_ops, 1612 - .pmxops = &ocelot_pmx_ops, 1613 - .owner = THIS_MODULE, 1587 + static struct ocelot_match_data ocelot_desc = { 1588 + .desc = { 1589 + .name = "ocelot-pinctrl", 1590 + .pins = ocelot_pins, 1591 + .npins = ARRAY_SIZE(ocelot_pins), 1592 + .pctlops = &ocelot_pctl_ops, 1593 + .pmxops = &ocelot_pmx_ops, 1594 + .owner = THIS_MODULE, 1595 + }, 1614 1596 }; 1615 1597 1616 - static struct pinctrl_desc jaguar2_desc = { 1617 - .name = "jaguar2-pinctrl", 1618 - .pins = jaguar2_pins, 1619 - .npins = ARRAY_SIZE(jaguar2_pins), 1620 - .pctlops = &ocelot_pctl_ops, 1621 - .pmxops = &ocelot_pmx_ops, 1622 - .owner = THIS_MODULE, 1598 + static struct ocelot_match_data jaguar2_desc = { 1599 + .desc = { 1600 + .name = "jaguar2-pinctrl", 1601 + .pins = jaguar2_pins, 1602 + .npins = ARRAY_SIZE(jaguar2_pins), 1603 + .pctlops = &ocelot_pctl_ops, 1604 + .pmxops = &ocelot_pmx_ops, 1605 + .owner = THIS_MODULE, 1606 + }, 1623 1607 }; 1624 1608 1625 - static struct pinctrl_desc servalt_desc = { 1626 - .name = "servalt-pinctrl", 1627 - .pins = servalt_pins, 1628 - .npins = ARRAY_SIZE(servalt_pins), 1629 - .pctlops = &ocelot_pctl_ops, 1630 - .pmxops = &ocelot_pmx_ops, 1631 - .owner = THIS_MODULE, 1609 + static struct ocelot_match_data servalt_desc = { 1610 + .desc = { 1611 + .name = "servalt-pinctrl", 1612 + .pins = servalt_pins, 1613 + .npins = ARRAY_SIZE(servalt_pins), 1614 + .pctlops = &ocelot_pctl_ops, 1615 + .pmxops = &ocelot_pmx_ops, 1616 + .owner = THIS_MODULE, 1617 + }, 1632 1618 }; 1633 1619 1634 - static struct pinctrl_desc sparx5_desc = { 1635 - .name = "sparx5-pinctrl", 1636 - .pins = sparx5_pins, 1637 - .npins = ARRAY_SIZE(sparx5_pins), 1638 - .pctlops = &ocelot_pctl_ops, 1639 - .pmxops = &ocelot_pmx_ops, 1640 - .confops = &ocelot_confops, 1641 - .owner = THIS_MODULE, 1620 + static struct ocelot_match_data sparx5_desc = { 1621 + .desc = { 1622 + .name = "sparx5-pinctrl", 1623 + .pins = sparx5_pins, 1624 + .npins = ARRAY_SIZE(sparx5_pins), 1625 + .pctlops = &ocelot_pctl_ops, 1626 + .pmxops = &ocelot_pmx_ops, 1627 + .confops = &ocelot_confops, 1628 + .owner = THIS_MODULE, 1629 + }, 1630 + .pincfg_data = { 1631 + .pd_bit = BIT(4), 1632 + .pu_bit = BIT(3), 1633 + .drive_bits = GENMASK(1, 0), 1634 + .schmitt_bit = BIT(2), 1635 + }, 1642 1636 }; 1643 1637 1644 - static struct pinctrl_desc lan966x_desc = { 1645 - .name = "lan966x-pinctrl", 1646 - .pins = lan966x_pins, 1647 - .npins = ARRAY_SIZE(lan966x_pins), 1648 - .pctlops = &ocelot_pctl_ops, 1649 - .pmxops = &lan966x_pmx_ops, 1650 - .confops = &ocelot_confops, 1651 - .owner = THIS_MODULE, 1638 + static struct ocelot_match_data lan966x_desc = { 1639 + .desc = { 1640 + .name = "lan966x-pinctrl", 1641 + .pins = lan966x_pins, 1642 + .npins = ARRAY_SIZE(lan966x_pins), 1643 + .pctlops = &ocelot_pctl_ops, 1644 + .pmxops = &lan966x_pmx_ops, 1645 + .confops = &ocelot_confops, 1646 + .owner = THIS_MODULE, 1647 + }, 1648 + .pincfg_data = { 1649 + .pd_bit = BIT(3), 1650 + .pu_bit = BIT(2), 1651 + .drive_bits = GENMASK(1, 0), 1652 + }, 1652 1653 }; 1653 1654 1654 1655 static int ocelot_create_group_func_map(struct device *dev, ··· 1939 1890 {}, 1940 1891 }; 1941 1892 1942 - static struct regmap *ocelot_pinctrl_create_pincfg(struct platform_device *pdev) 1893 + static struct regmap *ocelot_pinctrl_create_pincfg(struct platform_device *pdev, 1894 + const struct ocelot_pinctrl *info) 1943 1895 { 1944 1896 void __iomem *base; 1945 1897 ··· 1948 1898 .reg_bits = 32, 1949 1899 .val_bits = 32, 1950 1900 .reg_stride = 4, 1951 - .max_register = 32, 1901 + .max_register = info->desc->npins * 4, 1952 1902 .name = "pincfg", 1953 1903 }; 1954 1904 ··· 1963 1913 1964 1914 static int ocelot_pinctrl_probe(struct platform_device *pdev) 1965 1915 { 1916 + const struct ocelot_match_data *data; 1966 1917 struct device *dev = &pdev->dev; 1967 1918 struct ocelot_pinctrl *info; 1968 1919 struct reset_control *reset; ··· 1980 1929 if (!info) 1981 1930 return -ENOMEM; 1982 1931 1983 - info->desc = (struct pinctrl_desc *)device_get_match_data(dev); 1932 + data = device_get_match_data(dev); 1933 + if (!data) 1934 + return -EINVAL; 1935 + 1936 + info->desc = devm_kmemdup(dev, &data->desc, sizeof(*info->desc), 1937 + GFP_KERNEL); 1938 + if (!info->desc) 1939 + return -ENOMEM; 1940 + 1941 + info->pincfg_data = &data->pincfg_data; 1984 1942 1985 1943 reset = devm_reset_control_get_optional_shared(dev, "switch"); 1986 1944 if (IS_ERR(reset)) ··· 2016 1956 2017 1957 /* Pinconf registers */ 2018 1958 if (info->desc->confops) { 2019 - pincfg = ocelot_pinctrl_create_pincfg(pdev); 1959 + pincfg = ocelot_pinctrl_create_pincfg(pdev, info); 2020 1960 if (IS_ERR(pincfg)) 2021 1961 dev_dbg(dev, "Failed to create pincfg regmap\n"); 2022 1962 else
+2
drivers/pinctrl/ralink/pinctrl-ralink.c
··· 266 266 p->func[i]->pin_count, 267 267 sizeof(int), 268 268 GFP_KERNEL); 269 + if (!p->func[i]->pins) 270 + return -ENOMEM; 269 271 for (j = 0; j < p->func[i]->pin_count; j++) 270 272 p->func[i]->pins[j] = p->func[i]->pin_first + j; 271 273
+3
drivers/pinctrl/sunplus/sppctl.c
··· 871 871 } 872 872 873 873 *map = kcalloc(*num_maps + nmG, sizeof(**map), GFP_KERNEL); 874 + if (*map == NULL) 875 + return -ENOMEM; 876 + 874 877 for (i = 0; i < (*num_maps); i++) { 875 878 dt_pin = be32_to_cpu(list[i]); 876 879 pin_num = FIELD_GET(GENMASK(31, 24), dt_pin);