tjh.dev / kernel
Linux kernel mirror (for testing) git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git
kernel os linux
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Merge tag 'intel-pinctrl-v6.19-1' of git://git.kernel.org/pub/scm/linux/kernel/git/pinctrl/intel into devel

intel-pinctrl for v6.19-1

* Add and use common macro INTEL_GPP() to avoid duplication
* Export intel_gpio_add_pin_ranges() and reuse it instead of custom copies
* Unify error messages with help of dev_err_probe()

Signed-off-by: Linus Walleij <linus.walleij@linaro.org>

Linus Walleij 6156424a ebd61482

+319 -451
+30 -38
drivers/pinctrl/intel/pinctrl-alderlake.c
··· 27 27 #define ADL_S_GPI_IS 0x200 28 28 #define ADL_S_GPI_IE 0x220 29 29 30 - #define ADL_GPP(r, s, e, g) \ 31 - { \ 32 - .reg_num = (r), \ 33 - .base = (s), \ 34 - .size = ((e) - (s) + 1), \ 35 - .gpio_base = (g), \ 36 - } 37 - 38 30 #define ADL_N_COMMUNITY(b, s, e, g) \ 39 31 INTEL_COMMUNITY_GPPS(b, s, e, g, ADL_N) 40 32 ··· 308 316 }; 309 317 310 318 static const struct intel_padgroup adln_community0_gpps[] = { 311 - ADL_GPP(0, 0, 25, 0), /* GPP_B */ 312 - ADL_GPP(1, 26, 41, 32), /* GPP_T */ 313 - ADL_GPP(2, 42, 66, 64), /* GPP_A */ 319 + INTEL_GPP(0, 0, 25, 0), /* GPP_B */ 320 + INTEL_GPP(1, 26, 41, 32), /* GPP_T */ 321 + INTEL_GPP(2, 42, 66, 64), /* GPP_A */ 314 322 }; 315 323 316 324 static const struct intel_padgroup adln_community1_gpps[] = { 317 - ADL_GPP(0, 67, 74, 96), /* GPP_S */ 318 - ADL_GPP(1, 75, 94, 128), /* GPP_I */ 319 - ADL_GPP(2, 95, 118, 160), /* GPP_H */ 320 - ADL_GPP(3, 119, 139, 192), /* GPP_D */ 321 - ADL_GPP(4, 140, 168, 224), /* vGPIO */ 325 + INTEL_GPP(0, 67, 74, 96), /* GPP_S */ 326 + INTEL_GPP(1, 75, 94, 128), /* GPP_I */ 327 + INTEL_GPP(2, 95, 118, 160), /* GPP_H */ 328 + INTEL_GPP(3, 119, 139, 192), /* GPP_D */ 329 + INTEL_GPP(4, 140, 168, 224), /* vGPIO */ 322 330 }; 323 331 324 332 static const struct intel_padgroup adln_community4_gpps[] = { 325 - ADL_GPP(0, 169, 192, 256), /* GPP_C */ 326 - ADL_GPP(1, 193, 217, 288), /* GPP_F */ 327 - ADL_GPP(2, 218, 223, INTEL_GPIO_BASE_NOMAP), /* HVCMOS */ 328 - ADL_GPP(3, 224, 248, 320), /* GPP_E */ 333 + INTEL_GPP(0, 169, 192, 256), /* GPP_C */ 334 + INTEL_GPP(1, 193, 217, 288), /* GPP_F */ 335 + INTEL_GPP(2, 218, 223, INTEL_GPIO_BASE_NOMAP), /* HVCMOS */ 336 + INTEL_GPP(3, 224, 248, 320), /* GPP_E */ 329 337 }; 330 338 331 339 static const struct intel_padgroup adln_community5_gpps[] = { 332 - ADL_GPP(0, 249, 256, 352), /* GPP_R */ 340 + INTEL_GPP(0, 249, 256, 352), /* GPP_R */ 333 341 }; 334 342 335 343 static const struct intel_community adln_communities[] = { ··· 672 680 }; 673 681 674 682 static const struct intel_padgroup adls_community0_gpps[] = { 675 - ADL_GPP(0, 0, 24, 0), /* GPP_I */ 676 - ADL_GPP(1, 25, 47, 32), /* GPP_R */ 677 - ADL_GPP(2, 48, 59, 64), /* GPP_J */ 678 - ADL_GPP(3, 60, 86, 96), /* vGPIO */ 679 - ADL_GPP(4, 87, 94, 128), /* vGPIO_0 */ 683 + INTEL_GPP(0, 0, 24, 0), /* GPP_I */ 684 + INTEL_GPP(1, 25, 47, 32), /* GPP_R */ 685 + INTEL_GPP(2, 48, 59, 64), /* GPP_J */ 686 + INTEL_GPP(3, 60, 86, 96), /* vGPIO */ 687 + INTEL_GPP(4, 87, 94, 128), /* vGPIO_0 */ 680 688 }; 681 689 682 690 static const struct intel_padgroup adls_community1_gpps[] = { 683 - ADL_GPP(0, 95, 118, 160), /* GPP_B */ 684 - ADL_GPP(1, 119, 126, 192), /* GPP_G */ 685 - ADL_GPP(2, 127, 150, 224), /* GPP_H */ 691 + INTEL_GPP(0, 95, 118, 160), /* GPP_B */ 692 + INTEL_GPP(1, 119, 126, 192), /* GPP_G */ 693 + INTEL_GPP(2, 127, 150, 224), /* GPP_H */ 686 694 }; 687 695 688 696 static const struct intel_padgroup adls_community3_gpps[] = { 689 - ADL_GPP(0, 151, 159, INTEL_GPIO_BASE_NOMAP), /* SPI0 */ 690 - ADL_GPP(1, 160, 175, 256), /* GPP_A */ 691 - ADL_GPP(2, 176, 199, 288), /* GPP_C */ 697 + INTEL_GPP(0, 151, 159, INTEL_GPIO_BASE_NOMAP), /* SPI0 */ 698 + INTEL_GPP(1, 160, 175, 256), /* GPP_A */ 699 + INTEL_GPP(2, 176, 199, 288), /* GPP_C */ 692 700 }; 693 701 694 702 static const struct intel_padgroup adls_community4_gpps[] = { 695 - ADL_GPP(0, 200, 207, 320), /* GPP_S */ 696 - ADL_GPP(1, 208, 230, 352), /* GPP_E */ 697 - ADL_GPP(2, 231, 245, 384), /* GPP_K */ 698 - ADL_GPP(3, 246, 269, 416), /* GPP_F */ 703 + INTEL_GPP(0, 200, 207, 320), /* GPP_S */ 704 + INTEL_GPP(1, 208, 230, 352), /* GPP_E */ 705 + INTEL_GPP(2, 231, 245, 384), /* GPP_K */ 706 + INTEL_GPP(3, 246, 269, 416), /* GPP_F */ 699 707 }; 700 708 701 709 static const struct intel_padgroup adls_community5_gpps[] = { 702 - ADL_GPP(0, 270, 294, 448), /* GPP_D */ 703 - ADL_GPP(1, 295, 303, INTEL_GPIO_BASE_NOMAP), /* JTAG */ 710 + INTEL_GPP(0, 270, 294, 448), /* GPP_D */ 711 + INTEL_GPP(1, 295, 303, INTEL_GPIO_BASE_NOMAP), /* JTAG */ 704 712 }; 705 713 706 714 static const struct intel_community adls_communities[] = {
+8 -12
drivers/pinctrl/intel/pinctrl-baytrail.c
··· 1498 1498 1499 1499 ret = gpiochip_add_pin_range(chip, dev_name(dev), 0, 0, vg->soc->npins); 1500 1500 if (ret) 1501 - dev_err(dev, "failed to add GPIO pin range\n"); 1501 + return dev_err_probe(dev, ret, "failed to add GPIO pin range\n"); 1502 1502 1503 - return ret; 1503 + return 0; 1504 1504 } 1505 1505 1506 1506 static int byt_gpio_probe(struct intel_pinctrl *vg) ··· 1548 1548 1549 1549 ret = devm_gpiochip_add_data(vg->dev, gc, vg); 1550 1550 if (ret) 1551 - dev_err(vg->dev, "failed adding byt-gpio chip\n"); 1551 + return dev_err_probe(vg->dev, ret, "failed to register gpiochip\n"); 1552 1552 1553 - return ret; 1553 + return 0; 1554 1554 } 1555 1555 1556 1556 static int byt_set_soc_data(struct intel_pinctrl *vg, ··· 1601 1601 1602 1602 vg->dev = dev; 1603 1603 ret = byt_set_soc_data(vg, soc_data); 1604 - if (ret) { 1605 - dev_err(dev, "failed to set soc data\n"); 1606 - return ret; 1607 - } 1604 + if (ret) 1605 + return dev_err_probe(dev, ret, "failed to set soc data\n"); 1608 1606 1609 1607 vg->pctldesc = byt_pinctrl_desc; 1610 1608 vg->pctldesc.name = dev_name(dev); ··· 1610 1612 vg->pctldesc.npins = vg->soc->npins; 1611 1613 1612 1614 vg->pctldev = devm_pinctrl_register(dev, &vg->pctldesc, vg); 1613 - if (IS_ERR(vg->pctldev)) { 1614 - dev_err(dev, "failed to register pinctrl driver\n"); 1615 - return PTR_ERR(vg->pctldev); 1616 - } 1615 + if (IS_ERR(vg->pctldev)) 1616 + return dev_err_probe(dev, PTR_ERR(vg->pctldev), "failed to register pinctrl\n"); 1617 1617 1618 1618 ret = byt_gpio_probe(vg); 1619 1619 if (ret)
+30 -38
drivers/pinctrl/intel/pinctrl-cannonlake.c
··· 28 28 #define CNL_H_GPI_IS 0x100 29 29 #define CNL_H_GPI_IE 0x120 30 30 31 - #define CNL_GPP(r, s, e, g) \ 32 - { \ 33 - .reg_num = (r), \ 34 - .base = (s), \ 35 - .size = ((e) - (s) + 1), \ 36 - .gpio_base = (g), \ 37 - } 38 - 39 31 #define CNL_LP_COMMUNITY(b, s, e, g) \ 40 32 INTEL_COMMUNITY_GPPS(b, s, e, g, CNL_LP) 41 33 ··· 354 362 }; 355 363 356 364 static const struct intel_padgroup cnlh_community0_gpps[] = { 357 - CNL_GPP(0, 0, 24, 0), /* GPP_A */ 358 - CNL_GPP(1, 25, 50, 32), /* GPP_B */ 365 + INTEL_GPP(0, 0, 24, 0), /* GPP_A */ 366 + INTEL_GPP(1, 25, 50, 32), /* GPP_B */ 359 367 }; 360 368 361 369 static const struct intel_padgroup cnlh_community1_gpps[] = { 362 - CNL_GPP(0, 51, 74, 64), /* GPP_C */ 363 - CNL_GPP(1, 75, 98, 96), /* GPP_D */ 364 - CNL_GPP(2, 99, 106, 128), /* GPP_G */ 365 - CNL_GPP(3, 107, 114, INTEL_GPIO_BASE_NOMAP), /* AZA */ 366 - CNL_GPP(4, 115, 146, 160), /* vGPIO_0 */ 367 - CNL_GPP(5, 147, 154, INTEL_GPIO_BASE_NOMAP), /* vGPIO_1 */ 370 + INTEL_GPP(0, 51, 74, 64), /* GPP_C */ 371 + INTEL_GPP(1, 75, 98, 96), /* GPP_D */ 372 + INTEL_GPP(2, 99, 106, 128), /* GPP_G */ 373 + INTEL_GPP(3, 107, 114, INTEL_GPIO_BASE_NOMAP), /* AZA */ 374 + INTEL_GPP(4, 115, 146, 160), /* vGPIO_0 */ 375 + INTEL_GPP(5, 147, 154, INTEL_GPIO_BASE_NOMAP), /* vGPIO_1 */ 368 376 }; 369 377 370 378 static const struct intel_padgroup cnlh_community3_gpps[] = { 371 - CNL_GPP(0, 155, 178, 192), /* GPP_K */ 372 - CNL_GPP(1, 179, 202, 224), /* GPP_H */ 373 - CNL_GPP(2, 203, 215, 256), /* GPP_E */ 374 - CNL_GPP(3, 216, 239, 288), /* GPP_F */ 375 - CNL_GPP(4, 240, 248, INTEL_GPIO_BASE_NOMAP), /* SPI */ 379 + INTEL_GPP(0, 155, 178, 192), /* GPP_K */ 380 + INTEL_GPP(1, 179, 202, 224), /* GPP_H */ 381 + INTEL_GPP(2, 203, 215, 256), /* GPP_E */ 382 + INTEL_GPP(3, 216, 239, 288), /* GPP_F */ 383 + INTEL_GPP(4, 240, 248, INTEL_GPIO_BASE_NOMAP), /* SPI */ 376 384 }; 377 385 378 386 static const struct intel_padgroup cnlh_community4_gpps[] = { 379 - CNL_GPP(0, 249, 259, INTEL_GPIO_BASE_NOMAP), /* CPU */ 380 - CNL_GPP(1, 260, 268, INTEL_GPIO_BASE_NOMAP), /* JTAG */ 381 - CNL_GPP(2, 269, 286, 320), /* GPP_I */ 382 - CNL_GPP(3, 287, 298, 352), /* GPP_J */ 387 + INTEL_GPP(0, 249, 259, INTEL_GPIO_BASE_NOMAP), /* CPU */ 388 + INTEL_GPP(1, 260, 268, INTEL_GPIO_BASE_NOMAP), /* JTAG */ 389 + INTEL_GPP(2, 269, 286, 320), /* GPP_I */ 390 + INTEL_GPP(3, 287, 298, 352), /* GPP_J */ 383 391 }; 384 392 385 393 static const unsigned int cnlh_spi0_pins[] = { 40, 41, 42, 43 }; ··· 772 780 }; 773 781 774 782 static const struct intel_padgroup cnllp_community0_gpps[] = { 775 - CNL_GPP(0, 0, 24, 0), /* GPP_A */ 776 - CNL_GPP(1, 25, 50, 32), /* GPP_B */ 777 - CNL_GPP(2, 51, 58, 64), /* GPP_G */ 778 - CNL_GPP(3, 59, 67, INTEL_GPIO_BASE_NOMAP), /* SPI */ 783 + INTEL_GPP(0, 0, 24, 0), /* GPP_A */ 784 + INTEL_GPP(1, 25, 50, 32), /* GPP_B */ 785 + INTEL_GPP(2, 51, 58, 64), /* GPP_G */ 786 + INTEL_GPP(3, 59, 67, INTEL_GPIO_BASE_NOMAP), /* SPI */ 779 787 }; 780 788 781 789 static const struct intel_padgroup cnllp_community1_gpps[] = { 782 - CNL_GPP(0, 68, 92, 96), /* GPP_D */ 783 - CNL_GPP(1, 93, 116, 128), /* GPP_F */ 784 - CNL_GPP(2, 117, 140, 160), /* GPP_H */ 785 - CNL_GPP(3, 141, 172, 192), /* vGPIO */ 786 - CNL_GPP(4, 173, 180, 224), /* vGPIO */ 790 + INTEL_GPP(0, 68, 92, 96), /* GPP_D */ 791 + INTEL_GPP(1, 93, 116, 128), /* GPP_F */ 792 + INTEL_GPP(2, 117, 140, 160), /* GPP_H */ 793 + INTEL_GPP(3, 141, 172, 192), /* vGPIO */ 794 + INTEL_GPP(4, 173, 180, 224), /* vGPIO */ 787 795 }; 788 796 789 797 static const struct intel_padgroup cnllp_community4_gpps[] = { 790 - CNL_GPP(0, 181, 204, 256), /* GPP_C */ 791 - CNL_GPP(1, 205, 228, 288), /* GPP_E */ 792 - CNL_GPP(2, 229, 237, INTEL_GPIO_BASE_NOMAP), /* JTAG */ 793 - CNL_GPP(3, 238, 243, INTEL_GPIO_BASE_NOMAP), /* HVCMOS */ 798 + INTEL_GPP(0, 181, 204, 256), /* GPP_C */ 799 + INTEL_GPP(1, 205, 228, 288), /* GPP_E */ 800 + INTEL_GPP(2, 229, 237, INTEL_GPIO_BASE_NOMAP), /* JTAG */ 801 + INTEL_GPP(3, 238, 243, INTEL_GPIO_BASE_NOMAP), /* HVCMOS */ 794 802 }; 795 803 796 804 static const struct intel_community cnllp_communities[] = {
+15 -22
drivers/pinctrl/intel/pinctrl-cedarfork.c
··· 21 21 #define CDF_GPI_IS 0x200 22 22 #define CDF_GPI_IE 0x230 23 23 24 - #define CDF_GPP(r, s, e) \ 25 - { \ 26 - .reg_num = (r), \ 27 - .base = (s), \ 28 - .size = ((e) - (s) + 1), \ 29 - } 30 - 31 24 #define CDF_COMMUNITY(b, s, e, g) \ 32 25 INTEL_COMMUNITY_GPPS(b, s, e, g, CDF) 33 26 ··· 281 288 }; 282 289 283 290 static const struct intel_padgroup cdf_community0_gpps[] = { 284 - CDF_GPP(0, 0, 23), /* WEST2 */ 285 - CDF_GPP(1, 24, 47), /* WEST3 */ 286 - CDF_GPP(2, 48, 70), /* WEST01 */ 287 - CDF_GPP(3, 71, 90), /* WEST5 */ 288 - CDF_GPP(4, 91, 96), /* WESTC */ 289 - CDF_GPP(5, 97, 101), /* WESTC_DFX */ 290 - CDF_GPP(6, 102, 111), /* WESTA */ 291 - CDF_GPP(7, 112, 123), /* WESTB */ 292 - CDF_GPP(8, 124, 143), /* WESTD */ 293 - CDF_GPP(9, 144, 144), /* WESTD_PECI */ 294 - CDF_GPP(10, 145, 167), /* WESTF */ 291 + INTEL_GPP(0, 0, 23, 0), /* WEST2 */ 292 + INTEL_GPP(1, 24, 47, 24), /* WEST3 */ 293 + INTEL_GPP(2, 48, 70, 48), /* WEST01 */ 294 + INTEL_GPP(3, 71, 90, 71), /* WEST5 */ 295 + INTEL_GPP(4, 91, 96, 91), /* WESTC */ 296 + INTEL_GPP(5, 97, 101, 97), /* WESTC_DFX */ 297 + INTEL_GPP(6, 102, 111, 102), /* WESTA */ 298 + INTEL_GPP(7, 112, 123, 112), /* WESTB */ 299 + INTEL_GPP(8, 124, 143, 124), /* WESTD */ 300 + INTEL_GPP(9, 144, 144, 144), /* WESTD_PECI */ 301 + INTEL_GPP(10, 145, 167, 145), /* WESTF */ 295 302 }; 296 303 297 304 static const struct intel_padgroup cdf_community1_gpps[] = { 298 - CDF_GPP(0, 168, 191), /* EAST2 */ 299 - CDF_GPP(1, 192, 202), /* EAST3 */ 300 - CDF_GPP(2, 203, 225), /* EAST0 */ 301 - CDF_GPP(3, 226, 236), /* EMMC */ 305 + INTEL_GPP(0, 168, 191, 168), /* EAST2 */ 306 + INTEL_GPP(1, 192, 202, 192), /* EAST3 */ 307 + INTEL_GPP(2, 203, 225, 203), /* EAST0 */ 308 + INTEL_GPP(3, 226, 236, 226), /* EMMC */ 302 309 }; 303 310 304 311 static const struct intel_community cdf_communities[] = {
+27 -59
drivers/pinctrl/intel/pinctrl-cherryview.c
··· 92 92 93 93 #define PINMODE(m, i) ((m) | ((i) * PINMODE_INVERT_OE)) 94 94 95 - #define CHV_GPP(start, end) \ 96 - { \ 97 - .base = (start), \ 98 - .size = (end) - (start) + 1, \ 99 - } 100 - 101 95 #define CHV_COMMUNITY(g, i, a) \ 102 96 { \ 103 97 .gpps = (g), \ ··· 252 258 }; 253 259 254 260 static const struct intel_padgroup southwest_gpps[] = { 255 - CHV_GPP(0, 7), 256 - CHV_GPP(15, 22), 257 - CHV_GPP(30, 37), 258 - CHV_GPP(45, 52), 259 - CHV_GPP(60, 67), 260 - CHV_GPP(75, 82), 261 - CHV_GPP(90, 97), 261 + INTEL_GPP(0, 0, 7, 0), 262 + INTEL_GPP(1, 15, 22, 15), 263 + INTEL_GPP(2, 30, 37, 30), 264 + INTEL_GPP(3, 45, 52, 45), 265 + INTEL_GPP(4, 60, 67, 60), 266 + INTEL_GPP(5, 75, 82, 75), 267 + INTEL_GPP(6, 90, 97, 90), 262 268 }; 263 269 264 270 /* ··· 348 354 }; 349 355 350 356 static const struct intel_padgroup north_gpps[] = { 351 - CHV_GPP(0, 8), 352 - CHV_GPP(15, 27), 353 - CHV_GPP(30, 41), 354 - CHV_GPP(45, 56), 355 - CHV_GPP(60, 72), 357 + INTEL_GPP(0, 0, 8, 0), 358 + INTEL_GPP(1, 15, 27, 15), 359 + INTEL_GPP(2, 30, 41, 30), 360 + INTEL_GPP(3, 45, 56, 45), 361 + INTEL_GPP(4, 60, 72, 60), 356 362 }; 357 363 358 364 /* ··· 400 406 }; 401 407 402 408 static const struct intel_padgroup east_gpps[] = { 403 - CHV_GPP(0, 11), 404 - CHV_GPP(15, 26), 409 + INTEL_GPP(0, 0, 11, 0), 410 + INTEL_GPP(1, 15, 26, 15), 405 411 }; 406 412 407 413 static const struct intel_community east_communities[] = { ··· 520 526 }; 521 527 522 528 static const struct intel_padgroup southeast_gpps[] = { 523 - CHV_GPP(0, 7), 524 - CHV_GPP(15, 26), 525 - CHV_GPP(30, 35), 526 - CHV_GPP(45, 52), 527 - CHV_GPP(60, 69), 528 - CHV_GPP(75, 85), 529 + INTEL_GPP(0, 0, 7, 0), 530 + INTEL_GPP(1, 15, 26, 15), 531 + INTEL_GPP(2, 30, 35, 30), 532 + INTEL_GPP(3, 45, 52, 45), 533 + INTEL_GPP(4, 60, 69, 60), 534 + INTEL_GPP(5, 75, 85, 75), 529 535 }; 530 536 531 537 static const struct intel_community southeast_communities[] = { ··· 1511 1517 return 0; 1512 1518 } 1513 1519 1514 - static int chv_gpio_add_pin_ranges(struct gpio_chip *chip) 1515 - { 1516 - struct intel_pinctrl *pctrl = gpiochip_get_data(chip); 1517 - struct device *dev = pctrl->dev; 1518 - const struct intel_community *community = &pctrl->communities[0]; 1519 - const struct intel_padgroup *gpp; 1520 - int ret, i; 1521 - 1522 - for (i = 0; i < community->ngpps; i++) { 1523 - gpp = &community->gpps[i]; 1524 - ret = gpiochip_add_pin_range(chip, dev_name(dev), gpp->base, gpp->base, gpp->size); 1525 - if (ret) { 1526 - dev_err(dev, "failed to add GPIO pin range\n"); 1527 - return ret; 1528 - } 1529 - } 1530 - 1531 - return 0; 1532 - } 1533 - 1534 1520 static int chv_gpio_probe(struct intel_pinctrl *pctrl, int irq) 1535 1521 { 1536 1522 const struct intel_community *community = &pctrl->communities[0]; ··· 1524 1550 1525 1551 chip->ngpio = pctrl->soc->pins[pctrl->soc->npins - 1].number + 1; 1526 1552 chip->label = dev_name(dev); 1527 - chip->add_pin_ranges = chv_gpio_add_pin_ranges; 1553 + chip->add_pin_ranges = intel_gpio_add_pin_ranges; 1528 1554 chip->parent = dev; 1529 1555 chip->base = -1; 1530 1556 ··· 1541 1567 chip->irq.init_valid_mask = chv_init_irq_valid_mask; 1542 1568 } else { 1543 1569 irq_base = devm_irq_alloc_descs(dev, -1, 0, pctrl->soc->npins, NUMA_NO_NODE); 1544 - if (irq_base < 0) { 1545 - dev_err(dev, "Failed to allocate IRQ numbers\n"); 1546 - return irq_base; 1547 - } 1570 + if (irq_base < 0) 1571 + return dev_err_probe(dev, irq_base, "failed to allocate IRQ numbers\n"); 1548 1572 } 1549 1573 1550 1574 ret = devm_gpiochip_add_data(dev, chip, pctrl); 1551 - if (ret) { 1552 - dev_err(dev, "Failed to register gpiochip\n"); 1553 - return ret; 1554 - } 1575 + if (ret) 1576 + return dev_err_probe(dev, ret, "failed to register gpiochip\n"); 1555 1577 1556 1578 if (!need_valid_mask) { 1557 1579 for (i = 0; i < community->ngpps; i++) { ··· 1643 1673 pctrl->pctldesc.npins = pctrl->soc->npins; 1644 1674 1645 1675 pctrl->pctldev = devm_pinctrl_register(dev, &pctrl->pctldesc, pctrl); 1646 - if (IS_ERR(pctrl->pctldev)) { 1647 - dev_err(dev, "failed to register pinctrl driver\n"); 1648 - return PTR_ERR(pctrl->pctldev); 1649 - } 1676 + if (IS_ERR(pctrl->pctldev)) 1677 + return dev_err_probe(dev, PTR_ERR(pctrl->pctldev), "failed to register pinctrl\n"); 1650 1678 1651 1679 ret = chv_gpio_probe(pctrl, irq); 1652 1680 if (ret)
+7 -14
drivers/pinctrl/intel/pinctrl-denverton.c
··· 21 21 #define DNV_GPI_IS 0x100 22 22 #define DNV_GPI_IE 0x120 23 23 24 - #define DNV_GPP(n, s, e) \ 25 - { \ 26 - .reg_num = (n), \ 27 - .base = (s), \ 28 - .size = ((e) - (s) + 1), \ 29 - } 30 - 31 24 #define DNV_COMMUNITY(b, s, e, g) \ 32 25 INTEL_COMMUNITY_GPPS(b, s, e, g, DNV) 33 26 ··· 215 222 }; 216 223 217 224 static const struct intel_padgroup dnv_north_gpps[] = { 218 - DNV_GPP(0, 0, 31), /* North ALL_0 */ 219 - DNV_GPP(1, 32, 40), /* North ALL_1 */ 225 + INTEL_GPP(0, 0, 31, 0), /* North ALL_0 */ 226 + INTEL_GPP(1, 32, 40, 32), /* North ALL_1 */ 220 227 }; 221 228 222 229 static const struct intel_padgroup dnv_south_gpps[] = { 223 - DNV_GPP(0, 41, 58), /* South DFX */ 224 - DNV_GPP(1, 59, 90), /* South GPP0_0 */ 225 - DNV_GPP(2, 91, 111), /* South GPP0_1 */ 226 - DNV_GPP(3, 112, 143), /* South GPP1_0 */ 227 - DNV_GPP(4, 144, 153), /* South GPP1_1 */ 230 + INTEL_GPP(0, 41, 58, 41), /* South DFX */ 231 + INTEL_GPP(1, 59, 90, 59), /* South GPP0_0 */ 232 + INTEL_GPP(2, 91, 111, 91), /* South GPP0_1 */ 233 + INTEL_GPP(3, 112, 143, 112), /* South GPP1_0 */ 234 + INTEL_GPP(4, 144, 153, 144), /* South GPP1_1 */ 228 235 }; 229 236 230 237 static const struct intel_community dnv_communities[] = {
+18 -25
drivers/pinctrl/intel/pinctrl-elkhartlake.c
··· 21 21 #define EHL_GPI_IS 0x100 22 22 #define EHL_GPI_IE 0x120 23 23 24 - #define EHL_GPP(r, s, e) \ 25 - { \ 26 - .reg_num = (r), \ 27 - .base = (s), \ 28 - .size = ((e) - (s) + 1), \ 29 - } 30 - 31 24 #define EHL_COMMUNITY(b, s, e, g) \ 32 25 INTEL_COMMUNITY_GPPS(b, s, e, g, EHL) 33 26 ··· 99 106 }; 100 107 101 108 static const struct intel_padgroup ehl_community0_gpps[] = { 102 - EHL_GPP(0, 0, 25), /* GPP_B */ 103 - EHL_GPP(1, 26, 41), /* GPP_T */ 104 - EHL_GPP(2, 42, 66), /* GPP_G */ 109 + INTEL_GPP(0, 0, 25, 0), /* GPP_B */ 110 + INTEL_GPP(1, 26, 41, 26), /* GPP_T */ 111 + INTEL_GPP(2, 42, 66, 42), /* GPP_G */ 105 112 }; 106 113 107 114 static const struct intel_community ehl_community0[] = { ··· 238 245 }; 239 246 240 247 static const struct intel_padgroup ehl_community1_gpps[] = { 241 - EHL_GPP(0, 0, 15), /* GPP_V */ 242 - EHL_GPP(1, 16, 39), /* GPP_H */ 243 - EHL_GPP(2, 40, 60), /* GPP_D */ 244 - EHL_GPP(3, 61, 84), /* GPP_U */ 245 - EHL_GPP(4, 85, 112), /* vGPIO */ 248 + INTEL_GPP(0, 0, 15, 0), /* GPP_V */ 249 + INTEL_GPP(1, 16, 39, 16), /* GPP_H */ 250 + INTEL_GPP(2, 40, 60, 40), /* GPP_D */ 251 + INTEL_GPP(3, 61, 84, 61), /* GPP_U */ 252 + INTEL_GPP(4, 85, 112, 85), /* vGPIO */ 246 253 }; 247 254 248 255 static const struct intel_community ehl_community1[] = { ··· 279 286 }; 280 287 281 288 static const struct intel_padgroup ehl_community2_gpps[] = { 282 - EHL_GPP(0, 0, 16), /* DSW */ 289 + INTEL_GPP(0, 0, 16, 0), /* DSW */ 283 290 }; 284 291 285 292 static const struct intel_community ehl_community2[] = { ··· 349 356 }; 350 357 351 358 static const struct intel_padgroup ehl_community3_gpps[] = { 352 - EHL_GPP(0, 0, 16), /* CPU */ 353 - EHL_GPP(1, 17, 18), /* GPP_S */ 354 - EHL_GPP(2, 19, 42), /* GPP_A */ 355 - EHL_GPP(3, 43, 46), /* vGPIO_3 */ 359 + INTEL_GPP(0, 0, 16, 0), /* CPU */ 360 + INTEL_GPP(1, 17, 18, 17), /* GPP_S */ 361 + INTEL_GPP(2, 19, 42, 19), /* GPP_A */ 362 + INTEL_GPP(3, 43, 46, 43), /* vGPIO_3 */ 356 363 }; 357 364 358 365 static const struct intel_community ehl_community3[] = { ··· 455 462 }; 456 463 457 464 static const struct intel_padgroup ehl_community4_gpps[] = { 458 - EHL_GPP(0, 0, 23), /* GPP_C */ 459 - EHL_GPP(1, 24, 48), /* GPP_F */ 460 - EHL_GPP(2, 49, 54), /* HVCMOS */ 461 - EHL_GPP(3, 55, 79), /* GPP_E */ 465 + INTEL_GPP(0, 0, 23, 0), /* GPP_C */ 466 + INTEL_GPP(1, 24, 48, 24), /* GPP_F */ 467 + INTEL_GPP(2, 49, 54, 49), /* HVCMOS */ 468 + INTEL_GPP(3, 55, 79, 55), /* GPP_E */ 462 469 }; 463 470 464 471 static const struct intel_community ehl_community4[] = { ··· 486 493 }; 487 494 488 495 static const struct intel_padgroup ehl_community5_gpps[] = { 489 - EHL_GPP(0, 0, 7), /* GPP_R */ 496 + INTEL_GPP(0, 0, 7, 0), /* GPP_R */ 490 497 }; 491 498 492 499 static const struct intel_community ehl_community5[] = {
+13 -20
drivers/pinctrl/intel/pinctrl-emmitsburg.c
··· 21 21 #define EBG_GPI_IS 0x200 22 22 #define EBG_GPI_IE 0x210 23 23 24 - #define EBG_GPP(r, s, e) \ 25 - { \ 26 - .reg_num = (r), \ 27 - .base = (s), \ 28 - .size = ((e) - (s) + 1), \ 29 - } 30 - 31 24 #define EBG_COMMUNITY(b, s, e, g) \ 32 25 INTEL_COMMUNITY_GPPS(b, s, e, g, EBG) 33 26 ··· 304 311 }; 305 312 306 313 static const struct intel_padgroup ebg_community0_gpps[] = { 307 - EBG_GPP(0, 0, 20), /* GPP_A */ 308 - EBG_GPP(1, 21, 44), /* GPP_B */ 309 - EBG_GPP(2, 45, 65), /* SPI */ 314 + INTEL_GPP(0, 0, 20, 0), /* GPP_A */ 315 + INTEL_GPP(1, 21, 44, 21), /* GPP_B */ 316 + INTEL_GPP(2, 45, 65, 45), /* SPI */ 310 317 }; 311 318 312 319 static const struct intel_padgroup ebg_community1_gpps[] = { 313 - EBG_GPP(0, 66, 87), /* GPP_C */ 314 - EBG_GPP(1, 88, 111), /* GPP_D */ 320 + INTEL_GPP(0, 66, 87, 66), /* GPP_C */ 321 + INTEL_GPP(1, 88, 111, 88), /* GPP_D */ 315 322 }; 316 323 317 324 static const struct intel_padgroup ebg_community3_gpps[] = { 318 - EBG_GPP(0, 112, 135), /* GPP_E */ 319 - EBG_GPP(1, 136, 145), /* JTAG */ 325 + INTEL_GPP(0, 112, 135, 112), /* GPP_E */ 326 + INTEL_GPP(1, 136, 145, 136), /* JTAG */ 320 327 }; 321 328 322 329 static const struct intel_padgroup ebg_community4_gpps[] = { 323 - EBG_GPP(0, 146, 165), /* GPP_H */ 324 - EBG_GPP(1, 166, 183), /* GPP_J */ 330 + INTEL_GPP(0, 146, 165, 146), /* GPP_H */ 331 + INTEL_GPP(1, 166, 183, 166), /* GPP_J */ 325 332 }; 326 333 327 334 static const struct intel_padgroup ebg_community5_gpps[] = { 328 - EBG_GPP(0, 184, 207), /* GPP_I */ 329 - EBG_GPP(1, 208, 225), /* GPP_L */ 330 - EBG_GPP(2, 226, 243), /* GPP_M */ 331 - EBG_GPP(3, 244, 261), /* GPP_N */ 335 + INTEL_GPP(0, 184, 207, 184), /* GPP_I */ 336 + INTEL_GPP(1, 208, 225, 208), /* GPP_L */ 337 + INTEL_GPP(2, 226, 243, 226), /* GPP_M */ 338 + INTEL_GPP(3, 244, 261, 244), /* GPP_N */ 332 339 }; 333 340 334 341 static const struct intel_community ebg_communities[] = {
+26 -34
drivers/pinctrl/intel/pinctrl-icelake.c
··· 28 28 #define ICL_N_GPI_IS 0x100 29 29 #define ICL_N_GPI_IE 0x120 30 30 31 - #define ICL_GPP(r, s, e, g) \ 32 - { \ 33 - .reg_num = (r), \ 34 - .base = (s), \ 35 - .size = ((e) - (s) + 1), \ 36 - .gpio_base = (g), \ 37 - } 38 - 39 31 #define ICL_LP_COMMUNITY(b, s, e, g) \ 40 32 INTEL_COMMUNITY_GPPS(b, s, e, g, ICL_LP) 41 33 ··· 294 302 }; 295 303 296 304 static const struct intel_padgroup icllp_community0_gpps[] = { 297 - ICL_GPP(0, 0, 7, 0), /* GPP_G */ 298 - ICL_GPP(1, 8, 33, 32), /* GPP_B */ 299 - ICL_GPP(2, 34, 58, 64), /* GPP_A */ 305 + INTEL_GPP(0, 0, 7, 0), /* GPP_G */ 306 + INTEL_GPP(1, 8, 33, 32), /* GPP_B */ 307 + INTEL_GPP(2, 34, 58, 64), /* GPP_A */ 300 308 }; 301 309 302 310 static const struct intel_padgroup icllp_community1_gpps[] = { 303 - ICL_GPP(0, 59, 82, 96), /* GPP_H */ 304 - ICL_GPP(1, 83, 103, 128), /* GPP_D */ 305 - ICL_GPP(2, 104, 123, 160), /* GPP_F */ 306 - ICL_GPP(3, 124, 152, 192), /* vGPIO */ 311 + INTEL_GPP(0, 59, 82, 96), /* GPP_H */ 312 + INTEL_GPP(1, 83, 103, 128), /* GPP_D */ 313 + INTEL_GPP(2, 104, 123, 160), /* GPP_F */ 314 + INTEL_GPP(3, 124, 152, 192), /* vGPIO */ 307 315 }; 308 316 309 317 static const struct intel_padgroup icllp_community4_gpps[] = { 310 - ICL_GPP(0, 153, 176, 224), /* GPP_C */ 311 - ICL_GPP(1, 177, 182, INTEL_GPIO_BASE_NOMAP), /* HVCMOS */ 312 - ICL_GPP(2, 183, 206, 256), /* GPP_E */ 313 - ICL_GPP(3, 207, 215, INTEL_GPIO_BASE_NOMAP), /* JTAG */ 318 + INTEL_GPP(0, 153, 176, 224), /* GPP_C */ 319 + INTEL_GPP(1, 177, 182, INTEL_GPIO_BASE_NOMAP), /* HVCMOS */ 320 + INTEL_GPP(2, 183, 206, 256), /* GPP_E */ 321 + INTEL_GPP(3, 207, 215, INTEL_GPIO_BASE_NOMAP), /* JTAG */ 314 322 }; 315 323 316 324 static const struct intel_padgroup icllp_community5_gpps[] = { 317 - ICL_GPP(0, 216, 223, 288), /* GPP_R */ 318 - ICL_GPP(1, 224, 231, 320), /* GPP_S */ 319 - ICL_GPP(2, 232, 240, INTEL_GPIO_BASE_NOMAP), /* SPI */ 325 + INTEL_GPP(0, 216, 223, 288), /* GPP_R */ 326 + INTEL_GPP(1, 224, 231, 320), /* GPP_S */ 327 + INTEL_GPP(2, 232, 240, INTEL_GPIO_BASE_NOMAP), /* SPI */ 320 328 }; 321 329 322 330 static const struct intel_community icllp_communities[] = { ··· 624 632 }; 625 633 626 634 static const struct intel_padgroup icln_community0_gpps[] = { 627 - ICL_GPP(0, 0, 8, INTEL_GPIO_BASE_NOMAP), /* SPI */ 628 - ICL_GPP(1, 9, 34, 32), /* GPP_B */ 629 - ICL_GPP(2, 35, 55, 64), /* GPP_A */ 630 - ICL_GPP(3, 56, 63, 96), /* GPP_S */ 631 - ICL_GPP(4, 64, 71, 128), /* GPP_R */ 635 + INTEL_GPP(0, 0, 8, INTEL_GPIO_BASE_NOMAP), /* SPI */ 636 + INTEL_GPP(1, 9, 34, 32), /* GPP_B */ 637 + INTEL_GPP(2, 35, 55, 64), /* GPP_A */ 638 + INTEL_GPP(3, 56, 63, 96), /* GPP_S */ 639 + INTEL_GPP(4, 64, 71, 128), /* GPP_R */ 632 640 }; 633 641 634 642 static const struct intel_padgroup icln_community1_gpps[] = { 635 - ICL_GPP(0, 72, 95, 160), /* GPP_H */ 636 - ICL_GPP(1, 96, 121, 192), /* GPP_D */ 637 - ICL_GPP(2, 122, 150, 224), /* vGPIO */ 638 - ICL_GPP(3, 151, 174, 256), /* GPP_C */ 643 + INTEL_GPP(0, 72, 95, 160), /* GPP_H */ 644 + INTEL_GPP(1, 96, 121, 192), /* GPP_D */ 645 + INTEL_GPP(2, 122, 150, 224), /* vGPIO */ 646 + INTEL_GPP(3, 151, 174, 256), /* GPP_C */ 639 647 }; 640 648 641 649 static const struct intel_padgroup icln_community4_gpps[] = { 642 - ICL_GPP(0, 175, 180, INTEL_GPIO_BASE_NOMAP), /* HVCMOS */ 643 - ICL_GPP(1, 181, 204, 288), /* GPP_E */ 650 + INTEL_GPP(0, 175, 180, INTEL_GPIO_BASE_NOMAP), /* HVCMOS */ 651 + INTEL_GPP(1, 181, 204, 288), /* GPP_E */ 644 652 }; 645 653 646 654 static const struct intel_padgroup icln_community5_gpps[] = { 647 - ICL_GPP(0, 205, 212, INTEL_GPIO_BASE_ZERO), /* GPP_G */ 655 + INTEL_GPP(0, 205, 212, INTEL_GPIO_BASE_ZERO), /* GPP_G */ 648 656 }; 649 657 650 658 static const struct intel_community icln_communities[] = {
+19 -17
drivers/pinctrl/intel/pinctrl-intel.c
··· 1345 1345 return 0; 1346 1346 } 1347 1347 1348 - static int intel_gpio_add_pin_ranges(struct gpio_chip *gc) 1348 + /** 1349 + * intel_gpio_add_pin_ranges - add GPIO pin ranges for all groups in all communities 1350 + * @gc: GPIO chip structure 1351 + * 1352 + * This function iterates over all communities and all groups and adds the respective 1353 + * GPIO pin ranges, so the GPIO library will correctly map a GPIO offset to a pin number. 1354 + * 1355 + * Return: 0, or negative error code if range can't be added. 1356 + */ 1357 + int intel_gpio_add_pin_ranges(struct gpio_chip *gc) 1349 1358 { 1350 1359 struct intel_pinctrl *pctrl = gpiochip_get_data(gc); 1351 1360 const struct intel_community *community; ··· 1365 1356 ret = gpiochip_add_pin_range(&pctrl->chip, dev_name(pctrl->dev), 1366 1357 grp->gpio_base, grp->base, 1367 1358 grp->size); 1368 - if (ret) { 1369 - dev_err(pctrl->dev, "failed to add GPIO pin range\n"); 1370 - return ret; 1371 - } 1359 + if (ret) 1360 + return dev_err_probe(pctrl->dev, ret, "failed to add GPIO pin range\n"); 1372 1361 } 1373 1362 1374 1363 return 0; 1375 1364 } 1365 + EXPORT_SYMBOL_NS_GPL(intel_gpio_add_pin_ranges, "PINCTRL_INTEL"); 1376 1366 1377 1367 static unsigned int intel_gpio_ngpio(const struct intel_pinctrl *pctrl) 1378 1368 { ··· 1409 1401 ret = devm_request_irq(pctrl->dev, irq, intel_gpio_irq, 1410 1402 IRQF_SHARED | IRQF_NO_THREAD, 1411 1403 dev_name(pctrl->dev), pctrl); 1412 - if (ret) { 1413 - dev_err(pctrl->dev, "failed to request interrupt\n"); 1414 - return ret; 1415 - } 1404 + if (ret) 1405 + return dev_err_probe(pctrl->dev, ret, "failed to request interrupt\n"); 1416 1406 1417 1407 /* Setup IRQ chip */ 1418 1408 girq = &pctrl->chip.irq; ··· 1423 1417 girq->init_hw = intel_gpio_irq_init_hw; 1424 1418 1425 1419 ret = devm_gpiochip_add_data(pctrl->dev, &pctrl->chip, pctrl); 1426 - if (ret) { 1427 - dev_err(pctrl->dev, "failed to register gpiochip\n"); 1428 - return ret; 1429 - } 1420 + if (ret) 1421 + return dev_err_probe(pctrl->dev, ret, "failed to register gpiochip\n"); 1430 1422 1431 1423 return 0; 1432 1424 } ··· 1672 1668 pctrl->pctldesc.npins = pctrl->soc->npins; 1673 1669 1674 1670 pctrl->pctldev = devm_pinctrl_register(dev, &pctrl->pctldesc, pctrl); 1675 - if (IS_ERR(pctrl->pctldev)) { 1676 - dev_err(dev, "failed to register pinctrl driver\n"); 1677 - return PTR_ERR(pctrl->pctldev); 1678 - } 1671 + if (IS_ERR(pctrl->pctldev)) 1672 + return dev_err_probe(dev, PTR_ERR(pctrl->pctldev), "failed to register pinctrl\n"); 1679 1673 1680 1674 ret = intel_gpio_probe(pctrl, irq); 1681 1675 if (ret)
+11
drivers/pinctrl/intel/pinctrl-intel.h
··· 76 76 INTEL_GPIO_BASE_MATCH = 0, 77 77 }; 78 78 79 + /* Initialise struct intel_padgroup */ 80 + #define INTEL_GPP(r, s, e, g) \ 81 + { \ 82 + .reg_num = (r), \ 83 + .base = (s), \ 84 + .size = ((e) - (s) + 1), \ 85 + .gpio_base = (g), \ 86 + } 87 + 79 88 /** 80 89 * struct intel_community - Intel pin community description 81 90 * @barno: MMIO BAR number where registers for this community reside ··· 275 266 276 267 const struct intel_community *intel_get_community(const struct intel_pinctrl *pctrl, 277 268 unsigned int pin); 269 + 270 + int intel_gpio_add_pin_ranges(struct gpio_chip *gc); 278 271 279 272 int intel_get_groups_count(struct pinctrl_dev *pctldev); 280 273 const char *intel_get_group_name(struct pinctrl_dev *pctldev, unsigned int group);
+13 -21
drivers/pinctrl/intel/pinctrl-jasperlake.c
··· 21 21 #define JSL_GPI_IS 0x100 22 22 #define JSL_GPI_IE 0x120 23 23 24 - #define JSL_GPP(r, s, e, g) \ 25 - { \ 26 - .reg_num = (r), \ 27 - .base = (s), \ 28 - .size = ((e) - (s) + 1), \ 29 - .gpio_base = (g), \ 30 - } 31 - 32 24 #define JSL_COMMUNITY(b, s, e, g) \ 33 25 INTEL_COMMUNITY_GPPS(b, s, e, g, JSL) 34 26 ··· 275 283 }; 276 284 277 285 static const struct intel_padgroup jsl_community0_gpps[] = { 278 - JSL_GPP(0, 0, 19, 320), /* GPP_F */ 279 - JSL_GPP(1, 20, 28, INTEL_GPIO_BASE_NOMAP), /* SPI */ 280 - JSL_GPP(2, 29, 54, 32), /* GPP_B */ 281 - JSL_GPP(3, 55, 75, 64), /* GPP_A */ 282 - JSL_GPP(4, 76, 83, 96), /* GPP_S */ 283 - JSL_GPP(5, 84, 91, 128), /* GPP_R */ 286 + INTEL_GPP(0, 0, 19, 320), /* GPP_F */ 287 + INTEL_GPP(1, 20, 28, INTEL_GPIO_BASE_NOMAP), /* SPI */ 288 + INTEL_GPP(2, 29, 54, 32), /* GPP_B */ 289 + INTEL_GPP(3, 55, 75, 64), /* GPP_A */ 290 + INTEL_GPP(4, 76, 83, 96), /* GPP_S */ 291 + INTEL_GPP(5, 84, 91, 128), /* GPP_R */ 284 292 }; 285 293 286 294 static const struct intel_padgroup jsl_community1_gpps[] = { 287 - JSL_GPP(0, 92, 115, 160), /* GPP_H */ 288 - JSL_GPP(1, 116, 141, 192), /* GPP_D */ 289 - JSL_GPP(2, 142, 170, 224), /* vGPIO */ 290 - JSL_GPP(3, 171, 194, 256), /* GPP_C */ 295 + INTEL_GPP(0, 92, 115, 160), /* GPP_H */ 296 + INTEL_GPP(1, 116, 141, 192), /* GPP_D */ 297 + INTEL_GPP(2, 142, 170, 224), /* vGPIO */ 298 + INTEL_GPP(3, 171, 194, 256), /* GPP_C */ 291 299 }; 292 300 293 301 static const struct intel_padgroup jsl_community4_gpps[] = { 294 - JSL_GPP(0, 195, 200, INTEL_GPIO_BASE_NOMAP), /* HVCMOS */ 295 - JSL_GPP(1, 201, 224, 288), /* GPP_E */ 302 + INTEL_GPP(0, 195, 200, INTEL_GPIO_BASE_NOMAP), /* HVCMOS */ 303 + INTEL_GPP(1, 201, 224, 288), /* GPP_E */ 296 304 }; 297 305 298 306 static const struct intel_padgroup jsl_community5_gpps[] = { 299 - JSL_GPP(0, 225, 232, INTEL_GPIO_BASE_ZERO), /* GPP_G */ 307 + INTEL_GPP(0, 225, 232, INTEL_GPIO_BASE_ZERO), /* GPP_G */ 300 308 }; 301 309 302 310 static const struct intel_community jsl_communities[] = {
+9 -17
drivers/pinctrl/intel/pinctrl-lakefield.c
··· 21 21 #define LKF_GPI_IS 0x100 22 22 #define LKF_GPI_IE 0x110 23 23 24 - #define LKF_GPP(r, s, e, g) \ 25 - { \ 26 - .reg_num = (r), \ 27 - .base = (s), \ 28 - .size = ((e) - (s) + 1), \ 29 - .gpio_base = (g), \ 30 - } 31 - 32 24 #define LKF_COMMUNITY(b, s, e, g) \ 33 25 INTEL_COMMUNITY_GPPS(b, s, e, g, LKF) 34 26 ··· 300 308 }; 301 309 302 310 static const struct intel_padgroup lkf_community0_gpps[] = { 303 - LKF_GPP(0, 0, 31, 0), /* EAST_0 */ 304 - LKF_GPP(1, 32, 59, 32), /* EAST_1 */ 311 + INTEL_GPP(0, 0, 31, 0), /* EAST_0 */ 312 + INTEL_GPP(1, 32, 59, 32), /* EAST_1 */ 305 313 }; 306 314 307 315 static const struct intel_padgroup lkf_community1_gpps[] = { 308 - LKF_GPP(0, 60, 91, 64), /* NORTHWEST_0 */ 309 - LKF_GPP(1, 92, 123, 96), /* NORTHWEST_1 */ 310 - LKF_GPP(2, 124, 148, 128), /* NORTHWEST_2 */ 316 + INTEL_GPP(0, 60, 91, 64), /* NORTHWEST_0 */ 317 + INTEL_GPP(1, 92, 123, 96), /* NORTHWEST_1 */ 318 + INTEL_GPP(2, 124, 148, 128), /* NORTHWEST_2 */ 311 319 }; 312 320 313 321 static const struct intel_padgroup lkf_community2_gpps[] = { 314 - LKF_GPP(0, 149, 180, 160), /* WEST_0 */ 315 - LKF_GPP(1, 181, 212, 192), /* WEST_1 */ 316 - LKF_GPP(2, 213, 237, 224), /* WEST_2 */ 322 + INTEL_GPP(0, 149, 180, 160), /* WEST_0 */ 323 + INTEL_GPP(1, 181, 212, 192), /* WEST_1 */ 324 + INTEL_GPP(2, 213, 237, 224), /* WEST_2 */ 317 325 }; 318 326 319 327 static const struct intel_padgroup lkf_community3_gpps[] = { 320 - LKF_GPP(0, 238, 266, 256), /* SOUTHEAST */ 328 + INTEL_GPP(0, 238, 266, 256), /* SOUTHEAST */ 321 329 }; 322 330 323 331 static const struct intel_community lkf_communities[] = {
+10 -18
drivers/pinctrl/intel/pinctrl-lynxpoint.c
··· 700 700 701 701 ret = gpiochip_add_pin_range(chip, dev_name(dev), 0, 0, lg->soc->npins); 702 702 if (ret) 703 - dev_err(dev, "failed to add GPIO pin range\n"); 703 + return dev_err_probe(dev, ret, "failed to add GPIO pin range\n"); 704 704 705 - return ret; 705 + return 0; 706 706 } 707 707 708 708 static int lp_gpio_probe(struct platform_device *pdev) ··· 739 739 lg->pctldesc.npins = lg->soc->npins; 740 740 741 741 lg->pctldev = devm_pinctrl_register(dev, &lg->pctldesc, lg); 742 - if (IS_ERR(lg->pctldev)) { 743 - dev_err(dev, "failed to register pinctrl driver\n"); 744 - return PTR_ERR(lg->pctldev); 745 - } 742 + if (IS_ERR(lg->pctldev)) 743 + return dev_err_probe(dev, PTR_ERR(lg->pctldev), "failed to register pinctrl\n"); 746 744 747 745 platform_set_drvdata(pdev, lg); 748 746 749 747 io_rc = platform_get_resource(pdev, IORESOURCE_IO, 0); 750 - if (!io_rc) { 751 - dev_err(dev, "missing IO resources\n"); 752 - return -EINVAL; 753 - } 748 + if (!io_rc) 749 + return dev_err_probe(dev, -EINVAL, "missing IO resources\n"); 754 750 755 751 regs = devm_ioport_map(dev, io_rc->start, resource_size(io_rc)); 756 - if (!regs) { 757 - dev_err(dev, "failed mapping IO region %pR\n", &io_rc); 758 - return -EBUSY; 759 - } 752 + if (!regs) 753 + return dev_err_probe(dev, -EBUSY, "failed mapping IO region %pR\n", &io_rc); 760 754 761 755 for (i = 0; i < lg->soc->ncommunities; i++) { 762 756 struct intel_community *comm = &lg->communities[i]; ··· 801 807 } 802 808 803 809 ret = devm_gpiochip_add_data(dev, gc, lg); 804 - if (ret) { 805 - dev_err(dev, "failed adding lp-gpio chip\n"); 806 - return ret; 807 - } 810 + if (ret) 811 + return dev_err_probe(dev, ret, "failed to register gpiochip\n"); 808 812 809 813 return 0; 810 814 }
+23 -31
drivers/pinctrl/intel/pinctrl-meteorlake.c
··· 27 27 #define MTL_S_GPI_IS 0x200 28 28 #define MTL_S_GPI_IE 0x210 29 29 30 - #define MTL_GPP(r, s, e, g) \ 31 - { \ 32 - .reg_num = (r), \ 33 - .base = (s), \ 34 - .size = ((e) - (s) + 1), \ 35 - .gpio_base = (g), \ 36 - } 37 - 38 30 #define MTL_P_COMMUNITY(b, s, e, g) \ 39 31 INTEL_COMMUNITY_GPPS(b, s, e, g, MTL_P) 40 32 ··· 341 349 }; 342 350 343 351 static const struct intel_padgroup mtlp_community0_gpps[] = { 344 - MTL_GPP(0, 0, 4, 0), /* CPU */ 345 - MTL_GPP(1, 5, 28, 32), /* GPP_V */ 346 - MTL_GPP(2, 29, 52, 64), /* GPP_C */ 352 + INTEL_GPP(0, 0, 4, 0), /* CPU */ 353 + INTEL_GPP(1, 5, 28, 32), /* GPP_V */ 354 + INTEL_GPP(2, 29, 52, 64), /* GPP_C */ 347 355 }; 348 356 349 357 static const struct intel_padgroup mtlp_community1_gpps[] = { 350 - MTL_GPP(0, 53, 77, 96), /* GPP_A */ 351 - MTL_GPP(1, 78, 102, 128), /* GPP_E */ 358 + INTEL_GPP(0, 53, 77, 96), /* GPP_A */ 359 + INTEL_GPP(1, 78, 102, 128), /* GPP_E */ 352 360 }; 353 361 354 362 static const struct intel_padgroup mtlp_community3_gpps[] = { 355 - MTL_GPP(0, 103, 128, 160), /* GPP_H */ 356 - MTL_GPP(1, 129, 154, 192), /* GPP_F */ 357 - MTL_GPP(2, 155, 169, 224), /* SPI0 */ 358 - MTL_GPP(3, 170, 183, 256), /* vGPIO_3 */ 363 + INTEL_GPP(0, 103, 128, 160), /* GPP_H */ 364 + INTEL_GPP(1, 129, 154, 192), /* GPP_F */ 365 + INTEL_GPP(2, 155, 169, 224), /* SPI0 */ 366 + INTEL_GPP(3, 170, 183, 256), /* vGPIO_3 */ 359 367 }; 360 368 361 369 static const struct intel_padgroup mtlp_community4_gpps[] = { 362 - MTL_GPP(0, 184, 191, 288), /* GPP_S */ 363 - MTL_GPP(1, 192, 203, 320), /* JTAG */ 370 + INTEL_GPP(0, 184, 191, 288), /* GPP_S */ 371 + INTEL_GPP(1, 192, 203, 320), /* JTAG */ 364 372 }; 365 373 366 374 static const struct intel_padgroup mtlp_community5_gpps[] = { 367 - MTL_GPP(0, 204, 228, 352), /* GPP_B */ 368 - MTL_GPP(1, 229, 253, 384), /* GPP_D */ 369 - MTL_GPP(2, 254, 285, 416), /* vGPIO_0 */ 370 - MTL_GPP(3, 286, 288, 448), /* vGPIO_1 */ 375 + INTEL_GPP(0, 204, 228, 352), /* GPP_B */ 376 + INTEL_GPP(1, 229, 253, 384), /* GPP_D */ 377 + INTEL_GPP(2, 254, 285, 416), /* vGPIO_0 */ 378 + INTEL_GPP(3, 286, 288, 448), /* vGPIO_1 */ 371 379 }; 372 380 373 381 static const struct intel_community mtlp_communities[] = { ··· 546 554 }; 547 555 548 556 static const struct intel_padgroup mtls_community0_gpps[] = { 549 - MTL_GPP(0, 0, 27, 0), /* GPP_A */ 550 - MTL_GPP(1, 28, 46, 32), /* vGPIO_0 */ 551 - MTL_GPP(2, 47, 73, 64), /* GPP_C */ 557 + INTEL_GPP(0, 0, 27, 0), /* GPP_A */ 558 + INTEL_GPP(1, 28, 46, 32), /* vGPIO_0 */ 559 + INTEL_GPP(2, 47, 73, 64), /* GPP_C */ 552 560 }; 553 561 554 562 static const struct intel_padgroup mtls_community1_gpps[] = { 555 - MTL_GPP(0, 74, 93, 96), /* GPP_B */ 556 - MTL_GPP(1, 94, 95, 128), /* vGPIO_3 */ 557 - MTL_GPP(2, 96, 119, 160), /* GPP_D */ 563 + INTEL_GPP(0, 74, 93, 96), /* GPP_B */ 564 + INTEL_GPP(1, 94, 95, 128), /* vGPIO_3 */ 565 + INTEL_GPP(2, 96, 119, 160), /* GPP_D */ 558 566 }; 559 567 560 568 static const struct intel_padgroup mtls_community3_gpps[] = { 561 - MTL_GPP(0, 120, 135, 192), /* JTAG_CPU */ 562 - MTL_GPP(1, 136, 147, 224), /* vGPIO_4 */ 569 + INTEL_GPP(0, 120, 135, 192), /* JTAG_CPU */ 570 + INTEL_GPP(1, 136, 147, 224), /* vGPIO_4 */ 563 571 }; 564 572 565 573 static const struct intel_community mtls_communities[] = {
+19 -27
drivers/pinctrl/intel/pinctrl-meteorpoint.c
··· 21 21 #define MTP_GPI_IS 0x200 22 22 #define MTP_GPI_IE 0x220 23 23 24 - #define MTP_GPP(r, s, e, g) \ 25 - { \ 26 - .reg_num = (r), \ 27 - .base = (s), \ 28 - .size = ((e) - (s) + 1), \ 29 - .gpio_base = (g), \ 30 - } 31 - 32 24 #define MTP_COMMUNITY(b, s, e, g) \ 33 25 INTEL_COMMUNITY_GPPS(b, s, e, g, MTP) 34 26 ··· 387 395 }; 388 396 389 397 static const struct intel_padgroup mtps_community0_gpps[] = { 390 - MTP_GPP(0, 0, 24, 0), /* GPP_D */ 391 - MTP_GPP(1, 25, 38, 32), /* GPP_R */ 392 - MTP_GPP(2, 39, 56, 64), /* GPP_J */ 393 - MTP_GPP(3, 57, 87, 96), /* vGPIO */ 398 + INTEL_GPP(0, 0, 24, 0), /* GPP_D */ 399 + INTEL_GPP(1, 25, 38, 32), /* GPP_R */ 400 + INTEL_GPP(2, 39, 56, 64), /* GPP_J */ 401 + INTEL_GPP(3, 57, 87, 96), /* vGPIO */ 394 402 }; 395 403 396 404 static const struct intel_padgroup mtps_community1_gpps[] = { 397 - MTP_GPP(0, 88, 102, 128), /* GPP_A */ 398 - MTP_GPP(1, 103, 114, 160), /* DIR_ESPI */ 399 - MTP_GPP(2, 115, 136, 192), /* GPP_B */ 405 + INTEL_GPP(0, 88, 102, 128), /* GPP_A */ 406 + INTEL_GPP(1, 103, 114, 160), /* DIR_ESPI */ 407 + INTEL_GPP(2, 115, 136, 192), /* GPP_B */ 400 408 }; 401 409 402 410 static const struct intel_padgroup mtps_community3_gpps[] = { 403 - MTP_GPP(0, 137, 145, 224), /* SPI0 */ 404 - MTP_GPP(1, 146, 169, 256), /* GPP_C */ 405 - MTP_GPP(2, 170, 189, 288), /* GPP_H */ 406 - MTP_GPP(3, 190, 193, 320), /* vGPIO_3 */ 407 - MTP_GPP(4, 194, 201, 352), /* vGPIO_0 */ 408 - MTP_GPP(5, 202, 232, 384), /* vGPIO_4 */ 411 + INTEL_GPP(0, 137, 145, 224), /* SPI0 */ 412 + INTEL_GPP(1, 146, 169, 256), /* GPP_C */ 413 + INTEL_GPP(2, 170, 189, 288), /* GPP_H */ 414 + INTEL_GPP(3, 190, 193, 320), /* vGPIO_3 */ 415 + INTEL_GPP(4, 194, 201, 352), /* vGPIO_0 */ 416 + INTEL_GPP(5, 202, 232, 384), /* vGPIO_4 */ 409 417 }; 410 418 411 419 static const struct intel_padgroup mtps_community4_gpps[] = { 412 - MTP_GPP(0, 233, 240, 416), /* GPP_S */ 413 - MTP_GPP(1, 241, 263, 448), /* GPP_E */ 414 - MTP_GPP(2, 264, 277, 480), /* GPP_K */ 415 - MTP_GPP(3, 278, 301, 512), /* GPP_F */ 420 + INTEL_GPP(0, 233, 240, 416), /* GPP_S */ 421 + INTEL_GPP(1, 241, 263, 448), /* GPP_E */ 422 + INTEL_GPP(2, 264, 277, 480), /* GPP_K */ 423 + INTEL_GPP(3, 278, 301, 512), /* GPP_F */ 416 424 }; 417 425 418 426 static const struct intel_padgroup mtps_community5_gpps[] = { 419 - MTP_GPP(0, 302, 322, 544), /* GPP_I */ 420 - MTP_GPP(1, 323, 338, 576), /* JTAG_CPU */ 427 + INTEL_GPP(0, 302, 322, 544), /* GPP_I */ 428 + INTEL_GPP(1, 323, 338, 576), /* JTAG_CPU */ 421 429 }; 422 430 423 431 static const struct intel_community mtps_communities[] = {
+9 -17
drivers/pinctrl/intel/pinctrl-sunrisepoint.c
··· 28 28 #define SPT_LP_GPI_IS 0x100 29 29 #define SPT_LP_GPI_IE 0x120 30 30 31 - #define SPT_H_GPP(r, s, e, g) \ 32 - { \ 33 - .reg_num = (r), \ 34 - .base = (s), \ 35 - .size = ((e) - (s) + 1), \ 36 - .gpio_base = (g), \ 37 - } 38 - 39 31 #define SPT_H_COMMUNITY(b, s, e, g) \ 40 32 INTEL_COMMUNITY_GPPS(b, s, e, g, SPT_H) 41 33 ··· 530 538 }; 531 539 532 540 static const struct intel_padgroup spth_community0_gpps[] = { 533 - SPT_H_GPP(0, 0, 23, 0), /* GPP_A */ 534 - SPT_H_GPP(1, 24, 47, 24), /* GPP_B */ 541 + INTEL_GPP(0, 0, 23, 0), /* GPP_A */ 542 + INTEL_GPP(1, 24, 47, 24), /* GPP_B */ 535 543 }; 536 544 537 545 static const struct intel_padgroup spth_community1_gpps[] = { 538 - SPT_H_GPP(0, 48, 71, 48), /* GPP_C */ 539 - SPT_H_GPP(1, 72, 95, 72), /* GPP_D */ 540 - SPT_H_GPP(2, 96, 108, 96), /* GPP_E */ 541 - SPT_H_GPP(3, 109, 132, 120), /* GPP_F */ 542 - SPT_H_GPP(4, 133, 156, 144), /* GPP_G */ 543 - SPT_H_GPP(5, 157, 180, 168), /* GPP_H */ 546 + INTEL_GPP(0, 48, 71, 48), /* GPP_C */ 547 + INTEL_GPP(1, 72, 95, 72), /* GPP_D */ 548 + INTEL_GPP(2, 96, 108, 96), /* GPP_E */ 549 + INTEL_GPP(3, 109, 132, 120), /* GPP_F */ 550 + INTEL_GPP(4, 133, 156, 144), /* GPP_G */ 551 + INTEL_GPP(5, 157, 180, 168), /* GPP_H */ 544 552 }; 545 553 546 554 static const struct intel_padgroup spth_community3_gpps[] = { 547 - SPT_H_GPP(0, 181, 191, 192), /* GPP_I */ 555 + INTEL_GPP(0, 181, 191, 192), /* GPP_I */ 548 556 }; 549 557 550 558 static const struct intel_community spth_communities[] = {
+1 -2
drivers/pinctrl/intel/pinctrl-tangier.c
··· 562 562 563 563 tp->pctldev = devm_pinctrl_register(dev, &tp->pctldesc, tp); 564 564 if (IS_ERR(tp->pctldev)) 565 - return dev_err_probe(dev, PTR_ERR(tp->pctldev), 566 - "failed to register pinctrl driver\n"); 565 + return dev_err_probe(dev, PTR_ERR(tp->pctldev), "failed to register pinctrl\n"); 567 566 568 567 return 0; 569 568 }
+31 -39
drivers/pinctrl/intel/pinctrl-tigerlake.c
··· 28 28 #define TGL_H_GPI_IS 0x100 29 29 #define TGL_H_GPI_IE 0x120 30 30 31 - #define TGL_GPP(r, s, e, g) \ 32 - { \ 33 - .reg_num = (r), \ 34 - .base = (s), \ 35 - .size = ((e) - (s) + 1), \ 36 - .gpio_base = (g), \ 37 - } 38 - 39 31 #define TGL_LP_COMMUNITY(b, s, e, g) \ 40 32 INTEL_COMMUNITY_GPPS(b, s, e, g, TGL_LP) 41 33 ··· 331 339 }; 332 340 333 341 static const struct intel_padgroup tgllp_community0_gpps[] = { 334 - TGL_GPP(0, 0, 25, 0), /* GPP_B */ 335 - TGL_GPP(1, 26, 41, 32), /* GPP_T */ 336 - TGL_GPP(2, 42, 66, 64), /* GPP_A */ 342 + INTEL_GPP(0, 0, 25, 0), /* GPP_B */ 343 + INTEL_GPP(1, 26, 41, 32), /* GPP_T */ 344 + INTEL_GPP(2, 42, 66, 64), /* GPP_A */ 337 345 }; 338 346 339 347 static const struct intel_padgroup tgllp_community1_gpps[] = { 340 - TGL_GPP(0, 67, 74, 96), /* GPP_S */ 341 - TGL_GPP(1, 75, 98, 128), /* GPP_H */ 342 - TGL_GPP(2, 99, 119, 160), /* GPP_D */ 343 - TGL_GPP(3, 120, 143, 192), /* GPP_U */ 344 - TGL_GPP(4, 144, 170, 224), /* vGPIO */ 348 + INTEL_GPP(0, 67, 74, 96), /* GPP_S */ 349 + INTEL_GPP(1, 75, 98, 128), /* GPP_H */ 350 + INTEL_GPP(2, 99, 119, 160), /* GPP_D */ 351 + INTEL_GPP(3, 120, 143, 192), /* GPP_U */ 352 + INTEL_GPP(4, 144, 170, 224), /* vGPIO */ 345 353 }; 346 354 347 355 static const struct intel_padgroup tgllp_community4_gpps[] = { 348 - TGL_GPP(0, 171, 194, 256), /* GPP_C */ 349 - TGL_GPP(1, 195, 219, 288), /* GPP_F */ 350 - TGL_GPP(2, 220, 225, INTEL_GPIO_BASE_NOMAP), /* HVCMOS */ 351 - TGL_GPP(3, 226, 250, 320), /* GPP_E */ 352 - TGL_GPP(4, 251, 259, INTEL_GPIO_BASE_NOMAP), /* JTAG */ 356 + INTEL_GPP(0, 171, 194, 256), /* GPP_C */ 357 + INTEL_GPP(1, 195, 219, 288), /* GPP_F */ 358 + INTEL_GPP(2, 220, 225, INTEL_GPIO_BASE_NOMAP), /* HVCMOS */ 359 + INTEL_GPP(3, 226, 250, 320), /* GPP_E */ 360 + INTEL_GPP(4, 251, 259, INTEL_GPIO_BASE_NOMAP), /* JTAG */ 353 361 }; 354 362 355 363 static const struct intel_padgroup tgllp_community5_gpps[] = { 356 - TGL_GPP(0, 260, 267, 352), /* GPP_R */ 357 - TGL_GPP(1, 268, 276, INTEL_GPIO_BASE_NOMAP), /* SPI */ 364 + INTEL_GPP(0, 260, 267, 352), /* GPP_R */ 365 + INTEL_GPP(1, 268, 276, INTEL_GPIO_BASE_NOMAP), /* SPI */ 358 366 }; 359 367 360 368 static const struct intel_community tgllp_communities[] = { ··· 683 691 }; 684 692 685 693 static const struct intel_padgroup tglh_community0_gpps[] = { 686 - TGL_GPP(0, 0, 24, 0), /* GPP_A */ 687 - TGL_GPP(1, 25, 44, 32), /* GPP_R */ 688 - TGL_GPP(2, 45, 70, 64), /* GPP_B */ 689 - TGL_GPP(3, 71, 78, 96), /* vGPIO_0 */ 694 + INTEL_GPP(0, 0, 24, 0), /* GPP_A */ 695 + INTEL_GPP(1, 25, 44, 32), /* GPP_R */ 696 + INTEL_GPP(2, 45, 70, 64), /* GPP_B */ 697 + INTEL_GPP(3, 71, 78, 96), /* vGPIO_0 */ 690 698 }; 691 699 692 700 static const struct intel_padgroup tglh_community1_gpps[] = { 693 - TGL_GPP(0, 79, 104, 128), /* GPP_D */ 694 - TGL_GPP(1, 105, 128, 160), /* GPP_C */ 695 - TGL_GPP(2, 129, 136, 192), /* GPP_S */ 696 - TGL_GPP(3, 137, 153, 224), /* GPP_G */ 697 - TGL_GPP(4, 154, 180, 256), /* vGPIO */ 701 + INTEL_GPP(0, 79, 104, 128), /* GPP_D */ 702 + INTEL_GPP(1, 105, 128, 160), /* GPP_C */ 703 + INTEL_GPP(2, 129, 136, 192), /* GPP_S */ 704 + INTEL_GPP(3, 137, 153, 224), /* GPP_G */ 705 + INTEL_GPP(4, 154, 180, 256), /* vGPIO */ 698 706 }; 699 707 700 708 static const struct intel_padgroup tglh_community3_gpps[] = { 701 - TGL_GPP(0, 181, 193, 288), /* GPP_E */ 702 - TGL_GPP(1, 194, 217, 320), /* GPP_F */ 709 + INTEL_GPP(0, 181, 193, 288), /* GPP_E */ 710 + INTEL_GPP(1, 194, 217, 320), /* GPP_F */ 703 711 }; 704 712 705 713 static const struct intel_padgroup tglh_community4_gpps[] = { 706 - TGL_GPP(0, 218, 241, 352), /* GPP_H */ 707 - TGL_GPP(1, 242, 251, 384), /* GPP_J */ 708 - TGL_GPP(2, 252, 266, 416), /* GPP_K */ 714 + INTEL_GPP(0, 218, 241, 352), /* GPP_H */ 715 + INTEL_GPP(1, 242, 251, 384), /* GPP_J */ 716 + INTEL_GPP(2, 252, 266, 416), /* GPP_K */ 709 717 }; 710 718 711 719 static const struct intel_padgroup tglh_community5_gpps[] = { 712 - TGL_GPP(0, 267, 281, 448), /* GPP_I */ 713 - TGL_GPP(1, 282, 290, INTEL_GPIO_BASE_NOMAP), /* JTAG */ 720 + INTEL_GPP(0, 267, 281, 448), /* GPP_I */ 721 + INTEL_GPP(1, 282, 290, INTEL_GPIO_BASE_NOMAP), /* JTAG */ 714 722 }; 715 723 716 724 static const struct intel_community tglh_communities[] = {