-16

arch/arm64/Kconfig

reviewed

··· 1873 1873 The feature is detected at runtime, and will remain as a 'nop' 1874 1874 instruction if the cpu does not implement the feature. 1875 1875 1876 1876 - config ARM64_LSE_ATOMICS 1877 1877 - bool 1878 1878 - default ARM64_USE_LSE_ATOMICS 1879 1879 - 1880 1880 - config ARM64_USE_LSE_ATOMICS 1881 1881 - bool "Atomic instructions" 1882 1882 - default y 1883 1883 - help 1884 1884 - As part of the Large System Extensions, ARMv8.1 introduces new 1885 1885 - atomic instructions that are designed specifically to scale in 1886 1886 - very large systems. 1887 1887 - 1888 1888 - Say Y here to make use of these instructions for the in-kernel 1889 1889 - atomic routines. This incurs a small overhead on CPUs that do 1890 1890 - not support these instructions. 1891 1891 - 1892 1876 endmenu # "ARMv8.1 architectural features" 1893 1877 1894 1878 menu "ARMv8.2 architectural features"

-23

arch/arm64/include/asm/insn.h

reviewed

··· 671 671 enum aarch64_insn_register Rn, 672 672 enum aarch64_insn_register Rd, 673 673 u8 lsb); 674 674 - #ifdef CONFIG_ARM64_LSE_ATOMICS 675 674 u32 aarch64_insn_gen_atomic_ld_op(enum aarch64_insn_register result, 676 675 enum aarch64_insn_register address, 677 676 enum aarch64_insn_register value, ··· 682 683 enum aarch64_insn_register value, 683 684 enum aarch64_insn_size_type size, 684 685 enum aarch64_insn_mem_order_type order); 685 685 - #else 686 686 - static inline 687 687 - u32 aarch64_insn_gen_atomic_ld_op(enum aarch64_insn_register result, 688 688 - enum aarch64_insn_register address, 689 689 - enum aarch64_insn_register value, 690 690 - enum aarch64_insn_size_type size, 691 691 - enum aarch64_insn_mem_atomic_op op, 692 692 - enum aarch64_insn_mem_order_type order) 693 693 - { 694 694 - return AARCH64_BREAK_FAULT; 695 695 - } 696 696 - 697 697 - static inline 698 698 - u32 aarch64_insn_gen_cas(enum aarch64_insn_register result, 699 699 - enum aarch64_insn_register address, 700 700 - enum aarch64_insn_register value, 701 701 - enum aarch64_insn_size_type size, 702 702 - enum aarch64_insn_mem_order_type order) 703 703 - { 704 704 - return AARCH64_BREAK_FAULT; 705 705 - } 706 706 - #endif 707 686 u32 aarch64_insn_gen_dmb(enum aarch64_insn_mb_type type); 708 687 u32 aarch64_insn_gen_dsb(enum aarch64_insn_mb_type type); 709 688 u32 aarch64_insn_gen_mrs(enum aarch64_insn_register result,

-9

arch/arm64/include/asm/lse.h

reviewed

··· 4 4 5 5 #include <asm/atomic_ll_sc.h> 6 6 7 7 - #ifdef CONFIG_ARM64_LSE_ATOMICS 8 8 - 9 7 #define __LSE_PREAMBLE ".arch_extension lse\n" 10 8 11 9 #include <linux/compiler_types.h> ··· 25 27 #define ARM64_LSE_ATOMIC_INSN(llsc, lse) \ 26 28 ALTERNATIVE(llsc, __LSE_PREAMBLE lse, ARM64_HAS_LSE_ATOMICS) 27 29 28 28 - #else /* CONFIG_ARM64_LSE_ATOMICS */ 29 29 - 30 30 - #define __lse_ll_sc_body(op, ...) __ll_sc_##op(__VA_ARGS__) 31 31 - 32 32 - #define ARM64_LSE_ATOMIC_INSN(llsc, lse) llsc 33 33 - 34 34 - #endif /* CONFIG_ARM64_LSE_ATOMICS */ 35 30 #endif /* __ASM_LSE_H */

-2

arch/arm64/kernel/cpufeature.c

reviewed

··· 2560 2560 ARM64_CPUID_FIELDS(ID_AA64MMFR1_EL1, PAN, PAN3) 2561 2561 }, 2562 2562 #endif /* CONFIG_ARM64_EPAN */ 2563 2563 - #ifdef CONFIG_ARM64_LSE_ATOMICS 2564 2563 { 2565 2564 .desc = "LSE atomic instructions", 2566 2565 .capability = ARM64_HAS_LSE_ATOMICS, ··· 2567 2568 .matches = has_cpuid_feature, 2568 2569 ARM64_CPUID_FIELDS(ID_AA64ISAR0_EL1, ATOMIC, IMP) 2569 2570 }, 2570 2570 - #endif /* CONFIG_ARM64_LSE_ATOMICS */ 2571 2571 { 2572 2572 .desc = "Virtualization Host Extensions", 2573 2573 .capability = ARM64_HAS_VIRT_HOST_EXTN,

-7

arch/arm64/kvm/at.c

reviewed

··· 1700 1700 } 1701 1701 } 1702 1702 1703 1703 - #ifdef CONFIG_ARM64_LSE_ATOMICS 1704 1703 static int __lse_swap_desc(u64 __user *ptep, u64 old, u64 new) 1705 1704 { 1706 1705 u64 tmp = old; ··· 1724 1725 1725 1726 return ret; 1726 1727 } 1727 1727 - #else 1728 1728 - static int __lse_swap_desc(u64 __user *ptep, u64 old, u64 new) 1729 1729 - { 1730 1730 - return -EINVAL; 1731 1731 - } 1732 1732 - #endif 1733 1728 1734 1729 static int __llsc_swap_desc(u64 __user *ptep, u64 old, u64 new) 1735 1730 {

-2

arch/arm64/lib/insn.c

reviewed

··· 611 611 state); 612 612 } 613 613 614 614 - #ifdef CONFIG_ARM64_LSE_ATOMICS 615 614 static u32 aarch64_insn_encode_ldst_order(enum aarch64_insn_mem_order_type type, 616 615 u32 insn) 617 616 { ··· 754 755 return aarch64_insn_encode_register(AARCH64_INSN_REGTYPE_RS, insn, 755 756 value); 756 757 } 757 757 - #endif 758 758 759 759 u32 aarch64_insn_gen_add_sub_imm(enum aarch64_insn_register dst, 760 760 enum aarch64_insn_register src,

-7

arch/arm64/net/bpf_jit_comp.c

reviewed

··· 776 776 return 0; 777 777 } 778 778 779 779 - #ifdef CONFIG_ARM64_LSE_ATOMICS 780 779 static int emit_lse_atomic(const struct bpf_insn *insn, struct jit_ctx *ctx) 781 780 { 782 781 const u8 code = insn->code; ··· 842 843 843 844 return 0; 844 845 } 845 845 - #else 846 846 - static inline int emit_lse_atomic(const struct bpf_insn *insn, struct jit_ctx *ctx) 847 847 - { 848 848 - return -EINVAL; 849 849 - } 850 850 - #endif 851 846 852 847 static int emit_ll_sc_atomic(const struct bpf_insn *insn, struct jit_ctx *ctx) 853 848 {