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drm/msm/a6xx: Add support for Debug HFI Q

Add the Debug HFI Queue which contains the F2H messages posted from the
GMU firmware. Having this data in coredump is useful to debug firmware
issues.

Signed-off-by: Akhil P Oommen <akhilpo@oss.qualcomm.com>
Reviewed-by: Konrad Dybcio <konrad.dybcio@oss.qualcomm.com>
Patchwork: https://patchwork.freedesktop.org/patch/714666/
Message-ID: <20260327-a8xx-gpu-batch2-v2-7-2b53c38d2101@oss.qualcomm.com>
Signed-off-by: Rob Clark <robin.clark@oss.qualcomm.com>

authored by

Akhil P Oommen and committed by
Rob Clark 61957ab9 bb9b1d6e

+17 -5
+1 -1
drivers/gpu/drm/msm/adreno/a6xx_gmu.h
··· 111 111 112 112 unsigned long freq; 113 113 114 - struct a6xx_hfi_queue queues[2]; 114 + struct a6xx_hfi_queue queues[HFI_MAX_QUEUES]; 115 115 116 116 bool initialized; 117 117 bool hung;
+1 -1
drivers/gpu/drm/msm/adreno/a6xx_gpu_state.c
··· 57 57 struct msm_gpu_state_bo *gmu_hfi; 58 58 struct msm_gpu_state_bo *gmu_debug; 59 59 60 - s32 hfi_queue_history[2][HFI_HISTORY_SZ]; 60 + s32 hfi_queue_history[HFI_MAX_QUEUES][HFI_HISTORY_SZ]; 61 61 62 62 struct list_head objs; 63 63
+13 -3
drivers/gpu/drm/msm/adreno/a6xx_hfi.c
··· 1062 1062 struct a6xx_gmu_bo *hfi = &gmu->hfi; 1063 1063 struct a6xx_hfi_queue_table_header *table = hfi->virt; 1064 1064 struct a6xx_hfi_queue_header *headers = hfi->virt + sizeof(*table); 1065 + int table_size, idx; 1065 1066 u64 offset; 1066 - int table_size; 1067 1067 1068 1068 /* 1069 1069 * The table size is the size of the table header plus all of the queue ··· 1082 1082 table->active_queues = ARRAY_SIZE(gmu->queues); 1083 1083 1084 1084 /* Command queue */ 1085 + idx = 0; 1085 1086 offset = SZ_4K; 1086 - a6xx_hfi_queue_init(&gmu->queues[0], &headers[0], hfi->virt + offset, 1087 + a6xx_hfi_queue_init(&gmu->queues[idx], &headers[idx], hfi->virt + offset, 1087 1088 hfi->iova + offset, 0); 1088 1089 1089 1090 /* GMU response queue */ 1091 + idx++; 1090 1092 offset += SZ_4K; 1091 - a6xx_hfi_queue_init(&gmu->queues[1], &headers[1], hfi->virt + offset, 1093 + a6xx_hfi_queue_init(&gmu->queues[idx], &headers[idx], hfi->virt + offset, 1092 1094 hfi->iova + offset, gmu->legacy ? 4 : 1); 1095 + 1096 + /* GMU Debug queue */ 1097 + idx++; 1098 + offset += SZ_4K; 1099 + a6xx_hfi_queue_init(&gmu->queues[idx], &headers[idx], hfi->virt + offset, 1100 + hfi->iova + offset, gmu->legacy ? 5 : 2); 1101 + 1102 + WARN_ON(idx >= HFI_MAX_QUEUES); 1093 1103 }
+2
drivers/gpu/drm/msm/adreno/a6xx_hfi.h
··· 4 4 #ifndef _A6XX_HFI_H_ 5 5 #define _A6XX_HFI_H_ 6 6 7 + #define HFI_MAX_QUEUES 3 8 + 7 9 struct a6xx_hfi_queue_table_header { 8 10 u32 version; 9 11 u32 size; /* Size of the queue table in dwords */