Linux kernel mirror (for testing)
git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git
kernel
os
linux
drm/amdkfd: Set per-process flags only once for gfx9/10/11/12
Define set_cache_memory_policy() for these asics and move all static
changes from update_qpd() which is called each time a queue is created
to set_cache_memory_policy() which is called once during process
initialization
Signed-off-by: Harish Kasiviswanathan <Harish.Kasiviswanathan@amd.com>
Reviewed-by: Amber Lin <Amber.Lin@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
authored by
Harish Kasiviswanathan
and committed by
Alex Deucher
61972cd9
289e6850
+112
-57
+25
-18
drivers/gpu/drm/amd/amdkfd/kfd_device_queue_manager_v10.c
+25
-18
drivers/gpu/drm/amd/amdkfd/kfd_device_queue_manager_v10.c
···
31
31
struct qcm_process_device *qpd);
32
32
static void init_sdma_vm_v10(struct device_queue_manager *dqm, struct queue *q,
33
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struct qcm_process_device *qpd);
34
+
static bool set_cache_memory_policy_v10(struct device_queue_manager *dqm,
35
+
struct qcm_process_device *qpd,
36
+
enum cache_policy default_policy,
37
+
enum cache_policy alternate_policy,
38
+
void __user *alternate_aperture_base,
39
+
uint64_t alternate_aperture_size);
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void device_queue_manager_init_v10(
36
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struct device_queue_manager_asic_ops *asic_ops)
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{
44
+
asic_ops->set_cache_memory_policy = set_cache_memory_policy_v10;
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asic_ops->update_qpd = update_qpd_v10;
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asic_ops->init_sdma_vm = init_sdma_vm_v10;
40
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asic_ops->mqd_manager_init = mqd_manager_init_v10;
···
56
49
private_base;
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}
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+
static bool set_cache_memory_policy_v10(struct device_queue_manager *dqm,
53
+
struct qcm_process_device *qpd,
54
+
enum cache_policy default_policy,
55
+
enum cache_policy alternate_policy,
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+
void __user *alternate_aperture_base,
57
+
uint64_t alternate_aperture_size)
58
+
{
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+
qpd->sh_mem_config = (SH_MEM_ALIGNMENT_MODE_UNALIGNED <<
60
+
SH_MEM_CONFIG__ALIGNMENT_MODE__SHIFT) |
61
+
(3 << SH_MEM_CONFIG__INITIAL_INST_PREFETCH__SHIFT);
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+
qpd->sh_mem_ape1_limit = 0;
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+
qpd->sh_mem_ape1_base = 0;
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+
qpd->sh_mem_bases = compute_sh_mem_bases_64bit(qpd_to_pdd(qpd));
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+
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+
pr_debug("sh_mem_bases 0x%X\n", qpd->sh_mem_bases);
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+
return true;
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+
}
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+
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static int update_qpd_v10(struct device_queue_manager *dqm,
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struct qcm_process_device *qpd)
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{
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struct kfd_process_device *pdd;
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-
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pdd = qpd_to_pdd(qpd);
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-
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-
/* check if sh_mem_config register already configured */
67
-
if (qpd->sh_mem_config == 0) {
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-
qpd->sh_mem_config =
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-
(SH_MEM_ALIGNMENT_MODE_UNALIGNED <<
70
-
SH_MEM_CONFIG__ALIGNMENT_MODE__SHIFT) |
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-
(3 << SH_MEM_CONFIG__INITIAL_INST_PREFETCH__SHIFT);
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-
qpd->sh_mem_ape1_limit = 0;
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-
qpd->sh_mem_ape1_base = 0;
74
-
}
75
-
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-
qpd->sh_mem_bases = compute_sh_mem_bases_64bit(pdd);
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-
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-
pr_debug("sh_mem_bases 0x%X\n", qpd->sh_mem_bases);
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-
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return 0;
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}
82
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+26
-19
drivers/gpu/drm/amd/amdkfd/kfd_device_queue_manager_v11.c
+26
-19
drivers/gpu/drm/amd/amdkfd/kfd_device_queue_manager_v11.c
···
30
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struct qcm_process_device *qpd);
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static void init_sdma_vm_v11(struct device_queue_manager *dqm, struct queue *q,
32
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struct qcm_process_device *qpd);
33
+
static bool set_cache_memory_policy_v11(struct device_queue_manager *dqm,
34
+
struct qcm_process_device *qpd,
35
+
enum cache_policy default_policy,
36
+
enum cache_policy alternate_policy,
37
+
void __user *alternate_aperture_base,
38
+
uint64_t alternate_aperture_size);
33
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34
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void device_queue_manager_init_v11(
35
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struct device_queue_manager_asic_ops *asic_ops)
36
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{
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asic_ops->set_cache_memory_policy = set_cache_memory_policy_v11;
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asic_ops->update_qpd = update_qpd_v11;
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asic_ops->init_sdma_vm = init_sdma_vm_v11;
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asic_ops->mqd_manager_init = mqd_manager_init_v11;
···
55
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private_base;
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}
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51
+
static bool set_cache_memory_policy_v11(struct device_queue_manager *dqm,
52
+
struct qcm_process_device *qpd,
53
+
enum cache_policy default_policy,
54
+
enum cache_policy alternate_policy,
55
+
void __user *alternate_aperture_base,
56
+
uint64_t alternate_aperture_size)
57
+
{
58
+
qpd->sh_mem_config = (SH_MEM_ALIGNMENT_MODE_UNALIGNED <<
59
+
SH_MEM_CONFIG__ALIGNMENT_MODE__SHIFT) |
60
+
(3 << SH_MEM_CONFIG__INITIAL_INST_PREFETCH__SHIFT);
61
+
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+
qpd->sh_mem_ape1_limit = 0;
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+
qpd->sh_mem_ape1_base = 0;
64
+
qpd->sh_mem_bases = compute_sh_mem_bases_64bit(qpd_to_pdd(qpd));
65
+
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pr_debug("sh_mem_bases 0x%X\n", qpd->sh_mem_bases);
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return true;
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+
}
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+
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static int update_qpd_v11(struct device_queue_manager *dqm,
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struct qcm_process_device *qpd)
60
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{
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struct kfd_process_device *pdd;
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-
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pdd = qpd_to_pdd(qpd);
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-
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/* check if sh_mem_config register already configured */
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-
if (qpd->sh_mem_config == 0) {
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qpd->sh_mem_config =
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(SH_MEM_ALIGNMENT_MODE_UNALIGNED <<
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-
SH_MEM_CONFIG__ALIGNMENT_MODE__SHIFT) |
70
-
(3 << SH_MEM_CONFIG__INITIAL_INST_PREFETCH__SHIFT);
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-
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qpd->sh_mem_ape1_limit = 0;
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qpd->sh_mem_ape1_base = 0;
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-
}
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-
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qpd->sh_mem_bases = compute_sh_mem_bases_64bit(pdd);
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-
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pr_debug("sh_mem_bases 0x%X\n", qpd->sh_mem_bases);
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-
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return 0;
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}
82
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+26
-19
drivers/gpu/drm/amd/amdkfd/kfd_device_queue_manager_v12.c
+26
-19
drivers/gpu/drm/amd/amdkfd/kfd_device_queue_manager_v12.c
···
30
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struct qcm_process_device *qpd);
31
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static void init_sdma_vm_v12(struct device_queue_manager *dqm, struct queue *q,
32
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struct qcm_process_device *qpd);
33
+
static bool set_cache_memory_policy_v12(struct device_queue_manager *dqm,
34
+
struct qcm_process_device *qpd,
35
+
enum cache_policy default_policy,
36
+
enum cache_policy alternate_policy,
37
+
void __user *alternate_aperture_base,
38
+
uint64_t alternate_aperture_size);
33
39
34
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void device_queue_manager_init_v12(
35
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struct device_queue_manager_asic_ops *asic_ops)
36
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{
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asic_ops->set_cache_memory_policy = set_cache_memory_policy_v12;
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asic_ops->update_qpd = update_qpd_v12;
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asic_ops->init_sdma_vm = init_sdma_vm_v12;
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asic_ops->mqd_manager_init = mqd_manager_init_v12;
···
55
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private_base;
56
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}
57
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51
+
static bool set_cache_memory_policy_v12(struct device_queue_manager *dqm,
52
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struct qcm_process_device *qpd,
53
+
enum cache_policy default_policy,
54
+
enum cache_policy alternate_policy,
55
+
void __user *alternate_aperture_base,
56
+
uint64_t alternate_aperture_size)
57
+
{
58
+
qpd->sh_mem_config = (SH_MEM_ALIGNMENT_MODE_UNALIGNED <<
59
+
SH_MEM_CONFIG__ALIGNMENT_MODE__SHIFT) |
60
+
(3 << SH_MEM_CONFIG__INITIAL_INST_PREFETCH__SHIFT);
61
+
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qpd->sh_mem_ape1_limit = 0;
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qpd->sh_mem_ape1_base = 0;
64
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qpd->sh_mem_bases = compute_sh_mem_bases_64bit(qpd_to_pdd(qpd));
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+
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pr_debug("sh_mem_bases 0x%X\n", qpd->sh_mem_bases);
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return true;
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}
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+
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static int update_qpd_v12(struct device_queue_manager *dqm,
59
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struct qcm_process_device *qpd)
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{
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struct kfd_process_device *pdd;
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pdd = qpd_to_pdd(qpd);
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/* check if sh_mem_config register already configured */
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if (qpd->sh_mem_config == 0) {
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qpd->sh_mem_config =
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(SH_MEM_ALIGNMENT_MODE_UNALIGNED <<
69
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SH_MEM_CONFIG__ALIGNMENT_MODE__SHIFT) |
70
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(3 << SH_MEM_CONFIG__INITIAL_INST_PREFETCH__SHIFT);
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-
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qpd->sh_mem_ape1_limit = 0;
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qpd->sh_mem_ape1_base = 0;
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-
}
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-
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qpd->sh_mem_bases = compute_sh_mem_bases_64bit(pdd);
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-
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pr_debug("sh_mem_bases 0x%X\n", qpd->sh_mem_bases);
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return 0;
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}
82
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+35
-1
drivers/gpu/drm/amd/amdkfd/kfd_device_queue_manager_v9.c
+35
-1
drivers/gpu/drm/amd/amdkfd/kfd_device_queue_manager_v9.c
···
30
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struct qcm_process_device *qpd);
31
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static void init_sdma_vm_v9(struct device_queue_manager *dqm, struct queue *q,
32
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struct qcm_process_device *qpd);
33
+
static bool set_cache_memory_policy_v9(struct device_queue_manager *dqm,
34
+
struct qcm_process_device *qpd,
35
+
enum cache_policy default_policy,
36
+
enum cache_policy alternate_policy,
37
+
void __user *alternate_aperture_base,
38
+
uint64_t alternate_aperture_size);
33
39
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void device_queue_manager_init_v9(
35
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struct device_queue_manager_asic_ops *asic_ops)
36
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{
43
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asic_ops->set_cache_memory_policy = set_cache_memory_policy_v9;
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asic_ops->update_qpd = update_qpd_v9;
38
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asic_ops->init_sdma_vm = init_sdma_vm_v9;
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asic_ops->mqd_manager_init = mqd_manager_init_v9;
···
55
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private_base;
56
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}
57
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51
+
static bool set_cache_memory_policy_v9(struct device_queue_manager *dqm,
52
+
struct qcm_process_device *qpd,
53
+
enum cache_policy default_policy,
54
+
enum cache_policy alternate_policy,
55
+
void __user *alternate_aperture_base,
56
+
uint64_t alternate_aperture_size)
57
+
{
58
+
qpd->sh_mem_config = SH_MEM_ALIGNMENT_MODE_UNALIGNED <<
59
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SH_MEM_CONFIG__ALIGNMENT_MODE__SHIFT;
60
+
61
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if (dqm->dev->kfd->noretry)
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qpd->sh_mem_config |= 1 << SH_MEM_CONFIG__RETRY_DISABLE__SHIFT;
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+
64
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if (KFD_GC_VERSION(dqm->dev->kfd) == IP_VERSION(9, 4, 3) ||
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KFD_GC_VERSION(dqm->dev->kfd) == IP_VERSION(9, 4, 4) ||
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KFD_GC_VERSION(dqm->dev->kfd) == IP_VERSION(9, 5, 0))
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qpd->sh_mem_config |= (1 << SH_MEM_CONFIG__F8_MODE__SHIFT);
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+
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qpd->sh_mem_ape1_limit = 0;
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qpd->sh_mem_ape1_base = 0;
71
+
qpd->sh_mem_bases = compute_sh_mem_bases_64bit(qpd_to_pdd(qpd));
72
+
73
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pr_debug("sh_mem_bases 0x%X sh_mem_config 0x%X\n", qpd->sh_mem_bases,
74
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qpd->sh_mem_config);
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return true;
76
+
}
77
+
58
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static int update_qpd_v9(struct device_queue_manager *dqm,
59
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struct qcm_process_device *qpd)
60
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{
61
-
struct kfd_process_device *pdd;
81
+
struct kfd_process_device *pdd = qpd_to_pdd(qpd);
62
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pdd = qpd_to_pdd(qpd);
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