Linux kernel mirror (for testing)
git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git
kernel
os
linux
Merge tag 'clk-for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/clk/linux
Pull clk updates from Stephen Boyd:
"I'm actually surprised this time. There aren't any new Qualcomm SoC
clk drivers. And there's zero diff in the core clk framework.
Instead we have new clk drivers for STM and Sophgo, with
Samsung^WGoogle in third for the diffstat because they introduced HSI0
and HSI2 clk drivers for Google's GS101 SoC (high speed interface
things like PCIe, UFS, and MMC).
Beyond those big diffs there's the usual updates to various clk
drivers for incorrect parent descriptions or mising
MODULE_DEVICE_TABLE()s, etc. Nothing in particular stands out as super
interesting here.
New Drivers:
- STM32MP257 SoC clk driver
- Airoha EN7581 SoC clk driver
- Sophgo CV1800B, CV1812H and SG2000 SoC clk driver
- Loongson-2k0500 and Loongson-2k2000 SoC clk driver
- Add HSI0 and HSI2 clock controllers for Google GS101
- Add i.MX95 BLK CTL clock driver
Updates:
- Allocate clk_ops dynamically for SCMI clk driver
- Add support in qcom RCG and RCG2 for multiple configurations for
the same frequency
- Use above support for IPQ8074 NSS port 5 and 6 clocks to resolve
issues
- Fix the Qualcomm APSS IPQ5018 PLL to fix boot failures of some
boards
- Cleanups and fixes for Qualcomm Stromer PLLs
- Reduce max CPU frequency on Qualcomm APSS IPQ5018
- Fix Kconfig dependencies of Qualcomm SM8650 GPU and SC8280XP camera
clk drivers
- Make Qualcomm MSM8998 Venus clocks functional
- Cleanup downstream remnants related to DisplayPort across Qualcomm
SM8450, SM6350, SM8550, and SM8650
- Reuse the Huayra APSS register map on Qualcomm MSM8996 CBF PLL
- Use a specific Qualcomm QCS404 compatible for the otherwise generic
HFPLL
- Remove Qualcomm SM8150 CPUSS AHB clk as it is unused
- Remove an unused field in the Qualcomm RPM clk driver
- Add missing MODULE_DEVICE_TABLE to Qualcomm MSM8917 and MSM8953
global clock controller drivers
- Allow choice of manual or firmware-driven control over PLLs, needed
to fully implement CPU clock controllers on Exynos850
- Correct PLL clock IDs on ExynosAutov9
- Propagate certain clock rates to allow setting proper SPI clock
rates on Google GS101
- Mark certain Google GS101 clocks critical
- Convert old S3C64xx clock controller bindings to DT schema
- Add new PLL rate and missing mux on Rockchip rk3568
- Add missing reset line on Rockchip rk3588
- Removal of an unused field in struct rockchip_mmc_clock
- Amlogic s4/a1: add regmap maximum register for proper debugfs dump
- Amlogic s4: add MODULE_DEVICE_TABLE() on pll and periph controllers
- Amlogic pll driver: print clock name on lock error to help debug
- Amlogic vclk: finish dsi clock path support
- Amlogic license: fix occurence "GPL v2" as reported by checkpatch
- Add PM runtime support to i.MX8MP Audiomix
- Add DT schema for i.MX95 Display Master Block Control
- Convert to platform remove callback returning void for i.MX8MP
Audiomix
- Add SPI (MSIOF) and external interrupt (INTC-EX) clocks on Renesas
R-Car V4M
- Add interrupt controller (PLIC) clock and reset on Renesas RZ/Five
- Prepare power domain support for Renesas RZ/G2L family members, and
add actual support on Renesas RZ/G3S SoC
- Add thermal, serial (SCIF), and timer (CMT/TMU) clocks on Renesas
R-Car V4M
- Add additional constraints to Allwinner A64 PLL MIPI clock
- Fix autoloading sunxi-ng clocks when build as a module"
* tag 'clk-for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/clk/linux: (118 commits)
clk: samsung: Don't register clkdev lookup for the fixed rate clocks
clk, reset: microchip: mpfs: fix incorrect preprocessor conditions
clk: qcom: clk-alpha-pll: fix rate setting for Stromer PLLs
clk: qcom: apss-ipq-pll: fix PLL rate for IPQ5018
clk: qcom: Fix SM_GPUCC_8650 dependencies
clk: qcom: Fix SC_CAMCC_8280XP dependencies
dt-bindings: clocks: stm32mp25: add access-controllers description
clock, reset: microchip: move all mpfs reset code to the reset subsystem
clk: samsung: gs101: drop unused HSI2 clock parent data
clk: rockchip: rk3568: Add PLL rate for 724 MHz
clk: rockchip: Remove an unused field in struct rockchip_mmc_clock
dt-bindings: clock: fixed: Define a preferred node name
clk: meson: s4: fix module autoloading
clk: samsung: gs101: mark some apm UASC and XIU clocks critical
clk: imx: imx8mp: Convert to platform remove callback returning void
clk: imx: imx8mp: Switch to RUNTIME_PM_OPS()
clk: bcm: rpi: Assign ->num before accessing ->hws
clk: bcm: dvp: Assign ->num before accessing ->hws
clk: samsung: gs101: add support for cmu_hsi2
clk: samsung: gs101: add support for cmu_hsi0
...
+10956
-1200
+29
-2
Documentation/devicetree/bindings/clock/airoha,en7523-scu.yaml
+29
-2
Documentation/devicetree/bindings/clock/airoha,en7523-scu.yaml
···
29
29
properties:
30
30
compatible:
31
31
items:
32
-
- const: airoha,en7523-scu
32
+
- enum:
33
+
- airoha,en7523-scu
34
+
- airoha,en7581-scu
33
35
34
36
reg:
35
-
maxItems: 2
37
+
minItems: 2
38
+
maxItems: 3
36
39
37
40
"#clock-cells":
38
41
description:
···
47
44
- compatible
48
45
- reg
49
46
- '#clock-cells'
47
+
48
+
allOf:
49
+
- if:
50
+
properties:
51
+
compatible:
52
+
const: airoha,en7523-scu
53
+
then:
54
+
properties:
55
+
reg:
56
+
items:
57
+
- description: scu base address
58
+
- description: misc scu base address
59
+
60
+
- if:
61
+
properties:
62
+
compatible:
63
+
const: airoha,en7581-scu
64
+
then:
65
+
properties:
66
+
reg:
67
+
items:
68
+
- description: scu base address
69
+
- description: misc scu base address
70
+
- description: pb scu base address
50
71
51
72
additionalProperties: false
52
73
+9
Documentation/devicetree/bindings/clock/fixed-clock.yaml
+9
Documentation/devicetree/bindings/clock/fixed-clock.yaml
···
11
11
- Stephen Boyd <sboyd@kernel.org>
12
12
13
13
properties:
14
+
$nodename:
15
+
anyOf:
16
+
- description:
17
+
Preferred name is 'clock-<freq>' with <freq> being the output
18
+
frequency as defined in the 'clock-frequency' property.
19
+
pattern: "^clock-([0-9]+|[a-z0-9-]+)$"
20
+
- description: Any name allowed
21
+
deprecated: true
22
+
14
23
compatible:
15
24
const: fixed-clock
16
25
+9
Documentation/devicetree/bindings/clock/fixed-factor-clock.yaml
+9
Documentation/devicetree/bindings/clock/fixed-factor-clock.yaml
···
11
11
- Stephen Boyd <sboyd@kernel.org>
12
12
13
13
properties:
14
+
$nodename:
15
+
anyOf:
16
+
- description:
17
+
If the frequency is fixed, the preferred name is 'clock-<freq>' with
18
+
<freq> being the output frequency.
19
+
pattern: "^clock-([0-9]+|[0-9a-z-]+)$"
20
+
- description: Any name allowed
21
+
deprecated: true
22
+
14
23
compatible:
15
24
enum:
16
25
- fixed-factor-clock
+3
-1
Documentation/devicetree/bindings/clock/loongson,ls2k-clk.yaml
+3
-1
Documentation/devicetree/bindings/clock/loongson,ls2k-clk.yaml
+56
Documentation/devicetree/bindings/clock/nxp,imx95-blk-ctl.yaml
+56
Documentation/devicetree/bindings/clock/nxp,imx95-blk-ctl.yaml
···
1
+
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
2
+
%YAML 1.2
3
+
---
4
+
$id: http://devicetree.org/schemas/clock/nxp,imx95-blk-ctl.yaml#
5
+
$schema: http://devicetree.org/meta-schemas/core.yaml#
6
+
7
+
title: NXP i.MX95 Block Control
8
+
9
+
maintainers:
10
+
- Peng Fan <peng.fan@nxp.com>
11
+
12
+
properties:
13
+
compatible:
14
+
items:
15
+
- enum:
16
+
- nxp,imx95-lvds-csr
17
+
- nxp,imx95-display-csr
18
+
- nxp,imx95-camera-csr
19
+
- nxp,imx95-vpu-csr
20
+
- const: syscon
21
+
22
+
reg:
23
+
maxItems: 1
24
+
25
+
power-domains:
26
+
maxItems: 1
27
+
28
+
clocks:
29
+
maxItems: 1
30
+
31
+
'#clock-cells':
32
+
const: 1
33
+
description:
34
+
The clock consumer should specify the desired clock by having the clock
35
+
ID in its "clocks" phandle cell. See
36
+
include/dt-bindings/clock/nxp,imx95-clock.h
37
+
38
+
required:
39
+
- compatible
40
+
- reg
41
+
- '#clock-cells'
42
+
- power-domains
43
+
- clocks
44
+
45
+
additionalProperties: false
46
+
47
+
examples:
48
+
- |
49
+
syscon@4c410000 {
50
+
compatible = "nxp,imx95-vpu-csr", "syscon";
51
+
reg = <0x4c410000 0x10000>;
52
+
#clock-cells = <1>;
53
+
clocks = <&scmi_clk 114>;
54
+
power-domains = <&scmi_devpd 21>;
55
+
};
56
+
...
+64
Documentation/devicetree/bindings/clock/nxp,imx95-display-master-csr.yaml
+64
Documentation/devicetree/bindings/clock/nxp,imx95-display-master-csr.yaml
···
1
+
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
2
+
%YAML 1.2
3
+
---
4
+
$id: http://devicetree.org/schemas/clock/nxp,imx95-display-master-csr.yaml#
5
+
$schema: http://devicetree.org/meta-schemas/core.yaml#
6
+
7
+
title: NXP i.MX95 Display Master Block Control
8
+
9
+
maintainers:
10
+
- Peng Fan <peng.fan@nxp.com>
11
+
12
+
properties:
13
+
compatible:
14
+
items:
15
+
- const: nxp,imx95-display-master-csr
16
+
- const: syscon
17
+
18
+
reg:
19
+
maxItems: 1
20
+
21
+
power-domains:
22
+
maxItems: 1
23
+
24
+
clocks:
25
+
maxItems: 1
26
+
27
+
'#clock-cells':
28
+
const: 1
29
+
description:
30
+
The clock consumer should specify the desired clock by having the clock
31
+
ID in its "clocks" phandle cell. See
32
+
include/dt-bindings/clock/nxp,imx95-clock.h
33
+
34
+
mux-controller:
35
+
type: object
36
+
$ref: /schemas/mux/reg-mux.yaml
37
+
38
+
required:
39
+
- compatible
40
+
- reg
41
+
- '#clock-cells'
42
+
- mux-controller
43
+
- power-domains
44
+
- clocks
45
+
46
+
additionalProperties: false
47
+
48
+
examples:
49
+
- |
50
+
syscon@4c410000 {
51
+
compatible = "nxp,imx95-display-master-csr", "syscon";
52
+
reg = <0x4c410000 0x10000>;
53
+
#clock-cells = <1>;
54
+
clocks = <&scmi_clk 62>;
55
+
power-domains = <&scmi_devpd 3>;
56
+
57
+
mux: mux-controller {
58
+
compatible = "mmio-mux";
59
+
#mux-control-cells = <1>;
60
+
mux-reg-masks = <0x4 0x00000001>; /* Pixel_link_sel */
61
+
idle-states = <0>;
62
+
};
63
+
};
64
+
...
-63
Documentation/devicetree/bindings/clock/qcom,hfpll.txt
-63
Documentation/devicetree/bindings/clock/qcom,hfpll.txt
···
1
-
High-Frequency PLL (HFPLL)
2
-
3
-
PROPERTIES
4
-
5
-
- compatible:
6
-
Usage: required
7
-
Value type: <string>:
8
-
shall contain only one of the following. The generic
9
-
compatible "qcom,hfpll" should be also included.
10
-
11
-
"qcom,hfpll-ipq8064", "qcom,hfpll"
12
-
"qcom,hfpll-apq8064", "qcom,hfpll"
13
-
"qcom,hfpll-msm8974", "qcom,hfpll"
14
-
"qcom,hfpll-msm8960", "qcom,hfpll"
15
-
"qcom,msm8976-hfpll-a53", "qcom,hfpll"
16
-
"qcom,msm8976-hfpll-a72", "qcom,hfpll"
17
-
"qcom,msm8976-hfpll-cci", "qcom,hfpll"
18
-
19
-
- reg:
20
-
Usage: required
21
-
Value type: <prop-encoded-array>
22
-
Definition: address and size of HPLL registers. An optional second
23
-
element specifies the address and size of the alias
24
-
register region.
25
-
26
-
- clocks:
27
-
Usage: required
28
-
Value type: <prop-encoded-array>
29
-
Definition: reference to the xo clock.
30
-
31
-
- clock-names:
32
-
Usage: required
33
-
Value type: <stringlist>
34
-
Definition: must be "xo".
35
-
36
-
- clock-output-names:
37
-
Usage: required
38
-
Value type: <string>
39
-
Definition: Name of the PLL. Typically hfpllX where X is a CPU number
40
-
starting at 0. Otherwise hfpll_Y where Y is more specific
41
-
such as "l2".
42
-
43
-
Example:
44
-
45
-
1) An HFPLL for the L2 cache.
46
-
47
-
clock-controller@f9016000 {
48
-
compatible = "qcom,hfpll-ipq8064", "qcom,hfpll";
49
-
reg = <0xf9016000 0x30>;
50
-
clocks = <&xo_board>;
51
-
clock-names = "xo";
52
-
clock-output-names = "hfpll_l2";
53
-
};
54
-
55
-
2) An HFPLL for CPU0. This HFPLL has the alias register region.
56
-
57
-
clock-controller@f908a000 {
58
-
compatible = "qcom,hfpll-ipq8064", "qcom,hfpll";
59
-
reg = <0xf908a000 0x30>, <0xf900a000 0x30>;
60
-
clocks = <&xo_board>;
61
-
clock-names = "xo";
62
-
clock-output-names = "hfpll0";
63
-
};
+69
Documentation/devicetree/bindings/clock/qcom,hfpll.yaml
+69
Documentation/devicetree/bindings/clock/qcom,hfpll.yaml
···
1
+
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
2
+
%YAML 1.2
3
+
---
4
+
$id: http://devicetree.org/schemas/clock/qcom,hfpll.yaml#
5
+
$schema: http://devicetree.org/meta-schemas/core.yaml#
6
+
7
+
title: Qualcomm High-Frequency PLL
8
+
9
+
maintainers:
10
+
- Bjorn Andersson <andersson@kernel.org>
11
+
12
+
description:
13
+
The HFPLL is used as CPU PLL on various Qualcomm SoCs.
14
+
15
+
properties:
16
+
compatible:
17
+
oneOf:
18
+
- enum:
19
+
- qcom,msm8974-hfpll
20
+
- qcom,msm8976-hfpll-a53
21
+
- qcom,msm8976-hfpll-a72
22
+
- qcom,msm8976-hfpll-cci
23
+
- qcom,qcs404-hfpll
24
+
- const: qcom,hfpll
25
+
deprecated: true
26
+
27
+
reg:
28
+
items:
29
+
- description: HFPLL registers
30
+
- description: Alias register region
31
+
minItems: 1
32
+
33
+
'#clock-cells':
34
+
const: 0
35
+
36
+
clocks:
37
+
items:
38
+
- description: board XO clock
39
+
40
+
clock-names:
41
+
items:
42
+
- const: xo
43
+
44
+
clock-output-names:
45
+
description:
46
+
Name of the PLL. Typically hfpllX where X is a CPU number starting at 0.
47
+
Otherwise hfpll_Y where Y is more specific such as "l2".
48
+
maxItems: 1
49
+
50
+
required:
51
+
- compatible
52
+
- reg
53
+
- '#clock-cells'
54
+
- clocks
55
+
- clock-names
56
+
- clock-output-names
57
+
58
+
additionalProperties: false
59
+
60
+
examples:
61
+
- |
62
+
clock-controller@f908a000 {
63
+
compatible = "qcom,msm8974-hfpll";
64
+
reg = <0xf908a000 0x30>, <0xf900a000 0x30>;
65
+
#clock-cells = <0>;
66
+
clock-output-names = "hfpll0";
67
+
clocks = <&xo_board>;
68
+
clock-names = "xo";
69
+
};
+17
-1
Documentation/devicetree/bindings/clock/renesas,rzg2l-cpg.yaml
+17
-1
Documentation/devicetree/bindings/clock/renesas,rzg2l-cpg.yaml
···
57
57
can be power-managed through Module Standby should refer to the CPG device
58
58
node in their "power-domains" property, as documented by the generic PM
59
59
Domain bindings in Documentation/devicetree/bindings/power/power-domain.yaml.
60
-
const: 0
60
+
The power domain specifiers defined in <dt-bindings/clock/r9a0*-cpg.h> could
61
+
be used to reference individual CPG power domains.
61
62
62
63
'#reset-cells':
63
64
description:
···
76
75
- '#reset-cells'
77
76
78
77
additionalProperties: false
78
+
79
+
allOf:
80
+
- if:
81
+
properties:
82
+
compatible:
83
+
contains:
84
+
const: renesas,r9a08g045-cpg
85
+
then:
86
+
properties:
87
+
'#power-domain-cells':
88
+
const: 1
89
+
else:
90
+
properties:
91
+
'#power-domain-cells':
92
+
const: 0
79
93
80
94
examples:
81
95
- |
+57
Documentation/devicetree/bindings/clock/samsung,s3c6400-clock.yaml
+57
Documentation/devicetree/bindings/clock/samsung,s3c6400-clock.yaml
···
1
+
# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
2
+
%YAML 1.2
3
+
---
4
+
$id: http://devicetree.org/schemas/clock/samsung,s3c6400-clock.yaml#
5
+
$schema: http://devicetree.org/meta-schemas/core.yaml#
6
+
7
+
title: Samsung S3C6400 SoC clock controller
8
+
9
+
maintainers:
10
+
- Krzysztof Kozlowski <krzk@kernel.org>
11
+
12
+
description: |
13
+
There are several clocks that are generated outside the SoC. It is expected
14
+
that they are defined using standard clock bindings with following
15
+
clock-output-names and/or provided as clock inputs to this clock controller:
16
+
- "fin_pll" - PLL input clock (xtal/extclk) - required,
17
+
- "xusbxti" - USB xtal - required,
18
+
- "iiscdclk0" - I2S0 codec clock - optional,
19
+
- "iiscdclk1" - I2S1 codec clock - optional,
20
+
- "iiscdclk2" - I2S2 codec clock - optional,
21
+
- "pcmcdclk0" - PCM0 codec clock - optional,
22
+
- "pcmcdclk1" - PCM1 codec clock - optional, only S3C6410.
23
+
24
+
All available clocks are defined as preprocessor macros in
25
+
include/dt-bindings/clock/samsung,s3c64xx-clock.h header.
26
+
27
+
properties:
28
+
compatible:
29
+
enum:
30
+
- samsung,s3c6400-clock
31
+
- samsung,s3c6410-clock
32
+
33
+
reg:
34
+
maxItems: 1
35
+
36
+
clocks:
37
+
maxItems: 1
38
+
39
+
"#clock-cells":
40
+
const: 1
41
+
42
+
required:
43
+
- compatible
44
+
- reg
45
+
- clocks
46
+
- "#clock-cells"
47
+
48
+
additionalProperties: false
49
+
50
+
examples:
51
+
- |
52
+
clock-controller@7e00f000 {
53
+
compatible = "samsung,s3c6410-clock";
54
+
reg = <0x7e00f000 0x1000>;
55
+
#clock-cells = <1>;
56
+
clocks = <&fin_pll>;
57
+
};
-76
Documentation/devicetree/bindings/clock/samsung,s3c64xx-clock.txt
-76
Documentation/devicetree/bindings/clock/samsung,s3c64xx-clock.txt
···
1
-
* Samsung S3C64xx Clock Controller
2
-
3
-
The S3C64xx clock controller generates and supplies clock to various controllers
4
-
within the SoC. The clock binding described here is applicable to all SoCs in
5
-
the S3C64xx family.
6
-
7
-
Required Properties:
8
-
9
-
- compatible: should be one of the following.
10
-
- "samsung,s3c6400-clock" - controller compatible with S3C6400 SoC.
11
-
- "samsung,s3c6410-clock" - controller compatible with S3C6410 SoC.
12
-
13
-
- reg: physical base address of the controller and length of memory mapped
14
-
region.
15
-
16
-
- #clock-cells: should be 1.
17
-
18
-
Each clock is assigned an identifier and client nodes can use this identifier
19
-
to specify the clock which they consume. Some of the clocks are available only
20
-
on a particular S3C64xx SoC and this is specified where applicable.
21
-
22
-
All available clocks are defined as preprocessor macros in
23
-
dt-bindings/clock/samsung,s3c64xx-clock.h header and can be used in device
24
-
tree sources.
25
-
26
-
External clocks:
27
-
28
-
There are several clocks that are generated outside the SoC. It is expected
29
-
that they are defined using standard clock bindings with following
30
-
clock-output-names:
31
-
- "fin_pll" - PLL input clock (xtal/extclk) - required,
32
-
- "xusbxti" - USB xtal - required,
33
-
- "iiscdclk0" - I2S0 codec clock - optional,
34
-
- "iiscdclk1" - I2S1 codec clock - optional,
35
-
- "iiscdclk2" - I2S2 codec clock - optional,
36
-
- "pcmcdclk0" - PCM0 codec clock - optional,
37
-
- "pcmcdclk1" - PCM1 codec clock - optional, only S3C6410.
38
-
39
-
Example: Clock controller node:
40
-
41
-
clock: clock-controller@7e00f000 {
42
-
compatible = "samsung,s3c6410-clock";
43
-
reg = <0x7e00f000 0x1000>;
44
-
#clock-cells = <1>;
45
-
};
46
-
47
-
Example: Required external clocks:
48
-
49
-
fin_pll: clock-fin-pll {
50
-
compatible = "fixed-clock";
51
-
clock-output-names = "fin_pll";
52
-
clock-frequency = <12000000>;
53
-
#clock-cells = <0>;
54
-
};
55
-
56
-
xusbxti: clock-xusbxti {
57
-
compatible = "fixed-clock";
58
-
clock-output-names = "xusbxti";
59
-
clock-frequency = <48000000>;
60
-
#clock-cells = <0>;
61
-
};
62
-
63
-
Example: UART controller node that consumes the clock generated by the clock
64
-
controller (refer to the standard clock bindings for information about
65
-
"clocks" and "clock-names" properties):
66
-
67
-
uart0: serial@7f005000 {
68
-
compatible = "samsung,s3c6400-uart";
69
-
reg = <0x7f005000 0x100>;
70
-
interrupt-parent = <&vic1>;
71
-
interrupts = <5>;
72
-
clock-names = "uart", "clk_uart_baud2",
73
-
"clk_uart_baud3";
74
-
clocks = <&clock PCLK_UART0>, <&clocks PCLK_UART0>,
75
-
<&clock SCLK_UART>;
76
-
};
+2
-1
Documentation/devicetree/bindings/clock/sophgo,cv1800-clk.yaml
+2
-1
Documentation/devicetree/bindings/clock/sophgo,cv1800-clk.yaml
···
4
4
$id: http://devicetree.org/schemas/clock/sophgo,cv1800-clk.yaml#
5
5
$schema: http://devicetree.org/meta-schemas/core.yaml#
6
6
7
-
title: Sophgo CV1800 Series Clock Controller
7
+
title: Sophgo CV1800/SG2000 Series Clock Controller
8
8
9
9
maintainers:
10
10
- Inochi Amaoto <inochiama@outlook.com>
···
14
14
enum:
15
15
- sophgo,cv1800-clk
16
16
- sophgo,cv1810-clk
17
+
- sophgo,sg2000-clk
17
18
18
19
reg:
19
20
maxItems: 1
+158
-14
Documentation/devicetree/bindings/clock/st,stm32mp25-rcc.yaml
+158
-14
Documentation/devicetree/bindings/clock/st,stm32mp25-rcc.yaml
···
38
38
- description: CK_SCMI_MSI Low Power Internal oscillator (~ 4 MHz or ~ 16 MHz)
39
39
- description: CK_SCMI_LSE Low Speed External oscillator (32 KHz)
40
40
- description: CK_SCMI_LSI Low Speed Internal oscillator (~ 32 KHz)
41
+
- description: CK_SCMI_HSE_DIV2 CK_SCMI_HSE divided by 2 (coud be gated)
42
+
- description: CK_SCMI_ICN_HS_MCU High Speed interconnect bus clock
43
+
- description: CK_SCMI_ICN_LS_MCU Low Speed interconnect bus clock
44
+
- description: CK_SCMI_ICN_SDMMC SDMMC interconnect bus clock
45
+
- description: CK_SCMI_ICN_DDR DDR interconnect bus clock
46
+
- description: CK_SCMI_ICN_DISPLAY Display interconnect bus clock
47
+
- description: CK_SCMI_ICN_HSL HSL interconnect bus clock
48
+
- description: CK_SCMI_ICN_NIC NIC interconnect bus clock
49
+
- description: CK_SCMI_ICN_VID Video interconnect bus clock
50
+
- description: CK_SCMI_FLEXGEN_07 flexgen clock 7
51
+
- description: CK_SCMI_FLEXGEN_08 flexgen clock 8
52
+
- description: CK_SCMI_FLEXGEN_09 flexgen clock 9
53
+
- description: CK_SCMI_FLEXGEN_10 flexgen clock 10
54
+
- description: CK_SCMI_FLEXGEN_11 flexgen clock 11
55
+
- description: CK_SCMI_FLEXGEN_12 flexgen clock 12
56
+
- description: CK_SCMI_FLEXGEN_13 flexgen clock 13
57
+
- description: CK_SCMI_FLEXGEN_14 flexgen clock 14
58
+
- description: CK_SCMI_FLEXGEN_15 flexgen clock 15
59
+
- description: CK_SCMI_FLEXGEN_16 flexgen clock 16
60
+
- description: CK_SCMI_FLEXGEN_17 flexgen clock 17
61
+
- description: CK_SCMI_FLEXGEN_18 flexgen clock 18
62
+
- description: CK_SCMI_FLEXGEN_19 flexgen clock 19
63
+
- description: CK_SCMI_FLEXGEN_20 flexgen clock 20
64
+
- description: CK_SCMI_FLEXGEN_21 flexgen clock 21
65
+
- description: CK_SCMI_FLEXGEN_22 flexgen clock 22
66
+
- description: CK_SCMI_FLEXGEN_23 flexgen clock 23
67
+
- description: CK_SCMI_FLEXGEN_24 flexgen clock 24
68
+
- description: CK_SCMI_FLEXGEN_25 flexgen clock 25
69
+
- description: CK_SCMI_FLEXGEN_26 flexgen clock 26
70
+
- description: CK_SCMI_FLEXGEN_27 flexgen clock 27
71
+
- description: CK_SCMI_FLEXGEN_28 flexgen clock 28
72
+
- description: CK_SCMI_FLEXGEN_29 flexgen clock 29
73
+
- description: CK_SCMI_FLEXGEN_30 flexgen clock 30
74
+
- description: CK_SCMI_FLEXGEN_31 flexgen clock 31
75
+
- description: CK_SCMI_FLEXGEN_32 flexgen clock 32
76
+
- description: CK_SCMI_FLEXGEN_33 flexgen clock 33
77
+
- description: CK_SCMI_FLEXGEN_34 flexgen clock 34
78
+
- description: CK_SCMI_FLEXGEN_35 flexgen clock 35
79
+
- description: CK_SCMI_FLEXGEN_36 flexgen clock 36
80
+
- description: CK_SCMI_FLEXGEN_37 flexgen clock 37
81
+
- description: CK_SCMI_FLEXGEN_38 flexgen clock 38
82
+
- description: CK_SCMI_FLEXGEN_39 flexgen clock 39
83
+
- description: CK_SCMI_FLEXGEN_40 flexgen clock 40
84
+
- description: CK_SCMI_FLEXGEN_41 flexgen clock 41
85
+
- description: CK_SCMI_FLEXGEN_42 flexgen clock 42
86
+
- description: CK_SCMI_FLEXGEN_43 flexgen clock 43
87
+
- description: CK_SCMI_FLEXGEN_44 flexgen clock 44
88
+
- description: CK_SCMI_FLEXGEN_45 flexgen clock 45
89
+
- description: CK_SCMI_FLEXGEN_46 flexgen clock 46
90
+
- description: CK_SCMI_FLEXGEN_47 flexgen clock 47
91
+
- description: CK_SCMI_FLEXGEN_48 flexgen clock 48
92
+
- description: CK_SCMI_FLEXGEN_49 flexgen clock 49
93
+
- description: CK_SCMI_FLEXGEN_50 flexgen clock 50
94
+
- description: CK_SCMI_FLEXGEN_51 flexgen clock 51
95
+
- description: CK_SCMI_FLEXGEN_52 flexgen clock 52
96
+
- description: CK_SCMI_FLEXGEN_53 flexgen clock 53
97
+
- description: CK_SCMI_FLEXGEN_54 flexgen clock 54
98
+
- description: CK_SCMI_FLEXGEN_55 flexgen clock 55
99
+
- description: CK_SCMI_FLEXGEN_56 flexgen clock 56
100
+
- description: CK_SCMI_FLEXGEN_57 flexgen clock 57
101
+
- description: CK_SCMI_FLEXGEN_58 flexgen clock 58
102
+
- description: CK_SCMI_FLEXGEN_59 flexgen clock 59
103
+
- description: CK_SCMI_FLEXGEN_60 flexgen clock 60
104
+
- description: CK_SCMI_FLEXGEN_61 flexgen clock 61
105
+
- description: CK_SCMI_FLEXGEN_62 flexgen clock 62
106
+
- description: CK_SCMI_FLEXGEN_63 flexgen clock 63
107
+
- description: CK_SCMI_ICN_APB1 Peripheral bridge 1
108
+
- description: CK_SCMI_ICN_APB2 Peripheral bridge 2
109
+
- description: CK_SCMI_ICN_APB3 Peripheral bridge 3
110
+
- description: CK_SCMI_ICN_APB4 Peripheral bridge 4
111
+
- description: CK_SCMI_ICN_APBDBG Peripheral bridge for degub
112
+
- description: CK_SCMI_TIMG1 Peripheral bridge for timer1
113
+
- description: CK_SCMI_TIMG2 Peripheral bridge for timer2
114
+
- description: CK_SCMI_PLL3 PLL3 clock
115
+
- description: clk_dsi_txbyte DSI byte clock
41
116
42
-
clock-names:
43
-
items:
44
-
- const: hse
45
-
- const: hsi
46
-
- const: msi
47
-
- const: lse
48
-
- const: lsi
117
+
access-controllers:
118
+
minItems: 1
119
+
maxItems: 2
49
120
50
121
required:
51
122
- compatible
···
124
53
- '#clock-cells'
125
54
- '#reset-cells'
126
55
- clocks
127
-
- clock-names
128
56
129
57
additionalProperties: false
130
58
···
136
66
reg = <0x44200000 0x10000>;
137
67
#clock-cells = <1>;
138
68
#reset-cells = <1>;
139
-
clock-names = "hse", "hsi", "msi", "lse", "lsi";
140
-
clocks = <&scmi_clk CK_SCMI_HSE>,
141
-
<&scmi_clk CK_SCMI_HSI>,
142
-
<&scmi_clk CK_SCMI_MSI>,
143
-
<&scmi_clk CK_SCMI_LSE>,
144
-
<&scmi_clk CK_SCMI_LSI>;
69
+
clocks = <&scmi_clk CK_SCMI_HSE>,
70
+
<&scmi_clk CK_SCMI_HSI>,
71
+
<&scmi_clk CK_SCMI_MSI>,
72
+
<&scmi_clk CK_SCMI_LSE>,
73
+
<&scmi_clk CK_SCMI_LSI>,
74
+
<&scmi_clk CK_SCMI_HSE_DIV2>,
75
+
<&scmi_clk CK_SCMI_ICN_HS_MCU>,
76
+
<&scmi_clk CK_SCMI_ICN_LS_MCU>,
77
+
<&scmi_clk CK_SCMI_ICN_SDMMC>,
78
+
<&scmi_clk CK_SCMI_ICN_DDR>,
79
+
<&scmi_clk CK_SCMI_ICN_DISPLAY>,
80
+
<&scmi_clk CK_SCMI_ICN_HSL>,
81
+
<&scmi_clk CK_SCMI_ICN_NIC>,
82
+
<&scmi_clk CK_SCMI_ICN_VID>,
83
+
<&scmi_clk CK_SCMI_FLEXGEN_07>,
84
+
<&scmi_clk CK_SCMI_FLEXGEN_08>,
85
+
<&scmi_clk CK_SCMI_FLEXGEN_09>,
86
+
<&scmi_clk CK_SCMI_FLEXGEN_10>,
87
+
<&scmi_clk CK_SCMI_FLEXGEN_11>,
88
+
<&scmi_clk CK_SCMI_FLEXGEN_12>,
89
+
<&scmi_clk CK_SCMI_FLEXGEN_13>,
90
+
<&scmi_clk CK_SCMI_FLEXGEN_14>,
91
+
<&scmi_clk CK_SCMI_FLEXGEN_15>,
92
+
<&scmi_clk CK_SCMI_FLEXGEN_16>,
93
+
<&scmi_clk CK_SCMI_FLEXGEN_17>,
94
+
<&scmi_clk CK_SCMI_FLEXGEN_18>,
95
+
<&scmi_clk CK_SCMI_FLEXGEN_19>,
96
+
<&scmi_clk CK_SCMI_FLEXGEN_20>,
97
+
<&scmi_clk CK_SCMI_FLEXGEN_21>,
98
+
<&scmi_clk CK_SCMI_FLEXGEN_22>,
99
+
<&scmi_clk CK_SCMI_FLEXGEN_23>,
100
+
<&scmi_clk CK_SCMI_FLEXGEN_24>,
101
+
<&scmi_clk CK_SCMI_FLEXGEN_25>,
102
+
<&scmi_clk CK_SCMI_FLEXGEN_26>,
103
+
<&scmi_clk CK_SCMI_FLEXGEN_27>,
104
+
<&scmi_clk CK_SCMI_FLEXGEN_28>,
105
+
<&scmi_clk CK_SCMI_FLEXGEN_29>,
106
+
<&scmi_clk CK_SCMI_FLEXGEN_30>,
107
+
<&scmi_clk CK_SCMI_FLEXGEN_31>,
108
+
<&scmi_clk CK_SCMI_FLEXGEN_32>,
109
+
<&scmi_clk CK_SCMI_FLEXGEN_33>,
110
+
<&scmi_clk CK_SCMI_FLEXGEN_34>,
111
+
<&scmi_clk CK_SCMI_FLEXGEN_35>,
112
+
<&scmi_clk CK_SCMI_FLEXGEN_36>,
113
+
<&scmi_clk CK_SCMI_FLEXGEN_37>,
114
+
<&scmi_clk CK_SCMI_FLEXGEN_38>,
115
+
<&scmi_clk CK_SCMI_FLEXGEN_39>,
116
+
<&scmi_clk CK_SCMI_FLEXGEN_40>,
117
+
<&scmi_clk CK_SCMI_FLEXGEN_41>,
118
+
<&scmi_clk CK_SCMI_FLEXGEN_42>,
119
+
<&scmi_clk CK_SCMI_FLEXGEN_43>,
120
+
<&scmi_clk CK_SCMI_FLEXGEN_44>,
121
+
<&scmi_clk CK_SCMI_FLEXGEN_45>,
122
+
<&scmi_clk CK_SCMI_FLEXGEN_46>,
123
+
<&scmi_clk CK_SCMI_FLEXGEN_47>,
124
+
<&scmi_clk CK_SCMI_FLEXGEN_48>,
125
+
<&scmi_clk CK_SCMI_FLEXGEN_49>,
126
+
<&scmi_clk CK_SCMI_FLEXGEN_50>,
127
+
<&scmi_clk CK_SCMI_FLEXGEN_51>,
128
+
<&scmi_clk CK_SCMI_FLEXGEN_52>,
129
+
<&scmi_clk CK_SCMI_FLEXGEN_53>,
130
+
<&scmi_clk CK_SCMI_FLEXGEN_54>,
131
+
<&scmi_clk CK_SCMI_FLEXGEN_55>,
132
+
<&scmi_clk CK_SCMI_FLEXGEN_56>,
133
+
<&scmi_clk CK_SCMI_FLEXGEN_57>,
134
+
<&scmi_clk CK_SCMI_FLEXGEN_58>,
135
+
<&scmi_clk CK_SCMI_FLEXGEN_59>,
136
+
<&scmi_clk CK_SCMI_FLEXGEN_60>,
137
+
<&scmi_clk CK_SCMI_FLEXGEN_61>,
138
+
<&scmi_clk CK_SCMI_FLEXGEN_62>,
139
+
<&scmi_clk CK_SCMI_FLEXGEN_63>,
140
+
<&scmi_clk CK_SCMI_ICN_APB1>,
141
+
<&scmi_clk CK_SCMI_ICN_APB2>,
142
+
<&scmi_clk CK_SCMI_ICN_APB3>,
143
+
<&scmi_clk CK_SCMI_ICN_APB4>,
144
+
<&scmi_clk CK_SCMI_ICN_APBDBG>,
145
+
<&scmi_clk CK_SCMI_TIMG1>,
146
+
<&scmi_clk CK_SCMI_TIMG2>,
147
+
<&scmi_clk CK_SCMI_PLL3>,
148
+
<&clk_dsi_txbyte>;
145
149
};
146
150
...
+1
drivers/clk/Kconfig
+1
drivers/clk/Kconfig
···
489
489
source "drivers/clk/samsung/Kconfig"
490
490
source "drivers/clk/sifive/Kconfig"
491
491
source "drivers/clk/socfpga/Kconfig"
492
+
source "drivers/clk/sophgo/Kconfig"
492
493
source "drivers/clk/sprd/Kconfig"
493
494
source "drivers/clk/starfive/Kconfig"
494
495
source "drivers/clk/sunxi/Kconfig"
+1
drivers/clk/Makefile
+1
drivers/clk/Makefile
+2
-1
drivers/clk/bcm/clk-bcm2711-dvp.c
+2
-1
drivers/clk/bcm/clk-bcm2711-dvp.c
···
56
56
if (ret)
57
57
return ret;
58
58
59
+
data->num = NR_CLOCKS;
60
+
59
61
data->hws[0] = clk_hw_register_gate_parent_data(&pdev->dev,
60
62
"hdmi0-108MHz",
61
63
&clk_dvp_parent, 0,
···
78
76
goto unregister_clk0;
79
77
}
80
78
81
-
data->num = NR_CLOCKS;
82
79
ret = of_clk_add_hw_provider(pdev->dev.of_node, of_clk_hw_onecell_get,
83
80
data);
84
81
if (ret)
+1
-1
drivers/clk/bcm/clk-raspberrypi.c
+1
-1
drivers/clk/bcm/clk-raspberrypi.c
+173
-18
drivers/clk/clk-en7523.c
+173
-18
drivers/clk/clk-en7523.c
···
3
3
#include <linux/delay.h>
4
4
#include <linux/clk-provider.h>
5
5
#include <linux/io.h>
6
-
#include <linux/of.h>
7
6
#include <linux/platform_device.h>
7
+
#include <linux/property.h>
8
8
#include <dt-bindings/clock/en7523-clk.h>
9
9
10
10
#define REG_PCI_CONTROL 0x88
11
11
#define REG_PCI_CONTROL_PERSTOUT BIT(29)
12
12
#define REG_PCI_CONTROL_PERSTOUT1 BIT(26)
13
+
#define REG_PCI_CONTROL_REFCLK_EN0 BIT(23)
13
14
#define REG_PCI_CONTROL_REFCLK_EN1 BIT(22)
15
+
#define REG_PCI_CONTROL_PERSTOUT2 BIT(16)
14
16
#define REG_GSW_CLK_DIV_SEL 0x1b4
15
17
#define REG_EMI_CLK_DIV_SEL 0x1b8
16
18
#define REG_BUS_CLK_DIV_SEL 0x1bc
···
20
18
#define REG_SPI_CLK_FREQ_SEL 0x1c8
21
19
#define REG_NPU_CLK_DIV_SEL 0x1fc
22
20
#define REG_CRYPTO_CLKSRC 0x200
23
-
#define REG_RESET_CONTROL 0x834
21
+
#define REG_RESET_CONTROL2 0x830
22
+
#define REG_RESET2_CONTROL_PCIE2 BIT(27)
23
+
#define REG_RESET_CONTROL1 0x834
24
24
#define REG_RESET_CONTROL_PCIEHB BIT(29)
25
25
#define REG_RESET_CONTROL_PCIE1 BIT(27)
26
26
#define REG_RESET_CONTROL_PCIE2 BIT(26)
27
+
/* EN7581 */
28
+
#define REG_PCIE0_MEM 0x00
29
+
#define REG_PCIE0_MEM_MASK 0x04
30
+
#define REG_PCIE1_MEM 0x08
31
+
#define REG_PCIE1_MEM_MASK 0x0c
32
+
#define REG_PCIE2_MEM 0x10
33
+
#define REG_PCIE2_MEM_MASK 0x14
34
+
#define REG_PCIE_RESET_OPEN_DRAIN 0x018c
35
+
#define REG_PCIE_RESET_OPEN_DRAIN_MASK GENMASK(2, 0)
36
+
#define REG_NP_SCU_PCIC 0x88
37
+
#define REG_NP_SCU_SSTR 0x9c
38
+
#define REG_PCIE_XSI0_SEL_MASK GENMASK(14, 13)
39
+
#define REG_PCIE_XSI1_SEL_MASK GENMASK(12, 11)
27
40
28
41
struct en_clk_desc {
29
42
int id;
···
62
45
struct en_clk_gate {
63
46
void __iomem *base;
64
47
struct clk_hw hw;
48
+
};
49
+
50
+
struct en_clk_soc_data {
51
+
const struct clk_ops pcie_ops;
52
+
int (*hw_init)(struct platform_device *pdev, void __iomem *base,
53
+
void __iomem *np_base);
65
54
};
66
55
67
56
static const u32 gsw_base[] = { 400000000, 500000000 };
···
168
145
}
169
146
};
170
147
171
-
static const struct of_device_id of_match_clk_en7523[] = {
172
-
{ .compatible = "airoha,en7523-scu", },
173
-
{ /* sentinel */ }
174
-
};
175
-
176
148
static unsigned int en7523_get_base_rate(void __iomem *base, unsigned int i)
177
149
{
178
150
const struct en_clk_desc *desc = &en7523_base_clks[i];
···
230
212
usleep_range(1000, 2000);
231
213
232
214
/* Reset to default */
233
-
val = readl(np_base + REG_RESET_CONTROL);
215
+
val = readl(np_base + REG_RESET_CONTROL1);
234
216
mask = REG_RESET_CONTROL_PCIE1 | REG_RESET_CONTROL_PCIE2 |
235
217
REG_RESET_CONTROL_PCIEHB;
236
-
writel(val & ~mask, np_base + REG_RESET_CONTROL);
218
+
writel(val & ~mask, np_base + REG_RESET_CONTROL1);
237
219
usleep_range(1000, 2000);
238
-
writel(val | mask, np_base + REG_RESET_CONTROL);
220
+
writel(val | mask, np_base + REG_RESET_CONTROL1);
239
221
msleep(100);
240
-
writel(val & ~mask, np_base + REG_RESET_CONTROL);
222
+
writel(val & ~mask, np_base + REG_RESET_CONTROL1);
241
223
usleep_range(5000, 10000);
242
224
243
225
/* Release device */
···
265
247
static struct clk_hw *en7523_register_pcie_clk(struct device *dev,
266
248
void __iomem *np_base)
267
249
{
268
-
static const struct clk_ops pcie_gate_ops = {
269
-
.is_enabled = en7523_pci_is_enabled,
270
-
.prepare = en7523_pci_prepare,
271
-
.unprepare = en7523_pci_unprepare,
272
-
};
250
+
const struct en_clk_soc_data *soc_data = device_get_match_data(dev);
273
251
struct clk_init_data init = {
274
252
.name = "pcie",
275
-
.ops = &pcie_gate_ops,
253
+
.ops = &soc_data->pcie_ops,
276
254
};
277
255
struct en_clk_gate *cg;
278
256
···
278
264
279
265
cg->base = np_base;
280
266
cg->hw.init = &init;
281
-
en7523_pci_unprepare(&cg->hw);
267
+
268
+
if (init.ops->disable)
269
+
init.ops->disable(&cg->hw);
270
+
init.ops->unprepare(&cg->hw);
282
271
283
272
if (clk_hw_register(dev, &cg->hw))
284
273
return NULL;
285
274
286
275
return &cg->hw;
276
+
}
277
+
278
+
static int en7581_pci_is_enabled(struct clk_hw *hw)
279
+
{
280
+
struct en_clk_gate *cg = container_of(hw, struct en_clk_gate, hw);
281
+
u32 val, mask;
282
+
283
+
mask = REG_PCI_CONTROL_REFCLK_EN0 | REG_PCI_CONTROL_REFCLK_EN1;
284
+
val = readl(cg->base + REG_PCI_CONTROL);
285
+
return (val & mask) == mask;
286
+
}
287
+
288
+
static int en7581_pci_prepare(struct clk_hw *hw)
289
+
{
290
+
struct en_clk_gate *cg = container_of(hw, struct en_clk_gate, hw);
291
+
void __iomem *np_base = cg->base;
292
+
u32 val, mask;
293
+
294
+
mask = REG_RESET_CONTROL_PCIE1 | REG_RESET_CONTROL_PCIE2 |
295
+
REG_RESET_CONTROL_PCIEHB;
296
+
val = readl(np_base + REG_RESET_CONTROL1);
297
+
writel(val & ~mask, np_base + REG_RESET_CONTROL1);
298
+
val = readl(np_base + REG_RESET_CONTROL2);
299
+
writel(val & ~REG_RESET2_CONTROL_PCIE2, np_base + REG_RESET_CONTROL2);
300
+
usleep_range(5000, 10000);
301
+
302
+
return 0;
303
+
}
304
+
305
+
static int en7581_pci_enable(struct clk_hw *hw)
306
+
{
307
+
struct en_clk_gate *cg = container_of(hw, struct en_clk_gate, hw);
308
+
void __iomem *np_base = cg->base;
309
+
u32 val, mask;
310
+
311
+
mask = REG_PCI_CONTROL_REFCLK_EN0 | REG_PCI_CONTROL_REFCLK_EN1 |
312
+
REG_PCI_CONTROL_PERSTOUT1 | REG_PCI_CONTROL_PERSTOUT2 |
313
+
REG_PCI_CONTROL_PERSTOUT;
314
+
val = readl(np_base + REG_PCI_CONTROL);
315
+
writel(val | mask, np_base + REG_PCI_CONTROL);
316
+
msleep(250);
317
+
318
+
return 0;
319
+
}
320
+
321
+
static void en7581_pci_unprepare(struct clk_hw *hw)
322
+
{
323
+
struct en_clk_gate *cg = container_of(hw, struct en_clk_gate, hw);
324
+
void __iomem *np_base = cg->base;
325
+
u32 val, mask;
326
+
327
+
mask = REG_RESET_CONTROL_PCIE1 | REG_RESET_CONTROL_PCIE2 |
328
+
REG_RESET_CONTROL_PCIEHB;
329
+
val = readl(np_base + REG_RESET_CONTROL1);
330
+
writel(val | mask, np_base + REG_RESET_CONTROL1);
331
+
mask = REG_RESET_CONTROL_PCIE1 | REG_RESET_CONTROL_PCIE2;
332
+
writel(val | mask, np_base + REG_RESET_CONTROL1);
333
+
val = readl(np_base + REG_RESET_CONTROL2);
334
+
writel(val | REG_RESET_CONTROL_PCIE2, np_base + REG_RESET_CONTROL2);
335
+
msleep(100);
336
+
}
337
+
338
+
static void en7581_pci_disable(struct clk_hw *hw)
339
+
{
340
+
struct en_clk_gate *cg = container_of(hw, struct en_clk_gate, hw);
341
+
void __iomem *np_base = cg->base;
342
+
u32 val, mask;
343
+
344
+
mask = REG_PCI_CONTROL_REFCLK_EN0 | REG_PCI_CONTROL_REFCLK_EN1 |
345
+
REG_PCI_CONTROL_PERSTOUT1 | REG_PCI_CONTROL_PERSTOUT2 |
346
+
REG_PCI_CONTROL_PERSTOUT;
347
+
val = readl(np_base + REG_PCI_CONTROL);
348
+
writel(val & ~mask, np_base + REG_PCI_CONTROL);
349
+
usleep_range(1000, 2000);
350
+
}
351
+
352
+
static int en7581_clk_hw_init(struct platform_device *pdev,
353
+
void __iomem *base,
354
+
void __iomem *np_base)
355
+
{
356
+
void __iomem *pb_base;
357
+
u32 val;
358
+
359
+
pb_base = devm_platform_ioremap_resource(pdev, 2);
360
+
if (IS_ERR(pb_base))
361
+
return PTR_ERR(pb_base);
362
+
363
+
val = readl(np_base + REG_NP_SCU_SSTR);
364
+
val &= ~(REG_PCIE_XSI0_SEL_MASK | REG_PCIE_XSI1_SEL_MASK);
365
+
writel(val, np_base + REG_NP_SCU_SSTR);
366
+
val = readl(np_base + REG_NP_SCU_PCIC);
367
+
writel(val | 3, np_base + REG_NP_SCU_PCIC);
368
+
369
+
writel(0x20000000, pb_base + REG_PCIE0_MEM);
370
+
writel(0xfc000000, pb_base + REG_PCIE0_MEM_MASK);
371
+
writel(0x24000000, pb_base + REG_PCIE1_MEM);
372
+
writel(0xfc000000, pb_base + REG_PCIE1_MEM_MASK);
373
+
writel(0x28000000, pb_base + REG_PCIE2_MEM);
374
+
writel(0xfc000000, pb_base + REG_PCIE2_MEM_MASK);
375
+
376
+
val = readl(base + REG_PCIE_RESET_OPEN_DRAIN);
377
+
writel(val | REG_PCIE_RESET_OPEN_DRAIN_MASK,
378
+
base + REG_PCIE_RESET_OPEN_DRAIN);
379
+
380
+
return 0;
287
381
}
288
382
289
383
static void en7523_register_clocks(struct device *dev, struct clk_hw_onecell_data *clk_data,
···
426
304
static int en7523_clk_probe(struct platform_device *pdev)
427
305
{
428
306
struct device_node *node = pdev->dev.of_node;
307
+
const struct en_clk_soc_data *soc_data;
429
308
struct clk_hw_onecell_data *clk_data;
430
309
void __iomem *base, *np_base;
431
310
int r;
···
438
315
np_base = devm_platform_ioremap_resource(pdev, 1);
439
316
if (IS_ERR(np_base))
440
317
return PTR_ERR(np_base);
318
+
319
+
soc_data = device_get_match_data(&pdev->dev);
320
+
if (soc_data->hw_init) {
321
+
r = soc_data->hw_init(pdev, base, np_base);
322
+
if (r)
323
+
return r;
324
+
}
441
325
442
326
clk_data = devm_kzalloc(&pdev->dev,
443
327
struct_size(clk_data, hws, EN7523_NUM_CLOCKS),
···
462
332
463
333
return r;
464
334
}
335
+
336
+
static const struct en_clk_soc_data en7523_data = {
337
+
.pcie_ops = {
338
+
.is_enabled = en7523_pci_is_enabled,
339
+
.prepare = en7523_pci_prepare,
340
+
.unprepare = en7523_pci_unprepare,
341
+
},
342
+
};
343
+
344
+
static const struct en_clk_soc_data en7581_data = {
345
+
.pcie_ops = {
346
+
.is_enabled = en7581_pci_is_enabled,
347
+
.prepare = en7581_pci_prepare,
348
+
.enable = en7581_pci_enable,
349
+
.unprepare = en7581_pci_unprepare,
350
+
.disable = en7581_pci_disable,
351
+
},
352
+
.hw_init = en7581_clk_hw_init,
353
+
};
354
+
355
+
static const struct of_device_id of_match_clk_en7523[] = {
356
+
{ .compatible = "airoha,en7523-scu", .data = &en7523_data },
357
+
{ .compatible = "airoha,en7581-scu", .data = &en7581_data },
358
+
{ /* sentinel */ }
359
+
};
465
360
466
361
static struct platform_driver clk_en7523_drv = {
467
362
.probe = en7523_clk_probe,
-2
drivers/clk/clk-gemini.c
-2
drivers/clk/clk-gemini.c
···
67
67
* struct clk_gemini_pci - Gemini PCI clock
68
68
* @hw: corresponding clock hardware entry
69
69
* @map: regmap to access the registers
70
-
* @rate: current rate
71
70
*/
72
71
struct clk_gemini_pci {
73
72
struct clk_hw hw;
74
73
struct regmap *map;
75
-
unsigned long rate;
76
74
};
77
75
78
76
/**
-1
drivers/clk/clk-highbank.c
-1
drivers/clk/clk-highbank.c
+308
-276
drivers/clk/clk-loongson2.c
+308
-276
drivers/clk/clk-loongson2.c
···
13
13
#include <linux/io-64-nonatomic-lo-hi.h>
14
14
#include <dt-bindings/clock/loongson,ls2k-clk.h>
15
15
16
-
#define LOONGSON2_PLL_MULT_SHIFT 32
17
-
#define LOONGSON2_PLL_MULT_WIDTH 10
18
-
#define LOONGSON2_PLL_DIV_SHIFT 26
19
-
#define LOONGSON2_PLL_DIV_WIDTH 6
20
-
#define LOONGSON2_APB_FREQSCALE_SHIFT 20
21
-
#define LOONGSON2_APB_FREQSCALE_WIDTH 3
22
-
#define LOONGSON2_USB_FREQSCALE_SHIFT 16
23
-
#define LOONGSON2_USB_FREQSCALE_WIDTH 3
24
-
#define LOONGSON2_SATA_FREQSCALE_SHIFT 12
25
-
#define LOONGSON2_SATA_FREQSCALE_WIDTH 3
26
-
#define LOONGSON2_BOOT_FREQSCALE_SHIFT 8
27
-
#define LOONGSON2_BOOT_FREQSCALE_WIDTH 3
28
-
29
-
static void __iomem *loongson2_pll_base;
30
-
31
16
static const struct clk_parent_data pdata[] = {
32
-
{ .fw_name = "ref_100m",},
17
+
{ .fw_name = "ref_100m", },
33
18
};
34
19
35
-
static struct clk_hw *loongson2_clk_register(struct device *dev,
36
-
const char *name,
37
-
const char *parent_name,
38
-
const struct clk_ops *ops,
39
-
unsigned long flags)
40
-
{
41
-
int ret;
42
-
struct clk_hw *hw;
43
-
struct clk_init_data init = { };
44
-
45
-
hw = devm_kzalloc(dev, sizeof(*hw), GFP_KERNEL);
46
-
if (!hw)
47
-
return ERR_PTR(-ENOMEM);
48
-
49
-
init.name = name;
50
-
init.ops = ops;
51
-
init.flags = flags;
52
-
init.num_parents = 1;
53
-
54
-
if (!parent_name)
55
-
init.parent_data = pdata;
56
-
else
57
-
init.parent_names = &parent_name;
58
-
59
-
hw->init = &init;
60
-
61
-
ret = devm_clk_hw_register(dev, hw);
62
-
if (ret)
63
-
hw = ERR_PTR(ret);
64
-
65
-
return hw;
66
-
}
67
-
68
-
static unsigned long loongson2_calc_pll_rate(int offset, unsigned long rate)
69
-
{
70
-
u64 val;
71
-
u32 mult, div;
72
-
73
-
val = readq(loongson2_pll_base + offset);
74
-
75
-
mult = (val >> LOONGSON2_PLL_MULT_SHIFT) &
76
-
clk_div_mask(LOONGSON2_PLL_MULT_WIDTH);
77
-
div = (val >> LOONGSON2_PLL_DIV_SHIFT) &
78
-
clk_div_mask(LOONGSON2_PLL_DIV_WIDTH);
79
-
80
-
return div_u64((u64)rate * mult, div);
81
-
}
82
-
83
-
static unsigned long loongson2_node_recalc_rate(struct clk_hw *hw,
84
-
unsigned long parent_rate)
85
-
{
86
-
return loongson2_calc_pll_rate(0x0, parent_rate);
87
-
}
88
-
89
-
static const struct clk_ops loongson2_node_clk_ops = {
90
-
.recalc_rate = loongson2_node_recalc_rate,
20
+
enum loongson2_clk_type {
21
+
CLK_TYPE_PLL,
22
+
CLK_TYPE_SCALE,
23
+
CLK_TYPE_DIVIDER,
24
+
CLK_TYPE_GATE,
25
+
CLK_TYPE_FIXED,
26
+
CLK_TYPE_NONE,
91
27
};
92
28
93
-
static unsigned long loongson2_ddr_recalc_rate(struct clk_hw *hw,
94
-
unsigned long parent_rate)
95
-
{
96
-
return loongson2_calc_pll_rate(0x10, parent_rate);
97
-
}
98
-
99
-
static const struct clk_ops loongson2_ddr_clk_ops = {
100
-
.recalc_rate = loongson2_ddr_recalc_rate,
29
+
struct loongson2_clk_provider {
30
+
void __iomem *base;
31
+
struct device *dev;
32
+
struct clk_hw_onecell_data clk_data;
33
+
spinlock_t clk_lock; /* protect access to DIV registers */
101
34
};
102
35
103
-
static unsigned long loongson2_dc_recalc_rate(struct clk_hw *hw,
104
-
unsigned long parent_rate)
105
-
{
106
-
return loongson2_calc_pll_rate(0x20, parent_rate);
107
-
}
108
-
109
-
static const struct clk_ops loongson2_dc_clk_ops = {
110
-
.recalc_rate = loongson2_dc_recalc_rate,
36
+
struct loongson2_clk_data {
37
+
struct clk_hw hw;
38
+
void __iomem *reg;
39
+
u8 div_shift;
40
+
u8 div_width;
41
+
u8 mult_shift;
42
+
u8 mult_width;
111
43
};
112
44
113
-
static unsigned long loongson2_pix0_recalc_rate(struct clk_hw *hw,
114
-
unsigned long parent_rate)
115
-
{
116
-
return loongson2_calc_pll_rate(0x30, parent_rate);
117
-
}
118
-
119
-
static const struct clk_ops loongson2_pix0_clk_ops = {
120
-
.recalc_rate = loongson2_pix0_recalc_rate,
45
+
struct loongson2_clk_board_info {
46
+
u8 id;
47
+
enum loongson2_clk_type type;
48
+
const char *name;
49
+
const char *parent_name;
50
+
unsigned long fixed_rate;
51
+
u8 reg_offset;
52
+
u8 div_shift;
53
+
u8 div_width;
54
+
u8 mult_shift;
55
+
u8 mult_width;
56
+
u8 bit_idx;
121
57
};
122
58
123
-
static unsigned long loongson2_pix1_recalc_rate(struct clk_hw *hw,
124
-
unsigned long parent_rate)
125
-
{
126
-
return loongson2_calc_pll_rate(0x40, parent_rate);
127
-
}
59
+
#define CLK_DIV(_id, _name, _pname, _offset, _dshift, _dwidth) \
60
+
{ \
61
+
.id = _id, \
62
+
.type = CLK_TYPE_DIVIDER, \
63
+
.name = _name, \
64
+
.parent_name = _pname, \
65
+
.reg_offset = _offset, \
66
+
.div_shift = _dshift, \
67
+
.div_width = _dwidth, \
68
+
}
128
69
129
-
static const struct clk_ops loongson2_pix1_clk_ops = {
130
-
.recalc_rate = loongson2_pix1_recalc_rate,
70
+
#define CLK_PLL(_id, _name, _offset, _mshift, _mwidth, \
71
+
_dshift, _dwidth) \
72
+
{ \
73
+
.id = _id, \
74
+
.type = CLK_TYPE_PLL, \
75
+
.name = _name, \
76
+
.parent_name = NULL, \
77
+
.reg_offset = _offset, \
78
+
.mult_shift = _mshift, \
79
+
.mult_width = _mwidth, \
80
+
.div_shift = _dshift, \
81
+
.div_width = _dwidth, \
82
+
}
83
+
84
+
#define CLK_SCALE(_id, _name, _pname, _offset, \
85
+
_dshift, _dwidth) \
86
+
{ \
87
+
.id = _id, \
88
+
.type = CLK_TYPE_SCALE, \
89
+
.name = _name, \
90
+
.parent_name = _pname, \
91
+
.reg_offset = _offset, \
92
+
.div_shift = _dshift, \
93
+
.div_width = _dwidth, \
94
+
}
95
+
96
+
#define CLK_GATE(_id, _name, _pname, _offset, _bidx) \
97
+
{ \
98
+
.id = _id, \
99
+
.type = CLK_TYPE_GATE, \
100
+
.name = _name, \
101
+
.parent_name = _pname, \
102
+
.reg_offset = _offset, \
103
+
.bit_idx = _bidx, \
104
+
}
105
+
106
+
#define CLK_FIXED(_id, _name, _pname, _rate) \
107
+
{ \
108
+
.id = _id, \
109
+
.type = CLK_TYPE_FIXED, \
110
+
.name = _name, \
111
+
.parent_name = _pname, \
112
+
.fixed_rate = _rate, \
113
+
}
114
+
115
+
static const struct loongson2_clk_board_info ls2k0500_clks[] = {
116
+
CLK_PLL(LOONGSON2_NODE_PLL, "pll_node", 0, 16, 8, 8, 6),
117
+
CLK_PLL(LOONGSON2_DDR_PLL, "pll_ddr", 0x8, 16, 8, 8, 6),
118
+
CLK_PLL(LOONGSON2_DC_PLL, "pll_soc", 0x10, 16, 8, 8, 6),
119
+
CLK_PLL(LOONGSON2_PIX0_PLL, "pll_pix0", 0x18, 16, 8, 8, 6),
120
+
CLK_PLL(LOONGSON2_PIX1_PLL, "pll_pix1", 0x20, 16, 8, 8, 6),
121
+
CLK_DIV(LOONGSON2_NODE_CLK, "clk_node", "pll_node", 0, 24, 6),
122
+
CLK_DIV(LOONGSON2_DDR_CLK, "clk_ddr", "pll_ddr", 0x8, 24, 6),
123
+
CLK_DIV(LOONGSON2_HDA_CLK, "clk_hda", "pll_ddr", 0xc, 8, 6),
124
+
CLK_DIV(LOONGSON2_GPU_CLK, "clk_gpu", "pll_soc", 0x10, 24, 6),
125
+
CLK_DIV(LOONGSON2_DC_CLK, "clk_sb", "pll_soc", 0x14, 0, 6),
126
+
CLK_DIV(LOONGSON2_GMAC_CLK, "clk_gmac", "pll_soc", 0x14, 8, 6),
127
+
CLK_DIV(LOONGSON2_PIX0_CLK, "clk_pix0", "pll_pix0", 0x18, 24, 6),
128
+
CLK_DIV(LOONGSON2_PIX1_CLK, "clk_pix1", "pll_pix1", 0x20, 24, 6),
129
+
CLK_SCALE(LOONGSON2_BOOT_CLK, "clk_boot", "clk_sb", 0x28, 8, 3),
130
+
CLK_SCALE(LOONGSON2_SATA_CLK, "clk_sata", "clk_sb", 0x28, 12, 3),
131
+
CLK_SCALE(LOONGSON2_USB_CLK, "clk_usb", "clk_sb", 0x28, 16, 3),
132
+
CLK_SCALE(LOONGSON2_APB_CLK, "clk_apb", "clk_sb", 0x28, 20, 3),
133
+
{ /* Sentinel */ },
131
134
};
132
135
133
-
static unsigned long loongson2_calc_rate(unsigned long rate,
134
-
int shift, int width)
135
-
{
136
-
u64 val;
137
-
u32 mult;
138
-
139
-
val = readq(loongson2_pll_base + 0x50);
140
-
141
-
mult = (val >> shift) & clk_div_mask(width);
142
-
143
-
return div_u64((u64)rate * (mult + 1), 8);
144
-
}
145
-
146
-
static unsigned long loongson2_boot_recalc_rate(struct clk_hw *hw,
147
-
unsigned long parent_rate)
148
-
{
149
-
return loongson2_calc_rate(parent_rate,
150
-
LOONGSON2_BOOT_FREQSCALE_SHIFT,
151
-
LOONGSON2_BOOT_FREQSCALE_WIDTH);
152
-
}
153
-
154
-
static const struct clk_ops loongson2_boot_clk_ops = {
155
-
.recalc_rate = loongson2_boot_recalc_rate,
156
-
};
157
-
158
-
static unsigned long loongson2_apb_recalc_rate(struct clk_hw *hw,
159
-
unsigned long parent_rate)
160
-
{
161
-
return loongson2_calc_rate(parent_rate,
162
-
LOONGSON2_APB_FREQSCALE_SHIFT,
163
-
LOONGSON2_APB_FREQSCALE_WIDTH);
164
-
}
165
-
166
-
static const struct clk_ops loongson2_apb_clk_ops = {
167
-
.recalc_rate = loongson2_apb_recalc_rate,
168
-
};
169
-
170
-
static unsigned long loongson2_usb_recalc_rate(struct clk_hw *hw,
171
-
unsigned long parent_rate)
172
-
{
173
-
return loongson2_calc_rate(parent_rate,
174
-
LOONGSON2_USB_FREQSCALE_SHIFT,
175
-
LOONGSON2_USB_FREQSCALE_WIDTH);
176
-
}
177
-
178
-
static const struct clk_ops loongson2_usb_clk_ops = {
179
-
.recalc_rate = loongson2_usb_recalc_rate,
180
-
};
181
-
182
-
static unsigned long loongson2_sata_recalc_rate(struct clk_hw *hw,
183
-
unsigned long parent_rate)
184
-
{
185
-
return loongson2_calc_rate(parent_rate,
186
-
LOONGSON2_SATA_FREQSCALE_SHIFT,
187
-
LOONGSON2_SATA_FREQSCALE_WIDTH);
188
-
}
189
-
190
-
static const struct clk_ops loongson2_sata_clk_ops = {
191
-
.recalc_rate = loongson2_sata_recalc_rate,
192
-
};
193
-
194
-
static inline int loongson2_check_clk_hws(struct clk_hw *clks[], unsigned int count)
195
-
{
196
-
unsigned int i;
197
-
198
-
for (i = 0; i < count; i++)
199
-
if (IS_ERR(clks[i])) {
200
-
pr_err("Loongson2 clk %u: register failed with %ld\n",
201
-
i, PTR_ERR(clks[i]));
202
-
return PTR_ERR(clks[i]);
203
-
}
204
-
205
-
return 0;
206
-
}
207
-
208
-
static int loongson2_clk_probe(struct platform_device *pdev)
209
-
{
210
-
int ret;
211
-
struct clk_hw **hws;
212
-
struct clk_hw_onecell_data *clk_hw_data;
213
-
spinlock_t loongson2_clk_lock;
214
-
struct device *dev = &pdev->dev;
215
-
216
-
loongson2_pll_base = devm_platform_ioremap_resource(pdev, 0);
217
-
if (IS_ERR(loongson2_pll_base))
218
-
return PTR_ERR(loongson2_pll_base);
219
-
220
-
clk_hw_data = devm_kzalloc(dev, struct_size(clk_hw_data, hws, LOONGSON2_CLK_END),
221
-
GFP_KERNEL);
222
-
if (WARN_ON(!clk_hw_data))
223
-
return -ENOMEM;
224
-
225
-
clk_hw_data->num = LOONGSON2_CLK_END;
226
-
hws = clk_hw_data->hws;
227
-
228
-
hws[LOONGSON2_NODE_PLL] = loongson2_clk_register(dev, "node_pll",
229
-
NULL,
230
-
&loongson2_node_clk_ops, 0);
231
-
232
-
hws[LOONGSON2_DDR_PLL] = loongson2_clk_register(dev, "ddr_pll",
233
-
NULL,
234
-
&loongson2_ddr_clk_ops, 0);
235
-
236
-
hws[LOONGSON2_DC_PLL] = loongson2_clk_register(dev, "dc_pll",
237
-
NULL,
238
-
&loongson2_dc_clk_ops, 0);
239
-
240
-
hws[LOONGSON2_PIX0_PLL] = loongson2_clk_register(dev, "pix0_pll",
241
-
NULL,
242
-
&loongson2_pix0_clk_ops, 0);
243
-
244
-
hws[LOONGSON2_PIX1_PLL] = loongson2_clk_register(dev, "pix1_pll",
245
-
NULL,
246
-
&loongson2_pix1_clk_ops, 0);
247
-
248
-
hws[LOONGSON2_BOOT_CLK] = loongson2_clk_register(dev, "boot",
249
-
NULL,
250
-
&loongson2_boot_clk_ops, 0);
251
-
252
-
hws[LOONGSON2_NODE_CLK] = devm_clk_hw_register_divider(dev, "node",
253
-
"node_pll", 0,
254
-
loongson2_pll_base + 0x8, 0,
255
-
6, CLK_DIVIDER_ONE_BASED,
256
-
&loongson2_clk_lock);
257
-
136
+
static const struct loongson2_clk_board_info ls2k1000_clks[] = {
137
+
CLK_PLL(LOONGSON2_NODE_PLL, "pll_node", 0, 32, 10, 26, 6),
138
+
CLK_PLL(LOONGSON2_DDR_PLL, "pll_ddr", 0x10, 32, 10, 26, 6),
139
+
CLK_PLL(LOONGSON2_DC_PLL, "pll_dc", 0x20, 32, 10, 26, 6),
140
+
CLK_PLL(LOONGSON2_PIX0_PLL, "pll_pix0", 0x30, 32, 10, 26, 6),
141
+
CLK_PLL(LOONGSON2_PIX1_PLL, "pll_pix1", 0x40, 32, 10, 26, 6),
142
+
CLK_DIV(LOONGSON2_NODE_CLK, "clk_node", "pll_node", 0x8, 0, 6),
143
+
CLK_DIV(LOONGSON2_DDR_CLK, "clk_ddr", "pll_ddr", 0x18, 0, 6),
144
+
CLK_DIV(LOONGSON2_GPU_CLK, "clk_gpu", "pll_ddr", 0x18, 22, 6),
258
145
/*
259
146
* The hda clk divisor in the upper 32bits and the clk-prodiver
260
147
* layer code doesn't support 64bit io operation thus a conversion
261
148
* is required that subtract shift by 32 and add 4byte to the hda
262
149
* address
263
150
*/
264
-
hws[LOONGSON2_HDA_CLK] = devm_clk_hw_register_divider(dev, "hda",
265
-
"ddr_pll", 0,
266
-
loongson2_pll_base + 0x22, 12,
267
-
7, CLK_DIVIDER_ONE_BASED,
268
-
&loongson2_clk_lock);
151
+
CLK_DIV(LOONGSON2_HDA_CLK, "clk_hda", "pll_ddr", 0x22, 12, 7),
152
+
CLK_DIV(LOONGSON2_DC_CLK, "clk_dc", "pll_dc", 0x28, 0, 6),
153
+
CLK_DIV(LOONGSON2_GMAC_CLK, "clk_gmac", "pll_dc", 0x28, 22, 6),
154
+
CLK_DIV(LOONGSON2_PIX0_CLK, "clk_pix0", "pll_pix0", 0x38, 0, 6),
155
+
CLK_DIV(LOONGSON2_PIX1_CLK, "clk_pix1", "pll_pix1", 0x38, 0, 6),
156
+
CLK_SCALE(LOONGSON2_BOOT_CLK, "clk_boot", NULL, 0x50, 8, 3),
157
+
CLK_SCALE(LOONGSON2_SATA_CLK, "clk_sata", "clk_gmac", 0x50, 12, 3),
158
+
CLK_SCALE(LOONGSON2_USB_CLK, "clk_usb", "clk_gmac", 0x50, 16, 3),
159
+
CLK_SCALE(LOONGSON2_APB_CLK, "clk_apb", "clk_gmac", 0x50, 20, 3),
160
+
{ /* Sentinel */ },
161
+
};
269
162
270
-
hws[LOONGSON2_GPU_CLK] = devm_clk_hw_register_divider(dev, "gpu",
271
-
"ddr_pll", 0,
272
-
loongson2_pll_base + 0x18, 22,
273
-
6, CLK_DIVIDER_ONE_BASED,
274
-
&loongson2_clk_lock);
163
+
static const struct loongson2_clk_board_info ls2k2000_clks[] = {
164
+
CLK_PLL(LOONGSON2_DC_PLL, "pll_0", 0, 21, 9, 32, 6),
165
+
CLK_PLL(LOONGSON2_DDR_PLL, "pll_1", 0x10, 21, 9, 32, 6),
166
+
CLK_PLL(LOONGSON2_NODE_PLL, "pll_2", 0x20, 21, 9, 32, 6),
167
+
CLK_PLL(LOONGSON2_PIX0_PLL, "pll_pix0", 0x30, 21, 9, 32, 6),
168
+
CLK_PLL(LOONGSON2_PIX1_PLL, "pll_pix1", 0x40, 21, 9, 32, 6),
169
+
CLK_GATE(LOONGSON2_OUT0_GATE, "out0_gate", "pll_0", 0, 40),
170
+
CLK_GATE(LOONGSON2_GMAC_GATE, "gmac_gate", "pll_0", 0, 41),
171
+
CLK_GATE(LOONGSON2_RIO_GATE, "rio_gate", "pll_0", 0, 42),
172
+
CLK_GATE(LOONGSON2_DC_GATE, "dc_gate", "pll_1", 0x10, 40),
173
+
CLK_GATE(LOONGSON2_DDR_GATE, "ddr_gate", "pll_1", 0x10, 41),
174
+
CLK_GATE(LOONGSON2_GPU_GATE, "gpu_gate", "pll_1", 0x10, 42),
175
+
CLK_GATE(LOONGSON2_HDA_GATE, "hda_gate", "pll_2", 0x20, 40),
176
+
CLK_GATE(LOONGSON2_NODE_GATE, "node_gate", "pll_2", 0x20, 41),
177
+
CLK_GATE(LOONGSON2_EMMC_GATE, "emmc_gate", "pll_2", 0x20, 42),
178
+
CLK_GATE(LOONGSON2_PIX0_GATE, "pix0_gate", "pll_pix0", 0x30, 40),
179
+
CLK_GATE(LOONGSON2_PIX1_GATE, "pix1_gate", "pll_pix1", 0x40, 40),
180
+
CLK_DIV(LOONGSON2_OUT0_CLK, "clk_out0", "out0_gate", 0, 0, 6),
181
+
CLK_DIV(LOONGSON2_GMAC_CLK, "clk_gmac", "gmac_gate", 0, 7, 6),
182
+
CLK_DIV(LOONGSON2_RIO_CLK, "clk_rio", "rio_gate", 0, 14, 6),
183
+
CLK_DIV(LOONGSON2_DC_CLK, "clk_dc", "dc_gate", 0x10, 0, 6),
184
+
CLK_DIV(LOONGSON2_GPU_CLK, "clk_gpu", "gpu_gate", 0x10, 7, 6),
185
+
CLK_DIV(LOONGSON2_DDR_CLK, "clk_ddr", "ddr_gate", 0x10, 14, 6),
186
+
CLK_DIV(LOONGSON2_HDA_CLK, "clk_hda", "hda_gate", 0x20, 0, 6),
187
+
CLK_DIV(LOONGSON2_NODE_CLK, "clk_node", "node_gate", 0x20, 7, 6),
188
+
CLK_DIV(LOONGSON2_EMMC_CLK, "clk_emmc", "emmc_gate", 0x20, 14, 6),
189
+
CLK_DIV(LOONGSON2_PIX0_CLK, "clk_pix0", "pll_pix0", 0x30, 0, 6),
190
+
CLK_DIV(LOONGSON2_PIX1_CLK, "clk_pix1", "pll_pix1", 0x40, 0, 6),
191
+
CLK_SCALE(LOONGSON2_SATA_CLK, "clk_sata", "clk_out0", 0x50, 12, 3),
192
+
CLK_SCALE(LOONGSON2_USB_CLK, "clk_usb", "clk_out0", 0x50, 16, 3),
193
+
CLK_SCALE(LOONGSON2_APB_CLK, "clk_apb", "clk_node", 0x50, 20, 3),
194
+
CLK_SCALE(LOONGSON2_BOOT_CLK, "clk_boot", NULL, 0x50, 23, 3),
195
+
CLK_SCALE(LOONGSON2_DES_CLK, "clk_des", "clk_node", 0x50, 40, 3),
196
+
CLK_SCALE(LOONGSON2_I2S_CLK, "clk_i2s", "clk_node", 0x50, 44, 3),
197
+
CLK_FIXED(LOONGSON2_MISC_CLK, "clk_misc", NULL, 50000000),
198
+
{ /* Sentinel */ },
199
+
};
275
200
276
-
hws[LOONGSON2_DDR_CLK] = devm_clk_hw_register_divider(dev, "ddr",
277
-
"ddr_pll", 0,
278
-
loongson2_pll_base + 0x18, 0,
279
-
6, CLK_DIVIDER_ONE_BASED,
280
-
&loongson2_clk_lock);
201
+
static inline struct loongson2_clk_data *to_loongson2_clk(struct clk_hw *hw)
202
+
{
203
+
return container_of(hw, struct loongson2_clk_data, hw);
204
+
}
281
205
282
-
hws[LOONGSON2_GMAC_CLK] = devm_clk_hw_register_divider(dev, "gmac",
283
-
"dc_pll", 0,
284
-
loongson2_pll_base + 0x28, 22,
285
-
6, CLK_DIVIDER_ONE_BASED,
286
-
&loongson2_clk_lock);
206
+
static inline unsigned long loongson2_rate_part(u64 val, u8 shift, u8 width)
207
+
{
208
+
return (val & GENMASK(shift + width - 1, shift)) >> shift;
209
+
}
287
210
288
-
hws[LOONGSON2_DC_CLK] = devm_clk_hw_register_divider(dev, "dc",
289
-
"dc_pll", 0,
290
-
loongson2_pll_base + 0x28, 0,
291
-
6, CLK_DIVIDER_ONE_BASED,
292
-
&loongson2_clk_lock);
211
+
static unsigned long loongson2_pll_recalc_rate(struct clk_hw *hw,
212
+
unsigned long parent_rate)
213
+
{
214
+
u64 val, mult, div;
215
+
struct loongson2_clk_data *clk = to_loongson2_clk(hw);
293
216
294
-
hws[LOONGSON2_APB_CLK] = loongson2_clk_register(dev, "apb",
295
-
"gmac",
296
-
&loongson2_apb_clk_ops, 0);
217
+
val = readq(clk->reg);
218
+
mult = loongson2_rate_part(val, clk->mult_shift, clk->mult_width);
219
+
div = loongson2_rate_part(val, clk->div_shift, clk->div_width);
297
220
298
-
hws[LOONGSON2_USB_CLK] = loongson2_clk_register(dev, "usb",
299
-
"gmac",
300
-
&loongson2_usb_clk_ops, 0);
221
+
return div_u64((u64)parent_rate * mult, div);
222
+
}
301
223
302
-
hws[LOONGSON2_SATA_CLK] = loongson2_clk_register(dev, "sata",
303
-
"gmac",
304
-
&loongson2_sata_clk_ops, 0);
224
+
static const struct clk_ops loongson2_pll_recalc_ops = {
225
+
.recalc_rate = loongson2_pll_recalc_rate,
226
+
};
305
227
306
-
hws[LOONGSON2_PIX0_CLK] = clk_hw_register_divider(NULL, "pix0",
307
-
"pix0_pll", 0,
308
-
loongson2_pll_base + 0x38, 0, 6,
309
-
CLK_DIVIDER_ONE_BASED,
310
-
&loongson2_clk_lock);
228
+
static unsigned long loongson2_freqscale_recalc_rate(struct clk_hw *hw,
229
+
unsigned long parent_rate)
230
+
{
231
+
u64 val, mult;
232
+
struct loongson2_clk_data *clk = to_loongson2_clk(hw);
311
233
312
-
hws[LOONGSON2_PIX1_CLK] = clk_hw_register_divider(NULL, "pix1",
313
-
"pix1_pll", 0,
314
-
loongson2_pll_base + 0x48, 0, 6,
315
-
CLK_DIVIDER_ONE_BASED,
316
-
&loongson2_clk_lock);
234
+
val = readq(clk->reg);
235
+
mult = loongson2_rate_part(val, clk->div_shift, clk->div_width) + 1;
317
236
318
-
ret = loongson2_check_clk_hws(hws, LOONGSON2_CLK_END);
237
+
return div_u64((u64)parent_rate * mult, 8);
238
+
}
239
+
240
+
static const struct clk_ops loongson2_freqscale_recalc_ops = {
241
+
.recalc_rate = loongson2_freqscale_recalc_rate,
242
+
};
243
+
244
+
static struct clk_hw *loongson2_clk_register(struct loongson2_clk_provider *clp,
245
+
const struct loongson2_clk_board_info *cld,
246
+
const struct clk_ops *ops)
247
+
{
248
+
int ret;
249
+
struct clk_hw *hw;
250
+
struct loongson2_clk_data *clk;
251
+
struct clk_init_data init = { };
252
+
253
+
clk = devm_kzalloc(clp->dev, sizeof(*clk), GFP_KERNEL);
254
+
if (!clk)
255
+
return ERR_PTR(-ENOMEM);
256
+
257
+
init.name = cld->name;
258
+
init.ops = ops;
259
+
init.flags = 0;
260
+
init.num_parents = 1;
261
+
262
+
if (!cld->parent_name)
263
+
init.parent_data = pdata;
264
+
else
265
+
init.parent_names = &cld->parent_name;
266
+
267
+
clk->reg = clp->base + cld->reg_offset;
268
+
clk->div_shift = cld->div_shift;
269
+
clk->div_width = cld->div_width;
270
+
clk->mult_shift = cld->mult_shift;
271
+
clk->mult_width = cld->mult_width;
272
+
clk->hw.init = &init;
273
+
274
+
hw = &clk->hw;
275
+
ret = devm_clk_hw_register(clp->dev, hw);
319
276
if (ret)
320
-
return ret;
277
+
clk = ERR_PTR(ret);
321
278
322
-
return devm_of_clk_add_hw_provider(dev, of_clk_hw_onecell_get, clk_hw_data);
279
+
return hw;
280
+
}
281
+
282
+
static int loongson2_clk_probe(struct platform_device *pdev)
283
+
{
284
+
int i, clks_num = 0;
285
+
struct clk_hw *hw;
286
+
struct device *dev = &pdev->dev;
287
+
struct loongson2_clk_provider *clp;
288
+
const struct loongson2_clk_board_info *p, *data;
289
+
290
+
data = device_get_match_data(dev);
291
+
if (!data)
292
+
return -EINVAL;
293
+
294
+
for (p = data; p->name; p++)
295
+
clks_num++;
296
+
297
+
clp = devm_kzalloc(dev, struct_size(clp, clk_data.hws, clks_num),
298
+
GFP_KERNEL);
299
+
if (!clp)
300
+
return -ENOMEM;
301
+
302
+
clp->base = devm_platform_ioremap_resource(pdev, 0);
303
+
if (IS_ERR(clp->base))
304
+
return PTR_ERR(clp->base);
305
+
306
+
spin_lock_init(&clp->clk_lock);
307
+
clp->clk_data.num = clks_num + 1;
308
+
clp->dev = dev;
309
+
310
+
for (i = 0; i < clks_num; i++) {
311
+
p = &data[i];
312
+
switch (p->type) {
313
+
case CLK_TYPE_PLL:
314
+
hw = loongson2_clk_register(clp, p,
315
+
&loongson2_pll_recalc_ops);
316
+
break;
317
+
case CLK_TYPE_SCALE:
318
+
hw = loongson2_clk_register(clp, p,
319
+
&loongson2_freqscale_recalc_ops);
320
+
break;
321
+
case CLK_TYPE_DIVIDER:
322
+
hw = devm_clk_hw_register_divider(dev, p->name,
323
+
p->parent_name, 0,
324
+
clp->base + p->reg_offset,
325
+
p->div_shift, p->div_width,
326
+
CLK_DIVIDER_ONE_BASED,
327
+
&clp->clk_lock);
328
+
break;
329
+
case CLK_TYPE_GATE:
330
+
hw = devm_clk_hw_register_gate(dev, p->name, p->parent_name, 0,
331
+
clp->base + p->reg_offset,
332
+
p->bit_idx, 0,
333
+
&clp->clk_lock);
334
+
break;
335
+
case CLK_TYPE_FIXED:
336
+
hw = clk_hw_register_fixed_rate_parent_data(dev, p->name, pdata,
337
+
0, p->fixed_rate);
338
+
break;
339
+
default:
340
+
return dev_err_probe(dev, -EINVAL, "Invalid clk type\n");
341
+
}
342
+
343
+
if (IS_ERR(hw))
344
+
return dev_err_probe(dev, PTR_ERR(hw),
345
+
"Register clk: %s, type: %u failed!\n",
346
+
p->name, p->type);
347
+
348
+
clp->clk_data.hws[p->id] = hw;
349
+
}
350
+
351
+
return devm_of_clk_add_hw_provider(dev, of_clk_hw_onecell_get, &clp->clk_data);
323
352
}
324
353
325
354
static const struct of_device_id loongson2_clk_match_table[] = {
326
-
{ .compatible = "loongson,ls2k-clk" },
355
+
{ .compatible = "loongson,ls2k0500-clk", .data = &ls2k0500_clks },
356
+
{ .compatible = "loongson,ls2k-clk", .data = &ls2k1000_clks },
357
+
{ .compatible = "loongson,ls2k2000-clk", .data = &ls2k2000_clks },
327
358
{ }
328
359
};
329
360
MODULE_DEVICE_TABLE(of, loongson2_clk_match_table);
···
369
338
module_platform_driver(loongson2_clk_driver);
370
339
371
340
MODULE_DESCRIPTION("Loongson2 clock driver");
341
+
MODULE_AUTHOR("Loongson Technology Corporation Limited");
372
342
MODULE_LICENSE("GPL");
+6
-4
drivers/clk/clk-renesas-pcie.c
+6
-4
drivers/clk/clk-renesas-pcie.c
···
25
25
#define RS9_REG_SS_AMP_0V7 0x1
26
26
#define RS9_REG_SS_AMP_0V8 0x2
27
27
#define RS9_REG_SS_AMP_0V9 0x3
28
+
#define RS9_REG_SS_AMP_DEFAULT RS9_REG_SS_AMP_0V8
28
29
#define RS9_REG_SS_AMP_MASK 0x3
29
30
#define RS9_REG_SS_SSC_100 0
30
31
#define RS9_REG_SS_SSC_M025 (1 << 3)
31
32
#define RS9_REG_SS_SSC_M050 (3 << 3)
33
+
#define RS9_REG_SS_SSC_DEFAULT RS9_REG_SS_SSC_100
32
34
#define RS9_REG_SS_SSC_MASK (3 << 3)
33
35
#define RS9_REG_SS_SSC_LOCK BIT(5)
34
36
#define RS9_REG_SR 0x2
···
207
205
int ret;
208
206
209
207
/* Set defaults */
210
-
rs9->pll_amplitude = RS9_REG_SS_AMP_0V7;
211
-
rs9->pll_ssc = RS9_REG_SS_SSC_100;
208
+
rs9->pll_amplitude = RS9_REG_SS_AMP_DEFAULT;
209
+
rs9->pll_ssc = RS9_REG_SS_SSC_DEFAULT;
212
210
213
211
/* Output clock amplitude */
214
212
ret = of_property_read_u32(np, "renesas,out-amplitude-microvolt",
···
249
247
int i;
250
248
251
249
/* If amplitude is non-default, update it. */
252
-
if (rs9->pll_amplitude != RS9_REG_SS_AMP_0V7) {
250
+
if (rs9->pll_amplitude != RS9_REG_SS_AMP_DEFAULT) {
253
251
regmap_update_bits(rs9->regmap, RS9_REG_SS, RS9_REG_SS_AMP_MASK,
254
252
rs9->pll_amplitude);
255
253
}
256
254
257
255
/* If SSC is non-default, update it. */
258
-
if (rs9->pll_ssc != RS9_REG_SS_SSC_100) {
256
+
if (rs9->pll_ssc != RS9_REG_SS_SSC_DEFAULT) {
259
257
regmap_update_bits(rs9->regmap, RS9_REG_SS, RS9_REG_SS_SSC_MASK,
260
258
rs9->pll_ssc);
261
259
}
+201
-48
drivers/clk/clk-scmi.c
+201
-48
drivers/clk/clk-scmi.c
···
2
2
/*
3
3
* System Control and Power Interface (SCMI) Protocol based clock driver
4
4
*
5
-
* Copyright (C) 2018-2022 ARM Ltd.
5
+
* Copyright (C) 2018-2024 ARM Ltd.
6
6
*/
7
7
8
+
#include <linux/bits.h>
8
9
#include <linux/clk-provider.h>
9
10
#include <linux/device.h>
10
11
#include <linux/err.h>
···
16
15
17
16
#define NOT_ATOMIC false
18
17
#define ATOMIC true
18
+
19
+
enum scmi_clk_feats {
20
+
SCMI_CLK_ATOMIC_SUPPORTED,
21
+
SCMI_CLK_STATE_CTRL_SUPPORTED,
22
+
SCMI_CLK_RATE_CTRL_SUPPORTED,
23
+
SCMI_CLK_PARENT_CTRL_SUPPORTED,
24
+
SCMI_CLK_DUTY_CYCLE_SUPPORTED,
25
+
SCMI_CLK_FEATS_COUNT
26
+
};
27
+
28
+
#define SCMI_MAX_CLK_OPS BIT(SCMI_CLK_FEATS_COUNT)
19
29
20
30
static const struct scmi_clk_proto_ops *scmi_proto_clk_ops;
21
31
···
170
158
return !!enabled;
171
159
}
172
160
173
-
/*
174
-
* We can provide enable/disable/is_enabled atomic callbacks only if the
175
-
* underlying SCMI transport for an SCMI instance is configured to handle
176
-
* SCMI commands in an atomic manner.
177
-
*
178
-
* When no SCMI atomic transport support is available we instead provide only
179
-
* the prepare/unprepare API, as allowed by the clock framework when atomic
180
-
* calls are not available.
181
-
*
182
-
* Two distinct sets of clk_ops are provided since we could have multiple SCMI
183
-
* instances with different underlying transport quality, so they cannot be
184
-
* shared.
185
-
*/
186
-
static const struct clk_ops scmi_clk_ops = {
187
-
.recalc_rate = scmi_clk_recalc_rate,
188
-
.round_rate = scmi_clk_round_rate,
189
-
.set_rate = scmi_clk_set_rate,
190
-
.prepare = scmi_clk_enable,
191
-
.unprepare = scmi_clk_disable,
192
-
.set_parent = scmi_clk_set_parent,
193
-
.get_parent = scmi_clk_get_parent,
194
-
.determine_rate = scmi_clk_determine_rate,
195
-
};
161
+
static int scmi_clk_get_duty_cycle(struct clk_hw *hw, struct clk_duty *duty)
162
+
{
163
+
int ret;
164
+
u32 val;
165
+
struct scmi_clk *clk = to_scmi_clk(hw);
196
166
197
-
static const struct clk_ops scmi_atomic_clk_ops = {
198
-
.recalc_rate = scmi_clk_recalc_rate,
199
-
.round_rate = scmi_clk_round_rate,
200
-
.set_rate = scmi_clk_set_rate,
201
-
.enable = scmi_clk_atomic_enable,
202
-
.disable = scmi_clk_atomic_disable,
203
-
.is_enabled = scmi_clk_atomic_is_enabled,
204
-
.set_parent = scmi_clk_set_parent,
205
-
.get_parent = scmi_clk_get_parent,
206
-
.determine_rate = scmi_clk_determine_rate,
207
-
};
167
+
ret = scmi_proto_clk_ops->config_oem_get(clk->ph, clk->id,
168
+
SCMI_CLOCK_CFG_DUTY_CYCLE,
169
+
&val, NULL, false);
170
+
if (!ret) {
171
+
duty->num = val;
172
+
duty->den = 100;
173
+
} else {
174
+
dev_warn(clk->dev,
175
+
"Failed to get duty cycle for clock ID %d\n", clk->id);
176
+
}
177
+
178
+
return ret;
179
+
}
180
+
181
+
static int scmi_clk_set_duty_cycle(struct clk_hw *hw, struct clk_duty *duty)
182
+
{
183
+
int ret;
184
+
u32 val;
185
+
struct scmi_clk *clk = to_scmi_clk(hw);
186
+
187
+
/* SCMI OEM Duty Cycle is expressed as a percentage */
188
+
val = (duty->num * 100) / duty->den;
189
+
ret = scmi_proto_clk_ops->config_oem_set(clk->ph, clk->id,
190
+
SCMI_CLOCK_CFG_DUTY_CYCLE,
191
+
val, false);
192
+
if (ret)
193
+
dev_warn(clk->dev,
194
+
"Failed to set duty cycle(%u/%u) for clock ID %d\n",
195
+
duty->num, duty->den, clk->id);
196
+
197
+
return ret;
198
+
}
208
199
209
200
static int scmi_clk_ops_init(struct device *dev, struct scmi_clk *sclk,
210
201
const struct clk_ops *scmi_ops)
···
245
230
return ret;
246
231
}
247
232
233
+
/**
234
+
* scmi_clk_ops_alloc() - Alloc and configure clock operations
235
+
* @dev: A device reference for devres
236
+
* @feats_key: A bitmap representing the desired clk_ops capabilities
237
+
*
238
+
* Allocate and configure a proper set of clock operations depending on the
239
+
* specifically required SCMI clock features.
240
+
*
241
+
* Return: A pointer to the allocated and configured clk_ops on success,
242
+
* or NULL on allocation failure.
243
+
*/
244
+
static const struct clk_ops *
245
+
scmi_clk_ops_alloc(struct device *dev, unsigned long feats_key)
246
+
{
247
+
struct clk_ops *ops;
248
+
249
+
ops = devm_kzalloc(dev, sizeof(*ops), GFP_KERNEL);
250
+
if (!ops)
251
+
return NULL;
252
+
/*
253
+
* We can provide enable/disable/is_enabled atomic callbacks only if the
254
+
* underlying SCMI transport for an SCMI instance is configured to
255
+
* handle SCMI commands in an atomic manner.
256
+
*
257
+
* When no SCMI atomic transport support is available we instead provide
258
+
* only the prepare/unprepare API, as allowed by the clock framework
259
+
* when atomic calls are not available.
260
+
*/
261
+
if (feats_key & BIT(SCMI_CLK_STATE_CTRL_SUPPORTED)) {
262
+
if (feats_key & BIT(SCMI_CLK_ATOMIC_SUPPORTED)) {
263
+
ops->enable = scmi_clk_atomic_enable;
264
+
ops->disable = scmi_clk_atomic_disable;
265
+
} else {
266
+
ops->prepare = scmi_clk_enable;
267
+
ops->unprepare = scmi_clk_disable;
268
+
}
269
+
}
270
+
271
+
if (feats_key & BIT(SCMI_CLK_ATOMIC_SUPPORTED))
272
+
ops->is_enabled = scmi_clk_atomic_is_enabled;
273
+
274
+
/* Rate ops */
275
+
ops->recalc_rate = scmi_clk_recalc_rate;
276
+
ops->round_rate = scmi_clk_round_rate;
277
+
ops->determine_rate = scmi_clk_determine_rate;
278
+
if (feats_key & BIT(SCMI_CLK_RATE_CTRL_SUPPORTED))
279
+
ops->set_rate = scmi_clk_set_rate;
280
+
281
+
/* Parent ops */
282
+
ops->get_parent = scmi_clk_get_parent;
283
+
if (feats_key & BIT(SCMI_CLK_PARENT_CTRL_SUPPORTED))
284
+
ops->set_parent = scmi_clk_set_parent;
285
+
286
+
/* Duty cycle */
287
+
if (feats_key & BIT(SCMI_CLK_DUTY_CYCLE_SUPPORTED)) {
288
+
ops->get_duty_cycle = scmi_clk_get_duty_cycle;
289
+
ops->set_duty_cycle = scmi_clk_set_duty_cycle;
290
+
}
291
+
292
+
return ops;
293
+
}
294
+
295
+
/**
296
+
* scmi_clk_ops_select() - Select a proper set of clock operations
297
+
* @sclk: A reference to an SCMI clock descriptor
298
+
* @atomic_capable: A flag to indicate if atomic mode is supported by the
299
+
* transport
300
+
* @atomic_threshold_us: Platform atomic threshold value in microseconds:
301
+
* clk_ops are atomic when clock enable latency is less
302
+
* than this threshold
303
+
* @clk_ops_db: A reference to the array used as a database to store all the
304
+
* created clock operations combinations.
305
+
* @db_size: Maximum number of entries held by @clk_ops_db
306
+
*
307
+
* After having built a bitmap descriptor to represent the set of features
308
+
* needed by this SCMI clock, at first use it to lookup into the set of
309
+
* previously allocated clk_ops to check if a suitable combination of clock
310
+
* operations was already created; when no match is found allocate a brand new
311
+
* set of clk_ops satisfying the required combination of features and save it
312
+
* for future references.
313
+
*
314
+
* In this way only one set of clk_ops is ever created for each different
315
+
* combination that is effectively needed by a driver instance.
316
+
*
317
+
* Return: A pointer to the allocated and configured clk_ops on success, or
318
+
* NULL otherwise.
319
+
*/
320
+
static const struct clk_ops *
321
+
scmi_clk_ops_select(struct scmi_clk *sclk, bool atomic_capable,
322
+
unsigned int atomic_threshold_us,
323
+
const struct clk_ops **clk_ops_db, size_t db_size)
324
+
{
325
+
const struct scmi_clock_info *ci = sclk->info;
326
+
unsigned int feats_key = 0;
327
+
const struct clk_ops *ops;
328
+
329
+
/*
330
+
* Note that when transport is atomic but SCMI protocol did not
331
+
* specify (or support) an enable_latency associated with a
332
+
* clock, we default to use atomic operations mode.
333
+
*/
334
+
if (atomic_capable && ci->enable_latency <= atomic_threshold_us)
335
+
feats_key |= BIT(SCMI_CLK_ATOMIC_SUPPORTED);
336
+
337
+
if (!ci->state_ctrl_forbidden)
338
+
feats_key |= BIT(SCMI_CLK_STATE_CTRL_SUPPORTED);
339
+
340
+
if (!ci->rate_ctrl_forbidden)
341
+
feats_key |= BIT(SCMI_CLK_RATE_CTRL_SUPPORTED);
342
+
343
+
if (!ci->parent_ctrl_forbidden)
344
+
feats_key |= BIT(SCMI_CLK_PARENT_CTRL_SUPPORTED);
345
+
346
+
if (ci->extended_config)
347
+
feats_key |= BIT(SCMI_CLK_DUTY_CYCLE_SUPPORTED);
348
+
349
+
if (WARN_ON(feats_key >= db_size))
350
+
return NULL;
351
+
352
+
/* Lookup previously allocated ops */
353
+
ops = clk_ops_db[feats_key];
354
+
if (ops)
355
+
return ops;
356
+
357
+
/* Did not find a pre-allocated clock_ops */
358
+
ops = scmi_clk_ops_alloc(sclk->dev, feats_key);
359
+
if (!ops)
360
+
return NULL;
361
+
362
+
/* Store new ops combinations */
363
+
clk_ops_db[feats_key] = ops;
364
+
365
+
return ops;
366
+
}
367
+
248
368
static int scmi_clocks_probe(struct scmi_device *sdev)
249
369
{
250
370
int idx, count, err;
251
-
unsigned int atomic_threshold;
252
-
bool is_atomic;
371
+
unsigned int atomic_threshold_us;
372
+
bool transport_is_atomic;
253
373
struct clk_hw **hws;
254
374
struct clk_hw_onecell_data *clk_data;
255
375
struct device *dev = &sdev->dev;
256
376
struct device_node *np = dev->of_node;
257
377
const struct scmi_handle *handle = sdev->handle;
258
378
struct scmi_protocol_handle *ph;
379
+
const struct clk_ops *scmi_clk_ops_db[SCMI_MAX_CLK_OPS] = {};
259
380
260
381
if (!handle)
261
382
return -ENODEV;
···
415
264
clk_data->num = count;
416
265
hws = clk_data->hws;
417
266
418
-
is_atomic = handle->is_transport_atomic(handle, &atomic_threshold);
267
+
transport_is_atomic = handle->is_transport_atomic(handle,
268
+
&atomic_threshold_us);
419
269
420
270
for (idx = 0; idx < count; idx++) {
421
271
struct scmi_clk *sclk;
···
438
286
sclk->dev = dev;
439
287
440
288
/*
441
-
* Note that when transport is atomic but SCMI protocol did not
442
-
* specify (or support) an enable_latency associated with a
443
-
* clock, we default to use atomic operations mode.
289
+
* Note that the scmi_clk_ops_db is on the stack, not global,
290
+
* because it cannot be shared between mulitple probe-sequences
291
+
* to avoid sharing the devm_ allocated clk_ops between multiple
292
+
* SCMI clk driver instances.
444
293
*/
445
-
if (is_atomic &&
446
-
sclk->info->enable_latency <= atomic_threshold)
447
-
scmi_ops = &scmi_atomic_clk_ops;
448
-
else
449
-
scmi_ops = &scmi_clk_ops;
294
+
scmi_ops = scmi_clk_ops_select(sclk, transport_is_atomic,
295
+
atomic_threshold_us,
296
+
scmi_clk_ops_db,
297
+
ARRAY_SIZE(scmi_clk_ops_db));
298
+
if (!scmi_ops)
299
+
return -ENOMEM;
450
300
451
301
/* Initialize clock parent data. */
452
302
if (sclk->info->num_parents > 0) {
···
472
318
} else {
473
319
dev_dbg(dev, "Registered clock:%s%s\n",
474
320
sclk->info->name,
475
-
scmi_ops == &scmi_atomic_clk_ops ?
476
-
" (atomic ops)" : "");
321
+
scmi_ops->enable ? " (atomic ops)" : "");
477
322
hws[idx] = &sclk->hw;
478
323
}
479
324
}
+7
drivers/clk/imx/Kconfig
+7
drivers/clk/imx/Kconfig
···
114
114
help
115
115
Build the driver for i.MX93 CCM Clock Driver
116
116
117
+
config CLK_IMX95_BLK_CTL
118
+
tristate "IMX95 Clock Driver for BLK CTL"
119
+
depends on ARCH_MXC || COMPILE_TEST
120
+
select MXC_CLK
121
+
help
122
+
Build the clock driver for i.MX95 BLK CTL
123
+
117
124
config CLK_IMXRT1050
118
125
tristate "IMXRT1050 CCM Clock Driver"
119
126
depends on SOC_IMXRT || COMPILE_TEST
+1
drivers/clk/imx/Makefile
+1
drivers/clk/imx/Makefile
···
31
31
obj-$(CONFIG_CLK_IMX8MQ) += clk-imx8mq.o
32
32
33
33
obj-$(CONFIG_CLK_IMX93) += clk-imx93.o
34
+
obj-$(CONFIG_CLK_IMX95_BLK_CTL) += clk-imx95-blk-ctl.o
34
35
35
36
obj-$(CONFIG_MXC_CLK_SCU) += clk-imx-scu.o clk-imx-lpcg-scu.o clk-imx-acm.o
36
37
clk-imx-scu-$(CONFIG_CLK_IMX8QXP) += clk-scu.o clk-imx8qxp.o \
+134
-21
drivers/clk/imx/clk-imx8mp-audiomix.c
+134
-21
drivers/clk/imx/clk-imx8mp-audiomix.c
···
7
7
8
8
#include <linux/clk-provider.h>
9
9
#include <linux/device.h>
10
+
#include <linux/io.h>
10
11
#include <linux/mod_devicetable.h>
11
12
#include <linux/module.h>
12
13
#include <linux/of.h>
13
14
#include <linux/platform_device.h>
15
+
#include <linux/pm_runtime.h>
14
16
15
17
#include <dt-bindings/clock/imx8mp-clock.h>
16
18
···
20
18
21
19
#define CLKEN0 0x000
22
20
#define CLKEN1 0x004
21
+
#define EARC 0x200
23
22
#define SAI1_MCLK_SEL 0x300
24
23
#define SAI2_MCLK_SEL 0x304
25
24
#define SAI3_MCLK_SEL 0x308
···
29
26
#define SAI7_MCLK_SEL 0x314
30
27
#define PDM_SEL 0x318
31
28
#define SAI_PLL_GNRL_CTL 0x400
29
+
#define SAI_PLL_FDIVL_CTL0 0x404
30
+
#define SAI_PLL_FDIVL_CTL1 0x408
31
+
#define SAI_PLL_SSCG_CTL 0x40C
32
+
#define SAI_PLL_MNIT_CTL 0x410
33
+
#define IPG_LP_CTRL 0x504
32
34
33
35
#define SAIn_MCLK1_PARENT(n) \
34
36
static const struct clk_parent_data \
···
190
182
CLK_SAIn(7)
191
183
};
192
184
185
+
static const u16 audiomix_regs[] = {
186
+
CLKEN0,
187
+
CLKEN1,
188
+
EARC,
189
+
SAI1_MCLK_SEL,
190
+
SAI2_MCLK_SEL,
191
+
SAI3_MCLK_SEL,
192
+
SAI5_MCLK_SEL,
193
+
SAI6_MCLK_SEL,
194
+
SAI7_MCLK_SEL,
195
+
PDM_SEL,
196
+
SAI_PLL_GNRL_CTL,
197
+
SAI_PLL_FDIVL_CTL0,
198
+
SAI_PLL_FDIVL_CTL1,
199
+
SAI_PLL_SSCG_CTL,
200
+
SAI_PLL_MNIT_CTL,
201
+
IPG_LP_CTRL,
202
+
};
203
+
204
+
struct clk_imx8mp_audiomix_priv {
205
+
void __iomem *base;
206
+
u32 regs_save[ARRAY_SIZE(audiomix_regs)];
207
+
208
+
/* Must be last */
209
+
struct clk_hw_onecell_data clk_data;
210
+
};
211
+
212
+
static void clk_imx8mp_audiomix_save_restore(struct device *dev, bool save)
213
+
{
214
+
struct clk_imx8mp_audiomix_priv *priv = dev_get_drvdata(dev);
215
+
void __iomem *base = priv->base;
216
+
int i;
217
+
218
+
if (save) {
219
+
for (i = 0; i < ARRAY_SIZE(audiomix_regs); i++)
220
+
priv->regs_save[i] = readl(base + audiomix_regs[i]);
221
+
} else {
222
+
for (i = 0; i < ARRAY_SIZE(audiomix_regs); i++)
223
+
writel(priv->regs_save[i], base + audiomix_regs[i]);
224
+
}
225
+
}
226
+
193
227
static int clk_imx8mp_audiomix_probe(struct platform_device *pdev)
194
228
{
195
-
struct clk_hw_onecell_data *priv;
229
+
struct clk_imx8mp_audiomix_priv *priv;
230
+
struct clk_hw_onecell_data *clk_hw_data;
196
231
struct device *dev = &pdev->dev;
197
232
void __iomem *base;
198
233
struct clk_hw *hw;
199
-
int i;
234
+
int i, ret;
200
235
201
236
priv = devm_kzalloc(dev,
202
-
struct_size(priv, hws, IMX8MP_CLK_AUDIOMIX_END),
237
+
struct_size(priv, clk_data.hws, IMX8MP_CLK_AUDIOMIX_END),
203
238
GFP_KERNEL);
204
239
if (!priv)
205
240
return -ENOMEM;
206
241
207
-
priv->num = IMX8MP_CLK_AUDIOMIX_END;
242
+
clk_hw_data = &priv->clk_data;
243
+
clk_hw_data->num = IMX8MP_CLK_AUDIOMIX_END;
208
244
209
245
base = devm_platform_ioremap_resource(pdev, 0);
210
246
if (IS_ERR(base))
211
247
return PTR_ERR(base);
248
+
249
+
priv->base = base;
250
+
dev_set_drvdata(dev, priv);
251
+
252
+
/*
253
+
* pm_runtime_enable needs to be called before clk register.
254
+
* That is to make core->rpm_enabled to be true for clock
255
+
* usage.
256
+
*/
257
+
pm_runtime_get_noresume(dev);
258
+
pm_runtime_set_active(dev);
259
+
pm_runtime_enable(dev);
212
260
213
261
for (i = 0; i < ARRAY_SIZE(sels); i++) {
214
262
if (sels[i].num_parents == 1) {
···
280
216
0, NULL, NULL);
281
217
}
282
218
283
-
if (IS_ERR(hw))
284
-
return PTR_ERR(hw);
219
+
if (IS_ERR(hw)) {
220
+
ret = PTR_ERR(hw);
221
+
goto err_clk_register;
222
+
}
285
223
286
-
priv->hws[sels[i].clkid] = hw;
224
+
clk_hw_data->hws[sels[i].clkid] = hw;
287
225
}
288
226
289
227
/* SAI PLL */
···
294
228
ARRAY_SIZE(clk_imx8mp_audiomix_pll_parents),
295
229
CLK_SET_RATE_NO_REPARENT, base + SAI_PLL_GNRL_CTL,
296
230
0, 2, 0, NULL, NULL);
297
-
priv->hws[IMX8MP_CLK_AUDIOMIX_SAI_PLL_REF_SEL] = hw;
231
+
clk_hw_data->hws[IMX8MP_CLK_AUDIOMIX_SAI_PLL_REF_SEL] = hw;
298
232
299
233
hw = imx_dev_clk_hw_pll14xx(dev, "sai_pll", "sai_pll_ref_sel",
300
234
base + 0x400, &imx_1443x_pll);
301
-
if (IS_ERR(hw))
302
-
return PTR_ERR(hw);
303
-
priv->hws[IMX8MP_CLK_AUDIOMIX_SAI_PLL] = hw;
235
+
if (IS_ERR(hw)) {
236
+
ret = PTR_ERR(hw);
237
+
goto err_clk_register;
238
+
}
239
+
clk_hw_data->hws[IMX8MP_CLK_AUDIOMIX_SAI_PLL] = hw;
304
240
305
241
hw = devm_clk_hw_register_mux_parent_data_table(dev,
306
242
"sai_pll_bypass", clk_imx8mp_audiomix_pll_bypass_sels,
307
243
ARRAY_SIZE(clk_imx8mp_audiomix_pll_bypass_sels),
308
244
CLK_SET_RATE_NO_REPARENT | CLK_SET_RATE_PARENT,
309
245
base + SAI_PLL_GNRL_CTL, 16, 1, 0, NULL, NULL);
310
-
if (IS_ERR(hw))
311
-
return PTR_ERR(hw);
312
-
priv->hws[IMX8MP_CLK_AUDIOMIX_SAI_PLL_BYPASS] = hw;
246
+
if (IS_ERR(hw)) {
247
+
ret = PTR_ERR(hw);
248
+
goto err_clk_register;
249
+
}
250
+
251
+
clk_hw_data->hws[IMX8MP_CLK_AUDIOMIX_SAI_PLL_BYPASS] = hw;
313
252
314
253
hw = devm_clk_hw_register_gate(dev, "sai_pll_out", "sai_pll_bypass",
315
254
0, base + SAI_PLL_GNRL_CTL, 13,
316
255
0, NULL);
317
-
if (IS_ERR(hw))
318
-
return PTR_ERR(hw);
319
-
priv->hws[IMX8MP_CLK_AUDIOMIX_SAI_PLL_OUT] = hw;
256
+
if (IS_ERR(hw)) {
257
+
ret = PTR_ERR(hw);
258
+
goto err_clk_register;
259
+
}
260
+
clk_hw_data->hws[IMX8MP_CLK_AUDIOMIX_SAI_PLL_OUT] = hw;
320
261
321
262
hw = devm_clk_hw_register_fixed_factor(dev, "sai_pll_out_div2",
322
263
"sai_pll_out", 0, 1, 2);
323
-
if (IS_ERR(hw))
324
-
return PTR_ERR(hw);
264
+
if (IS_ERR(hw)) {
265
+
ret = PTR_ERR(hw);
266
+
goto err_clk_register;
267
+
}
325
268
326
-
return devm_of_clk_add_hw_provider(&pdev->dev, of_clk_hw_onecell_get,
327
-
priv);
269
+
ret = devm_of_clk_add_hw_provider(&pdev->dev, of_clk_hw_onecell_get,
270
+
clk_hw_data);
271
+
if (ret)
272
+
goto err_clk_register;
273
+
274
+
pm_runtime_put_sync(dev);
275
+
return 0;
276
+
277
+
err_clk_register:
278
+
pm_runtime_put_sync(dev);
279
+
pm_runtime_disable(dev);
280
+
return ret;
328
281
}
282
+
283
+
static void clk_imx8mp_audiomix_remove(struct platform_device *pdev)
284
+
{
285
+
pm_runtime_disable(&pdev->dev);
286
+
}
287
+
288
+
static int clk_imx8mp_audiomix_runtime_suspend(struct device *dev)
289
+
{
290
+
clk_imx8mp_audiomix_save_restore(dev, true);
291
+
292
+
return 0;
293
+
}
294
+
295
+
static int clk_imx8mp_audiomix_runtime_resume(struct device *dev)
296
+
{
297
+
clk_imx8mp_audiomix_save_restore(dev, false);
298
+
299
+
return 0;
300
+
}
301
+
302
+
static const struct dev_pm_ops clk_imx8mp_audiomix_pm_ops = {
303
+
RUNTIME_PM_OPS(clk_imx8mp_audiomix_runtime_suspend,
304
+
clk_imx8mp_audiomix_runtime_resume, NULL)
305
+
SET_NOIRQ_SYSTEM_SLEEP_PM_OPS(pm_runtime_force_suspend,
306
+
pm_runtime_force_resume)
307
+
};
329
308
330
309
static const struct of_device_id clk_imx8mp_audiomix_of_match[] = {
331
310
{ .compatible = "fsl,imx8mp-audio-blk-ctrl" },
···
380
269
381
270
static struct platform_driver clk_imx8mp_audiomix_driver = {
382
271
.probe = clk_imx8mp_audiomix_probe,
272
+
.remove_new = clk_imx8mp_audiomix_remove,
383
273
.driver = {
384
274
.name = "imx8mp-audio-blk-ctrl",
385
275
.of_match_table = clk_imx8mp_audiomix_of_match,
276
+
.pm = pm_ptr(&clk_imx8mp_audiomix_pm_ops),
386
277
},
387
278
};
388
279
+438
drivers/clk/imx/clk-imx95-blk-ctl.c
+438
drivers/clk/imx/clk-imx95-blk-ctl.c
···
1
+
// SPDX-License-Identifier: GPL-2.0
2
+
/*
3
+
* Copyright 2024 NXP
4
+
*/
5
+
6
+
#include <dt-bindings/clock/nxp,imx95-clock.h>
7
+
#include <linux/clk.h>
8
+
#include <linux/clk-provider.h>
9
+
#include <linux/pm_runtime.h>
10
+
#include <linux/debugfs.h>
11
+
#include <linux/device.h>
12
+
#include <linux/err.h>
13
+
#include <linux/io.h>
14
+
#include <linux/module.h>
15
+
#include <linux/of_address.h>
16
+
#include <linux/of_device.h>
17
+
#include <linux/of_platform.h>
18
+
#include <linux/platform_device.h>
19
+
#include <linux/regmap.h>
20
+
#include <linux/slab.h>
21
+
#include <linux/spinlock.h>
22
+
#include <linux/types.h>
23
+
24
+
enum {
25
+
CLK_GATE,
26
+
CLK_DIVIDER,
27
+
CLK_MUX,
28
+
};
29
+
30
+
struct imx95_blk_ctl {
31
+
struct device *dev;
32
+
spinlock_t lock;
33
+
struct clk *clk_apb;
34
+
35
+
void __iomem *base;
36
+
/* clock gate register */
37
+
u32 clk_reg_restore;
38
+
};
39
+
40
+
struct imx95_blk_ctl_clk_dev_data {
41
+
const char *name;
42
+
const char * const *parent_names;
43
+
u32 num_parents;
44
+
u32 reg;
45
+
u32 bit_idx;
46
+
u32 bit_width;
47
+
u32 clk_type;
48
+
u32 flags;
49
+
u32 flags2;
50
+
u32 type;
51
+
};
52
+
53
+
struct imx95_blk_ctl_dev_data {
54
+
const struct imx95_blk_ctl_clk_dev_data *clk_dev_data;
55
+
u32 num_clks;
56
+
bool rpm_enabled;
57
+
u32 clk_reg_offset;
58
+
};
59
+
60
+
static const struct imx95_blk_ctl_clk_dev_data vpublk_clk_dev_data[] = {
61
+
[IMX95_CLK_VPUBLK_WAVE] = {
62
+
.name = "vpublk_wave_vpu",
63
+
.parent_names = (const char *[]){ "vpu", },
64
+
.num_parents = 1,
65
+
.reg = 8,
66
+
.bit_idx = 0,
67
+
.type = CLK_GATE,
68
+
.flags = CLK_SET_RATE_PARENT,
69
+
.flags2 = CLK_GATE_SET_TO_DISABLE,
70
+
},
71
+
[IMX95_CLK_VPUBLK_JPEG_ENC] = {
72
+
.name = "vpublk_jpeg_enc",
73
+
.parent_names = (const char *[]){ "vpujpeg", },
74
+
.num_parents = 1,
75
+
.reg = 8,
76
+
.bit_idx = 1,
77
+
.type = CLK_GATE,
78
+
.flags = CLK_SET_RATE_PARENT,
79
+
.flags2 = CLK_GATE_SET_TO_DISABLE,
80
+
},
81
+
[IMX95_CLK_VPUBLK_JPEG_DEC] = {
82
+
.name = "vpublk_jpeg_dec",
83
+
.parent_names = (const char *[]){ "vpujpeg", },
84
+
.num_parents = 1,
85
+
.reg = 8,
86
+
.bit_idx = 2,
87
+
.type = CLK_GATE,
88
+
.flags = CLK_SET_RATE_PARENT,
89
+
.flags2 = CLK_GATE_SET_TO_DISABLE,
90
+
}
91
+
};
92
+
93
+
static const struct imx95_blk_ctl_dev_data vpublk_dev_data = {
94
+
.num_clks = ARRAY_SIZE(vpublk_clk_dev_data),
95
+
.clk_dev_data = vpublk_clk_dev_data,
96
+
.rpm_enabled = true,
97
+
.clk_reg_offset = 8,
98
+
};
99
+
100
+
static const struct imx95_blk_ctl_clk_dev_data camblk_clk_dev_data[] = {
101
+
[IMX95_CLK_CAMBLK_CSI2_FOR0] = {
102
+
.name = "camblk_csi2_for0",
103
+
.parent_names = (const char *[]){ "camisi", },
104
+
.num_parents = 1,
105
+
.reg = 0,
106
+
.bit_idx = 0,
107
+
.type = CLK_GATE,
108
+
.flags = CLK_SET_RATE_PARENT,
109
+
.flags2 = CLK_GATE_SET_TO_DISABLE,
110
+
},
111
+
[IMX95_CLK_CAMBLK_CSI2_FOR1] = {
112
+
.name = "camblk_csi2_for1",
113
+
.parent_names = (const char *[]){ "camisi", },
114
+
.num_parents = 1,
115
+
.reg = 0,
116
+
.bit_idx = 1,
117
+
.type = CLK_GATE,
118
+
.flags = CLK_SET_RATE_PARENT,
119
+
.flags2 = CLK_GATE_SET_TO_DISABLE,
120
+
},
121
+
[IMX95_CLK_CAMBLK_ISP_AXI] = {
122
+
.name = "camblk_isp_axi",
123
+
.parent_names = (const char *[]){ "camaxi", },
124
+
.num_parents = 1,
125
+
.reg = 0,
126
+
.bit_idx = 4,
127
+
.type = CLK_GATE,
128
+
.flags = CLK_SET_RATE_PARENT,
129
+
.flags2 = CLK_GATE_SET_TO_DISABLE,
130
+
},
131
+
[IMX95_CLK_CAMBLK_ISP_PIXEL] = {
132
+
.name = "camblk_isp_pixel",
133
+
.parent_names = (const char *[]){ "camisi", },
134
+
.num_parents = 1,
135
+
.reg = 0,
136
+
.bit_idx = 5,
137
+
.type = CLK_GATE,
138
+
.flags = CLK_SET_RATE_PARENT,
139
+
.flags2 = CLK_GATE_SET_TO_DISABLE,
140
+
},
141
+
[IMX95_CLK_CAMBLK_ISP] = {
142
+
.name = "camblk_isp",
143
+
.parent_names = (const char *[]){ "camisi", },
144
+
.num_parents = 1,
145
+
.reg = 0,
146
+
.bit_idx = 6,
147
+
.type = CLK_GATE,
148
+
.flags = CLK_SET_RATE_PARENT,
149
+
.flags2 = CLK_GATE_SET_TO_DISABLE,
150
+
}
151
+
};
152
+
153
+
static const struct imx95_blk_ctl_dev_data camblk_dev_data = {
154
+
.num_clks = ARRAY_SIZE(camblk_clk_dev_data),
155
+
.clk_dev_data = camblk_clk_dev_data,
156
+
.clk_reg_offset = 0,
157
+
};
158
+
159
+
static const struct imx95_blk_ctl_clk_dev_data lvds_clk_dev_data[] = {
160
+
[IMX95_CLK_DISPMIX_LVDS_PHY_DIV] = {
161
+
.name = "ldb_phy_div",
162
+
.parent_names = (const char *[]){ "ldbpll", },
163
+
.num_parents = 1,
164
+
.reg = 0,
165
+
.bit_idx = 0,
166
+
.bit_width = 1,
167
+
.type = CLK_DIVIDER,
168
+
.flags2 = CLK_DIVIDER_POWER_OF_TWO,
169
+
},
170
+
[IMX95_CLK_DISPMIX_LVDS_CH0_GATE] = {
171
+
.name = "lvds_ch0_gate",
172
+
.parent_names = (const char *[]){ "ldb_phy_div", },
173
+
.num_parents = 1,
174
+
.reg = 0,
175
+
.bit_idx = 1,
176
+
.bit_width = 1,
177
+
.type = CLK_GATE,
178
+
.flags = CLK_SET_RATE_PARENT,
179
+
.flags2 = CLK_GATE_SET_TO_DISABLE,
180
+
},
181
+
[IMX95_CLK_DISPMIX_LVDS_CH1_GATE] = {
182
+
.name = "lvds_ch1_gate",
183
+
.parent_names = (const char *[]){ "ldb_phy_div", },
184
+
.num_parents = 1,
185
+
.reg = 0,
186
+
.bit_idx = 2,
187
+
.bit_width = 1,
188
+
.type = CLK_GATE,
189
+
.flags = CLK_SET_RATE_PARENT,
190
+
.flags2 = CLK_GATE_SET_TO_DISABLE,
191
+
},
192
+
[IMX95_CLK_DISPMIX_PIX_DI0_GATE] = {
193
+
.name = "lvds_di0_gate",
194
+
.parent_names = (const char *[]){ "ldb_pll_div7", },
195
+
.num_parents = 1,
196
+
.reg = 0,
197
+
.bit_idx = 3,
198
+
.bit_width = 1,
199
+
.type = CLK_GATE,
200
+
.flags = CLK_SET_RATE_PARENT,
201
+
.flags2 = CLK_GATE_SET_TO_DISABLE,
202
+
},
203
+
[IMX95_CLK_DISPMIX_PIX_DI1_GATE] = {
204
+
.name = "lvds_di1_gate",
205
+
.parent_names = (const char *[]){ "ldb_pll_div7", },
206
+
.num_parents = 1,
207
+
.reg = 0,
208
+
.bit_idx = 4,
209
+
.bit_width = 1,
210
+
.type = CLK_GATE,
211
+
.flags = CLK_SET_RATE_PARENT,
212
+
.flags2 = CLK_GATE_SET_TO_DISABLE,
213
+
},
214
+
};
215
+
216
+
static const struct imx95_blk_ctl_dev_data lvds_csr_dev_data = {
217
+
.num_clks = ARRAY_SIZE(lvds_clk_dev_data),
218
+
.clk_dev_data = lvds_clk_dev_data,
219
+
.clk_reg_offset = 0,
220
+
};
221
+
222
+
static const struct imx95_blk_ctl_clk_dev_data dispmix_csr_clk_dev_data[] = {
223
+
[IMX95_CLK_DISPMIX_ENG0_SEL] = {
224
+
.name = "disp_engine0_sel",
225
+
.parent_names = (const char *[]){"videopll1", "dsi_pll", "ldb_pll_div7", },
226
+
.num_parents = 4,
227
+
.reg = 0,
228
+
.bit_idx = 0,
229
+
.bit_width = 2,
230
+
.type = CLK_MUX,
231
+
.flags = CLK_SET_RATE_NO_REPARENT | CLK_SET_RATE_PARENT,
232
+
},
233
+
[IMX95_CLK_DISPMIX_ENG1_SEL] = {
234
+
.name = "disp_engine1_sel",
235
+
.parent_names = (const char *[]){"videopll1", "dsi_pll", "ldb_pll_div7", },
236
+
.num_parents = 4,
237
+
.reg = 0,
238
+
.bit_idx = 2,
239
+
.bit_width = 2,
240
+
.type = CLK_MUX,
241
+
.flags = CLK_SET_RATE_NO_REPARENT | CLK_SET_RATE_PARENT,
242
+
}
243
+
};
244
+
245
+
static const struct imx95_blk_ctl_dev_data dispmix_csr_dev_data = {
246
+
.num_clks = ARRAY_SIZE(dispmix_csr_clk_dev_data),
247
+
.clk_dev_data = dispmix_csr_clk_dev_data,
248
+
.clk_reg_offset = 0,
249
+
};
250
+
251
+
static int imx95_bc_probe(struct platform_device *pdev)
252
+
{
253
+
struct device *dev = &pdev->dev;
254
+
const struct imx95_blk_ctl_dev_data *bc_data;
255
+
struct imx95_blk_ctl *bc;
256
+
struct clk_hw_onecell_data *clk_hw_data;
257
+
struct clk_hw **hws;
258
+
void __iomem *base;
259
+
int i, ret;
260
+
261
+
bc = devm_kzalloc(dev, sizeof(*bc), GFP_KERNEL);
262
+
if (!bc)
263
+
return -ENOMEM;
264
+
bc->dev = dev;
265
+
dev_set_drvdata(&pdev->dev, bc);
266
+
267
+
spin_lock_init(&bc->lock);
268
+
269
+
base = devm_platform_ioremap_resource(pdev, 0);
270
+
if (IS_ERR(base))
271
+
return PTR_ERR(base);
272
+
273
+
bc->base = base;
274
+
bc->clk_apb = devm_clk_get(dev, NULL);
275
+
if (IS_ERR(bc->clk_apb))
276
+
return dev_err_probe(dev, PTR_ERR(bc->clk_apb), "failed to get APB clock\n");
277
+
278
+
ret = clk_prepare_enable(bc->clk_apb);
279
+
if (ret) {
280
+
dev_err(dev, "failed to enable apb clock: %d\n", ret);
281
+
return ret;
282
+
}
283
+
284
+
bc_data = of_device_get_match_data(dev);
285
+
if (!bc_data)
286
+
return devm_of_platform_populate(dev);
287
+
288
+
clk_hw_data = devm_kzalloc(dev, struct_size(clk_hw_data, hws, bc_data->num_clks),
289
+
GFP_KERNEL);
290
+
if (!clk_hw_data)
291
+
return -ENOMEM;
292
+
293
+
if (bc_data->rpm_enabled)
294
+
pm_runtime_enable(&pdev->dev);
295
+
296
+
clk_hw_data->num = bc_data->num_clks;
297
+
hws = clk_hw_data->hws;
298
+
299
+
for (i = 0; i < bc_data->num_clks; i++) {
300
+
const struct imx95_blk_ctl_clk_dev_data *data = &bc_data->clk_dev_data[i];
301
+
void __iomem *reg = base + data->reg;
302
+
303
+
if (data->type == CLK_MUX) {
304
+
hws[i] = clk_hw_register_mux(dev, data->name, data->parent_names,
305
+
data->num_parents, data->flags, reg,
306
+
data->bit_idx, data->bit_width,
307
+
data->flags2, &bc->lock);
308
+
} else if (data->type == CLK_DIVIDER) {
309
+
hws[i] = clk_hw_register_divider(dev, data->name, data->parent_names[0],
310
+
data->flags, reg, data->bit_idx,
311
+
data->bit_width, data->flags2, &bc->lock);
312
+
} else {
313
+
hws[i] = clk_hw_register_gate(dev, data->name, data->parent_names[0],
314
+
data->flags, reg, data->bit_idx,
315
+
data->flags2, &bc->lock);
316
+
}
317
+
if (IS_ERR(hws[i])) {
318
+
ret = PTR_ERR(hws[i]);
319
+
dev_err(dev, "failed to register: %s:%d\n", data->name, ret);
320
+
goto cleanup;
321
+
}
322
+
}
323
+
324
+
ret = of_clk_add_hw_provider(dev->of_node, of_clk_hw_onecell_get, clk_hw_data);
325
+
if (ret)
326
+
goto cleanup;
327
+
328
+
ret = devm_of_platform_populate(dev);
329
+
if (ret) {
330
+
of_clk_del_provider(dev->of_node);
331
+
goto cleanup;
332
+
}
333
+
334
+
if (pm_runtime_enabled(bc->dev))
335
+
clk_disable_unprepare(bc->clk_apb);
336
+
337
+
return 0;
338
+
339
+
cleanup:
340
+
for (i = 0; i < bc_data->num_clks; i++) {
341
+
if (IS_ERR_OR_NULL(hws[i]))
342
+
continue;
343
+
clk_hw_unregister(hws[i]);
344
+
}
345
+
346
+
if (bc_data->rpm_enabled)
347
+
pm_runtime_disable(&pdev->dev);
348
+
349
+
return ret;
350
+
}
351
+
352
+
#ifdef CONFIG_PM
353
+
static int imx95_bc_runtime_suspend(struct device *dev)
354
+
{
355
+
struct imx95_blk_ctl *bc = dev_get_drvdata(dev);
356
+
357
+
clk_disable_unprepare(bc->clk_apb);
358
+
return 0;
359
+
}
360
+
361
+
static int imx95_bc_runtime_resume(struct device *dev)
362
+
{
363
+
struct imx95_blk_ctl *bc = dev_get_drvdata(dev);
364
+
365
+
return clk_prepare_enable(bc->clk_apb);
366
+
}
367
+
#endif
368
+
369
+
#ifdef CONFIG_PM_SLEEP
370
+
static int imx95_bc_suspend(struct device *dev)
371
+
{
372
+
struct imx95_blk_ctl *bc = dev_get_drvdata(dev);
373
+
const struct imx95_blk_ctl_dev_data *bc_data;
374
+
int ret;
375
+
376
+
bc_data = of_device_get_match_data(dev);
377
+
if (!bc_data)
378
+
return 0;
379
+
380
+
if (bc_data->rpm_enabled) {
381
+
ret = pm_runtime_get_sync(bc->dev);
382
+
if (ret < 0) {
383
+
pm_runtime_put_noidle(bc->dev);
384
+
return ret;
385
+
}
386
+
}
387
+
388
+
bc->clk_reg_restore = readl(bc->base + bc_data->clk_reg_offset);
389
+
390
+
return 0;
391
+
}
392
+
393
+
static int imx95_bc_resume(struct device *dev)
394
+
{
395
+
struct imx95_blk_ctl *bc = dev_get_drvdata(dev);
396
+
const struct imx95_blk_ctl_dev_data *bc_data;
397
+
398
+
bc_data = of_device_get_match_data(dev);
399
+
if (!bc_data)
400
+
return 0;
401
+
402
+
writel(bc->clk_reg_restore, bc->base + bc_data->clk_reg_offset);
403
+
404
+
if (bc_data->rpm_enabled)
405
+
pm_runtime_put(bc->dev);
406
+
407
+
return 0;
408
+
}
409
+
#endif
410
+
411
+
static const struct dev_pm_ops imx95_bc_pm_ops = {
412
+
SET_RUNTIME_PM_OPS(imx95_bc_runtime_suspend, imx95_bc_runtime_resume, NULL)
413
+
SET_SYSTEM_SLEEP_PM_OPS(imx95_bc_suspend, imx95_bc_resume)
414
+
};
415
+
416
+
static const struct of_device_id imx95_bc_of_match[] = {
417
+
{ .compatible = "nxp,imx95-camera-csr", .data = &camblk_dev_data },
418
+
{ .compatible = "nxp,imx95-display-master-csr", },
419
+
{ .compatible = "nxp,imx95-lvds-csr", .data = &lvds_csr_dev_data },
420
+
{ .compatible = "nxp,imx95-display-csr", .data = &dispmix_csr_dev_data },
421
+
{ .compatible = "nxp,imx95-vpu-csr", .data = &vpublk_dev_data },
422
+
{ /* Sentinel */ },
423
+
};
424
+
MODULE_DEVICE_TABLE(of, imx95_bc_of_match);
425
+
426
+
static struct platform_driver imx95_bc_driver = {
427
+
.probe = imx95_bc_probe,
428
+
.driver = {
429
+
.name = "imx95-blk-ctl",
430
+
.of_match_table = imx95_bc_of_match,
431
+
.pm = &imx95_bc_pm_ops,
432
+
},
433
+
};
434
+
module_platform_driver(imx95_bc_driver);
435
+
436
+
MODULE_DESCRIPTION("NXP i.MX95 blk ctl driver");
437
+
MODULE_AUTHOR("Peng Fan <peng.fan@nxp.com>");
438
+
MODULE_LICENSE("GPL");
+1
-1
drivers/clk/mediatek/clk-mt8365-mm.c
+1
-1
drivers/clk/mediatek/clk-mt8365-mm.c
···
53
53
GATE_MM0(CLK_MM_MM_DSI0, "mm_dsi0", "mm_sel", 17),
54
54
GATE_MM0(CLK_MM_MM_DISP_RDMA1, "mm_disp_rdma1", "mm_sel", 18),
55
55
GATE_MM0(CLK_MM_MM_MDP_RDMA1, "mm_mdp_rdma1", "mm_sel", 19),
56
-
GATE_MM0(CLK_MM_DPI0_DPI0, "mm_dpi0_dpi0", "vpll_dpix", 20),
56
+
GATE_MM0(CLK_MM_DPI0_DPI0, "mm_dpi0_dpi0", "dpi0_sel", 20),
57
57
GATE_MM0(CLK_MM_MM_FAKE, "mm_fake", "mm_sel", 21),
58
58
GATE_MM0(CLK_MM_MM_SMI_COMMON, "mm_smi_common", "mm_sel", 22),
59
59
GATE_MM0(CLK_MM_MM_SMI_LARB0, "mm_smi_larb0", "mm_sel", 23),
+1
-1
drivers/clk/mediatek/clk-pllfh.c
+1
-1
drivers/clk/mediatek/clk-pllfh.c
+5
drivers/clk/meson/Kconfig
+5
drivers/clk/meson/Kconfig
···
30
30
tristate
31
31
select COMMON_CLK_MESON_REGMAP
32
32
33
+
config COMMON_CLK_MESON_VCLK
34
+
tristate
35
+
select COMMON_CLK_MESON_REGMAP
36
+
33
37
config COMMON_CLK_MESON_CLKC_UTILS
34
38
tristate
35
39
···
144
140
select COMMON_CLK_MESON_EE_CLKC
145
141
select COMMON_CLK_MESON_CPU_DYNDIV
146
142
select COMMON_CLK_MESON_VID_PLL_DIV
143
+
select COMMON_CLK_MESON_VCLK
147
144
select MFD_SYSCON
148
145
help
149
146
Support for the clock controller on Amlogic S905D2, S905X2 and S905Y2
+1
drivers/clk/meson/Makefile
+1
drivers/clk/meson/Makefile
+1
drivers/clk/meson/a1-peripherals.c
+1
drivers/clk/meson/a1-peripherals.c
+1
drivers/clk/meson/a1-pll.c
+1
drivers/clk/meson/a1-pll.c
+1
-1
drivers/clk/meson/axg-aoclk.c
+1
-1
drivers/clk/meson/axg-aoclk.c
+1
-1
drivers/clk/meson/axg-audio.c
+1
-1
drivers/clk/meson/axg-audio.c
+1
-1
drivers/clk/meson/axg.c
+1
-1
drivers/clk/meson/axg.c
+1
-1
drivers/clk/meson/clk-cpu-dyndiv.c
+1
-1
drivers/clk/meson/clk-cpu-dyndiv.c
+1
-1
drivers/clk/meson/clk-dualdiv.c
+1
-1
drivers/clk/meson/clk-dualdiv.c
+1
-1
drivers/clk/meson/clk-mpll.c
+1
-1
drivers/clk/meson/clk-mpll.c
+1
-1
drivers/clk/meson/clk-phase.c
+1
-1
drivers/clk/meson/clk-phase.c
+3
-3
drivers/clk/meson/clk-pll.c
+3
-3
drivers/clk/meson/clk-pll.c
···
436
436
437
437
ret = meson_clk_pll_enable(hw);
438
438
if (ret) {
439
-
pr_warn("%s: pll did not lock, trying to restore old rate %lu\n",
440
-
__func__, old_rate);
439
+
pr_warn("%s: pll %s didn't lock, trying to set old rate %lu\n",
440
+
__func__, clk_hw_get_name(hw), old_rate);
441
441
/*
442
442
* FIXME: Do we really need/want this HACK ?
443
443
* It looks unsafe. what happens if the clock gets into a
···
486
486
MODULE_DESCRIPTION("Amlogic PLL driver");
487
487
MODULE_AUTHOR("Carlo Caione <carlo@endlessm.com>");
488
488
MODULE_AUTHOR("Jerome Brunet <jbrunet@baylibre.com>");
489
-
MODULE_LICENSE("GPL v2");
489
+
MODULE_LICENSE("GPL");
+1
-1
drivers/clk/meson/clk-regmap.c
+1
-1
drivers/clk/meson/clk-regmap.c
+1
-1
drivers/clk/meson/g12a-aoclk.c
+1
-1
drivers/clk/meson/g12a-aoclk.c
+57
-21
drivers/clk/meson/g12a.c
+57
-21
drivers/clk/meson/g12a.c
···
22
22
#include "clk-regmap.h"
23
23
#include "clk-cpu-dyndiv.h"
24
24
#include "vid-pll-div.h"
25
+
#include "vclk.h"
25
26
#include "meson-eeclk.h"
26
27
#include "g12a.h"
27
28
···
3166
3165
.ops = &clk_regmap_mux_ops,
3167
3166
.parent_hws = g12a_vclk_parent_hws,
3168
3167
.num_parents = ARRAY_SIZE(g12a_vclk_parent_hws),
3169
-
.flags = CLK_SET_RATE_NO_REPARENT | CLK_GET_RATE_NOCACHE,
3168
+
.flags = CLK_SET_RATE_NO_REPARENT,
3170
3169
},
3171
3170
};
3172
3171
···
3194
3193
.ops = &clk_regmap_gate_ops,
3195
3194
.parent_hws = (const struct clk_hw *[]) { &g12a_vclk2_sel.hw },
3196
3195
.num_parents = 1,
3197
-
.flags = CLK_SET_RATE_PARENT | CLK_IGNORE_UNUSED,
3198
3196
},
3199
3197
};
3200
3198
···
3215
3215
};
3216
3216
3217
3217
static struct clk_regmap g12a_vclk2_div = {
3218
-
.data = &(struct clk_regmap_div_data){
3219
-
.offset = HHI_VIID_CLK_DIV,
3220
-
.shift = 0,
3221
-
.width = 8,
3218
+
.data = &(struct meson_vclk_div_data){
3219
+
.div = {
3220
+
.reg_off = HHI_VIID_CLK_DIV,
3221
+
.shift = 0,
3222
+
.width = 8,
3223
+
},
3224
+
.enable = {
3225
+
.reg_off = HHI_VIID_CLK_DIV,
3226
+
.shift = 16,
3227
+
.width = 1,
3228
+
},
3229
+
.reset = {
3230
+
.reg_off = HHI_VIID_CLK_DIV,
3231
+
.shift = 17,
3232
+
.width = 1,
3233
+
},
3234
+
.flags = CLK_DIVIDER_ROUND_CLOSEST,
3222
3235
},
3223
3236
.hw.init = &(struct clk_init_data){
3224
3237
.name = "vclk2_div",
3225
-
.ops = &clk_regmap_divider_ops,
3238
+
.ops = &meson_vclk_div_ops,
3226
3239
.parent_hws = (const struct clk_hw *[]) {
3227
3240
&g12a_vclk2_input.hw
3228
3241
},
3229
3242
.num_parents = 1,
3230
-
.flags = CLK_GET_RATE_NOCACHE,
3243
+
.flags = CLK_SET_RATE_GATE,
3231
3244
},
3232
3245
};
3233
3246
···
3259
3246
};
3260
3247
3261
3248
static struct clk_regmap g12a_vclk2 = {
3262
-
.data = &(struct clk_regmap_gate_data){
3263
-
.offset = HHI_VIID_CLK_CNTL,
3264
-
.bit_idx = 19,
3249
+
.data = &(struct meson_vclk_gate_data){
3250
+
.enable = {
3251
+
.reg_off = HHI_VIID_CLK_CNTL,
3252
+
.shift = 19,
3253
+
.width = 1,
3254
+
},
3255
+
.reset = {
3256
+
.reg_off = HHI_VIID_CLK_CNTL,
3257
+
.shift = 15,
3258
+
.width = 1,
3259
+
},
3265
3260
},
3266
3261
.hw.init = &(struct clk_init_data) {
3267
3262
.name = "vclk2",
3268
-
.ops = &clk_regmap_gate_ops,
3263
+
.ops = &meson_vclk_gate_ops,
3269
3264
.parent_hws = (const struct clk_hw *[]) { &g12a_vclk2_div.hw },
3270
3265
.num_parents = 1,
3271
-
.flags = CLK_SET_RATE_PARENT | CLK_IGNORE_UNUSED,
3266
+
.flags = CLK_SET_RATE_PARENT,
3272
3267
},
3273
3268
};
3274
3269
···
3360
3339
.ops = &clk_regmap_gate_ops,
3361
3340
.parent_hws = (const struct clk_hw *[]) { &g12a_vclk2.hw },
3362
3341
.num_parents = 1,
3363
-
.flags = CLK_SET_RATE_PARENT | CLK_IGNORE_UNUSED,
3342
+
.flags = CLK_SET_RATE_PARENT,
3364
3343
},
3365
3344
};
3366
3345
···
3374
3353
.ops = &clk_regmap_gate_ops,
3375
3354
.parent_hws = (const struct clk_hw *[]) { &g12a_vclk2.hw },
3376
3355
.num_parents = 1,
3377
-
.flags = CLK_SET_RATE_PARENT | CLK_IGNORE_UNUSED,
3356
+
.flags = CLK_SET_RATE_PARENT,
3378
3357
},
3379
3358
};
3380
3359
···
3388
3367
.ops = &clk_regmap_gate_ops,
3389
3368
.parent_hws = (const struct clk_hw *[]) { &g12a_vclk2.hw },
3390
3369
.num_parents = 1,
3391
-
.flags = CLK_SET_RATE_PARENT | CLK_IGNORE_UNUSED,
3370
+
.flags = CLK_SET_RATE_PARENT,
3392
3371
},
3393
3372
};
3394
3373
···
3402
3381
.ops = &clk_regmap_gate_ops,
3403
3382
.parent_hws = (const struct clk_hw *[]) { &g12a_vclk2.hw },
3404
3383
.num_parents = 1,
3405
-
.flags = CLK_SET_RATE_PARENT | CLK_IGNORE_UNUSED,
3384
+
.flags = CLK_SET_RATE_PARENT,
3406
3385
},
3407
3386
};
3408
3387
···
3416
3395
.ops = &clk_regmap_gate_ops,
3417
3396
.parent_hws = (const struct clk_hw *[]) { &g12a_vclk2.hw },
3418
3397
.num_parents = 1,
3419
-
.flags = CLK_SET_RATE_PARENT | CLK_IGNORE_UNUSED,
3398
+
.flags = CLK_SET_RATE_PARENT,
3420
3399
},
3421
3400
};
3422
3401
···
3482
3461
&g12a_vclk2_div2_en.hw
3483
3462
},
3484
3463
.num_parents = 1,
3464
+
.flags = CLK_SET_RATE_PARENT,
3485
3465
},
3486
3466
};
3487
3467
···
3496
3474
&g12a_vclk2_div4_en.hw
3497
3475
},
3498
3476
.num_parents = 1,
3477
+
.flags = CLK_SET_RATE_PARENT,
3499
3478
},
3500
3479
};
3501
3480
···
3510
3487
&g12a_vclk2_div6_en.hw
3511
3488
},
3512
3489
.num_parents = 1,
3490
+
.flags = CLK_SET_RATE_PARENT,
3513
3491
},
3514
3492
};
3515
3493
···
3524
3500
&g12a_vclk2_div12_en.hw
3525
3501
},
3526
3502
.num_parents = 1,
3503
+
.flags = CLK_SET_RATE_PARENT,
3527
3504
},
3528
3505
};
3529
3506
···
3586
3561
.ops = &clk_regmap_mux_ops,
3587
3562
.parent_hws = g12a_cts_parent_hws,
3588
3563
.num_parents = ARRAY_SIZE(g12a_cts_parent_hws),
3589
-
.flags = CLK_SET_RATE_NO_REPARENT | CLK_GET_RATE_NOCACHE,
3564
+
.flags = CLK_SET_RATE_PARENT | CLK_SET_RATE_NO_REPARENT,
3590
3565
},
3591
3566
};
3592
3567
···
3742
3717
.ops = &clk_regmap_mux_ops,
3743
3718
.parent_hws = g12a_mipi_dsi_pxclk_parent_hws,
3744
3719
.num_parents = ARRAY_SIZE(g12a_mipi_dsi_pxclk_parent_hws),
3745
-
.flags = CLK_SET_RATE_NO_REPARENT,
3720
+
.flags = CLK_SET_RATE_NO_REPARENT | CLK_SET_RATE_PARENT,
3746
3721
},
3722
+
};
3723
+
3724
+
/*
3725
+
* FIXME: Force as bypass by forcing a single /1 table entry, and doensn't on boot value
3726
+
* when setting a clock whith this node in the clock path, but doesn't garantee the divider
3727
+
* is at /1 at boot until a rate is set.
3728
+
*/
3729
+
static const struct clk_div_table g12a_mipi_dsi_pxclk_div_table[] = {
3730
+
{ .val = 0, .div = 1 },
3731
+
{ /* sentinel */ },
3747
3732
};
3748
3733
3749
3734
static struct clk_regmap g12a_mipi_dsi_pxclk_div = {
···
3761
3726
.offset = HHI_MIPIDSI_PHY_CLK_CNTL,
3762
3727
.shift = 0,
3763
3728
.width = 7,
3729
+
.table = g12a_mipi_dsi_pxclk_div_table,
3764
3730
},
3765
3731
.hw.init = &(struct clk_init_data){
3766
3732
.name = "mipi_dsi_pxclk_div",
···
5614
5578
};
5615
5579
5616
5580
module_platform_driver(g12a_driver);
5617
-
MODULE_LICENSE("GPL v2");
5581
+
MODULE_LICENSE("GPL");
+1
-1
drivers/clk/meson/gxbb-aoclk.c
+1
-1
drivers/clk/meson/gxbb-aoclk.c
+1
-1
drivers/clk/meson/gxbb.c
+1
-1
drivers/clk/meson/gxbb.c
+1
-1
drivers/clk/meson/meson-aoclk.c
+1
-1
drivers/clk/meson/meson-aoclk.c
+1
-1
drivers/clk/meson/meson-eeclk.c
+1
-1
drivers/clk/meson/meson-eeclk.c
+2
drivers/clk/meson/s4-peripherals.c
+2
drivers/clk/meson/s4-peripherals.c
···
3751
3751
.reg_bits = 32,
3752
3752
.val_bits = 32,
3753
3753
.reg_stride = 4,
3754
+
.max_register = CLKCTRL_DEMOD_CLK_CTRL,
3754
3755
};
3755
3756
3756
3757
static struct meson_clk_hw_data s4_periphs_clks = {
···
3800
3799
},
3801
3800
{}
3802
3801
};
3802
+
MODULE_DEVICE_TABLE(of, clkc_match_table);
3803
3803
3804
3804
static struct platform_driver s4_driver = {
3805
3805
.probe = meson_s4_periphs_probe,
+2
drivers/clk/meson/s4-pll.c
+2
drivers/clk/meson/s4-pll.c
···
798
798
.reg_bits = 32,
799
799
.val_bits = 32,
800
800
.reg_stride = 4,
801
+
.max_register = ANACTRL_HDMIPLL_CTRL0,
801
802
};
802
803
803
804
static struct meson_clk_hw_data s4_pll_clks = {
···
854
853
},
855
854
{}
856
855
};
856
+
MODULE_DEVICE_TABLE(of, clkc_match_table);
857
857
858
858
static struct platform_driver s4_driver = {
859
859
.probe = meson_s4_pll_probe,
+1
-1
drivers/clk/meson/sclk-div.c
+1
-1
drivers/clk/meson/sclk-div.c
+141
drivers/clk/meson/vclk.c
+141
drivers/clk/meson/vclk.c
···
1
+
// SPDX-License-Identifier: GPL-2.0
2
+
/*
3
+
* Copyright (c) 2024 Neil Armstrong <neil.armstrong@linaro.org>
4
+
*/
5
+
6
+
#include <linux/module.h>
7
+
#include "vclk.h"
8
+
9
+
/* The VCLK gate has a supplementary reset bit to pulse after ungating */
10
+
11
+
static inline struct meson_vclk_gate_data *
12
+
clk_get_meson_vclk_gate_data(struct clk_regmap *clk)
13
+
{
14
+
return (struct meson_vclk_gate_data *)clk->data;
15
+
}
16
+
17
+
static int meson_vclk_gate_enable(struct clk_hw *hw)
18
+
{
19
+
struct clk_regmap *clk = to_clk_regmap(hw);
20
+
struct meson_vclk_gate_data *vclk = clk_get_meson_vclk_gate_data(clk);
21
+
22
+
meson_parm_write(clk->map, &vclk->enable, 1);
23
+
24
+
/* Do a reset pulse */
25
+
meson_parm_write(clk->map, &vclk->reset, 1);
26
+
meson_parm_write(clk->map, &vclk->reset, 0);
27
+
28
+
return 0;
29
+
}
30
+
31
+
static void meson_vclk_gate_disable(struct clk_hw *hw)
32
+
{
33
+
struct clk_regmap *clk = to_clk_regmap(hw);
34
+
struct meson_vclk_gate_data *vclk = clk_get_meson_vclk_gate_data(clk);
35
+
36
+
meson_parm_write(clk->map, &vclk->enable, 0);
37
+
}
38
+
39
+
static int meson_vclk_gate_is_enabled(struct clk_hw *hw)
40
+
{
41
+
struct clk_regmap *clk = to_clk_regmap(hw);
42
+
struct meson_vclk_gate_data *vclk = clk_get_meson_vclk_gate_data(clk);
43
+
44
+
return meson_parm_read(clk->map, &vclk->enable);
45
+
}
46
+
47
+
const struct clk_ops meson_vclk_gate_ops = {
48
+
.enable = meson_vclk_gate_enable,
49
+
.disable = meson_vclk_gate_disable,
50
+
.is_enabled = meson_vclk_gate_is_enabled,
51
+
};
52
+
EXPORT_SYMBOL_GPL(meson_vclk_gate_ops);
53
+
54
+
/* The VCLK Divider has supplementary reset & enable bits */
55
+
56
+
static inline struct meson_vclk_div_data *
57
+
clk_get_meson_vclk_div_data(struct clk_regmap *clk)
58
+
{
59
+
return (struct meson_vclk_div_data *)clk->data;
60
+
}
61
+
62
+
static unsigned long meson_vclk_div_recalc_rate(struct clk_hw *hw,
63
+
unsigned long prate)
64
+
{
65
+
struct clk_regmap *clk = to_clk_regmap(hw);
66
+
struct meson_vclk_div_data *vclk = clk_get_meson_vclk_div_data(clk);
67
+
68
+
return divider_recalc_rate(hw, prate, meson_parm_read(clk->map, &vclk->div),
69
+
vclk->table, vclk->flags, vclk->div.width);
70
+
}
71
+
72
+
static int meson_vclk_div_determine_rate(struct clk_hw *hw,
73
+
struct clk_rate_request *req)
74
+
{
75
+
struct clk_regmap *clk = to_clk_regmap(hw);
76
+
struct meson_vclk_div_data *vclk = clk_get_meson_vclk_div_data(clk);
77
+
78
+
return divider_determine_rate(hw, req, vclk->table, vclk->div.width,
79
+
vclk->flags);
80
+
}
81
+
82
+
static int meson_vclk_div_set_rate(struct clk_hw *hw, unsigned long rate,
83
+
unsigned long parent_rate)
84
+
{
85
+
struct clk_regmap *clk = to_clk_regmap(hw);
86
+
struct meson_vclk_div_data *vclk = clk_get_meson_vclk_div_data(clk);
87
+
int ret;
88
+
89
+
ret = divider_get_val(rate, parent_rate, vclk->table, vclk->div.width,
90
+
vclk->flags);
91
+
if (ret < 0)
92
+
return ret;
93
+
94
+
meson_parm_write(clk->map, &vclk->div, ret);
95
+
96
+
return 0;
97
+
};
98
+
99
+
static int meson_vclk_div_enable(struct clk_hw *hw)
100
+
{
101
+
struct clk_regmap *clk = to_clk_regmap(hw);
102
+
struct meson_vclk_div_data *vclk = clk_get_meson_vclk_div_data(clk);
103
+
104
+
/* Unreset the divider when ungating */
105
+
meson_parm_write(clk->map, &vclk->reset, 0);
106
+
meson_parm_write(clk->map, &vclk->enable, 1);
107
+
108
+
return 0;
109
+
}
110
+
111
+
static void meson_vclk_div_disable(struct clk_hw *hw)
112
+
{
113
+
struct clk_regmap *clk = to_clk_regmap(hw);
114
+
struct meson_vclk_div_data *vclk = clk_get_meson_vclk_div_data(clk);
115
+
116
+
/* Reset the divider when gating */
117
+
meson_parm_write(clk->map, &vclk->enable, 0);
118
+
meson_parm_write(clk->map, &vclk->reset, 1);
119
+
}
120
+
121
+
static int meson_vclk_div_is_enabled(struct clk_hw *hw)
122
+
{
123
+
struct clk_regmap *clk = to_clk_regmap(hw);
124
+
struct meson_vclk_div_data *vclk = clk_get_meson_vclk_div_data(clk);
125
+
126
+
return meson_parm_read(clk->map, &vclk->enable);
127
+
}
128
+
129
+
const struct clk_ops meson_vclk_div_ops = {
130
+
.recalc_rate = meson_vclk_div_recalc_rate,
131
+
.determine_rate = meson_vclk_div_determine_rate,
132
+
.set_rate = meson_vclk_div_set_rate,
133
+
.enable = meson_vclk_div_enable,
134
+
.disable = meson_vclk_div_disable,
135
+
.is_enabled = meson_vclk_div_is_enabled,
136
+
};
137
+
EXPORT_SYMBOL_GPL(meson_vclk_div_ops);
138
+
139
+
MODULE_DESCRIPTION("Amlogic vclk clock driver");
140
+
MODULE_AUTHOR("Neil Armstrong <neil.armstrong@linaro.org>");
141
+
MODULE_LICENSE("GPL");
+51
drivers/clk/meson/vclk.h
+51
drivers/clk/meson/vclk.h
···
1
+
/* SPDX-License-Identifier: GPL-2.0 */
2
+
/*
3
+
* Copyright (c) 2024 Neil Armstrong <neil.armstrong@linaro.org>
4
+
*/
5
+
6
+
#ifndef __VCLK_H
7
+
#define __VCLK_H
8
+
9
+
#include "clk-regmap.h"
10
+
#include "parm.h"
11
+
12
+
/**
13
+
* struct meson_vclk_gate_data - vclk_gate regmap backed specific data
14
+
*
15
+
* @enable: vclk enable field
16
+
* @reset: vclk reset field
17
+
* @flags: hardware-specific flags
18
+
*
19
+
* Flags:
20
+
* Same as clk_gate except CLK_GATE_HIWORD_MASK which is ignored
21
+
*/
22
+
struct meson_vclk_gate_data {
23
+
struct parm enable;
24
+
struct parm reset;
25
+
u8 flags;
26
+
};
27
+
28
+
extern const struct clk_ops meson_vclk_gate_ops;
29
+
30
+
/**
31
+
* struct meson_vclk_div_data - vclk_div regmap back specific data
32
+
*
33
+
* @div: divider field
34
+
* @enable: vclk divider enable field
35
+
* @reset: vclk divider reset field
36
+
* @table: array of value/divider pairs, last entry should have div = 0
37
+
*
38
+
* Flags:
39
+
* Same as clk_divider except CLK_DIVIDER_HIWORD_MASK which is ignored
40
+
*/
41
+
struct meson_vclk_div_data {
42
+
struct parm div;
43
+
struct parm enable;
44
+
struct parm reset;
45
+
const struct clk_div_table *table;
46
+
u8 flags;
47
+
};
48
+
49
+
extern const struct clk_ops meson_vclk_div_ops;
50
+
51
+
#endif /* __VCLK_H */
+1
-1
drivers/clk/meson/vid-pll-div.c
+1
-1
drivers/clk/meson/vid-pll-div.c
+2
-90
drivers/clk/microchip/clk-mpfs.c
+2
-90
drivers/clk/microchip/clk-mpfs.c
···
4
4
*
5
5
* Copyright (C) 2020-2022 Microchip Technology Inc. All rights reserved.
6
6
*/
7
-
#include <linux/auxiliary_bus.h>
8
7
#include <linux/clk-provider.h>
9
8
#include <linux/io.h>
10
9
#include <linux/module.h>
11
10
#include <linux/platform_device.h>
12
-
#include <linux/slab.h>
13
11
#include <dt-bindings/clock/microchip,mpfs-clock.h>
14
12
#include <soc/microchip/mpfs.h>
15
13
···
359
361
return 0;
360
362
}
361
363
362
-
/*
363
-
* Peripheral clock resets
364
-
*/
365
-
366
-
#if IS_ENABLED(CONFIG_RESET_CONTROLLER)
367
-
368
-
u32 mpfs_reset_read(struct device *dev)
369
-
{
370
-
struct mpfs_clock_data *clock_data = dev_get_drvdata(dev->parent);
371
-
372
-
return readl_relaxed(clock_data->base + REG_SUBBLK_RESET_CR);
373
-
}
374
-
EXPORT_SYMBOL_NS_GPL(mpfs_reset_read, MCHP_CLK_MPFS);
375
-
376
-
void mpfs_reset_write(struct device *dev, u32 val)
377
-
{
378
-
struct mpfs_clock_data *clock_data = dev_get_drvdata(dev->parent);
379
-
380
-
writel_relaxed(val, clock_data->base + REG_SUBBLK_RESET_CR);
381
-
}
382
-
EXPORT_SYMBOL_NS_GPL(mpfs_reset_write, MCHP_CLK_MPFS);
383
-
384
-
static void mpfs_reset_unregister_adev(void *_adev)
385
-
{
386
-
struct auxiliary_device *adev = _adev;
387
-
388
-
auxiliary_device_delete(adev);
389
-
auxiliary_device_uninit(adev);
390
-
}
391
-
392
-
static void mpfs_reset_adev_release(struct device *dev)
393
-
{
394
-
struct auxiliary_device *adev = to_auxiliary_dev(dev);
395
-
396
-
kfree(adev);
397
-
}
398
-
399
-
static struct auxiliary_device *mpfs_reset_adev_alloc(struct mpfs_clock_data *clk_data)
400
-
{
401
-
struct auxiliary_device *adev;
402
-
int ret;
403
-
404
-
adev = kzalloc(sizeof(*adev), GFP_KERNEL);
405
-
if (!adev)
406
-
return ERR_PTR(-ENOMEM);
407
-
408
-
adev->name = "reset-mpfs";
409
-
adev->dev.parent = clk_data->dev;
410
-
adev->dev.release = mpfs_reset_adev_release;
411
-
adev->id = 666u;
412
-
413
-
ret = auxiliary_device_init(adev);
414
-
if (ret) {
415
-
kfree(adev);
416
-
return ERR_PTR(ret);
417
-
}
418
-
419
-
return adev;
420
-
}
421
-
422
-
static int mpfs_reset_controller_register(struct mpfs_clock_data *clk_data)
423
-
{
424
-
struct auxiliary_device *adev;
425
-
int ret;
426
-
427
-
adev = mpfs_reset_adev_alloc(clk_data);
428
-
if (IS_ERR(adev))
429
-
return PTR_ERR(adev);
430
-
431
-
ret = auxiliary_device_add(adev);
432
-
if (ret) {
433
-
auxiliary_device_uninit(adev);
434
-
return ret;
435
-
}
436
-
437
-
return devm_add_action_or_reset(clk_data->dev, mpfs_reset_unregister_adev, adev);
438
-
}
439
-
440
-
#else /* !CONFIG_RESET_CONTROLLER */
441
-
442
-
static int mpfs_reset_controller_register(struct mpfs_clock_data *clk_data)
443
-
{
444
-
return 0;
445
-
}
446
-
447
-
#endif /* !CONFIG_RESET_CONTROLLER */
448
-
449
364
static int mpfs_clk_probe(struct platform_device *pdev)
450
365
{
451
366
struct device *dev = &pdev->dev;
···
410
499
if (ret)
411
500
return ret;
412
501
413
-
return mpfs_reset_controller_register(clk_data);
502
+
return mpfs_reset_controller_register(dev, clk_data->base + REG_SUBBLK_RESET_CR);
414
503
}
415
504
416
505
static const struct of_device_id mpfs_clk_of_match_table[] = {
···
443
532
MODULE_AUTHOR("Padmarao Begari <padmarao.begari@microchip.com>");
444
533
MODULE_AUTHOR("Daire McNamara <daire.mcnamara@microchip.com>");
445
534
MODULE_AUTHOR("Conor Dooley <conor.dooley@microchip.com>");
535
+
MODULE_IMPORT_NS(MCHP_CLK_MPFS);
-1
drivers/clk/nxp/clk-lpc18xx-cgu.c
-1
drivers/clk/nxp/clk-lpc18xx-cgu.c
+2
drivers/clk/qcom/Kconfig
+2
drivers/clk/qcom/Kconfig
···
474
474
475
475
config SC_CAMCC_8280XP
476
476
tristate "SC8280XP Camera Clock Controller"
477
+
depends on ARM64 || COMPILE_TEST
477
478
select SC_GCC_8280XP
478
479
help
479
480
Support for the camera clock controller on Qualcomm Technologies, Inc
···
1095
1094
1096
1095
config SM_GPUCC_8650
1097
1096
tristate "SM8650 Graphics Clock Controller"
1097
+
depends on ARM64 || COMPILE_TEST
1098
1098
select SM_GCC_8650
1099
1099
help
1100
1100
Support for the graphics clock controller on SM8650 devices.
+37
-42
drivers/clk/qcom/apss-ipq-pll.c
+37
-42
drivers/clk/qcom/apss-ipq-pll.c
···
8
8
9
9
#include "clk-alpha-pll.h"
10
10
11
-
/*
12
-
* Even though APSS PLL type is of existing one (like Huayra), its offsets
13
-
* are different from the one mentioned in the clk-alpha-pll.c, since the
14
-
* PLL is specific to APSS, so lets the define the same.
15
-
*/
16
-
static const u8 ipq_pll_offsets[][PLL_OFF_MAX_REGS] = {
17
-
[CLK_ALPHA_PLL_TYPE_HUAYRA] = {
18
-
[PLL_OFF_L_VAL] = 0x08,
19
-
[PLL_OFF_ALPHA_VAL] = 0x10,
20
-
[PLL_OFF_USER_CTL] = 0x18,
21
-
[PLL_OFF_CONFIG_CTL] = 0x20,
22
-
[PLL_OFF_CONFIG_CTL_U] = 0x24,
23
-
[PLL_OFF_STATUS] = 0x28,
24
-
[PLL_OFF_TEST_CTL] = 0x30,
25
-
[PLL_OFF_TEST_CTL_U] = 0x34,
26
-
},
27
-
[CLK_ALPHA_PLL_TYPE_STROMER_PLUS] = {
28
-
[PLL_OFF_L_VAL] = 0x08,
29
-
[PLL_OFF_ALPHA_VAL] = 0x10,
30
-
[PLL_OFF_ALPHA_VAL_U] = 0x14,
31
-
[PLL_OFF_USER_CTL] = 0x18,
32
-
[PLL_OFF_USER_CTL_U] = 0x1c,
33
-
[PLL_OFF_CONFIG_CTL] = 0x20,
34
-
[PLL_OFF_STATUS] = 0x28,
35
-
[PLL_OFF_TEST_CTL] = 0x30,
36
-
[PLL_OFF_TEST_CTL_U] = 0x34,
37
-
},
38
-
};
39
-
40
11
static struct clk_alpha_pll ipq_pll_huayra = {
41
12
.offset = 0x0,
42
-
.regs = ipq_pll_offsets[CLK_ALPHA_PLL_TYPE_HUAYRA],
13
+
.regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_HUAYRA_APSS],
43
14
.flags = SUPPORTS_DYNAMIC_UPDATE,
44
15
.clkr = {
45
16
.enable_reg = 0x0,
46
17
.enable_mask = BIT(0),
47
-
.hw.init = &(struct clk_init_data){
18
+
.hw.init = &(const struct clk_init_data) {
48
19
.name = "a53pll",
49
20
.parent_data = &(const struct clk_parent_data) {
50
21
.fw_name = "xo",
···
26
55
},
27
56
};
28
57
29
-
static struct clk_alpha_pll ipq_pll_stromer_plus = {
58
+
static struct clk_alpha_pll ipq_pll_stromer = {
30
59
.offset = 0x0,
31
-
.regs = ipq_pll_offsets[CLK_ALPHA_PLL_TYPE_STROMER_PLUS],
60
+
.regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_STROMER],
32
61
.flags = SUPPORTS_DYNAMIC_UPDATE,
33
62
.clkr = {
34
63
.enable_reg = 0x0,
35
64
.enable_mask = BIT(0),
36
-
.hw.init = &(struct clk_init_data){
65
+
.hw.init = &(const struct clk_init_data) {
66
+
.name = "a53pll",
67
+
.parent_data = &(const struct clk_parent_data) {
68
+
.fw_name = "xo",
69
+
},
70
+
.num_parents = 1,
71
+
.ops = &clk_alpha_pll_stromer_ops,
72
+
},
73
+
},
74
+
};
75
+
76
+
static struct clk_alpha_pll ipq_pll_stromer_plus = {
77
+
.offset = 0x0,
78
+
/*
79
+
* The register offsets of the Stromer Plus PLL used in IPQ5332
80
+
* are the same as the Stromer PLL's offsets.
81
+
*/
82
+
.regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_STROMER],
83
+
.flags = SUPPORTS_DYNAMIC_UPDATE,
84
+
.clkr = {
85
+
.enable_reg = 0x0,
86
+
.enable_mask = BIT(0),
87
+
.hw.init = &(const struct clk_init_data) {
37
88
.name = "a53pll",
38
89
.parent_data = &(const struct clk_parent_data) {
39
90
.fw_name = "xo",
···
66
73
},
67
74
};
68
75
76
+
/* 1.008 GHz configuration */
69
77
static const struct alpha_pll_config ipq5018_pll_config = {
70
-
.l = 0x32,
78
+
.l = 0x2a,
71
79
.config_ctl_val = 0x4001075b,
72
80
.config_ctl_hi_val = 0x304,
73
81
.main_output_mask = BIT(0),
···
138
144
};
139
145
140
146
static const struct apss_pll_data ipq5018_pll_data = {
141
-
.pll_type = CLK_ALPHA_PLL_TYPE_STROMER_PLUS,
142
-
.pll = &ipq_pll_stromer_plus,
147
+
.pll_type = CLK_ALPHA_PLL_TYPE_STROMER,
148
+
.pll = &ipq_pll_stromer,
143
149
.pll_config = &ipq5018_pll_config,
144
150
};
145
151
146
-
static struct apss_pll_data ipq5332_pll_data = {
152
+
static const struct apss_pll_data ipq5332_pll_data = {
147
153
.pll_type = CLK_ALPHA_PLL_TYPE_STROMER_PLUS,
148
154
.pll = &ipq_pll_stromer_plus,
149
155
.pll_config = &ipq5332_pll_config,
150
156
};
151
157
152
-
static struct apss_pll_data ipq8074_pll_data = {
158
+
static const struct apss_pll_data ipq8074_pll_data = {
153
159
.pll_type = CLK_ALPHA_PLL_TYPE_HUAYRA,
154
160
.pll = &ipq_pll_huayra,
155
161
.pll_config = &ipq8074_pll_config,
156
162
};
157
163
158
-
static struct apss_pll_data ipq6018_pll_data = {
164
+
static const struct apss_pll_data ipq6018_pll_data = {
159
165
.pll_type = CLK_ALPHA_PLL_TYPE_HUAYRA,
160
166
.pll = &ipq_pll_huayra,
161
167
.pll_config = &ipq6018_pll_config,
162
168
};
163
169
164
-
static struct apss_pll_data ipq9574_pll_data = {
170
+
static const struct apss_pll_data ipq9574_pll_data = {
165
171
.pll_type = CLK_ALPHA_PLL_TYPE_HUAYRA,
166
172
.pll = &ipq_pll_huayra,
167
173
.pll_config = &ipq9574_pll_config,
···
197
203
198
204
if (data->pll_type == CLK_ALPHA_PLL_TYPE_HUAYRA)
199
205
clk_alpha_pll_configure(data->pll, regmap, data->pll_config);
200
-
else if (data->pll_type == CLK_ALPHA_PLL_TYPE_STROMER_PLUS)
206
+
else if (data->pll_type == CLK_ALPHA_PLL_TYPE_STROMER ||
207
+
data->pll_type == CLK_ALPHA_PLL_TYPE_STROMER_PLUS)
201
208
clk_stromer_pll_configure(data->pll, regmap, data->pll_config);
202
209
203
210
ret = devm_clk_register_regmap(dev, &data->pll->clkr);
+22
-2
drivers/clk/qcom/clk-alpha-pll.c
+22
-2
drivers/clk/qcom/clk-alpha-pll.c
···
83
83
[PLL_OFF_TEST_CTL_U] = 0x20,
84
84
[PLL_OFF_STATUS] = 0x24,
85
85
},
86
+
[CLK_ALPHA_PLL_TYPE_HUAYRA_APSS] = {
87
+
[PLL_OFF_L_VAL] = 0x08,
88
+
[PLL_OFF_ALPHA_VAL] = 0x10,
89
+
[PLL_OFF_USER_CTL] = 0x18,
90
+
[PLL_OFF_CONFIG_CTL] = 0x20,
91
+
[PLL_OFF_CONFIG_CTL_U] = 0x24,
92
+
[PLL_OFF_STATUS] = 0x28,
93
+
[PLL_OFF_TEST_CTL] = 0x30,
94
+
[PLL_OFF_TEST_CTL_U] = 0x34,
95
+
},
86
96
[CLK_ALPHA_PLL_TYPE_BRAMMO] = {
87
97
[PLL_OFF_L_VAL] = 0x04,
88
98
[PLL_OFF_ALPHA_VAL] = 0x08,
···
223
213
[PLL_OFF_USER_CTL] = 0x18,
224
214
[PLL_OFF_USER_CTL_U] = 0x1c,
225
215
[PLL_OFF_CONFIG_CTL] = 0x20,
226
-
[PLL_OFF_CONFIG_CTL_U] = 0xff,
216
+
[PLL_OFF_STATUS] = 0x28,
227
217
[PLL_OFF_TEST_CTL] = 0x30,
228
218
[PLL_OFF_TEST_CTL_U] = 0x34,
229
-
[PLL_OFF_STATUS] = 0x28,
230
219
},
231
220
[CLK_ALPHA_PLL_TYPE_STROMER_PLUS] = {
232
221
[PLL_OFF_L_VAL] = 0x04,
···
2123
2114
{
2124
2115
u32 lval = config->l;
2125
2116
2117
+
/*
2118
+
* If the bootloader left the PLL enabled it's likely that there are
2119
+
* RCGs that will lock up if we disable the PLL below.
2120
+
*/
2121
+
if (trion_pll_is_enabled(pll, regmap)) {
2122
+
pr_debug("Lucid Evo PLL is already enabled, skipping configuration\n");
2123
+
return;
2124
+
}
2125
+
2126
2126
lval |= TRION_PLL_CAL_VAL << LUCID_EVO_PLL_CAL_L_VAL_SHIFT;
2127
2127
clk_alpha_pll_write_config(regmap, PLL_L_VAL(pll), lval);
2128
2128
clk_alpha_pll_write_config(regmap, PLL_ALPHA_VAL(pll), config->alpha);
···
2508
2490
rate = alpha_pll_round_rate(rate, prate, &l, &a, ALPHA_REG_BITWIDTH);
2509
2491
2510
2492
regmap_write(pll->clkr.regmap, PLL_L_VAL(pll), l);
2493
+
2494
+
a <<= ALPHA_REG_BITWIDTH - ALPHA_BITWIDTH;
2511
2495
regmap_write(pll->clkr.regmap, PLL_ALPHA_VAL(pll), a);
2512
2496
regmap_write(pll->clkr.regmap, PLL_ALPHA_VAL_U(pll),
2513
2497
a >> ALPHA_BITWIDTH);
+4
-1
drivers/clk/qcom/clk-alpha-pll.h
+4
-1
drivers/clk/qcom/clk-alpha-pll.h
···
15
15
enum {
16
16
CLK_ALPHA_PLL_TYPE_DEFAULT,
17
17
CLK_ALPHA_PLL_TYPE_HUAYRA,
18
+
CLK_ALPHA_PLL_TYPE_HUAYRA_APSS,
18
19
CLK_ALPHA_PLL_TYPE_BRAMMO,
19
20
CLK_ALPHA_PLL_TYPE_FABIA,
20
21
CLK_ALPHA_PLL_TYPE_TRION,
···
74
73
/**
75
74
* struct clk_alpha_pll - phase locked loop (PLL)
76
75
* @offset: base address of registers
77
-
* @vco_table: array of VCO settings
78
76
* @regs: alpha pll register map (see @clk_alpha_pll_regs)
77
+
* @vco_table: array of VCO settings
78
+
* @num_vco: number of VCO settings in @vco_table
79
+
* @flags: bitmask to indicate features supported by the hardware
79
80
* @clkr: regmap clock handle
80
81
*/
81
82
struct clk_alpha_pll {
+1
-12
drivers/clk/qcom/clk-cbf-8996.c
+1
-12
drivers/clk/qcom/clk-cbf-8996.c
···
41
41
42
42
#define CBF_PLL_OFFSET 0xf000
43
43
44
-
static const u8 cbf_pll_regs[PLL_OFF_MAX_REGS] = {
45
-
[PLL_OFF_L_VAL] = 0x08,
46
-
[PLL_OFF_ALPHA_VAL] = 0x10,
47
-
[PLL_OFF_USER_CTL] = 0x18,
48
-
[PLL_OFF_CONFIG_CTL] = 0x20,
49
-
[PLL_OFF_CONFIG_CTL_U] = 0x24,
50
-
[PLL_OFF_TEST_CTL] = 0x30,
51
-
[PLL_OFF_TEST_CTL_U] = 0x34,
52
-
[PLL_OFF_STATUS] = 0x28,
53
-
};
54
-
55
44
static struct alpha_pll_config cbfpll_config = {
56
45
.l = 72,
57
46
.config_ctl_val = 0x200d4828,
···
56
67
57
68
static struct clk_alpha_pll cbf_pll = {
58
69
.offset = CBF_PLL_OFFSET,
59
-
.regs = cbf_pll_regs,
70
+
.regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_HUAYRA_APSS],
60
71
.flags = SUPPORTS_DYNAMIC_UPDATE | SUPPORTS_FSM_MODE,
61
72
.clkr.hw.init = &(struct clk_init_data){
62
73
.name = "cbf_pll",
+23
-1
drivers/clk/qcom/clk-rcg.h
+23
-1
drivers/clk/qcom/clk-rcg.h
···
17
17
u16 n;
18
18
};
19
19
20
+
#define C(s, h, m, n) { (s), (2 * (h) - 1), (m), (n) }
21
+
#define FM(f, confs) { (f), ARRAY_SIZE(confs), (confs) }
22
+
#define FMS(f, s, h, m, n) { (f), 1, (const struct freq_conf []){ C(s, h, m, n) } }
23
+
24
+
struct freq_conf {
25
+
u8 src;
26
+
u8 pre_div;
27
+
u16 m;
28
+
u16 n;
29
+
};
30
+
31
+
struct freq_multi_tbl {
32
+
unsigned long freq;
33
+
size_t num_confs;
34
+
const struct freq_conf *confs;
35
+
};
36
+
20
37
/**
21
38
* struct mn - M/N:D counter
22
39
* @mnctr_en_bit: bit to enable mn counter
···
155
138
* @safe_src_index: safe src index value
156
139
* @parent_map: map from software's parent index to hardware's src_sel field
157
140
* @freq_tbl: frequency table
141
+
* @freq_multi_tbl: frequency table for clocks reachable with multiple RCGs conf
158
142
* @clkr: regmap clock handle
159
143
* @cfg_off: defines the cfg register offset from the CMD_RCGR + CFG_REG
160
144
* @parked_cfg: cached value of the CFG register for parked RCGs
···
167
149
u8 hid_width;
168
150
u8 safe_src_index;
169
151
const struct parent_map *parent_map;
170
-
const struct freq_tbl *freq_tbl;
152
+
union {
153
+
const struct freq_tbl *freq_tbl;
154
+
const struct freq_multi_tbl *freq_multi_tbl;
155
+
};
171
156
struct clk_regmap clkr;
172
157
u8 cfg_off;
173
158
u32 parked_cfg;
···
190
169
191
170
extern const struct clk_ops clk_rcg2_ops;
192
171
extern const struct clk_ops clk_rcg2_floor_ops;
172
+
extern const struct clk_ops clk_rcg2_fm_ops;
193
173
extern const struct clk_ops clk_rcg2_mux_closest_ops;
194
174
extern const struct clk_ops clk_edp_pixel_ops;
195
175
extern const struct clk_ops clk_byte_ops;
+166
drivers/clk/qcom/clk-rcg2.c
+166
drivers/clk/qcom/clk-rcg2.c
···
260
260
return 0;
261
261
}
262
262
263
+
static const struct freq_conf *
264
+
__clk_rcg2_select_conf(struct clk_hw *hw, const struct freq_multi_tbl *f,
265
+
unsigned long req_rate)
266
+
{
267
+
unsigned long rate_diff, best_rate_diff = ULONG_MAX;
268
+
const struct freq_conf *conf, *best_conf = NULL;
269
+
struct clk_rcg2 *rcg = to_clk_rcg2(hw);
270
+
const char *name = clk_hw_get_name(hw);
271
+
unsigned long parent_rate, rate;
272
+
struct clk_hw *p;
273
+
int index, i;
274
+
275
+
/* Exit early if only one config is defined */
276
+
if (f->num_confs == 1) {
277
+
best_conf = f->confs;
278
+
goto exit;
279
+
}
280
+
281
+
/* Search in each provided config the one that is near the wanted rate */
282
+
for (i = 0, conf = f->confs; i < f->num_confs; i++, conf++) {
283
+
index = qcom_find_src_index(hw, rcg->parent_map, conf->src);
284
+
if (index < 0)
285
+
continue;
286
+
287
+
p = clk_hw_get_parent_by_index(hw, index);
288
+
if (!p)
289
+
continue;
290
+
291
+
parent_rate = clk_hw_get_rate(p);
292
+
rate = calc_rate(parent_rate, conf->n, conf->m, conf->n, conf->pre_div);
293
+
294
+
if (rate == req_rate) {
295
+
best_conf = conf;
296
+
goto exit;
297
+
}
298
+
299
+
rate_diff = abs_diff(req_rate, rate);
300
+
if (rate_diff < best_rate_diff) {
301
+
best_rate_diff = rate_diff;
302
+
best_conf = conf;
303
+
}
304
+
}
305
+
306
+
/*
307
+
* Very unlikely. Warn if we couldn't find a correct config
308
+
* due to parent not found in every config.
309
+
*/
310
+
if (unlikely(!best_conf)) {
311
+
WARN(1, "%s: can't find a configuration for rate %lu\n",
312
+
name, req_rate);
313
+
return ERR_PTR(-EINVAL);
314
+
}
315
+
316
+
exit:
317
+
return best_conf;
318
+
}
319
+
320
+
static int _freq_tbl_fm_determine_rate(struct clk_hw *hw, const struct freq_multi_tbl *f,
321
+
struct clk_rate_request *req)
322
+
{
323
+
unsigned long clk_flags, rate = req->rate;
324
+
struct clk_rcg2 *rcg = to_clk_rcg2(hw);
325
+
const struct freq_conf *conf;
326
+
struct clk_hw *p;
327
+
int index;
328
+
329
+
f = qcom_find_freq_multi(f, rate);
330
+
if (!f || !f->confs)
331
+
return -EINVAL;
332
+
333
+
conf = __clk_rcg2_select_conf(hw, f, rate);
334
+
if (IS_ERR(conf))
335
+
return PTR_ERR(conf);
336
+
index = qcom_find_src_index(hw, rcg->parent_map, conf->src);
337
+
if (index < 0)
338
+
return index;
339
+
340
+
clk_flags = clk_hw_get_flags(hw);
341
+
p = clk_hw_get_parent_by_index(hw, index);
342
+
if (!p)
343
+
return -EINVAL;
344
+
345
+
if (clk_flags & CLK_SET_RATE_PARENT) {
346
+
rate = f->freq;
347
+
if (conf->pre_div) {
348
+
if (!rate)
349
+
rate = req->rate;
350
+
rate /= 2;
351
+
rate *= conf->pre_div + 1;
352
+
}
353
+
354
+
if (conf->n) {
355
+
u64 tmp = rate;
356
+
357
+
tmp = tmp * conf->n;
358
+
do_div(tmp, conf->m);
359
+
rate = tmp;
360
+
}
361
+
} else {
362
+
rate = clk_hw_get_rate(p);
363
+
}
364
+
365
+
req->best_parent_hw = p;
366
+
req->best_parent_rate = rate;
367
+
req->rate = f->freq;
368
+
369
+
return 0;
370
+
}
371
+
263
372
static int clk_rcg2_determine_rate(struct clk_hw *hw,
264
373
struct clk_rate_request *req)
265
374
{
···
383
274
struct clk_rcg2 *rcg = to_clk_rcg2(hw);
384
275
385
276
return _freq_tbl_determine_rate(hw, rcg->freq_tbl, req, FLOOR);
277
+
}
278
+
279
+
static int clk_rcg2_fm_determine_rate(struct clk_hw *hw,
280
+
struct clk_rate_request *req)
281
+
{
282
+
struct clk_rcg2 *rcg = to_clk_rcg2(hw);
283
+
284
+
return _freq_tbl_fm_determine_rate(hw, rcg->freq_multi_tbl, req);
386
285
}
387
286
388
287
static int __clk_rcg2_configure(struct clk_rcg2 *rcg, const struct freq_tbl *f,
···
488
371
return clk_rcg2_configure(rcg, f);
489
372
}
490
373
374
+
static int __clk_rcg2_fm_set_rate(struct clk_hw *hw, unsigned long rate)
375
+
{
376
+
struct clk_rcg2 *rcg = to_clk_rcg2(hw);
377
+
const struct freq_multi_tbl *f;
378
+
const struct freq_conf *conf;
379
+
struct freq_tbl f_tbl = {};
380
+
381
+
f = qcom_find_freq_multi(rcg->freq_multi_tbl, rate);
382
+
if (!f || !f->confs)
383
+
return -EINVAL;
384
+
385
+
conf = __clk_rcg2_select_conf(hw, f, rate);
386
+
if (IS_ERR(conf))
387
+
return PTR_ERR(conf);
388
+
389
+
f_tbl.freq = f->freq;
390
+
f_tbl.src = conf->src;
391
+
f_tbl.pre_div = conf->pre_div;
392
+
f_tbl.m = conf->m;
393
+
f_tbl.n = conf->n;
394
+
395
+
return clk_rcg2_configure(rcg, &f_tbl);
396
+
}
397
+
491
398
static int clk_rcg2_set_rate(struct clk_hw *hw, unsigned long rate,
492
399
unsigned long parent_rate)
493
400
{
···
524
383
return __clk_rcg2_set_rate(hw, rate, FLOOR);
525
384
}
526
385
386
+
static int clk_rcg2_fm_set_rate(struct clk_hw *hw, unsigned long rate,
387
+
unsigned long parent_rate)
388
+
{
389
+
return __clk_rcg2_fm_set_rate(hw, rate);
390
+
}
391
+
527
392
static int clk_rcg2_set_rate_and_parent(struct clk_hw *hw,
528
393
unsigned long rate, unsigned long parent_rate, u8 index)
529
394
{
···
540
393
unsigned long rate, unsigned long parent_rate, u8 index)
541
394
{
542
395
return __clk_rcg2_set_rate(hw, rate, FLOOR);
396
+
}
397
+
398
+
static int clk_rcg2_fm_set_rate_and_parent(struct clk_hw *hw,
399
+
unsigned long rate, unsigned long parent_rate, u8 index)
400
+
{
401
+
return __clk_rcg2_fm_set_rate(hw, rate);
543
402
}
544
403
545
404
static int clk_rcg2_get_duty_cycle(struct clk_hw *hw, struct clk_duty *duty)
···
657
504
.set_duty_cycle = clk_rcg2_set_duty_cycle,
658
505
};
659
506
EXPORT_SYMBOL_GPL(clk_rcg2_floor_ops);
507
+
508
+
const struct clk_ops clk_rcg2_fm_ops = {
509
+
.is_enabled = clk_rcg2_is_enabled,
510
+
.get_parent = clk_rcg2_get_parent,
511
+
.set_parent = clk_rcg2_set_parent,
512
+
.recalc_rate = clk_rcg2_recalc_rate,
513
+
.determine_rate = clk_rcg2_fm_determine_rate,
514
+
.set_rate = clk_rcg2_fm_set_rate,
515
+
.set_rate_and_parent = clk_rcg2_fm_set_rate_and_parent,
516
+
.get_duty_cycle = clk_rcg2_get_duty_cycle,
517
+
.set_duty_cycle = clk_rcg2_set_duty_cycle,
518
+
};
519
+
EXPORT_SYMBOL_GPL(clk_rcg2_fm_ops);
660
520
661
521
const struct clk_ops clk_rcg2_mux_closest_ops = {
662
522
.determine_rate = __clk_mux_determine_rate_closest,
-1
drivers/clk/qcom/clk-rpm.c
-1
drivers/clk/qcom/clk-rpm.c
+18
drivers/clk/qcom/common.c
+18
drivers/clk/qcom/common.c
···
41
41
}
42
42
EXPORT_SYMBOL_GPL(qcom_find_freq);
43
43
44
+
const struct freq_multi_tbl *qcom_find_freq_multi(const struct freq_multi_tbl *f,
45
+
unsigned long rate)
46
+
{
47
+
if (!f)
48
+
return NULL;
49
+
50
+
if (!f->freq)
51
+
return f;
52
+
53
+
for (; f->freq; f++)
54
+
if (rate <= f->freq)
55
+
return f;
56
+
57
+
/* Default to our fastest rate */
58
+
return f - 1;
59
+
}
60
+
EXPORT_SYMBOL_GPL(qcom_find_freq_multi);
61
+
44
62
const struct freq_tbl *qcom_find_freq_floor(const struct freq_tbl *f,
45
63
unsigned long rate)
46
64
{
+2
drivers/clk/qcom/common.h
+2
drivers/clk/qcom/common.h
···
45
45
unsigned long rate);
46
46
extern const struct freq_tbl *qcom_find_freq_floor(const struct freq_tbl *f,
47
47
unsigned long rate);
48
+
extern const struct freq_multi_tbl *qcom_find_freq_multi(const struct freq_multi_tbl *f,
49
+
unsigned long rate);
48
50
extern void
49
51
qcom_pll_set_fsm_mode(struct regmap *m, u32 reg, u8 bias_count, u8 lock_count);
50
52
extern int qcom_find_src_index(struct clk_hw *hw, const struct parent_map *map,
+1
-10
drivers/clk/qcom/dispcc-sm6350.c
+1
-10
drivers/clk/qcom/dispcc-sm6350.c
···
221
221
},
222
222
};
223
223
224
-
static const struct freq_tbl ftbl_disp_cc_mdss_dp_link_clk_src[] = {
225
-
F(162000, P_DP_PHY_PLL_LINK_CLK, 1, 0, 0),
226
-
F(270000, P_DP_PHY_PLL_LINK_CLK, 1, 0, 0),
227
-
F(540000, P_DP_PHY_PLL_LINK_CLK, 1, 0, 0),
228
-
F(810000, P_DP_PHY_PLL_LINK_CLK, 1, 0, 0),
229
-
{ }
230
-
};
231
-
232
224
static struct clk_rcg2 disp_cc_mdss_dp_link_clk_src = {
233
225
.cmd_rcgr = 0x10f8,
234
226
.mnd_width = 0,
235
227
.hid_width = 5,
236
228
.parent_map = disp_cc_parent_map_0,
237
-
.freq_tbl = ftbl_disp_cc_mdss_dp_link_clk_src,
238
229
.clkr.hw.init = &(struct clk_init_data){
239
230
.name = "disp_cc_mdss_dp_link_clk_src",
240
231
.parent_data = disp_cc_parent_data_0,
241
232
.num_parents = ARRAY_SIZE(disp_cc_parent_data_0),
242
233
.flags = CLK_SET_RATE_PARENT | CLK_GET_RATE_NOCACHE,
243
-
.ops = &clk_rcg2_ops,
234
+
.ops = &clk_byte2_ops,
244
235
},
245
236
};
246
237
+4
-16
drivers/clk/qcom/dispcc-sm8450.c
+4
-16
drivers/clk/qcom/dispcc-sm8450.c
···
309
309
},
310
310
};
311
311
312
-
static const struct freq_tbl ftbl_disp_cc_mdss_dptx0_link_clk_src[] = {
313
-
F(162000, P_DP0_PHY_PLL_LINK_CLK, 1, 0, 0),
314
-
F(270000, P_DP0_PHY_PLL_LINK_CLK, 1, 0, 0),
315
-
F(540000, P_DP0_PHY_PLL_LINK_CLK, 1, 0, 0),
316
-
F(810000, P_DP0_PHY_PLL_LINK_CLK, 1, 0, 0),
317
-
{ }
318
-
};
319
-
320
312
static struct clk_rcg2 disp_cc_mdss_dptx0_link_clk_src = {
321
313
.cmd_rcgr = 0x819c,
322
314
.mnd_width = 0,
323
315
.hid_width = 5,
324
316
.parent_map = disp_cc_parent_map_3,
325
-
.freq_tbl = ftbl_disp_cc_mdss_dptx0_link_clk_src,
326
317
.clkr.hw.init = &(struct clk_init_data) {
327
318
.name = "disp_cc_mdss_dptx0_link_clk_src",
328
319
.parent_data = disp_cc_parent_data_3,
329
320
.num_parents = ARRAY_SIZE(disp_cc_parent_data_3),
330
321
.flags = CLK_SET_RATE_PARENT,
331
-
.ops = &clk_rcg2_ops,
322
+
.ops = &clk_byte2_ops,
332
323
},
333
324
};
334
325
···
373
382
.mnd_width = 0,
374
383
.hid_width = 5,
375
384
.parent_map = disp_cc_parent_map_3,
376
-
.freq_tbl = ftbl_disp_cc_mdss_dptx0_link_clk_src,
377
385
.clkr.hw.init = &(struct clk_init_data) {
378
386
.name = "disp_cc_mdss_dptx1_link_clk_src",
379
387
.parent_data = disp_cc_parent_data_3,
380
388
.num_parents = ARRAY_SIZE(disp_cc_parent_data_3),
381
389
.flags = CLK_SET_RATE_PARENT,
382
-
.ops = &clk_rcg2_ops,
390
+
.ops = &clk_byte2_ops,
383
391
},
384
392
};
385
393
···
432
442
.mnd_width = 0,
433
443
.hid_width = 5,
434
444
.parent_map = disp_cc_parent_map_3,
435
-
.freq_tbl = ftbl_disp_cc_mdss_dptx0_link_clk_src,
436
445
.clkr.hw.init = &(struct clk_init_data) {
437
446
.name = "disp_cc_mdss_dptx2_link_clk_src",
438
447
.parent_data = disp_cc_parent_data_3,
439
448
.num_parents = ARRAY_SIZE(disp_cc_parent_data_3),
440
449
.flags = CLK_SET_RATE_PARENT,
441
-
.ops = &clk_rcg2_ops,
450
+
.ops = &clk_byte2_ops,
442
451
},
443
452
};
444
453
···
491
502
.mnd_width = 0,
492
503
.hid_width = 5,
493
504
.parent_map = disp_cc_parent_map_3,
494
-
.freq_tbl = ftbl_disp_cc_mdss_dptx0_link_clk_src,
495
505
.clkr.hw.init = &(struct clk_init_data) {
496
506
.name = "disp_cc_mdss_dptx3_link_clk_src",
497
507
.parent_data = disp_cc_parent_data_3,
498
508
.num_parents = ARRAY_SIZE(disp_cc_parent_data_3),
499
509
.flags = CLK_SET_RATE_PARENT,
500
-
.ops = &clk_rcg2_ops,
510
+
.ops = &clk_byte2_ops,
501
511
},
502
512
};
503
513
+4
-16
drivers/clk/qcom/dispcc-sm8550.c
+4
-16
drivers/clk/qcom/dispcc-sm8550.c
···
345
345
},
346
346
};
347
347
348
-
static const struct freq_tbl ftbl_disp_cc_mdss_dptx0_link_clk_src[] = {
349
-
F(162000, P_DP0_PHY_PLL_LINK_CLK, 1, 0, 0),
350
-
F(270000, P_DP0_PHY_PLL_LINK_CLK, 1, 0, 0),
351
-
F(540000, P_DP0_PHY_PLL_LINK_CLK, 1, 0, 0),
352
-
F(810000, P_DP0_PHY_PLL_LINK_CLK, 1, 0, 0),
353
-
{ }
354
-
};
355
-
356
348
static struct clk_rcg2 disp_cc_mdss_dptx0_link_clk_src = {
357
349
.cmd_rcgr = 0x8170,
358
350
.mnd_width = 0,
359
351
.hid_width = 5,
360
352
.parent_map = disp_cc_parent_map_7,
361
-
.freq_tbl = ftbl_disp_cc_mdss_dptx0_link_clk_src,
362
353
.clkr.hw.init = &(struct clk_init_data) {
363
354
.name = "disp_cc_mdss_dptx0_link_clk_src",
364
355
.parent_data = disp_cc_parent_data_7,
365
356
.num_parents = ARRAY_SIZE(disp_cc_parent_data_7),
366
357
.flags = CLK_SET_RATE_PARENT,
367
-
.ops = &clk_rcg2_ops,
358
+
.ops = &clk_byte2_ops,
368
359
},
369
360
};
370
361
···
409
418
.mnd_width = 0,
410
419
.hid_width = 5,
411
420
.parent_map = disp_cc_parent_map_3,
412
-
.freq_tbl = ftbl_disp_cc_mdss_dptx0_link_clk_src,
413
421
.clkr.hw.init = &(struct clk_init_data) {
414
422
.name = "disp_cc_mdss_dptx1_link_clk_src",
415
423
.parent_data = disp_cc_parent_data_3,
416
424
.num_parents = ARRAY_SIZE(disp_cc_parent_data_3),
417
425
.flags = CLK_SET_RATE_PARENT,
418
-
.ops = &clk_rcg2_ops,
426
+
.ops = &clk_byte2_ops,
419
427
},
420
428
};
421
429
···
468
478
.mnd_width = 0,
469
479
.hid_width = 5,
470
480
.parent_map = disp_cc_parent_map_3,
471
-
.freq_tbl = ftbl_disp_cc_mdss_dptx0_link_clk_src,
472
481
.clkr.hw.init = &(struct clk_init_data) {
473
482
.name = "disp_cc_mdss_dptx2_link_clk_src",
474
483
.parent_data = disp_cc_parent_data_3,
475
484
.num_parents = ARRAY_SIZE(disp_cc_parent_data_3),
476
485
.flags = CLK_SET_RATE_PARENT,
477
-
.ops = &clk_rcg2_ops,
486
+
.ops = &clk_byte2_ops,
478
487
},
479
488
};
480
489
···
527
538
.mnd_width = 0,
528
539
.hid_width = 5,
529
540
.parent_map = disp_cc_parent_map_3,
530
-
.freq_tbl = ftbl_disp_cc_mdss_dptx0_link_clk_src,
531
541
.clkr.hw.init = &(struct clk_init_data) {
532
542
.name = "disp_cc_mdss_dptx3_link_clk_src",
533
543
.parent_data = disp_cc_parent_data_3,
534
544
.num_parents = ARRAY_SIZE(disp_cc_parent_data_3),
535
545
.flags = CLK_SET_RATE_PARENT,
536
-
.ops = &clk_rcg2_ops,
546
+
.ops = &clk_byte2_ops,
537
547
},
538
548
};
539
549
+4
-16
drivers/clk/qcom/dispcc-sm8650.c
+4
-16
drivers/clk/qcom/dispcc-sm8650.c
···
343
343
},
344
344
};
345
345
346
-
static const struct freq_tbl ftbl_disp_cc_mdss_dptx0_link_clk_src[] = {
347
-
F(162000, P_DP0_PHY_PLL_LINK_CLK, 1, 0, 0),
348
-
F(270000, P_DP0_PHY_PLL_LINK_CLK, 1, 0, 0),
349
-
F(540000, P_DP0_PHY_PLL_LINK_CLK, 1, 0, 0),
350
-
F(810000, P_DP0_PHY_PLL_LINK_CLK, 1, 0, 0),
351
-
{ }
352
-
};
353
-
354
346
static struct clk_rcg2 disp_cc_mdss_dptx0_link_clk_src = {
355
347
.cmd_rcgr = 0x8170,
356
348
.mnd_width = 0,
357
349
.hid_width = 5,
358
350
.parent_map = disp_cc_parent_map_7,
359
-
.freq_tbl = ftbl_disp_cc_mdss_dptx0_link_clk_src,
360
351
.clkr.hw.init = &(const struct clk_init_data) {
361
352
.name = "disp_cc_mdss_dptx0_link_clk_src",
362
353
.parent_data = disp_cc_parent_data_7,
363
354
.num_parents = ARRAY_SIZE(disp_cc_parent_data_7),
364
355
.flags = CLK_SET_RATE_PARENT,
365
-
.ops = &clk_rcg2_ops,
356
+
.ops = &clk_byte2_ops,
366
357
},
367
358
};
368
359
···
407
416
.mnd_width = 0,
408
417
.hid_width = 5,
409
418
.parent_map = disp_cc_parent_map_3,
410
-
.freq_tbl = ftbl_disp_cc_mdss_dptx0_link_clk_src,
411
419
.clkr.hw.init = &(const struct clk_init_data) {
412
420
.name = "disp_cc_mdss_dptx1_link_clk_src",
413
421
.parent_data = disp_cc_parent_data_3,
414
422
.num_parents = ARRAY_SIZE(disp_cc_parent_data_3),
415
423
.flags = CLK_SET_RATE_PARENT,
416
-
.ops = &clk_rcg2_ops,
424
+
.ops = &clk_byte2_ops,
417
425
},
418
426
};
419
427
···
466
476
.mnd_width = 0,
467
477
.hid_width = 5,
468
478
.parent_map = disp_cc_parent_map_3,
469
-
.freq_tbl = ftbl_disp_cc_mdss_dptx0_link_clk_src,
470
479
.clkr.hw.init = &(const struct clk_init_data) {
471
480
.name = "disp_cc_mdss_dptx2_link_clk_src",
472
481
.parent_data = disp_cc_parent_data_3,
473
482
.num_parents = ARRAY_SIZE(disp_cc_parent_data_3),
474
483
.flags = CLK_SET_RATE_PARENT,
475
-
.ops = &clk_rcg2_ops,
484
+
.ops = &clk_byte2_ops,
476
485
},
477
486
};
478
487
···
525
536
.mnd_width = 0,
526
537
.hid_width = 5,
527
538
.parent_map = disp_cc_parent_map_3,
528
-
.freq_tbl = ftbl_disp_cc_mdss_dptx0_link_clk_src,
529
539
.clkr.hw.init = &(const struct clk_init_data) {
530
540
.name = "disp_cc_mdss_dptx3_link_clk_src",
531
541
.parent_data = disp_cc_parent_data_3,
532
542
.num_parents = ARRAY_SIZE(disp_cc_parent_data_3),
533
543
.flags = CLK_SET_RATE_PARENT,
534
-
.ops = &clk_rcg2_ops,
544
+
.ops = &clk_byte2_ops,
535
545
},
536
546
};
537
547
+76
-44
drivers/clk/qcom/gcc-ipq8074.c
+76
-44
drivers/clk/qcom/gcc-ipq8074.c
···
1677
1677
},
1678
1678
};
1679
1679
1680
-
static const struct freq_tbl ftbl_nss_port5_rx_clk_src[] = {
1681
-
F(19200000, P_XO, 1, 0, 0),
1682
-
F(25000000, P_UNIPHY1_RX, 12.5, 0, 0),
1683
-
F(25000000, P_UNIPHY0_RX, 5, 0, 0),
1684
-
F(78125000, P_UNIPHY1_RX, 4, 0, 0),
1685
-
F(125000000, P_UNIPHY1_RX, 2.5, 0, 0),
1686
-
F(125000000, P_UNIPHY0_RX, 1, 0, 0),
1687
-
F(156250000, P_UNIPHY1_RX, 2, 0, 0),
1688
-
F(312500000, P_UNIPHY1_RX, 1, 0, 0),
1680
+
static const struct freq_conf ftbl_nss_port5_rx_clk_src_25[] = {
1681
+
C(P_UNIPHY1_RX, 12.5, 0, 0),
1682
+
C(P_UNIPHY0_RX, 5, 0, 0),
1683
+
};
1684
+
1685
+
static const struct freq_conf ftbl_nss_port5_rx_clk_src_125[] = {
1686
+
C(P_UNIPHY1_RX, 2.5, 0, 0),
1687
+
C(P_UNIPHY0_RX, 1, 0, 0),
1688
+
};
1689
+
1690
+
static const struct freq_multi_tbl ftbl_nss_port5_rx_clk_src[] = {
1691
+
FMS(19200000, P_XO, 1, 0, 0),
1692
+
FM(25000000, ftbl_nss_port5_rx_clk_src_25),
1693
+
FMS(78125000, P_UNIPHY1_RX, 4, 0, 0),
1694
+
FM(125000000, ftbl_nss_port5_rx_clk_src_125),
1695
+
FMS(156250000, P_UNIPHY1_RX, 2, 0, 0),
1696
+
FMS(312500000, P_UNIPHY1_RX, 1, 0, 0),
1689
1697
{ }
1690
1698
};
1691
1699
···
1720
1712
1721
1713
static struct clk_rcg2 nss_port5_rx_clk_src = {
1722
1714
.cmd_rcgr = 0x68060,
1723
-
.freq_tbl = ftbl_nss_port5_rx_clk_src,
1715
+
.freq_multi_tbl = ftbl_nss_port5_rx_clk_src,
1724
1716
.hid_width = 5,
1725
1717
.parent_map = gcc_xo_uniphy0_rx_tx_uniphy1_rx_tx_ubi32_bias_map,
1726
1718
.clkr.hw.init = &(struct clk_init_data){
1727
1719
.name = "nss_port5_rx_clk_src",
1728
1720
.parent_data = gcc_xo_uniphy0_rx_tx_uniphy1_rx_tx_ubi32_bias,
1729
1721
.num_parents = ARRAY_SIZE(gcc_xo_uniphy0_rx_tx_uniphy1_rx_tx_ubi32_bias),
1730
-
.ops = &clk_rcg2_ops,
1722
+
.ops = &clk_rcg2_fm_ops,
1731
1723
},
1732
1724
};
1733
1725
···
1747
1739
},
1748
1740
};
1749
1741
1750
-
static const struct freq_tbl ftbl_nss_port5_tx_clk_src[] = {
1751
-
F(19200000, P_XO, 1, 0, 0),
1752
-
F(25000000, P_UNIPHY1_TX, 12.5, 0, 0),
1753
-
F(25000000, P_UNIPHY0_TX, 5, 0, 0),
1754
-
F(78125000, P_UNIPHY1_TX, 4, 0, 0),
1755
-
F(125000000, P_UNIPHY1_TX, 2.5, 0, 0),
1756
-
F(125000000, P_UNIPHY0_TX, 1, 0, 0),
1757
-
F(156250000, P_UNIPHY1_TX, 2, 0, 0),
1758
-
F(312500000, P_UNIPHY1_TX, 1, 0, 0),
1742
+
static const struct freq_conf ftbl_nss_port5_tx_clk_src_25[] = {
1743
+
C(P_UNIPHY1_TX, 12.5, 0, 0),
1744
+
C(P_UNIPHY0_TX, 5, 0, 0),
1745
+
};
1746
+
1747
+
static const struct freq_conf ftbl_nss_port5_tx_clk_src_125[] = {
1748
+
C(P_UNIPHY1_TX, 2.5, 0, 0),
1749
+
C(P_UNIPHY0_TX, 1, 0, 0),
1750
+
};
1751
+
1752
+
static const struct freq_multi_tbl ftbl_nss_port5_tx_clk_src[] = {
1753
+
FMS(19200000, P_XO, 1, 0, 0),
1754
+
FM(25000000, ftbl_nss_port5_tx_clk_src_25),
1755
+
FMS(78125000, P_UNIPHY1_TX, 4, 0, 0),
1756
+
FM(125000000, ftbl_nss_port5_tx_clk_src_125),
1757
+
FMS(156250000, P_UNIPHY1_TX, 2, 0, 0),
1758
+
FMS(312500000, P_UNIPHY1_TX, 1, 0, 0),
1759
1759
{ }
1760
1760
};
1761
1761
···
1790
1774
1791
1775
static struct clk_rcg2 nss_port5_tx_clk_src = {
1792
1776
.cmd_rcgr = 0x68068,
1793
-
.freq_tbl = ftbl_nss_port5_tx_clk_src,
1777
+
.freq_multi_tbl = ftbl_nss_port5_tx_clk_src,
1794
1778
.hid_width = 5,
1795
1779
.parent_map = gcc_xo_uniphy0_tx_rx_uniphy1_tx_rx_ubi32_bias_map,
1796
1780
.clkr.hw.init = &(struct clk_init_data){
1797
1781
.name = "nss_port5_tx_clk_src",
1798
1782
.parent_data = gcc_xo_uniphy0_tx_rx_uniphy1_tx_rx_ubi32_bias,
1799
1783
.num_parents = ARRAY_SIZE(gcc_xo_uniphy0_tx_rx_uniphy1_tx_rx_ubi32_bias),
1800
-
.ops = &clk_rcg2_ops,
1784
+
.ops = &clk_rcg2_fm_ops,
1801
1785
},
1802
1786
};
1803
1787
···
1817
1801
},
1818
1802
};
1819
1803
1820
-
static const struct freq_tbl ftbl_nss_port6_rx_clk_src[] = {
1821
-
F(19200000, P_XO, 1, 0, 0),
1822
-
F(25000000, P_UNIPHY2_RX, 5, 0, 0),
1823
-
F(25000000, P_UNIPHY2_RX, 12.5, 0, 0),
1824
-
F(78125000, P_UNIPHY2_RX, 4, 0, 0),
1825
-
F(125000000, P_UNIPHY2_RX, 1, 0, 0),
1826
-
F(125000000, P_UNIPHY2_RX, 2.5, 0, 0),
1827
-
F(156250000, P_UNIPHY2_RX, 2, 0, 0),
1828
-
F(312500000, P_UNIPHY2_RX, 1, 0, 0),
1804
+
static const struct freq_conf ftbl_nss_port6_rx_clk_src_25[] = {
1805
+
C(P_UNIPHY2_RX, 5, 0, 0),
1806
+
C(P_UNIPHY2_RX, 12.5, 0, 0),
1807
+
};
1808
+
1809
+
static const struct freq_conf ftbl_nss_port6_rx_clk_src_125[] = {
1810
+
C(P_UNIPHY2_RX, 1, 0, 0),
1811
+
C(P_UNIPHY2_RX, 2.5, 0, 0),
1812
+
};
1813
+
1814
+
static const struct freq_multi_tbl ftbl_nss_port6_rx_clk_src[] = {
1815
+
FMS(19200000, P_XO, 1, 0, 0),
1816
+
FM(25000000, ftbl_nss_port6_rx_clk_src_25),
1817
+
FMS(78125000, P_UNIPHY2_RX, 4, 0, 0),
1818
+
FM(125000000, ftbl_nss_port6_rx_clk_src_125),
1819
+
FMS(156250000, P_UNIPHY2_RX, 2, 0, 0),
1820
+
FMS(312500000, P_UNIPHY2_RX, 1, 0, 0),
1829
1821
{ }
1830
1822
};
1831
1823
···
1855
1831
1856
1832
static struct clk_rcg2 nss_port6_rx_clk_src = {
1857
1833
.cmd_rcgr = 0x68070,
1858
-
.freq_tbl = ftbl_nss_port6_rx_clk_src,
1834
+
.freq_multi_tbl = ftbl_nss_port6_rx_clk_src,
1859
1835
.hid_width = 5,
1860
1836
.parent_map = gcc_xo_uniphy2_rx_tx_ubi32_bias_map,
1861
1837
.clkr.hw.init = &(struct clk_init_data){
1862
1838
.name = "nss_port6_rx_clk_src",
1863
1839
.parent_data = gcc_xo_uniphy2_rx_tx_ubi32_bias,
1864
1840
.num_parents = ARRAY_SIZE(gcc_xo_uniphy2_rx_tx_ubi32_bias),
1865
-
.ops = &clk_rcg2_ops,
1841
+
.ops = &clk_rcg2_fm_ops,
1866
1842
},
1867
1843
};
1868
1844
···
1882
1858
},
1883
1859
};
1884
1860
1885
-
static const struct freq_tbl ftbl_nss_port6_tx_clk_src[] = {
1886
-
F(19200000, P_XO, 1, 0, 0),
1887
-
F(25000000, P_UNIPHY2_TX, 5, 0, 0),
1888
-
F(25000000, P_UNIPHY2_TX, 12.5, 0, 0),
1889
-
F(78125000, P_UNIPHY2_TX, 4, 0, 0),
1890
-
F(125000000, P_UNIPHY2_TX, 1, 0, 0),
1891
-
F(125000000, P_UNIPHY2_TX, 2.5, 0, 0),
1892
-
F(156250000, P_UNIPHY2_TX, 2, 0, 0),
1893
-
F(312500000, P_UNIPHY2_TX, 1, 0, 0),
1861
+
static const struct freq_conf ftbl_nss_port6_tx_clk_src_25[] = {
1862
+
C(P_UNIPHY2_TX, 5, 0, 0),
1863
+
C(P_UNIPHY2_TX, 12.5, 0, 0),
1864
+
};
1865
+
1866
+
static const struct freq_conf ftbl_nss_port6_tx_clk_src_125[] = {
1867
+
C(P_UNIPHY2_TX, 1, 0, 0),
1868
+
C(P_UNIPHY2_TX, 2.5, 0, 0),
1869
+
};
1870
+
1871
+
static const struct freq_multi_tbl ftbl_nss_port6_tx_clk_src[] = {
1872
+
FMS(19200000, P_XO, 1, 0, 0),
1873
+
FM(25000000, ftbl_nss_port6_tx_clk_src_25),
1874
+
FMS(78125000, P_UNIPHY1_RX, 4, 0, 0),
1875
+
FM(125000000, ftbl_nss_port6_tx_clk_src_125),
1876
+
FMS(156250000, P_UNIPHY1_RX, 2, 0, 0),
1877
+
FMS(312500000, P_UNIPHY1_RX, 1, 0, 0),
1894
1878
{ }
1895
1879
};
1896
1880
···
1920
1888
1921
1889
static struct clk_rcg2 nss_port6_tx_clk_src = {
1922
1890
.cmd_rcgr = 0x68078,
1923
-
.freq_tbl = ftbl_nss_port6_tx_clk_src,
1891
+
.freq_multi_tbl = ftbl_nss_port6_tx_clk_src,
1924
1892
.hid_width = 5,
1925
1893
.parent_map = gcc_xo_uniphy2_tx_rx_ubi32_bias_map,
1926
1894
.clkr.hw.init = &(struct clk_init_data){
1927
1895
.name = "nss_port6_tx_clk_src",
1928
1896
.parent_data = gcc_xo_uniphy2_tx_rx_ubi32_bias,
1929
1897
.num_parents = ARRAY_SIZE(gcc_xo_uniphy2_tx_rx_ubi32_bias),
1930
-
.ops = &clk_rcg2_ops,
1898
+
.ops = &clk_rcg2_fm_ops,
1931
1899
},
1932
1900
};
1933
1901
+1
drivers/clk/qcom/gcc-msm8917.c
+1
drivers/clk/qcom/gcc-msm8917.c
+1
drivers/clk/qcom/gcc-msm8953.c
+1
drivers/clk/qcom/gcc-msm8953.c
-61
drivers/clk/qcom/gcc-sm8150.c
-61
drivers/clk/qcom/gcc-sm8150.c
···
207
207
{ .hw = &gpll0_out_even.clkr.hw },
208
208
};
209
209
210
-
static const struct freq_tbl ftbl_gcc_cpuss_ahb_clk_src[] = {
211
-
F(19200000, P_BI_TCXO, 1, 0, 0),
212
-
F(50000000, P_GPLL0_OUT_MAIN, 12, 0, 0),
213
-
F(100000000, P_GPLL0_OUT_MAIN, 6, 0, 0),
214
-
{ }
215
-
};
216
-
217
-
static struct clk_rcg2 gcc_cpuss_ahb_clk_src = {
218
-
.cmd_rcgr = 0x48014,
219
-
.mnd_width = 0,
220
-
.hid_width = 5,
221
-
.parent_map = gcc_parent_map_0,
222
-
.freq_tbl = ftbl_gcc_cpuss_ahb_clk_src,
223
-
.clkr.hw.init = &(struct clk_init_data){
224
-
.name = "gcc_cpuss_ahb_clk_src",
225
-
.parent_data = gcc_parents_0,
226
-
.num_parents = ARRAY_SIZE(gcc_parents_0),
227
-
.flags = CLK_SET_RATE_PARENT,
228
-
.ops = &clk_rcg2_ops,
229
-
},
230
-
};
231
-
232
210
static const struct freq_tbl ftbl_gcc_emac_ptp_clk_src[] = {
233
211
F(19200000, P_BI_TCXO, 1, 0, 0),
234
212
F(50000000, P_GPLL0_OUT_EVEN, 6, 0, 0),
···
1334
1356
&gcc_usb30_sec_master_clk_src.clkr.hw },
1335
1357
.num_parents = 1,
1336
1358
.flags = CLK_SET_RATE_PARENT,
1337
-
.ops = &clk_branch2_ops,
1338
-
},
1339
-
},
1340
-
};
1341
-
1342
-
static struct clk_branch gcc_cpuss_ahb_clk = {
1343
-
.halt_reg = 0x48000,
1344
-
.halt_check = BRANCH_HALT_VOTED,
1345
-
.clkr = {
1346
-
.enable_reg = 0x52004,
1347
-
.enable_mask = BIT(21),
1348
-
.hw.init = &(struct clk_init_data){
1349
-
.name = "gcc_cpuss_ahb_clk",
1350
-
.parent_hws = (const struct clk_hw *[]){
1351
-
&gcc_cpuss_ahb_clk_src.clkr.hw },
1352
-
.num_parents = 1,
1353
-
/* required for cpuss */
1354
-
.flags = CLK_IS_CRITICAL | CLK_SET_RATE_PARENT,
1355
1359
.ops = &clk_branch2_ops,
1356
1360
},
1357
1361
},
···
2645
2685
},
2646
2686
};
2647
2687
2648
-
static struct clk_branch gcc_sys_noc_cpuss_ahb_clk = {
2649
-
.halt_reg = 0x4819c,
2650
-
.halt_check = BRANCH_HALT_VOTED,
2651
-
.clkr = {
2652
-
.enable_reg = 0x52004,
2653
-
.enable_mask = BIT(0),
2654
-
.hw.init = &(struct clk_init_data){
2655
-
.name = "gcc_sys_noc_cpuss_ahb_clk",
2656
-
.parent_hws = (const struct clk_hw *[]){
2657
-
&gcc_cpuss_ahb_clk_src.clkr.hw },
2658
-
.num_parents = 1,
2659
-
/* required for cpuss */
2660
-
.flags = CLK_IS_CRITICAL | CLK_SET_RATE_PARENT,
2661
-
.ops = &clk_branch2_ops,
2662
-
},
2663
-
},
2664
-
};
2665
-
2666
2688
static struct clk_branch gcc_tsif_ahb_clk = {
2667
2689
.halt_reg = 0x36004,
2668
2690
.halt_check = BRANCH_HALT,
···
3492
3550
[GCC_CAMERA_XO_CLK] = &gcc_camera_xo_clk.clkr,
3493
3551
[GCC_CFG_NOC_USB3_PRIM_AXI_CLK] = &gcc_cfg_noc_usb3_prim_axi_clk.clkr,
3494
3552
[GCC_CFG_NOC_USB3_SEC_AXI_CLK] = &gcc_cfg_noc_usb3_sec_axi_clk.clkr,
3495
-
[GCC_CPUSS_AHB_CLK] = &gcc_cpuss_ahb_clk.clkr,
3496
-
[GCC_CPUSS_AHB_CLK_SRC] = &gcc_cpuss_ahb_clk_src.clkr,
3497
3553
[GCC_CPUSS_DVM_BUS_CLK] = &gcc_cpuss_dvm_bus_clk.clkr,
3498
3554
[GCC_CPUSS_GNOC_CLK] = &gcc_cpuss_gnoc_clk.clkr,
3499
3555
[GCC_CPUSS_RBCPR_CLK] = &gcc_cpuss_rbcpr_clk.clkr,
···
3609
3669
[GCC_SDCC4_AHB_CLK] = &gcc_sdcc4_ahb_clk.clkr,
3610
3670
[GCC_SDCC4_APPS_CLK] = &gcc_sdcc4_apps_clk.clkr,
3611
3671
[GCC_SDCC4_APPS_CLK_SRC] = &gcc_sdcc4_apps_clk_src.clkr,
3612
-
[GCC_SYS_NOC_CPUSS_AHB_CLK] = &gcc_sys_noc_cpuss_ahb_clk.clkr,
3613
3672
[GCC_TSIF_AHB_CLK] = &gcc_tsif_ahb_clk.clkr,
3614
3673
[GCC_TSIF_INACTIVITY_TIMERS_CLK] = &gcc_tsif_inactivity_timers_clk.clkr,
3615
3674
[GCC_TSIF_REF_CLK] = &gcc_tsif_ref_clk.clkr,
+4
-2
drivers/clk/qcom/hfpll.c
+4
-2
drivers/clk/qcom/hfpll.c
···
14
14
#include "clk-regmap.h"
15
15
#include "clk-hfpll.h"
16
16
17
-
static const struct hfpll_data hdata = {
17
+
static const struct hfpll_data qcs404 = {
18
18
.mode_reg = 0x00,
19
19
.l_reg = 0x04,
20
20
.m_reg = 0x08,
···
84
84
};
85
85
86
86
static const struct of_device_id qcom_hfpll_match_table[] = {
87
-
{ .compatible = "qcom,hfpll", .data = &hdata },
88
87
{ .compatible = "qcom,msm8976-hfpll-a53", .data = &msm8976_a53 },
89
88
{ .compatible = "qcom,msm8976-hfpll-a72", .data = &msm8976_a72 },
90
89
{ .compatible = "qcom,msm8976-hfpll-cci", .data = &msm8976_cci },
90
+
{ .compatible = "qcom,qcs404-hfpll", .data = &qcs404 },
91
+
/* Deprecated in bindings */
92
+
{ .compatible = "qcom,hfpll", .data = &qcs404 },
91
93
{ }
92
94
};
93
95
MODULE_DEVICE_TABLE(of, qcom_hfpll_match_table);
+8
drivers/clk/qcom/mmcc-msm8998.c
+8
drivers/clk/qcom/mmcc-msm8998.c
···
2535
2535
2536
2536
static struct gdsc video_top_gdsc = {
2537
2537
.gdscr = 0x1024,
2538
+
.cxcs = (unsigned int []){ 0x1028, 0x1034, 0x1038 },
2539
+
.cxc_count = 3,
2538
2540
.pd = {
2539
2541
.name = "video_top",
2540
2542
},
···
2545
2543
2546
2544
static struct gdsc video_subcore0_gdsc = {
2547
2545
.gdscr = 0x1040,
2546
+
.cxcs = (unsigned int []){ 0x1048 },
2547
+
.cxc_count = 1,
2548
2548
.pd = {
2549
2549
.name = "video_subcore0",
2550
2550
},
2551
2551
.parent = &video_top_gdsc.pd,
2552
2552
.pwrsts = PWRSTS_OFF_ON,
2553
+
.flags = HW_CTRL,
2553
2554
};
2554
2555
2555
2556
static struct gdsc video_subcore1_gdsc = {
2556
2557
.gdscr = 0x1044,
2558
+
.cxcs = (unsigned int []){ 0x104c },
2559
+
.cxc_count = 1,
2557
2560
.pd = {
2558
2561
.name = "video_subcore1",
2559
2562
},
2560
2563
.parent = &video_top_gdsc.pd,
2561
2564
.pwrsts = PWRSTS_OFF_ON,
2565
+
.flags = HW_CTRL,
2562
2566
};
2563
2567
2564
2568
static struct gdsc mdss_gdsc = {
-2
drivers/clk/renesas/clk-r8a73a4.c
-2
drivers/clk/renesas/clk-r8a73a4.c
+12
-15
drivers/clk/renesas/clk-r8a7740.c
+12
-15
drivers/clk/renesas/clk-r8a7740.c
···
26
26
#define CPG_USBCKCR 0x8c
27
27
#define CPG_FRQCRC 0xe0
28
28
29
-
#define CLK_ENABLE_ON_INIT BIT(0)
30
-
31
29
struct div4_clk {
32
30
const char *name;
33
31
unsigned int reg;
34
32
unsigned int shift;
35
-
int flags;
36
33
};
37
34
38
35
static struct div4_clk div4_clks[] = {
39
-
{ "i", CPG_FRQCRA, 20, CLK_ENABLE_ON_INIT },
40
-
{ "zg", CPG_FRQCRA, 16, CLK_ENABLE_ON_INIT },
41
-
{ "b", CPG_FRQCRA, 8, CLK_ENABLE_ON_INIT },
42
-
{ "m1", CPG_FRQCRA, 4, CLK_ENABLE_ON_INIT },
43
-
{ "hp", CPG_FRQCRB, 4, 0 },
44
-
{ "hpp", CPG_FRQCRC, 20, 0 },
45
-
{ "usbp", CPG_FRQCRC, 16, 0 },
46
-
{ "s", CPG_FRQCRC, 12, 0 },
47
-
{ "zb", CPG_FRQCRC, 8, 0 },
48
-
{ "m3", CPG_FRQCRC, 4, 0 },
49
-
{ "cp", CPG_FRQCRC, 0, 0 },
50
-
{ NULL, 0, 0, 0 },
36
+
{ "i", CPG_FRQCRA, 20 },
37
+
{ "zg", CPG_FRQCRA, 16 },
38
+
{ "b", CPG_FRQCRA, 8 },
39
+
{ "m1", CPG_FRQCRA, 4 },
40
+
{ "hp", CPG_FRQCRB, 4 },
41
+
{ "hpp", CPG_FRQCRC, 20 },
42
+
{ "usbp", CPG_FRQCRC, 16 },
43
+
{ "s", CPG_FRQCRC, 12 },
44
+
{ "zb", CPG_FRQCRC, 8 },
45
+
{ "m3", CPG_FRQCRC, 4 },
46
+
{ "cp", CPG_FRQCRC, 0 },
47
+
{ NULL, 0, 0 },
51
48
};
52
49
53
50
static const struct clk_div_table div4_div_table[] = {
-2
drivers/clk/renesas/clk-sh73a0.c
-2
drivers/clk/renesas/clk-sh73a0.c
+1
-1
drivers/clk/renesas/r8a779a0-cpg-mssr.c
+1
-1
drivers/clk/renesas/r8a779a0-cpg-mssr.c
···
139
139
DEF_MOD("avb3", 214, R8A779A0_CLK_S3D2),
140
140
DEF_MOD("avb4", 215, R8A779A0_CLK_S3D2),
141
141
DEF_MOD("avb5", 216, R8A779A0_CLK_S3D2),
142
-
DEF_MOD("canfd0", 328, R8A779A0_CLK_CANFD),
142
+
DEF_MOD("canfd0", 328, R8A779A0_CLK_S3D2),
143
143
DEF_MOD("csi40", 331, R8A779A0_CLK_CSI0),
144
144
DEF_MOD("csi41", 400, R8A779A0_CLK_CSI0),
145
145
DEF_MOD("csi42", 401, R8A779A0_CLK_CSI0),
+21
drivers/clk/renesas/r8a779h0-cpg-mssr.c
+21
drivers/clk/renesas/r8a779h0-cpg-mssr.c
···
184
184
DEF_MOD("i2c1", 519, R8A779H0_CLK_S0D6_PER),
185
185
DEF_MOD("i2c2", 520, R8A779H0_CLK_S0D6_PER),
186
186
DEF_MOD("i2c3", 521, R8A779H0_CLK_S0D6_PER),
187
+
DEF_MOD("irqc", 611, R8A779H0_CLK_CL16M),
188
+
DEF_MOD("msi0", 618, R8A779H0_CLK_MSO),
189
+
DEF_MOD("msi1", 619, R8A779H0_CLK_MSO),
190
+
DEF_MOD("msi2", 620, R8A779H0_CLK_MSO),
191
+
DEF_MOD("msi3", 621, R8A779H0_CLK_MSO),
192
+
DEF_MOD("msi4", 622, R8A779H0_CLK_MSO),
193
+
DEF_MOD("msi5", 623, R8A779H0_CLK_MSO),
187
194
DEF_MOD("rpc-if", 629, R8A779H0_CLK_RPCD2),
195
+
DEF_MOD("scif0", 702, R8A779H0_CLK_SASYNCPERD4),
196
+
DEF_MOD("scif1", 703, R8A779H0_CLK_SASYNCPERD4),
197
+
DEF_MOD("scif3", 704, R8A779H0_CLK_SASYNCPERD4),
198
+
DEF_MOD("scif4", 705, R8A779H0_CLK_SASYNCPERD4),
188
199
DEF_MOD("sdhi0", 706, R8A779H0_CLK_SD0),
189
200
DEF_MOD("sydm1", 709, R8A779H0_CLK_S0D6_PER),
190
201
DEF_MOD("sydm2", 710, R8A779H0_CLK_S0D6_PER),
202
+
DEF_MOD("tmu0", 713, R8A779H0_CLK_SASYNCRT),
203
+
DEF_MOD("tmu1", 714, R8A779H0_CLK_SASYNCPERD2),
204
+
DEF_MOD("tmu2", 715, R8A779H0_CLK_SASYNCPERD2),
205
+
DEF_MOD("tmu3", 716, R8A779H0_CLK_SASYNCPERD2),
206
+
DEF_MOD("tmu4", 717, R8A779H0_CLK_SASYNCPERD2),
191
207
DEF_MOD("wdt1:wdt0", 907, R8A779H0_CLK_R),
208
+
DEF_MOD("cmt0", 910, R8A779H0_CLK_R),
209
+
DEF_MOD("cmt1", 911, R8A779H0_CLK_R),
210
+
DEF_MOD("cmt2", 912, R8A779H0_CLK_R),
211
+
DEF_MOD("cmt3", 913, R8A779H0_CLK_R),
192
212
DEF_MOD("pfc0", 915, R8A779H0_CLK_CP),
193
213
DEF_MOD("pfc1", 916, R8A779H0_CLK_CP),
194
214
DEF_MOD("pfc2", 917, R8A779H0_CLK_CP),
215
+
DEF_MOD("tsc2:tsc1", 919, R8A779H0_CLK_CL16M),
195
216
};
196
217
197
218
/*
+11
-2
drivers/clk/renesas/r9a07g043-cpg.c
+11
-2
drivers/clk/renesas/r9a07g043-cpg.c
···
149
149
#endif
150
150
};
151
151
152
-
static struct rzg2l_mod_clk r9a07g043_mod_clks[] = {
152
+
static const struct rzg2l_mod_clk r9a07g043_mod_clks[] = {
153
153
#ifdef CONFIG_ARM64
154
154
DEF_MOD("gic", R9A07G043_GIC600_GICCLK, R9A07G043_CLK_P1,
155
155
0x514, 0),
···
280
280
0x5a8, 1),
281
281
DEF_MOD("tsu_pclk", R9A07G043_TSU_PCLK, R9A07G043_CLK_TSU,
282
282
0x5ac, 0),
283
+
#ifdef CONFIG_RISCV
284
+
DEF_MOD("nceplic_aclk", R9A07G043_NCEPLIC_ACLK, R9A07G043_CLK_P1,
285
+
0x608, 0),
286
+
#endif
283
287
};
284
288
285
-
static struct rzg2l_reset r9a07g043_resets[] = {
289
+
static const struct rzg2l_reset r9a07g043_resets[] = {
286
290
#ifdef CONFIG_ARM64
287
291
DEF_RST(R9A07G043_GIC600_GICRESET_N, 0x814, 0),
288
292
DEF_RST(R9A07G043_GIC600_DBG_GICRESET_N, 0x814, 1),
···
342
338
DEF_RST(R9A07G043_ADC_PRESETN, 0x8a8, 0),
343
339
DEF_RST(R9A07G043_ADC_ADRST_N, 0x8a8, 1),
344
340
DEF_RST(R9A07G043_TSU_PRESETN, 0x8ac, 0),
341
+
#ifdef CONFIG_RISCV
342
+
DEF_RST(R9A07G043_NCEPLIC_ARESETN, 0x908, 0),
343
+
#endif
344
+
345
345
};
346
346
347
347
static const unsigned int r9a07g043_crit_mod_clks[] __initconst = {
···
355
347
#endif
356
348
#ifdef CONFIG_RISCV
357
349
MOD_CLK_BASE + R9A07G043_IAX45_CLK,
350
+
MOD_CLK_BASE + R9A07G043_NCEPLIC_ACLK,
358
351
#endif
359
352
MOD_CLK_BASE + R9A07G043_DMAC_ACLK,
360
353
};
+1
-1
drivers/clk/renesas/r9a07g044-cpg.c
+1
-1
drivers/clk/renesas/r9a07g044-cpg.c
···
368
368
#endif
369
369
};
370
370
371
-
static struct rzg2l_reset r9a07g044_resets[] = {
371
+
static const struct rzg2l_reset r9a07g044_resets[] = {
372
372
DEF_RST(R9A07G044_GIC600_GICRESET_N, 0x814, 0),
373
373
DEF_RST(R9A07G044_GIC600_DBG_GICRESET_N, 0x814, 1),
374
374
DEF_RST(R9A07G044_IA55_RESETN, 0x818, 0),
+41
drivers/clk/renesas/r9a08g045-cpg.c
+41
drivers/clk/renesas/r9a08g045-cpg.c
···
240
240
MOD_CLK_BASE + R9A08G045_DMAC_ACLK,
241
241
};
242
242
243
+
static const struct rzg2l_cpg_pm_domain_init_data r9a08g045_pm_domains[] = {
244
+
/* Keep always-on domain on the first position for proper domains registration. */
245
+
DEF_PD("always-on", R9A08G045_PD_ALWAYS_ON,
246
+
DEF_REG_CONF(0, 0),
247
+
RZG2L_PD_F_ALWAYS_ON),
248
+
DEF_PD("gic", R9A08G045_PD_GIC,
249
+
DEF_REG_CONF(CPG_BUS_ACPU_MSTOP, BIT(3)),
250
+
RZG2L_PD_F_ALWAYS_ON),
251
+
DEF_PD("ia55", R9A08G045_PD_IA55,
252
+
DEF_REG_CONF(CPG_BUS_PERI_CPU_MSTOP, BIT(13)),
253
+
RZG2L_PD_F_ALWAYS_ON),
254
+
DEF_PD("dmac", R9A08G045_PD_DMAC,
255
+
DEF_REG_CONF(CPG_BUS_REG1_MSTOP, GENMASK(3, 0)),
256
+
RZG2L_PD_F_ALWAYS_ON),
257
+
DEF_PD("wdt0", R9A08G045_PD_WDT0,
258
+
DEF_REG_CONF(CPG_BUS_REG0_MSTOP, BIT(0)),
259
+
RZG2L_PD_F_NONE),
260
+
DEF_PD("sdhi0", R9A08G045_PD_SDHI0,
261
+
DEF_REG_CONF(CPG_BUS_PERI_COM_MSTOP, BIT(0)),
262
+
RZG2L_PD_F_NONE),
263
+
DEF_PD("sdhi1", R9A08G045_PD_SDHI1,
264
+
DEF_REG_CONF(CPG_BUS_PERI_COM_MSTOP, BIT(1)),
265
+
RZG2L_PD_F_NONE),
266
+
DEF_PD("sdhi2", R9A08G045_PD_SDHI2,
267
+
DEF_REG_CONF(CPG_BUS_PERI_COM_MSTOP, BIT(11)),
268
+
RZG2L_PD_F_NONE),
269
+
DEF_PD("eth0", R9A08G045_PD_ETHER0,
270
+
DEF_REG_CONF(CPG_BUS_PERI_COM_MSTOP, BIT(2)),
271
+
RZG2L_PD_F_NONE),
272
+
DEF_PD("eth1", R9A08G045_PD_ETHER1,
273
+
DEF_REG_CONF(CPG_BUS_PERI_COM_MSTOP, BIT(3)),
274
+
RZG2L_PD_F_NONE),
275
+
DEF_PD("scif0", R9A08G045_PD_SCIF0,
276
+
DEF_REG_CONF(CPG_BUS_MCPU2_MSTOP, BIT(1)),
277
+
RZG2L_PD_F_NONE),
278
+
};
279
+
243
280
const struct rzg2l_cpg_info r9a08g045_cpg_info = {
244
281
/* Core Clocks */
245
282
.core_clks = r9a08g045_core_clks,
···
296
259
/* Resets */
297
260
.resets = r9a08g045_resets,
298
261
.num_resets = R9A08G045_VBAT_BRESETN + 1, /* Last reset ID + 1 */
262
+
263
+
/* Power domains */
264
+
.pm_domains = r9a08g045_pm_domains,
265
+
.num_pm_domains = ARRAY_SIZE(r9a08g045_pm_domains),
299
266
300
267
.has_clk_mon_regs = true,
301
268
};
+185
-14
drivers/clk/renesas/rzg2l-cpg.c
+185
-14
drivers/clk/renesas/rzg2l-cpg.c
···
139
139
* @num_resets: Number of Module Resets in info->resets[]
140
140
* @last_dt_core_clk: ID of the last Core Clock exported to DT
141
141
* @info: Pointer to platform data
142
-
* @genpd: PM domain
143
142
* @mux_dsi_div_params: pll5 mux and dsi div parameters
144
143
*/
145
144
struct rzg2l_cpg_priv {
···
154
155
unsigned int last_dt_core_clk;
155
156
156
157
const struct rzg2l_cpg_info *info;
157
-
158
-
struct generic_pm_domain genpd;
159
158
160
159
struct rzg2l_pll5_mux_dsi_div_param mux_dsi_div_params;
161
160
};
···
1556
1559
return true;
1557
1560
}
1558
1561
1562
+
/**
1563
+
* struct rzg2l_cpg_pm_domains - RZ/G2L PM domains data structure
1564
+
* @onecell_data: cell data
1565
+
* @domains: generic PM domains
1566
+
*/
1567
+
struct rzg2l_cpg_pm_domains {
1568
+
struct genpd_onecell_data onecell_data;
1569
+
struct generic_pm_domain *domains[];
1570
+
};
1571
+
1572
+
/**
1573
+
* struct rzg2l_cpg_pd - RZ/G2L power domain data structure
1574
+
* @genpd: generic PM domain
1575
+
* @priv: pointer to CPG private data structure
1576
+
* @conf: CPG PM domain configuration info
1577
+
* @id: RZ/G2L power domain ID
1578
+
*/
1579
+
struct rzg2l_cpg_pd {
1580
+
struct generic_pm_domain genpd;
1581
+
struct rzg2l_cpg_priv *priv;
1582
+
struct rzg2l_cpg_pm_domain_conf conf;
1583
+
u16 id;
1584
+
};
1585
+
1559
1586
static int rzg2l_cpg_attach_dev(struct generic_pm_domain *domain, struct device *dev)
1560
1587
{
1561
-
struct rzg2l_cpg_priv *priv = container_of(domain, struct rzg2l_cpg_priv, genpd);
1588
+
struct rzg2l_cpg_pd *pd = container_of(domain, struct rzg2l_cpg_pd, genpd);
1589
+
struct rzg2l_cpg_priv *priv = pd->priv;
1562
1590
struct device_node *np = dev->of_node;
1563
1591
struct of_phandle_args clkspec;
1564
1592
bool once = true;
···
1640
1618
1641
1619
static void rzg2l_cpg_genpd_remove(void *data)
1642
1620
{
1621
+
struct genpd_onecell_data *celldata = data;
1622
+
1623
+
for (unsigned int i = 0; i < celldata->num_domains; i++)
1624
+
pm_genpd_remove(celldata->domains[i]);
1625
+
}
1626
+
1627
+
static void rzg2l_cpg_genpd_remove_simple(void *data)
1628
+
{
1643
1629
pm_genpd_remove(data);
1630
+
}
1631
+
1632
+
static int rzg2l_cpg_power_on(struct generic_pm_domain *domain)
1633
+
{
1634
+
struct rzg2l_cpg_pd *pd = container_of(domain, struct rzg2l_cpg_pd, genpd);
1635
+
struct rzg2l_cpg_reg_conf mstop = pd->conf.mstop;
1636
+
struct rzg2l_cpg_priv *priv = pd->priv;
1637
+
1638
+
/* Set MSTOP. */
1639
+
if (mstop.mask)
1640
+
writel(mstop.mask << 16, priv->base + mstop.off);
1641
+
1642
+
return 0;
1643
+
}
1644
+
1645
+
static int rzg2l_cpg_power_off(struct generic_pm_domain *domain)
1646
+
{
1647
+
struct rzg2l_cpg_pd *pd = container_of(domain, struct rzg2l_cpg_pd, genpd);
1648
+
struct rzg2l_cpg_reg_conf mstop = pd->conf.mstop;
1649
+
struct rzg2l_cpg_priv *priv = pd->priv;
1650
+
1651
+
/* Set MSTOP. */
1652
+
if (mstop.mask)
1653
+
writel(mstop.mask | (mstop.mask << 16), priv->base + mstop.off);
1654
+
1655
+
return 0;
1656
+
}
1657
+
1658
+
static int __init rzg2l_cpg_pd_setup(struct rzg2l_cpg_pd *pd, bool always_on)
1659
+
{
1660
+
struct dev_power_governor *governor;
1661
+
1662
+
pd->genpd.flags |= GENPD_FLAG_PM_CLK | GENPD_FLAG_ACTIVE_WAKEUP;
1663
+
pd->genpd.attach_dev = rzg2l_cpg_attach_dev;
1664
+
pd->genpd.detach_dev = rzg2l_cpg_detach_dev;
1665
+
if (always_on) {
1666
+
pd->genpd.flags |= GENPD_FLAG_ALWAYS_ON;
1667
+
governor = &pm_domain_always_on_gov;
1668
+
} else {
1669
+
pd->genpd.power_on = rzg2l_cpg_power_on;
1670
+
pd->genpd.power_off = rzg2l_cpg_power_off;
1671
+
governor = &simple_qos_governor;
1672
+
}
1673
+
1674
+
return pm_genpd_init(&pd->genpd, governor, !always_on);
1644
1675
}
1645
1676
1646
1677
static int __init rzg2l_cpg_add_clk_domain(struct rzg2l_cpg_priv *priv)
1647
1678
{
1648
1679
struct device *dev = priv->dev;
1649
1680
struct device_node *np = dev->of_node;
1650
-
struct generic_pm_domain *genpd = &priv->genpd;
1681
+
struct rzg2l_cpg_pd *pd;
1651
1682
int ret;
1652
1683
1653
-
genpd->name = np->name;
1654
-
genpd->flags = GENPD_FLAG_PM_CLK | GENPD_FLAG_ALWAYS_ON |
1655
-
GENPD_FLAG_ACTIVE_WAKEUP;
1656
-
genpd->attach_dev = rzg2l_cpg_attach_dev;
1657
-
genpd->detach_dev = rzg2l_cpg_detach_dev;
1658
-
ret = pm_genpd_init(genpd, &pm_domain_always_on_gov, false);
1684
+
pd = devm_kzalloc(dev, sizeof(*pd), GFP_KERNEL);
1685
+
if (!pd)
1686
+
return -ENOMEM;
1687
+
1688
+
pd->genpd.name = np->name;
1689
+
pd->priv = priv;
1690
+
ret = rzg2l_cpg_pd_setup(pd, true);
1659
1691
if (ret)
1660
1692
return ret;
1661
1693
1662
-
ret = devm_add_action_or_reset(dev, rzg2l_cpg_genpd_remove, genpd);
1694
+
ret = devm_add_action_or_reset(dev, rzg2l_cpg_genpd_remove_simple, &pd->genpd);
1663
1695
if (ret)
1664
1696
return ret;
1665
1697
1666
-
return of_genpd_add_provider_simple(np, genpd);
1698
+
return of_genpd_add_provider_simple(np, &pd->genpd);
1699
+
}
1700
+
1701
+
static struct generic_pm_domain *
1702
+
rzg2l_cpg_pm_domain_xlate(const struct of_phandle_args *spec, void *data)
1703
+
{
1704
+
struct generic_pm_domain *domain = ERR_PTR(-ENOENT);
1705
+
struct genpd_onecell_data *genpd = data;
1706
+
1707
+
if (spec->args_count != 1)
1708
+
return ERR_PTR(-EINVAL);
1709
+
1710
+
for (unsigned int i = 0; i < genpd->num_domains; i++) {
1711
+
struct rzg2l_cpg_pd *pd = container_of(genpd->domains[i], struct rzg2l_cpg_pd,
1712
+
genpd);
1713
+
1714
+
if (pd->id == spec->args[0]) {
1715
+
domain = &pd->genpd;
1716
+
break;
1717
+
}
1718
+
}
1719
+
1720
+
return domain;
1721
+
}
1722
+
1723
+
static int __init rzg2l_cpg_add_pm_domains(struct rzg2l_cpg_priv *priv)
1724
+
{
1725
+
const struct rzg2l_cpg_info *info = priv->info;
1726
+
struct device *dev = priv->dev;
1727
+
struct device_node *np = dev->of_node;
1728
+
struct rzg2l_cpg_pm_domains *domains;
1729
+
struct generic_pm_domain *parent;
1730
+
u32 ncells;
1731
+
int ret;
1732
+
1733
+
ret = of_property_read_u32(np, "#power-domain-cells", &ncells);
1734
+
if (ret)
1735
+
return ret;
1736
+
1737
+
/* For backward compatibility. */
1738
+
if (!ncells)
1739
+
return rzg2l_cpg_add_clk_domain(priv);
1740
+
1741
+
domains = devm_kzalloc(dev, struct_size(domains, domains, info->num_pm_domains),
1742
+
GFP_KERNEL);
1743
+
if (!domains)
1744
+
return -ENOMEM;
1745
+
1746
+
domains->onecell_data.domains = domains->domains;
1747
+
domains->onecell_data.num_domains = info->num_pm_domains;
1748
+
domains->onecell_data.xlate = rzg2l_cpg_pm_domain_xlate;
1749
+
1750
+
ret = devm_add_action_or_reset(dev, rzg2l_cpg_genpd_remove, &domains->onecell_data);
1751
+
if (ret)
1752
+
return ret;
1753
+
1754
+
for (unsigned int i = 0; i < info->num_pm_domains; i++) {
1755
+
bool always_on = !!(info->pm_domains[i].flags & RZG2L_PD_F_ALWAYS_ON);
1756
+
struct rzg2l_cpg_pd *pd;
1757
+
1758
+
pd = devm_kzalloc(dev, sizeof(*pd), GFP_KERNEL);
1759
+
if (!pd)
1760
+
return -ENOMEM;
1761
+
1762
+
pd->genpd.name = info->pm_domains[i].name;
1763
+
pd->conf = info->pm_domains[i].conf;
1764
+
pd->id = info->pm_domains[i].id;
1765
+
pd->priv = priv;
1766
+
1767
+
ret = rzg2l_cpg_pd_setup(pd, always_on);
1768
+
if (ret)
1769
+
return ret;
1770
+
1771
+
if (always_on) {
1772
+
ret = rzg2l_cpg_power_on(&pd->genpd);
1773
+
if (ret)
1774
+
return ret;
1775
+
}
1776
+
1777
+
domains->domains[i] = &pd->genpd;
1778
+
/* Parent should be on the very first entry of info->pm_domains[]. */
1779
+
if (!i) {
1780
+
parent = &pd->genpd;
1781
+
continue;
1782
+
}
1783
+
1784
+
ret = pm_genpd_add_subdomain(parent, &pd->genpd);
1785
+
if (ret)
1786
+
return ret;
1787
+
}
1788
+
1789
+
ret = of_genpd_add_provider_onecell(np, &domains->onecell_data);
1790
+
if (ret)
1791
+
return ret;
1792
+
1793
+
return 0;
1667
1794
}
1668
1795
1669
1796
static int __init rzg2l_cpg_probe(struct platform_device *pdev)
···
1868
1697
if (error)
1869
1698
return error;
1870
1699
1871
-
error = rzg2l_cpg_add_clk_domain(priv);
1700
+
error = rzg2l_cpg_add_pm_domains(priv);
1872
1701
if (error)
1873
1702
return error;
1874
1703
+67
drivers/clk/renesas/rzg2l-cpg.h
+67
drivers/clk/renesas/rzg2l-cpg.h
···
27
27
#define CPG_PL6_ETH_SSEL (0x418)
28
28
#define CPG_PL5_SDIV (0x420)
29
29
#define CPG_RST_MON (0x680)
30
+
#define CPG_BUS_ACPU_MSTOP (0xB60)
31
+
#define CPG_BUS_MCPU1_MSTOP (0xB64)
32
+
#define CPG_BUS_MCPU2_MSTOP (0xB68)
33
+
#define CPG_BUS_PERI_COM_MSTOP (0xB6C)
34
+
#define CPG_BUS_PERI_CPU_MSTOP (0xB70)
35
+
#define CPG_BUS_PERI_DDR_MSTOP (0xB74)
36
+
#define CPG_BUS_REG0_MSTOP (0xB7C)
37
+
#define CPG_BUS_REG1_MSTOP (0xB80)
38
+
#define CPG_BUS_TZCDDR_MSTOP (0xB84)
39
+
#define CPG_MHU_MSTOP (0xB88)
40
+
#define CPG_BUS_MCPU3_MSTOP (0xB90)
41
+
#define CPG_BUS_PERI_CPU2_MSTOP (0xB94)
30
42
#define CPG_OTHERFUNC1_REG (0xBE8)
31
43
32
44
#define CPG_SIPLL5_STBY_RESETB BIT(0)
···
247
235
DEF_RST_MON(_id, _off, _bit, -1)
248
236
249
237
/**
238
+
* struct rzg2l_cpg_reg_conf - RZ/G2L register configuration data structure
239
+
* @off: register offset
240
+
* @mask: register mask
241
+
*/
242
+
struct rzg2l_cpg_reg_conf {
243
+
u16 off;
244
+
u16 mask;
245
+
};
246
+
247
+
#define DEF_REG_CONF(_off, _mask) ((struct rzg2l_cpg_reg_conf) { .off = (_off), .mask = (_mask) })
248
+
249
+
/**
250
+
* struct rzg2l_cpg_pm_domain_conf - PM domain configuration data structure
251
+
* @mstop: MSTOP register configuration
252
+
*/
253
+
struct rzg2l_cpg_pm_domain_conf {
254
+
struct rzg2l_cpg_reg_conf mstop;
255
+
};
256
+
257
+
/**
258
+
* struct rzg2l_cpg_pm_domain_init_data - PM domain init data
259
+
* @name: PM domain name
260
+
* @conf: PM domain configuration
261
+
* @flags: RZG2L PM domain flags (see RZG2L_PD_F_*)
262
+
* @id: PM domain ID (similar to the ones defined in
263
+
* include/dt-bindings/clock/<soc-id>-cpg.h)
264
+
*/
265
+
struct rzg2l_cpg_pm_domain_init_data {
266
+
const char * const name;
267
+
struct rzg2l_cpg_pm_domain_conf conf;
268
+
u32 flags;
269
+
u16 id;
270
+
};
271
+
272
+
#define DEF_PD(_name, _id, _mstop_conf, _flags) \
273
+
{ \
274
+
.name = (_name), \
275
+
.id = (_id), \
276
+
.conf = { \
277
+
.mstop = (_mstop_conf), \
278
+
}, \
279
+
.flags = (_flags), \
280
+
}
281
+
282
+
/* Power domain flags. */
283
+
#define RZG2L_PD_F_ALWAYS_ON BIT(0)
284
+
#define RZG2L_PD_F_NONE (0)
285
+
286
+
/**
250
287
* struct rzg2l_cpg_info - SoC-specific CPG Description
251
288
*
252
289
* @core_clks: Array of Core Clock definitions
···
313
252
* @crit_mod_clks: Array with Module Clock IDs of critical clocks that
314
253
* should not be disabled without a knowledgeable driver
315
254
* @num_crit_mod_clks: Number of entries in crit_mod_clks[]
255
+
* @pm_domains: PM domains init data array
256
+
* @num_pm_domains: Number of PM domains
316
257
* @has_clk_mon_regs: Flag indicating whether the SoC has CLK_MON registers
317
258
*/
318
259
struct rzg2l_cpg_info {
···
340
277
/* Critical Module Clocks that should not be disabled */
341
278
const unsigned int *crit_mod_clks;
342
279
unsigned int num_crit_mod_clks;
280
+
281
+
/* Power domain. */
282
+
const struct rzg2l_cpg_pm_domain_init_data *pm_domains;
283
+
unsigned int num_pm_domains;
343
284
344
285
bool has_clk_mon_regs;
345
286
};
-1
drivers/clk/rockchip/clk-mmc-phase.c
-1
drivers/clk/rockchip/clk-mmc-phase.c
+5
drivers/clk/rockchip/clk-rk3568.c
+5
drivers/clk/rockchip/clk-rk3568.c
···
64
64
RK3036_PLL_RATE(912000000, 1, 76, 2, 1, 1, 0),
65
65
RK3036_PLL_RATE(816000000, 1, 68, 2, 1, 1, 0),
66
66
RK3036_PLL_RATE(800000000, 3, 200, 2, 1, 1, 0),
67
+
RK3036_PLL_RATE(724000000, 3, 181, 2, 1, 1, 0),
67
68
RK3036_PLL_RATE(700000000, 3, 350, 4, 1, 1, 0),
68
69
RK3036_PLL_RATE(696000000, 1, 116, 4, 1, 1, 0),
69
70
RK3036_PLL_RATE(600000000, 1, 100, 4, 1, 1, 0),
···
216
215
217
216
PNAME(mux_pll_p) = { "xin24m" };
218
217
PNAME(mux_usb480m_p) = { "xin24m", "usb480m_phy", "clk_rtc_32k" };
218
+
PNAME(mux_usb480m_phy_p) = { "clk_usbphy0_480m", "clk_usbphy1_480m"};
219
219
PNAME(mux_armclk_p) = { "apll", "gpll" };
220
220
PNAME(clk_i2s0_8ch_tx_p) = { "clk_i2s0_8ch_tx_src", "clk_i2s0_8ch_tx_frac", "i2s0_mclkin", "xin_osc0_half" };
221
221
PNAME(clk_i2s0_8ch_rx_p) = { "clk_i2s0_8ch_rx_src", "clk_i2s0_8ch_rx_frac", "i2s0_mclkin", "xin_osc0_half" };
···
486
484
FACTOR(0, "xin_osc0_half", "xin24m", 0, 1, 2),
487
485
MUX(USB480M, "usb480m", mux_usb480m_p, CLK_SET_RATE_PARENT,
488
486
RK3568_MODE_CON0, 14, 2, MFLAGS),
487
+
488
+
MUX(USB480M_PHY, "usb480m_phy", mux_usb480m_phy_p, CLK_SET_RATE_PARENT,
489
+
RK3568_MISC_CON2, 15, 1, MFLAGS),
489
490
490
491
/* PD_CORE */
491
492
COMPOSITE(0, "sclk_core_src", apll_gpll_npll_p, CLK_IGNORE_UNUSED,
+1
drivers/clk/rockchip/rst-rk3588.c
+1
drivers/clk/rockchip/rst-rk3588.c
···
577
577
578
578
/* SOFTRST_CON59 */
579
579
RK3588_CRU_RESET_OFFSET(SRST_A_HDCP1_BIU, 59, 6),
580
+
RK3588_CRU_RESET_OFFSET(SRST_A_HDMIRX_BIU, 59, 7),
580
581
RK3588_CRU_RESET_OFFSET(SRST_A_VO1_BIU, 59, 8),
581
582
RK3588_CRU_RESET_OFFSET(SRST_H_VOP1_BIU, 59, 9),
582
583
RK3588_CRU_RESET_OFFSET(SRST_H_VOP1_S_BIU, 59, 10),
+41
-15
drivers/clk/samsung/clk-exynos-arm64.c
+41
-15
drivers/clk/samsung/clk-exynos-arm64.c
···
17
17
18
18
#include "clk-exynos-arm64.h"
19
19
20
+
/* PLL register bits */
21
+
#define PLL_CON1_MANUAL BIT(1)
22
+
20
23
/* Gate register bits */
21
24
#define GATE_MANUAL BIT(20)
22
25
#define GATE_ENABLE_HWACG BIT(28)
26
+
27
+
/* PLL_CONx_PLL register offsets range */
28
+
#define PLL_CON_OFF_START 0x100
29
+
#define PLL_CON_OFF_END 0x600
23
30
24
31
/* Gate register offsets range */
25
32
#define GATE_OFF_START 0x2000
···
45
38
struct samsung_clk_provider *ctx;
46
39
};
47
40
41
+
/* Check if the register offset is a GATE register */
42
+
static bool is_gate_reg(unsigned long off)
43
+
{
44
+
return off >= GATE_OFF_START && off <= GATE_OFF_END;
45
+
}
46
+
47
+
/* Check if the register offset is a PLL_CONx register */
48
+
static bool is_pll_conx_reg(unsigned long off)
49
+
{
50
+
return off >= PLL_CON_OFF_START && off <= PLL_CON_OFF_END;
51
+
}
52
+
53
+
/* Check if the register offset is a PLL_CON1 register */
54
+
static bool is_pll_con1_reg(unsigned long off)
55
+
{
56
+
return is_pll_conx_reg(off) && (off & 0xf) == 0x4 && !(off & 0x10);
57
+
}
58
+
48
59
/**
49
60
* exynos_arm64_init_clocks - Set clocks initial configuration
50
-
* @np: CMU device tree node with "reg" property (CMU addr)
51
-
* @reg_offs: Register offsets array for clocks to init
52
-
* @reg_offs_len: Number of register offsets in reg_offs array
61
+
* @np: CMU device tree node with "reg" property (CMU addr)
62
+
* @cmu: CMU data
53
63
*
54
-
* Set manual control mode for all gate clocks.
64
+
* Set manual control mode for all gate and PLL clocks.
55
65
*/
56
66
static void __init exynos_arm64_init_clocks(struct device_node *np,
57
-
const unsigned long *reg_offs, size_t reg_offs_len)
67
+
const struct samsung_cmu_info *cmu)
58
68
{
69
+
const unsigned long *reg_offs = cmu->clk_regs;
70
+
size_t reg_offs_len = cmu->nr_clk_regs;
59
71
void __iomem *reg_base;
60
72
size_t i;
61
73
···
86
60
void __iomem *reg = reg_base + reg_offs[i];
87
61
u32 val;
88
62
89
-
/* Modify only gate clock registers */
90
-
if (reg_offs[i] < GATE_OFF_START || reg_offs[i] > GATE_OFF_END)
91
-
continue;
92
-
93
-
val = readl(reg);
94
-
val |= GATE_MANUAL;
95
-
val &= ~GATE_ENABLE_HWACG;
96
-
writel(val, reg);
63
+
if (cmu->manual_plls && is_pll_con1_reg(reg_offs[i])) {
64
+
writel(PLL_CON1_MANUAL, reg);
65
+
} else if (is_gate_reg(reg_offs[i])) {
66
+
val = readl(reg);
67
+
val |= GATE_MANUAL;
68
+
val &= ~GATE_ENABLE_HWACG;
69
+
writel(val, reg);
70
+
}
97
71
}
98
72
99
73
iounmap(reg_base);
···
203
177
pr_err("%s: could not enable bus clock %s; err = %d\n",
204
178
__func__, cmu->clk_name, err);
205
179
206
-
exynos_arm64_init_clocks(np, cmu->clk_regs, cmu->nr_clk_regs);
180
+
exynos_arm64_init_clocks(np, cmu);
207
181
samsung_cmu_register_one(np, cmu);
208
182
}
209
183
···
250
224
__func__, cmu->clk_name, ret);
251
225
252
226
if (set_manual)
253
-
exynos_arm64_init_clocks(np, cmu->clk_regs, cmu->nr_clk_regs);
227
+
exynos_arm64_init_clocks(np, cmu);
254
228
255
229
reg_base = devm_platform_ioremap_resource(pdev, 0);
256
230
if (IS_ERR(reg_base))
+439
-1
drivers/clk/samsung/clk-exynos850.c
+439
-1
drivers/clk/samsung/clk-exynos850.c
···
14
14
#include <dt-bindings/clock/exynos850.h>
15
15
16
16
#include "clk.h"
17
+
#include "clk-cpu.h"
17
18
#include "clk-exynos-arm64.h"
18
19
19
20
/* NOTE: Must be equal to the last clock ID increased by one */
20
-
#define CLKS_NR_TOP (CLK_DOUT_G3D_SWITCH + 1)
21
+
#define CLKS_NR_TOP (CLK_DOUT_CPUCL1_SWITCH + 1)
21
22
#define CLKS_NR_APM (CLK_GOUT_SYSREG_APM_PCLK + 1)
22
23
#define CLKS_NR_AUD (CLK_GOUT_AUD_CMU_AUD_PCLK + 1)
23
24
#define CLKS_NR_CMGP (CLK_GOUT_SYSREG_CMGP_PCLK + 1)
25
+
#define CLKS_NR_CPUCL0 (CLK_CLUSTER0_SCLK + 1)
26
+
#define CLKS_NR_CPUCL1 (CLK_CLUSTER1_SCLK + 1)
24
27
#define CLKS_NR_G3D (CLK_GOUT_G3D_SYSREG_PCLK + 1)
25
28
#define CLKS_NR_HSI (CLK_GOUT_HSI_CMU_HSI_PCLK + 1)
26
29
#define CLKS_NR_IS (CLK_GOUT_IS_SYSREG_PCLK + 1)
···
50
47
#define CLK_CON_MUX_MUX_CLKCMU_CORE_CCI 0x1018
51
48
#define CLK_CON_MUX_MUX_CLKCMU_CORE_MMC_EMBD 0x101c
52
49
#define CLK_CON_MUX_MUX_CLKCMU_CORE_SSS 0x1020
50
+
#define CLK_CON_MUX_MUX_CLKCMU_CPUCL0_DBG 0x1024
51
+
#define CLK_CON_MUX_MUX_CLKCMU_CPUCL0_SWITCH 0x1028
52
+
#define CLK_CON_MUX_MUX_CLKCMU_CPUCL1_DBG 0x102c
53
+
#define CLK_CON_MUX_MUX_CLKCMU_CPUCL1_SWITCH 0x1030
53
54
#define CLK_CON_MUX_MUX_CLKCMU_DPU 0x1034
54
55
#define CLK_CON_MUX_MUX_CLKCMU_G3D_SWITCH 0x1038
55
56
#define CLK_CON_MUX_MUX_CLKCMU_HSI_BUS 0x103c
···
76
69
#define CLK_CON_DIV_CLKCMU_CORE_CCI 0x1824
77
70
#define CLK_CON_DIV_CLKCMU_CORE_MMC_EMBD 0x1828
78
71
#define CLK_CON_DIV_CLKCMU_CORE_SSS 0x182c
72
+
#define CLK_CON_DIV_CLKCMU_CPUCL0_DBG 0x1830
73
+
#define CLK_CON_DIV_CLKCMU_CPUCL0_SWITCH 0x1834
74
+
#define CLK_CON_DIV_CLKCMU_CPUCL1_DBG 0x1838
75
+
#define CLK_CON_DIV_CLKCMU_CPUCL1_SWITCH 0x183c
79
76
#define CLK_CON_DIV_CLKCMU_DPU 0x1840
80
77
#define CLK_CON_DIV_CLKCMU_G3D_SWITCH 0x1844
81
78
#define CLK_CON_DIV_CLKCMU_HSI_BUS 0x1848
···
108
97
#define CLK_CON_GAT_GATE_CLKCMU_CORE_CCI 0x2020
109
98
#define CLK_CON_GAT_GATE_CLKCMU_CORE_MMC_EMBD 0x2024
110
99
#define CLK_CON_GAT_GATE_CLKCMU_CORE_SSS 0x2028
100
+
#define CLK_CON_GAT_GATE_CLKCMU_CPUCL0_DBG 0x202c
101
+
#define CLK_CON_GAT_GATE_CLKCMU_CPUCL0_SWITCH 0x2030
102
+
#define CLK_CON_GAT_GATE_CLKCMU_CPUCL1_DBG 0x2034
103
+
#define CLK_CON_GAT_GATE_CLKCMU_CPUCL1_SWITCH 0x2038
111
104
#define CLK_CON_GAT_GATE_CLKCMU_DPU 0x203c
112
105
#define CLK_CON_GAT_GATE_CLKCMU_G3D_SWITCH 0x2040
113
106
#define CLK_CON_GAT_GATE_CLKCMU_HSI_BUS 0x2044
···
145
130
CLK_CON_MUX_MUX_CLKCMU_CORE_CCI,
146
131
CLK_CON_MUX_MUX_CLKCMU_CORE_MMC_EMBD,
147
132
CLK_CON_MUX_MUX_CLKCMU_CORE_SSS,
133
+
CLK_CON_MUX_MUX_CLKCMU_CPUCL0_DBG,
134
+
CLK_CON_MUX_MUX_CLKCMU_CPUCL0_SWITCH,
135
+
CLK_CON_MUX_MUX_CLKCMU_CPUCL1_DBG,
136
+
CLK_CON_MUX_MUX_CLKCMU_CPUCL1_SWITCH,
148
137
CLK_CON_MUX_MUX_CLKCMU_DPU,
149
138
CLK_CON_MUX_MUX_CLKCMU_G3D_SWITCH,
150
139
CLK_CON_MUX_MUX_CLKCMU_HSI_BUS,
···
171
152
CLK_CON_DIV_CLKCMU_CORE_CCI,
172
153
CLK_CON_DIV_CLKCMU_CORE_MMC_EMBD,
173
154
CLK_CON_DIV_CLKCMU_CORE_SSS,
155
+
CLK_CON_DIV_CLKCMU_CPUCL0_DBG,
156
+
CLK_CON_DIV_CLKCMU_CPUCL0_SWITCH,
157
+
CLK_CON_DIV_CLKCMU_CPUCL1_DBG,
158
+
CLK_CON_DIV_CLKCMU_CPUCL1_SWITCH,
174
159
CLK_CON_DIV_CLKCMU_DPU,
175
160
CLK_CON_DIV_CLKCMU_G3D_SWITCH,
176
161
CLK_CON_DIV_CLKCMU_HSI_BUS,
···
203
180
CLK_CON_GAT_GATE_CLKCMU_CORE_CCI,
204
181
CLK_CON_GAT_GATE_CLKCMU_CORE_MMC_EMBD,
205
182
CLK_CON_GAT_GATE_CLKCMU_CORE_SSS,
183
+
CLK_CON_GAT_GATE_CLKCMU_CPUCL0_DBG,
184
+
CLK_CON_GAT_GATE_CLKCMU_CPUCL0_SWITCH,
185
+
CLK_CON_GAT_GATE_CLKCMU_CPUCL1_DBG,
186
+
CLK_CON_GAT_GATE_CLKCMU_CPUCL1_SWITCH,
206
187
CLK_CON_GAT_GATE_CLKCMU_DPU,
207
188
CLK_CON_GAT_GATE_CLKCMU_G3D_SWITCH,
208
189
CLK_CON_GAT_GATE_CLKCMU_HSI_BUS,
···
261
234
"oscclk", "oscclk" };
262
235
PNAME(mout_core_sss_p) = { "dout_shared0_div3", "dout_shared1_div3",
263
236
"dout_shared0_div4", "dout_shared1_div4" };
237
+
/* List of parent clocks for Muxes in CMU_TOP: for CMU_CPUCL0 */
238
+
PNAME(mout_cpucl0_switch_p) = { "fout_shared0_pll", "fout_shared1_pll",
239
+
"dout_shared0_div2", "dout_shared1_div2" };
240
+
PNAME(mout_cpucl0_dbg_p) = { "dout_shared0_div4", "dout_shared1_div4" };
241
+
/* List of parent clocks for Muxes in CMU_TOP: for CMU_CPUCL1 */
242
+
PNAME(mout_cpucl1_switch_p) = { "fout_shared0_pll", "fout_shared1_pll",
243
+
"dout_shared0_div2", "dout_shared1_div2" };
244
+
PNAME(mout_cpucl1_dbg_p) = { "dout_shared0_div4", "dout_shared1_div4" };
264
245
/* List of parent clocks for Muxes in CMU_TOP: for CMU_G3D */
265
246
PNAME(mout_g3d_switch_p) = { "dout_shared0_div2", "dout_shared1_div2",
266
247
"dout_shared0_div3", "dout_shared1_div3" };
···
334
299
CLK_CON_MUX_MUX_CLKCMU_CORE_MMC_EMBD, 0, 3),
335
300
MUX(CLK_MOUT_CORE_SSS, "mout_core_sss", mout_core_sss_p,
336
301
CLK_CON_MUX_MUX_CLKCMU_CORE_SSS, 0, 2),
302
+
303
+
/* CPUCL0 */
304
+
MUX(CLK_MOUT_CPUCL0_DBG, "mout_cpucl0_dbg", mout_cpucl0_dbg_p,
305
+
CLK_CON_MUX_MUX_CLKCMU_CPUCL0_DBG, 0, 1),
306
+
MUX(CLK_MOUT_CPUCL0_SWITCH, "mout_cpucl0_switch", mout_cpucl0_switch_p,
307
+
CLK_CON_MUX_MUX_CLKCMU_CPUCL0_SWITCH, 0, 2),
308
+
309
+
/* CPUCL1 */
310
+
MUX(CLK_MOUT_CPUCL1_DBG, "mout_cpucl1_dbg", mout_cpucl1_dbg_p,
311
+
CLK_CON_MUX_MUX_CLKCMU_CPUCL1_DBG, 0, 1),
312
+
MUX(CLK_MOUT_CPUCL1_SWITCH, "mout_cpucl1_switch", mout_cpucl1_switch_p,
313
+
CLK_CON_MUX_MUX_CLKCMU_CPUCL1_SWITCH, 0, 2),
337
314
338
315
/* DPU */
339
316
MUX(CLK_MOUT_DPU, "mout_dpu", mout_dpu_p,
···
425
378
DIV(CLK_DOUT_CORE_SSS, "dout_core_sss", "gout_core_sss",
426
379
CLK_CON_DIV_CLKCMU_CORE_SSS, 0, 4),
427
380
381
+
/* CPUCL0 */
382
+
DIV(CLK_DOUT_CPUCL0_DBG, "dout_cpucl0_dbg", "gout_cpucl0_dbg",
383
+
CLK_CON_DIV_CLKCMU_CPUCL0_DBG, 0, 3),
384
+
DIV(CLK_DOUT_CPUCL0_SWITCH, "dout_cpucl0_switch", "gout_cpucl0_switch",
385
+
CLK_CON_DIV_CLKCMU_CPUCL0_SWITCH, 0, 3),
386
+
387
+
/* CPUCL1 */
388
+
DIV(CLK_DOUT_CPUCL1_DBG, "dout_cpucl1_dbg", "gout_cpucl1_dbg",
389
+
CLK_CON_DIV_CLKCMU_CPUCL1_DBG, 0, 3),
390
+
DIV(CLK_DOUT_CPUCL1_SWITCH, "dout_cpucl1_switch", "gout_cpucl1_switch",
391
+
CLK_CON_DIV_CLKCMU_CPUCL1_SWITCH, 0, 3),
392
+
428
393
/* DPU */
429
394
DIV(CLK_DOUT_DPU, "dout_dpu", "gout_dpu",
430
395
CLK_CON_DIV_CLKCMU_DPU, 0, 4),
···
500
441
/* AUD */
501
442
GATE(CLK_GOUT_AUD, "gout_aud", "mout_aud",
502
443
CLK_CON_GAT_GATE_CLKCMU_AUD, 21, 0, 0),
444
+
445
+
/* CPUCL0 */
446
+
GATE(CLK_GOUT_CPUCL0_DBG, "gout_cpucl0_dbg", "mout_cpucl0_dbg",
447
+
CLK_CON_GAT_GATE_CLKCMU_CPUCL0_DBG, 21, 0, 0),
448
+
GATE(CLK_GOUT_CPUCL0_SWITCH, "gout_cpucl0_switch", "mout_cpucl0_switch",
449
+
CLK_CON_GAT_GATE_CLKCMU_CPUCL0_SWITCH, 21, 0, 0),
450
+
451
+
/* CPUCL1 */
452
+
GATE(CLK_GOUT_CPUCL1_DBG, "gout_cpucl1_dbg", "mout_cpucl1_dbg",
453
+
CLK_CON_GAT_GATE_CLKCMU_CPUCL1_DBG, 21, 0, 0),
454
+
GATE(CLK_GOUT_CPUCL1_SWITCH, "gout_cpucl1_switch", "mout_cpucl1_switch",
455
+
CLK_CON_GAT_GATE_CLKCMU_CPUCL1_SWITCH, 21, 0, 0),
503
456
504
457
/* DPU */
505
458
GATE(CLK_GOUT_DPU, "gout_dpu", "mout_dpu",
···
1100
1029
.nr_clk_regs = ARRAY_SIZE(cmgp_clk_regs),
1101
1030
.clk_name = "gout_clkcmu_cmgp_bus",
1102
1031
};
1032
+
1033
+
/* ---- CMU_CPUCL0 ---------------------------------------------------------- */
1034
+
1035
+
/* Register Offset definitions for CMU_CPUCL0 (0x10900000) */
1036
+
#define PLL_LOCKTIME_PLL_CPUCL0 0x0000
1037
+
#define PLL_CON0_PLL_CPUCL0 0x0100
1038
+
#define PLL_CON1_PLL_CPUCL0 0x0104
1039
+
#define PLL_CON3_PLL_CPUCL0 0x010c
1040
+
#define PLL_CON0_MUX_CLKCMU_CPUCL0_DBG_USER 0x0600
1041
+
#define PLL_CON0_MUX_CLKCMU_CPUCL0_SWITCH_USER 0x0610
1042
+
#define CLK_CON_MUX_MUX_CLK_CPUCL0_PLL 0x100c
1043
+
#define CLK_CON_DIV_DIV_CLK_CLUSTER0_ACLK 0x1800
1044
+
#define CLK_CON_DIV_DIV_CLK_CLUSTER0_ATCLK 0x1808
1045
+
#define CLK_CON_DIV_DIV_CLK_CLUSTER0_PCLKDBG 0x180c
1046
+
#define CLK_CON_DIV_DIV_CLK_CLUSTER0_PERIPHCLK 0x1810
1047
+
#define CLK_CON_DIV_DIV_CLK_CPUCL0_CMUREF 0x1814
1048
+
#define CLK_CON_DIV_DIV_CLK_CPUCL0_CPU 0x1818
1049
+
#define CLK_CON_DIV_DIV_CLK_CPUCL0_PCLK 0x181c
1050
+
#define CLK_CON_GAT_CLK_CPUCL0_CLUSTER0_ATCLK 0x2000
1051
+
#define CLK_CON_GAT_CLK_CPUCL0_CLUSTER0_PCLK 0x2004
1052
+
#define CLK_CON_GAT_CLK_CPUCL0_CLUSTER0_PERIPHCLK 0x2008
1053
+
#define CLK_CON_GAT_CLK_CPUCL0_CLUSTER0_SCLK 0x200c
1054
+
#define CLK_CON_GAT_CLK_CPUCL0_CMU_CPUCL0_PCLK 0x2010
1055
+
#define CLK_CON_GAT_GATE_CLK_CPUCL0_CPU 0x2020
1056
+
1057
+
static const unsigned long cpucl0_clk_regs[] __initconst = {
1058
+
PLL_LOCKTIME_PLL_CPUCL0,
1059
+
PLL_CON0_PLL_CPUCL0,
1060
+
PLL_CON1_PLL_CPUCL0,
1061
+
PLL_CON3_PLL_CPUCL0,
1062
+
PLL_CON0_MUX_CLKCMU_CPUCL0_DBG_USER,
1063
+
PLL_CON0_MUX_CLKCMU_CPUCL0_SWITCH_USER,
1064
+
CLK_CON_MUX_MUX_CLK_CPUCL0_PLL,
1065
+
CLK_CON_DIV_DIV_CLK_CLUSTER0_ACLK,
1066
+
CLK_CON_DIV_DIV_CLK_CLUSTER0_ATCLK,
1067
+
CLK_CON_DIV_DIV_CLK_CLUSTER0_PCLKDBG,
1068
+
CLK_CON_DIV_DIV_CLK_CLUSTER0_PERIPHCLK,
1069
+
CLK_CON_DIV_DIV_CLK_CPUCL0_CMUREF,
1070
+
CLK_CON_DIV_DIV_CLK_CPUCL0_CPU,
1071
+
CLK_CON_DIV_DIV_CLK_CPUCL0_PCLK,
1072
+
CLK_CON_GAT_CLK_CPUCL0_CLUSTER0_ATCLK,
1073
+
CLK_CON_GAT_CLK_CPUCL0_CLUSTER0_PCLK,
1074
+
CLK_CON_GAT_CLK_CPUCL0_CLUSTER0_PERIPHCLK,
1075
+
CLK_CON_GAT_CLK_CPUCL0_CLUSTER0_SCLK,
1076
+
CLK_CON_GAT_CLK_CPUCL0_CMU_CPUCL0_PCLK,
1077
+
CLK_CON_GAT_GATE_CLK_CPUCL0_CPU,
1078
+
};
1079
+
1080
+
/* List of parent clocks for Muxes in CMU_CPUCL0 */
1081
+
PNAME(mout_pll_cpucl0_p) = { "oscclk", "fout_cpucl0_pll" };
1082
+
PNAME(mout_cpucl0_switch_user_p) = { "oscclk", "dout_cpucl0_switch" };
1083
+
PNAME(mout_cpucl0_dbg_user_p) = { "oscclk", "dout_cpucl0_dbg" };
1084
+
PNAME(mout_cpucl0_pll_p) = { "mout_pll_cpucl0",
1085
+
"mout_cpucl0_switch_user" };
1086
+
1087
+
static const struct samsung_pll_rate_table cpu_pll_rates[] __initconst = {
1088
+
PLL_35XX_RATE(26 * MHZ, 2210000000U, 255, 3, 0),
1089
+
PLL_35XX_RATE(26 * MHZ, 2106000000U, 243, 3, 0),
1090
+
PLL_35XX_RATE(26 * MHZ, 2002000000U, 231, 3, 0),
1091
+
PLL_35XX_RATE(26 * MHZ, 1846000000U, 213, 3, 0),
1092
+
PLL_35XX_RATE(26 * MHZ, 1742000000U, 201, 3, 0),
1093
+
PLL_35XX_RATE(26 * MHZ, 1586000000U, 183, 3, 0),
1094
+
PLL_35XX_RATE(26 * MHZ, 1456000000U, 168, 3, 0),
1095
+
PLL_35XX_RATE(26 * MHZ, 1300000000U, 150, 3, 0),
1096
+
PLL_35XX_RATE(26 * MHZ, 1157000000U, 267, 3, 1),
1097
+
PLL_35XX_RATE(26 * MHZ, 1053000000U, 243, 3, 1),
1098
+
PLL_35XX_RATE(26 * MHZ, 949000000U, 219, 3, 1),
1099
+
PLL_35XX_RATE(26 * MHZ, 806000000U, 186, 3, 1),
1100
+
PLL_35XX_RATE(26 * MHZ, 650000000U, 150, 3, 1),
1101
+
PLL_35XX_RATE(26 * MHZ, 546000000U, 252, 3, 2),
1102
+
PLL_35XX_RATE(26 * MHZ, 442000000U, 204, 3, 2),
1103
+
PLL_35XX_RATE(26 * MHZ, 351000000U, 162, 3, 2),
1104
+
PLL_35XX_RATE(26 * MHZ, 247000000U, 114, 3, 2),
1105
+
PLL_35XX_RATE(26 * MHZ, 182000000U, 168, 3, 3),
1106
+
PLL_35XX_RATE(26 * MHZ, 130000000U, 120, 3, 3),
1107
+
};
1108
+
1109
+
static const struct samsung_pll_clock cpucl0_pll_clks[] __initconst = {
1110
+
PLL(pll_0822x, CLK_FOUT_CPUCL0_PLL, "fout_cpucl0_pll", "oscclk",
1111
+
PLL_LOCKTIME_PLL_CPUCL0, PLL_CON3_PLL_CPUCL0, cpu_pll_rates),
1112
+
};
1113
+
1114
+
static const struct samsung_mux_clock cpucl0_mux_clks[] __initconst = {
1115
+
MUX_F(CLK_MOUT_PLL_CPUCL0, "mout_pll_cpucl0", mout_pll_cpucl0_p,
1116
+
PLL_CON0_PLL_CPUCL0, 4, 1,
1117
+
CLK_SET_RATE_PARENT | CLK_RECALC_NEW_RATES, 0),
1118
+
MUX_F(CLK_MOUT_CPUCL0_SWITCH_USER, "mout_cpucl0_switch_user",
1119
+
mout_cpucl0_switch_user_p,
1120
+
PLL_CON0_MUX_CLKCMU_CPUCL0_SWITCH_USER, 4, 1,
1121
+
CLK_SET_RATE_PARENT, 0),
1122
+
MUX(CLK_MOUT_CPUCL0_DBG_USER, "mout_cpucl0_dbg_user",
1123
+
mout_cpucl0_dbg_user_p,
1124
+
PLL_CON0_MUX_CLKCMU_CPUCL0_DBG_USER, 4, 1),
1125
+
MUX_F(CLK_MOUT_CPUCL0_PLL, "mout_cpucl0_pll", mout_cpucl0_pll_p,
1126
+
CLK_CON_MUX_MUX_CLK_CPUCL0_PLL, 0, 1, CLK_SET_RATE_PARENT, 0),
1127
+
};
1128
+
1129
+
static const struct samsung_div_clock cpucl0_div_clks[] __initconst = {
1130
+
DIV_F(CLK_DOUT_CPUCL0_CPU, "dout_cpucl0_cpu", "mout_cpucl0_pll",
1131
+
CLK_CON_DIV_DIV_CLK_CPUCL0_CPU, 0, 1,
1132
+
CLK_GET_RATE_NOCACHE, CLK_DIVIDER_READ_ONLY),
1133
+
DIV_F(CLK_DOUT_CPUCL0_CMUREF, "dout_cpucl0_cmuref", "dout_cpucl0_cpu",
1134
+
CLK_CON_DIV_DIV_CLK_CPUCL0_CMUREF, 0, 3,
1135
+
CLK_GET_RATE_NOCACHE, CLK_DIVIDER_READ_ONLY),
1136
+
DIV_F(CLK_DOUT_CPUCL0_PCLK, "dout_cpucl0_pclk", "dout_cpucl0_cpu",
1137
+
CLK_CON_DIV_DIV_CLK_CPUCL0_PCLK, 0, 4,
1138
+
CLK_GET_RATE_NOCACHE, CLK_DIVIDER_READ_ONLY),
1139
+
1140
+
/* EMBEDDED_CMU_CPUCL0 */
1141
+
DIV_F(CLK_DOUT_CLUSTER0_ACLK, "dout_cluster0_aclk", "gout_cluster0_cpu",
1142
+
CLK_CON_DIV_DIV_CLK_CLUSTER0_ACLK, 0, 4,
1143
+
CLK_GET_RATE_NOCACHE, CLK_DIVIDER_READ_ONLY),
1144
+
DIV_F(CLK_DOUT_CLUSTER0_ATCLK, "dout_cluster0_atclk",
1145
+
"gout_cluster0_cpu", CLK_CON_DIV_DIV_CLK_CLUSTER0_ATCLK, 0, 4,
1146
+
CLK_GET_RATE_NOCACHE, CLK_DIVIDER_READ_ONLY),
1147
+
DIV_F(CLK_DOUT_CLUSTER0_PCLKDBG, "dout_cluster0_pclkdbg",
1148
+
"gout_cluster0_cpu", CLK_CON_DIV_DIV_CLK_CLUSTER0_PCLKDBG, 0, 4,
1149
+
CLK_GET_RATE_NOCACHE, CLK_DIVIDER_READ_ONLY),
1150
+
DIV_F(CLK_DOUT_CLUSTER0_PERIPHCLK, "dout_cluster0_periphclk",
1151
+
"gout_cluster0_cpu", CLK_CON_DIV_DIV_CLK_CLUSTER0_PERIPHCLK, 0, 4,
1152
+
CLK_GET_RATE_NOCACHE, CLK_DIVIDER_READ_ONLY),
1153
+
};
1154
+
1155
+
static const struct samsung_gate_clock cpucl0_gate_clks[] __initconst = {
1156
+
GATE(CLK_GOUT_CPUCL0_CMU_CPUCL0_PCLK, "gout_cpucl0_cmu_cpucl0_pclk",
1157
+
"dout_cpucl0_pclk",
1158
+
CLK_CON_GAT_CLK_CPUCL0_CMU_CPUCL0_PCLK, 21, CLK_IGNORE_UNUSED, 0),
1159
+
1160
+
/* EMBEDDED_CMU_CPUCL0 */
1161
+
GATE(CLK_GOUT_CLUSTER0_CPU, "gout_cluster0_cpu", "dout_cpucl0_cpu",
1162
+
CLK_CON_GAT_GATE_CLK_CPUCL0_CPU, 21, CLK_IGNORE_UNUSED, 0),
1163
+
GATE(CLK_GOUT_CLUSTER0_SCLK, "gout_cluster0_sclk", "gout_cluster0_cpu",
1164
+
CLK_CON_GAT_CLK_CPUCL0_CLUSTER0_SCLK, 21, CLK_IGNORE_UNUSED, 0),
1165
+
GATE(CLK_GOUT_CLUSTER0_ATCLK, "gout_cluster0_atclk",
1166
+
"dout_cluster0_atclk",
1167
+
CLK_CON_GAT_CLK_CPUCL0_CLUSTER0_ATCLK, 21, CLK_IGNORE_UNUSED, 0),
1168
+
GATE(CLK_GOUT_CLUSTER0_PERIPHCLK, "gout_cluster0_periphclk",
1169
+
"dout_cluster0_periphclk",
1170
+
CLK_CON_GAT_CLK_CPUCL0_CLUSTER0_PERIPHCLK, 21,
1171
+
CLK_IGNORE_UNUSED, 0),
1172
+
GATE(CLK_GOUT_CLUSTER0_PCLK, "gout_cluster0_pclk",
1173
+
"dout_cluster0_pclkdbg",
1174
+
CLK_CON_GAT_CLK_CPUCL0_CLUSTER0_PCLK, 21, CLK_IGNORE_UNUSED, 0),
1175
+
};
1176
+
1177
+
/*
1178
+
* Each parameter is going to be written into the corresponding DIV register. So
1179
+
* the actual divider value for each parameter will be 1/(param+1). All these
1180
+
* parameters must be in the range of 0..15, as the divider range for all of
1181
+
* these DIV clocks is 1..16. The default values for these dividers is
1182
+
* (1, 3, 3, 1).
1183
+
*/
1184
+
#define E850_CPU_DIV0(aclk, atclk, pclkdbg, periphclk) \
1185
+
(((aclk) << 16) | ((atclk) << 12) | ((pclkdbg) << 8) | \
1186
+
((periphclk) << 4))
1187
+
1188
+
static const struct exynos_cpuclk_cfg_data exynos850_cluster_clk_d[] __initconst
1189
+
= {
1190
+
{ 2210000, E850_CPU_DIV0(1, 3, 3, 1) },
1191
+
{ 2106000, E850_CPU_DIV0(1, 3, 3, 1) },
1192
+
{ 2002000, E850_CPU_DIV0(1, 3, 3, 1) },
1193
+
{ 1846000, E850_CPU_DIV0(1, 3, 3, 1) },
1194
+
{ 1742000, E850_CPU_DIV0(1, 3, 3, 1) },
1195
+
{ 1586000, E850_CPU_DIV0(1, 3, 3, 1) },
1196
+
{ 1456000, E850_CPU_DIV0(1, 3, 3, 1) },
1197
+
{ 1300000, E850_CPU_DIV0(1, 3, 3, 1) },
1198
+
{ 1157000, E850_CPU_DIV0(1, 3, 3, 1) },
1199
+
{ 1053000, E850_CPU_DIV0(1, 3, 3, 1) },
1200
+
{ 949000, E850_CPU_DIV0(1, 3, 3, 1) },
1201
+
{ 806000, E850_CPU_DIV0(1, 3, 3, 1) },
1202
+
{ 650000, E850_CPU_DIV0(1, 3, 3, 1) },
1203
+
{ 546000, E850_CPU_DIV0(1, 3, 3, 1) },
1204
+
{ 442000, E850_CPU_DIV0(1, 3, 3, 1) },
1205
+
{ 351000, E850_CPU_DIV0(1, 3, 3, 1) },
1206
+
{ 247000, E850_CPU_DIV0(1, 3, 3, 1) },
1207
+
{ 182000, E850_CPU_DIV0(1, 3, 3, 1) },
1208
+
{ 130000, E850_CPU_DIV0(1, 3, 3, 1) },
1209
+
{ 0 }
1210
+
};
1211
+
1212
+
static const struct samsung_cpu_clock cpucl0_cpu_clks[] __initconst = {
1213
+
CPU_CLK(CLK_CLUSTER0_SCLK, "cluster0_clk", CLK_MOUT_PLL_CPUCL0,
1214
+
CLK_MOUT_CPUCL0_SWITCH_USER, 0, 0x0, CPUCLK_LAYOUT_E850_CL0,
1215
+
exynos850_cluster_clk_d),
1216
+
};
1217
+
1218
+
static const struct samsung_cmu_info cpucl0_cmu_info __initconst = {
1219
+
.pll_clks = cpucl0_pll_clks,
1220
+
.nr_pll_clks = ARRAY_SIZE(cpucl0_pll_clks),
1221
+
.mux_clks = cpucl0_mux_clks,
1222
+
.nr_mux_clks = ARRAY_SIZE(cpucl0_mux_clks),
1223
+
.div_clks = cpucl0_div_clks,
1224
+
.nr_div_clks = ARRAY_SIZE(cpucl0_div_clks),
1225
+
.gate_clks = cpucl0_gate_clks,
1226
+
.nr_gate_clks = ARRAY_SIZE(cpucl0_gate_clks),
1227
+
.cpu_clks = cpucl0_cpu_clks,
1228
+
.nr_cpu_clks = ARRAY_SIZE(cpucl0_cpu_clks),
1229
+
.nr_clk_ids = CLKS_NR_CPUCL0,
1230
+
.clk_regs = cpucl0_clk_regs,
1231
+
.nr_clk_regs = ARRAY_SIZE(cpucl0_clk_regs),
1232
+
.clk_name = "dout_cpucl0_switch",
1233
+
.manual_plls = true,
1234
+
};
1235
+
1236
+
static void __init exynos850_cmu_cpucl0_init(struct device_node *np)
1237
+
{
1238
+
exynos_arm64_register_cmu(NULL, np, &cpucl0_cmu_info);
1239
+
}
1240
+
1241
+
/* Register CMU_CPUCL0 early, as CPU clocks should be available ASAP */
1242
+
CLK_OF_DECLARE(exynos850_cmu_cpucl0, "samsung,exynos850-cmu-cpucl0",
1243
+
exynos850_cmu_cpucl0_init);
1244
+
1245
+
/* ---- CMU_CPUCL1 ---------------------------------------------------------- */
1246
+
1247
+
/* Register Offset definitions for CMU_CPUCL1 (0x10800000) */
1248
+
#define PLL_LOCKTIME_PLL_CPUCL1 0x0000
1249
+
#define PLL_CON0_PLL_CPUCL1 0x0100
1250
+
#define PLL_CON1_PLL_CPUCL1 0x0104
1251
+
#define PLL_CON3_PLL_CPUCL1 0x010c
1252
+
#define PLL_CON0_MUX_CLKCMU_CPUCL1_DBG_USER 0x0600
1253
+
#define PLL_CON0_MUX_CLKCMU_CPUCL1_SWITCH_USER 0x0610
1254
+
#define CLK_CON_MUX_MUX_CLK_CPUCL1_PLL 0x1000
1255
+
#define CLK_CON_DIV_DIV_CLK_CLUSTER1_ACLK 0x1800
1256
+
#define CLK_CON_DIV_DIV_CLK_CLUSTER1_ATCLK 0x1808
1257
+
#define CLK_CON_DIV_DIV_CLK_CLUSTER1_PCLKDBG 0x180c
1258
+
#define CLK_CON_DIV_DIV_CLK_CLUSTER1_PERIPHCLK 0x1810
1259
+
#define CLK_CON_DIV_DIV_CLK_CPUCL1_CMUREF 0x1814
1260
+
#define CLK_CON_DIV_DIV_CLK_CPUCL1_CPU 0x1818
1261
+
#define CLK_CON_DIV_DIV_CLK_CPUCL1_PCLK 0x181c
1262
+
#define CLK_CON_GAT_CLK_CPUCL1_CLUSTER1_ATCLK 0x2000
1263
+
#define CLK_CON_GAT_CLK_CPUCL1_CLUSTER1_PCLK 0x2004
1264
+
#define CLK_CON_GAT_CLK_CPUCL1_CLUSTER1_PERIPHCLK 0x2008
1265
+
#define CLK_CON_GAT_CLK_CPUCL1_CLUSTER1_SCLK 0x200c
1266
+
#define CLK_CON_GAT_CLK_CPUCL1_CMU_CPUCL1_PCLK 0x2010
1267
+
#define CLK_CON_GAT_GATE_CLK_CPUCL1_CPU 0x2020
1268
+
1269
+
static const unsigned long cpucl1_clk_regs[] __initconst = {
1270
+
PLL_LOCKTIME_PLL_CPUCL1,
1271
+
PLL_CON0_PLL_CPUCL1,
1272
+
PLL_CON1_PLL_CPUCL1,
1273
+
PLL_CON3_PLL_CPUCL1,
1274
+
PLL_CON0_MUX_CLKCMU_CPUCL1_DBG_USER,
1275
+
PLL_CON0_MUX_CLKCMU_CPUCL1_SWITCH_USER,
1276
+
CLK_CON_MUX_MUX_CLK_CPUCL1_PLL,
1277
+
CLK_CON_DIV_DIV_CLK_CLUSTER1_ACLK,
1278
+
CLK_CON_DIV_DIV_CLK_CLUSTER1_ATCLK,
1279
+
CLK_CON_DIV_DIV_CLK_CLUSTER1_PCLKDBG,
1280
+
CLK_CON_DIV_DIV_CLK_CLUSTER1_PERIPHCLK,
1281
+
CLK_CON_DIV_DIV_CLK_CPUCL1_CMUREF,
1282
+
CLK_CON_DIV_DIV_CLK_CPUCL1_CPU,
1283
+
CLK_CON_DIV_DIV_CLK_CPUCL1_PCLK,
1284
+
CLK_CON_GAT_CLK_CPUCL1_CLUSTER1_ATCLK,
1285
+
CLK_CON_GAT_CLK_CPUCL1_CLUSTER1_PCLK,
1286
+
CLK_CON_GAT_CLK_CPUCL1_CLUSTER1_PERIPHCLK,
1287
+
CLK_CON_GAT_CLK_CPUCL1_CLUSTER1_SCLK,
1288
+
CLK_CON_GAT_CLK_CPUCL1_CMU_CPUCL1_PCLK,
1289
+
CLK_CON_GAT_GATE_CLK_CPUCL1_CPU,
1290
+
};
1291
+
1292
+
/* List of parent clocks for Muxes in CMU_CPUCL0 */
1293
+
PNAME(mout_pll_cpucl1_p) = { "oscclk", "fout_cpucl1_pll" };
1294
+
PNAME(mout_cpucl1_switch_user_p) = { "oscclk", "dout_cpucl1_switch" };
1295
+
PNAME(mout_cpucl1_dbg_user_p) = { "oscclk", "dout_cpucl1_dbg" };
1296
+
PNAME(mout_cpucl1_pll_p) = { "mout_pll_cpucl1",
1297
+
"mout_cpucl1_switch_user" };
1298
+
1299
+
static const struct samsung_pll_clock cpucl1_pll_clks[] __initconst = {
1300
+
PLL(pll_0822x, CLK_FOUT_CPUCL1_PLL, "fout_cpucl1_pll", "oscclk",
1301
+
PLL_LOCKTIME_PLL_CPUCL1, PLL_CON3_PLL_CPUCL1, cpu_pll_rates),
1302
+
};
1303
+
1304
+
static const struct samsung_mux_clock cpucl1_mux_clks[] __initconst = {
1305
+
MUX_F(CLK_MOUT_PLL_CPUCL1, "mout_pll_cpucl1", mout_pll_cpucl1_p,
1306
+
PLL_CON0_PLL_CPUCL1, 4, 1,
1307
+
CLK_SET_RATE_PARENT | CLK_RECALC_NEW_RATES, 0),
1308
+
MUX_F(CLK_MOUT_CPUCL1_SWITCH_USER, "mout_cpucl1_switch_user",
1309
+
mout_cpucl1_switch_user_p,
1310
+
PLL_CON0_MUX_CLKCMU_CPUCL1_SWITCH_USER, 4, 1,
1311
+
CLK_SET_RATE_PARENT, 0),
1312
+
MUX(CLK_MOUT_CPUCL1_DBG_USER, "mout_cpucl1_dbg_user",
1313
+
mout_cpucl1_dbg_user_p,
1314
+
PLL_CON0_MUX_CLKCMU_CPUCL1_DBG_USER, 4, 1),
1315
+
MUX_F(CLK_MOUT_CPUCL1_PLL, "mout_cpucl1_pll", mout_cpucl1_pll_p,
1316
+
CLK_CON_MUX_MUX_CLK_CPUCL1_PLL, 0, 1, CLK_SET_RATE_PARENT, 0),
1317
+
};
1318
+
1319
+
static const struct samsung_div_clock cpucl1_div_clks[] __initconst = {
1320
+
DIV_F(CLK_DOUT_CPUCL1_CPU, "dout_cpucl1_cpu", "mout_cpucl1_pll",
1321
+
CLK_CON_DIV_DIV_CLK_CPUCL1_CPU, 0, 1,
1322
+
CLK_GET_RATE_NOCACHE, CLK_DIVIDER_READ_ONLY),
1323
+
DIV_F(CLK_DOUT_CPUCL1_CMUREF, "dout_cpucl1_cmuref", "dout_cpucl1_cpu",
1324
+
CLK_CON_DIV_DIV_CLK_CPUCL1_CMUREF, 0, 3,
1325
+
CLK_GET_RATE_NOCACHE, CLK_DIVIDER_READ_ONLY),
1326
+
DIV_F(CLK_DOUT_CPUCL1_PCLK, "dout_cpucl1_pclk", "dout_cpucl1_cpu",
1327
+
CLK_CON_DIV_DIV_CLK_CPUCL1_PCLK, 0, 4,
1328
+
CLK_GET_RATE_NOCACHE, CLK_DIVIDER_READ_ONLY),
1329
+
1330
+
/* EMBEDDED_CMU_CPUCL1 */
1331
+
DIV_F(CLK_DOUT_CLUSTER1_ACLK, "dout_cluster1_aclk", "gout_cluster1_cpu",
1332
+
CLK_CON_DIV_DIV_CLK_CLUSTER1_ACLK, 0, 4,
1333
+
CLK_GET_RATE_NOCACHE, CLK_DIVIDER_READ_ONLY),
1334
+
DIV_F(CLK_DOUT_CLUSTER1_ATCLK, "dout_cluster1_atclk",
1335
+
"gout_cluster1_cpu", CLK_CON_DIV_DIV_CLK_CLUSTER1_ATCLK, 0, 4,
1336
+
CLK_GET_RATE_NOCACHE, CLK_DIVIDER_READ_ONLY),
1337
+
DIV_F(CLK_DOUT_CLUSTER1_PCLKDBG, "dout_cluster1_pclkdbg",
1338
+
"gout_cluster1_cpu", CLK_CON_DIV_DIV_CLK_CLUSTER1_PCLKDBG, 0, 4,
1339
+
CLK_GET_RATE_NOCACHE, CLK_DIVIDER_READ_ONLY),
1340
+
DIV_F(CLK_DOUT_CLUSTER1_PERIPHCLK, "dout_cluster1_periphclk",
1341
+
"gout_cluster1_cpu", CLK_CON_DIV_DIV_CLK_CLUSTER1_PERIPHCLK, 0, 4,
1342
+
CLK_GET_RATE_NOCACHE, CLK_DIVIDER_READ_ONLY),
1343
+
};
1344
+
1345
+
static const struct samsung_gate_clock cpucl1_gate_clks[] __initconst = {
1346
+
GATE(CLK_GOUT_CPUCL1_CMU_CPUCL1_PCLK, "gout_cpucl1_cmu_cpucl1_pclk",
1347
+
"dout_cpucl1_pclk",
1348
+
CLK_CON_GAT_CLK_CPUCL1_CMU_CPUCL1_PCLK, 21, CLK_IGNORE_UNUSED, 0),
1349
+
1350
+
/* EMBEDDED_CMU_CPUCL1 */
1351
+
GATE(CLK_GOUT_CLUSTER1_CPU, "gout_cluster1_cpu", "dout_cpucl1_cpu",
1352
+
CLK_CON_GAT_GATE_CLK_CPUCL1_CPU, 21, CLK_IGNORE_UNUSED, 0),
1353
+
GATE(CLK_GOUT_CLUSTER1_SCLK, "gout_cluster1_sclk", "gout_cluster1_cpu",
1354
+
CLK_CON_GAT_CLK_CPUCL1_CLUSTER1_SCLK, 21, CLK_IGNORE_UNUSED, 0),
1355
+
GATE(CLK_GOUT_CLUSTER1_ATCLK, "gout_cluster1_atclk",
1356
+
"dout_cluster1_atclk",
1357
+
CLK_CON_GAT_CLK_CPUCL1_CLUSTER1_ATCLK, 21, CLK_IGNORE_UNUSED, 0),
1358
+
GATE(CLK_GOUT_CLUSTER1_PERIPHCLK, "gout_cluster1_periphclk",
1359
+
"dout_cluster1_periphclk",
1360
+
CLK_CON_GAT_CLK_CPUCL1_CLUSTER1_PERIPHCLK, 21,
1361
+
CLK_IGNORE_UNUSED, 0),
1362
+
GATE(CLK_GOUT_CLUSTER1_PCLK, "gout_cluster1_pclk",
1363
+
"dout_cluster1_pclkdbg",
1364
+
CLK_CON_GAT_CLK_CPUCL1_CLUSTER1_PCLK, 21, CLK_IGNORE_UNUSED, 0),
1365
+
};
1366
+
1367
+
static const struct samsung_cpu_clock cpucl1_cpu_clks[] __initconst = {
1368
+
CPU_CLK(CLK_CLUSTER1_SCLK, "cluster1_clk", CLK_MOUT_PLL_CPUCL1,
1369
+
CLK_MOUT_CPUCL1_SWITCH_USER, 0, 0x0, CPUCLK_LAYOUT_E850_CL1,
1370
+
exynos850_cluster_clk_d),
1371
+
};
1372
+
1373
+
static const struct samsung_cmu_info cpucl1_cmu_info __initconst = {
1374
+
.pll_clks = cpucl1_pll_clks,
1375
+
.nr_pll_clks = ARRAY_SIZE(cpucl1_pll_clks),
1376
+
.mux_clks = cpucl1_mux_clks,
1377
+
.nr_mux_clks = ARRAY_SIZE(cpucl1_mux_clks),
1378
+
.div_clks = cpucl1_div_clks,
1379
+
.nr_div_clks = ARRAY_SIZE(cpucl1_div_clks),
1380
+
.gate_clks = cpucl1_gate_clks,
1381
+
.nr_gate_clks = ARRAY_SIZE(cpucl1_gate_clks),
1382
+
.cpu_clks = cpucl1_cpu_clks,
1383
+
.nr_cpu_clks = ARRAY_SIZE(cpucl1_cpu_clks),
1384
+
.nr_clk_ids = CLKS_NR_CPUCL1,
1385
+
.clk_regs = cpucl1_clk_regs,
1386
+
.nr_clk_regs = ARRAY_SIZE(cpucl1_clk_regs),
1387
+
.clk_name = "dout_cpucl1_switch",
1388
+
.manual_plls = true,
1389
+
};
1390
+
1391
+
static void __init exynos850_cmu_cpucl1_init(struct device_node *np)
1392
+
{
1393
+
exynos_arm64_register_cmu(NULL, np, &cpucl1_cmu_info);
1394
+
}
1395
+
1396
+
/* Register CMU_CPUCL1 early, as CPU clocks should be available ASAP */
1397
+
CLK_OF_DECLARE(exynos850_cmu_cpucl1, "samsung,exynos850-cmu-cpucl1",
1398
+
exynos850_cmu_cpucl1_init);
1103
1399
1104
1400
/* ---- CMU_G3D ------------------------------------------------------------- */
1105
1401
+4
-4
drivers/clk/samsung/clk-exynosautov9.c
+4
-4
drivers/clk/samsung/clk-exynosautov9.c
···
352
352
/* CMU_TOP_PURECLKCOMP */
353
353
PLL(pll_0822x, FOUT_SHARED0_PLL, "fout_shared0_pll", "oscclk",
354
354
PLL_LOCKTIME_PLL_SHARED0, PLL_CON3_PLL_SHARED0, NULL),
355
-
PLL(pll_0822x, FOUT_SHARED0_PLL, "fout_shared1_pll", "oscclk",
355
+
PLL(pll_0822x, FOUT_SHARED1_PLL, "fout_shared1_pll", "oscclk",
356
356
PLL_LOCKTIME_PLL_SHARED1, PLL_CON3_PLL_SHARED1, NULL),
357
-
PLL(pll_0822x, FOUT_SHARED0_PLL, "fout_shared2_pll", "oscclk",
357
+
PLL(pll_0822x, FOUT_SHARED2_PLL, "fout_shared2_pll", "oscclk",
358
358
PLL_LOCKTIME_PLL_SHARED2, PLL_CON3_PLL_SHARED2, NULL),
359
-
PLL(pll_0822x, FOUT_SHARED0_PLL, "fout_shared3_pll", "oscclk",
359
+
PLL(pll_0822x, FOUT_SHARED3_PLL, "fout_shared3_pll", "oscclk",
360
360
PLL_LOCKTIME_PLL_SHARED3, PLL_CON3_PLL_SHARED3, NULL),
361
-
PLL(pll_0822x, FOUT_SHARED0_PLL, "fout_shared4_pll", "oscclk",
361
+
PLL(pll_0822x, FOUT_SHARED4_PLL, "fout_shared4_pll", "oscclk",
362
362
PLL_LOCKTIME_PLL_SHARED4, PLL_CON3_PLL_SHARED4, NULL),
363
363
};
364
364
+1084
-108
drivers/clk/samsung/clk-gs101.c
+1084
-108
drivers/clk/samsung/clk-gs101.c
···
15
15
16
16
#include "clk.h"
17
17
#include "clk-exynos-arm64.h"
18
+
#include "clk-pll.h"
18
19
19
20
/* NOTE: Must be equal to the last clock ID increased by one */
20
21
#define CLKS_NR_TOP (CLK_GOUT_CMU_TPU_UART + 1)
21
22
#define CLKS_NR_APM (CLK_APM_PLL_DIV16_APM + 1)
23
+
#define CLKS_NR_HSI0 (CLK_GOUT_HSI0_XIU_P_HSI0_ACLK + 1)
24
+
#define CLKS_NR_HSI2 (CLK_GOUT_HSI2_XIU_P_HSI2_ACLK + 1)
22
25
#define CLKS_NR_MISC (CLK_GOUT_MISC_XIU_D_MISC_ACLK + 1)
23
26
#define CLKS_NR_PERIC0 (CLK_GOUT_PERIC0_SYSREG_PERIC0_PCLK + 1)
24
27
#define CLKS_NR_PERIC1 (CLK_GOUT_PERIC1_SYSREG_PERIC1_PCLK + 1)
···
1896
1893
CLK_CON_GAT_GOUT_BLK_APM_UID_UASC_G_SWD_IPCLKPORT_PCLK, 21, 0, 0),
1897
1894
GATE(CLK_GOUT_APM_UASC_P_APM_ACLK,
1898
1895
"gout_apm_uasc_p_apm_aclk", "gout_apm_func",
1899
-
CLK_CON_GAT_GOUT_BLK_APM_UID_UASC_P_APM_IPCLKPORT_ACLK, 21, 0, 0),
1896
+
CLK_CON_GAT_GOUT_BLK_APM_UID_UASC_P_APM_IPCLKPORT_ACLK, 21, CLK_IS_CRITICAL, 0),
1900
1897
GATE(CLK_GOUT_APM_UASC_P_APM_PCLK,
1901
1898
"gout_apm_uasc_p_apm_pclk", "gout_apm_func",
1902
-
CLK_CON_GAT_GOUT_BLK_APM_UID_UASC_P_APM_IPCLKPORT_PCLK, 21, 0, 0),
1899
+
CLK_CON_GAT_GOUT_BLK_APM_UID_UASC_P_APM_IPCLKPORT_PCLK, 21, CLK_IS_CRITICAL, 0),
1903
1900
GATE(CLK_GOUT_APM_WDT_APM_PCLK,
1904
1901
"gout_apm_wdt_apm_pclk", "gout_apm_func",
1905
1902
CLK_CON_GAT_GOUT_BLK_APM_UID_WDT_APM_IPCLKPORT_PCLK, 21, 0, 0),
1906
1903
GATE(CLK_GOUT_APM_XIU_DP_APM_ACLK,
1907
1904
"gout_apm_xiu_dp_apm_aclk", "gout_apm_func",
1908
-
CLK_CON_GAT_GOUT_BLK_APM_UID_XIU_DP_APM_IPCLKPORT_ACLK, 21, 0, 0),
1905
+
CLK_CON_GAT_GOUT_BLK_APM_UID_XIU_DP_APM_IPCLKPORT_ACLK, 21, CLK_IS_CRITICAL, 0),
1909
1906
};
1910
1907
1911
1908
static const struct samsung_cmu_info apm_cmu_info __initconst = {
···
1920
1917
.nr_clk_ids = CLKS_NR_APM,
1921
1918
.clk_regs = apm_clk_regs,
1922
1919
.nr_clk_regs = ARRAY_SIZE(apm_clk_regs),
1920
+
};
1921
+
1922
+
/* ---- CMU_HSI0 ------------------------------------------------------------ */
1923
+
1924
+
/* Register Offset definitions for CMU_HSI0 (0x11000000) */
1925
+
#define PLL_LOCKTIME_PLL_USB 0x0004
1926
+
#define PLL_CON0_PLL_USB 0x0140
1927
+
#define PLL_CON1_PLL_USB 0x0144
1928
+
#define PLL_CON2_PLL_USB 0x0148
1929
+
#define PLL_CON3_PLL_USB 0x014c
1930
+
#define PLL_CON4_PLL_USB 0x0150
1931
+
#define PLL_CON0_MUX_CLKCMU_HSI0_ALT_USER 0x0600
1932
+
#define PLL_CON1_MUX_CLKCMU_HSI0_ALT_USER 0x0604
1933
+
#define PLL_CON0_MUX_CLKCMU_HSI0_BUS_USER 0x0610
1934
+
#define PLL_CON1_MUX_CLKCMU_HSI0_BUS_USER 0x0614
1935
+
#define PLL_CON0_MUX_CLKCMU_HSI0_DPGTC_USER 0x0620
1936
+
#define PLL_CON1_MUX_CLKCMU_HSI0_DPGTC_USER 0x0624
1937
+
#define PLL_CON0_MUX_CLKCMU_HSI0_TCXO_USER 0x0630
1938
+
#define PLL_CON1_MUX_CLKCMU_HSI0_TCXO_USER 0x0634
1939
+
#define PLL_CON0_MUX_CLKCMU_HSI0_USB20_USER 0x0640
1940
+
#define PLL_CON1_MUX_CLKCMU_HSI0_USB20_USER 0x0644
1941
+
#define PLL_CON0_MUX_CLKCMU_HSI0_USB31DRD_USER 0x0650
1942
+
#define PLL_CON1_MUX_CLKCMU_HSI0_USB31DRD_USER 0x0654
1943
+
#define PLL_CON0_MUX_CLKCMU_HSI0_USPDPDBG_USER 0x0660
1944
+
#define PLL_CON1_MUX_CLKCMU_HSI0_USPDPDBG_USER 0x0664
1945
+
#define HSI0_CMU_HSI0_CONTROLLER_OPTION 0x0800
1946
+
#define CLKOUT_CON_BLK_HSI0_CMU_HSI0_CLKOUT0 0x0810
1947
+
#define CLK_CON_MUX_MUX_CLK_HSI0_BUS 0x1000
1948
+
#define CLK_CON_MUX_MUX_CLK_HSI0_USB20_REF 0x1004
1949
+
#define CLK_CON_MUX_MUX_CLK_HSI0_USB31DRD 0x1008
1950
+
#define CLK_CON_DIV_DIV_CLK_HSI0_USB31DRD 0x1800
1951
+
#define CLK_CON_GAT_CLK_BLK_HSI0_UID_HSI0_CMU_HSI0_IPCLKPORT_PCLK 0x2000
1952
+
#define CLK_CON_GAT_CLK_BLK_HSI0_UID_USB31DRD_IPCLKPORT_I_USB31DRD_SUSPEND_CLK_26 0x2004
1953
+
#define CLK_CON_GAT_CLK_HSI0_ALT 0x2008
1954
+
#define CLK_CON_GAT_GOUT_BLK_HSI0_UID_DP_LINK_IPCLKPORT_I_DP_GTC_CLK 0x200c
1955
+
#define CLK_CON_GAT_GOUT_BLK_HSI0_UID_DP_LINK_IPCLKPORT_I_PCLK 0x2010
1956
+
#define CLK_CON_GAT_GOUT_BLK_HSI0_UID_D_TZPC_HSI0_IPCLKPORT_PCLK 0x2014
1957
+
#define CLK_CON_GAT_GOUT_BLK_HSI0_UID_ETR_MIU_IPCLKPORT_I_ACLK 0x2018
1958
+
#define CLK_CON_GAT_GOUT_BLK_HSI0_UID_ETR_MIU_IPCLKPORT_I_PCLK 0x201c
1959
+
#define CLK_CON_GAT_GOUT_BLK_HSI0_UID_GPC_HSI0_IPCLKPORT_PCLK 0x2020
1960
+
#define CLK_CON_GAT_GOUT_BLK_HSI0_UID_LHM_AXI_G_ETR_HSI0_IPCLKPORT_I_CLK 0x2024
1961
+
#define CLK_CON_GAT_GOUT_BLK_HSI0_UID_LHM_AXI_P_AOCHSI0_IPCLKPORT_I_CLK 0x2028
1962
+
#define CLK_CON_GAT_GOUT_BLK_HSI0_UID_LHM_AXI_P_HSI0_IPCLKPORT_I_CLK 0x202c
1963
+
#define CLK_CON_GAT_GOUT_BLK_HSI0_UID_LHS_ACEL_D_HSI0_IPCLKPORT_I_CLK 0x2030
1964
+
#define CLK_CON_GAT_GOUT_BLK_HSI0_UID_LHS_AXI_D_HSI0AOC_IPCLKPORT_I_CLK 0x2034
1965
+
#define CLK_CON_GAT_GOUT_BLK_HSI0_UID_PPMU_HSI0_AOC_IPCLKPORT_ACLK 0x2038
1966
+
#define CLK_CON_GAT_GOUT_BLK_HSI0_UID_PPMU_HSI0_AOC_IPCLKPORT_PCLK 0x203c
1967
+
#define CLK_CON_GAT_GOUT_BLK_HSI0_UID_PPMU_HSI0_BUS0_IPCLKPORT_ACLK 0x2040
1968
+
#define CLK_CON_GAT_GOUT_BLK_HSI0_UID_PPMU_HSI0_BUS0_IPCLKPORT_PCLK 0x2044
1969
+
#define CLK_CON_GAT_GOUT_BLK_HSI0_UID_RSTNSYNC_CLK_HSI0_BUS_IPCLKPORT_CLK 0x2048
1970
+
#define CLK_CON_GAT_GOUT_BLK_HSI0_UID_SSMT_USB_IPCLKPORT_ACLK 0x204c
1971
+
#define CLK_CON_GAT_GOUT_BLK_HSI0_UID_SSMT_USB_IPCLKPORT_PCLK 0x2050
1972
+
#define CLK_CON_GAT_GOUT_BLK_HSI0_UID_SYSMMU_USB_IPCLKPORT_CLK_S2 0x2054
1973
+
#define CLK_CON_GAT_GOUT_BLK_HSI0_UID_SYSREG_HSI0_IPCLKPORT_PCLK 0x2058
1974
+
#define CLK_CON_GAT_GOUT_BLK_HSI0_UID_UASC_HSI0_CTRL_IPCLKPORT_ACLK 0x205c
1975
+
#define CLK_CON_GAT_GOUT_BLK_HSI0_UID_UASC_HSI0_CTRL_IPCLKPORT_PCLK 0x2060
1976
+
#define CLK_CON_GAT_GOUT_BLK_HSI0_UID_UASC_HSI0_LINK_IPCLKPORT_ACLK 0x2064
1977
+
#define CLK_CON_GAT_GOUT_BLK_HSI0_UID_UASC_HSI0_LINK_IPCLKPORT_PCLK 0x2068
1978
+
#define CLK_CON_GAT_GOUT_BLK_HSI0_UID_USB31DRD_IPCLKPORT_ACLK_PHYCTRL 0x206c
1979
+
#define CLK_CON_GAT_GOUT_BLK_HSI0_UID_USB31DRD_IPCLKPORT_BUS_CLK_EARLY 0x2070
1980
+
#define CLK_CON_GAT_GOUT_BLK_HSI0_UID_USB31DRD_IPCLKPORT_I_USB20_PHY_REFCLK_26 0x2074
1981
+
#define CLK_CON_GAT_GOUT_BLK_HSI0_UID_USB31DRD_IPCLKPORT_I_USB31DRD_REF_CLK_40 0x2078
1982
+
#define CLK_CON_GAT_GOUT_BLK_HSI0_UID_USB31DRD_IPCLKPORT_I_USBDPPHY_REF_SOC_PLL 0x207c
1983
+
#define CLK_CON_GAT_GOUT_BLK_HSI0_UID_USB31DRD_IPCLKPORT_I_USBDPPHY_SCL_APB_PCLK 0x2080
1984
+
#define CLK_CON_GAT_GOUT_BLK_HSI0_UID_USB31DRD_IPCLKPORT_I_USBPCS_APB_CLK 0x2084
1985
+
#define CLK_CON_GAT_GOUT_BLK_HSI0_UID_USB31DRD_IPCLKPORT_USBDPPHY_I_ACLK 0x2088
1986
+
#define CLK_CON_GAT_GOUT_BLK_HSI0_UID_USB31DRD_IPCLKPORT_USBDPPHY_UDBG_I_APB_PCLK 0x208c
1987
+
#define CLK_CON_GAT_GOUT_BLK_HSI0_UID_XIU_D0_HSI0_IPCLKPORT_ACLK 0x2090
1988
+
#define CLK_CON_GAT_GOUT_BLK_HSI0_UID_XIU_D1_HSI0_IPCLKPORT_ACLK 0x2094
1989
+
#define CLK_CON_GAT_GOUT_BLK_HSI0_UID_XIU_P_HSI0_IPCLKPORT_ACLK 0x2098
1990
+
#define DMYQCH_CON_USB31DRD_QCH 0x3000
1991
+
#define DMYQCH_CON_USB31DRD_QCH_REF 0x3004
1992
+
#define PCH_CON_LHM_AXI_G_ETR_HSI0_PCH 0x3008
1993
+
#define PCH_CON_LHM_AXI_P_AOCHSI0_PCH 0x300c
1994
+
#define PCH_CON_LHM_AXI_P_HSI0_PCH 0x3010
1995
+
#define PCH_CON_LHS_ACEL_D_HSI0_PCH 0x3014
1996
+
#define PCH_CON_LHS_AXI_D_HSI0AOC_PCH 0x3018
1997
+
#define QCH_CON_DP_LINK_QCH_GTC_CLK 0x301c
1998
+
#define QCH_CON_DP_LINK_QCH_PCLK 0x3020
1999
+
#define QCH_CON_D_TZPC_HSI0_QCH 0x3024
2000
+
#define QCH_CON_ETR_MIU_QCH_ACLK 0x3028
2001
+
#define QCH_CON_ETR_MIU_QCH_PCLK 0x302c
2002
+
#define QCH_CON_GPC_HSI0_QCH 0x3030
2003
+
#define QCH_CON_HSI0_CMU_HSI0_QCH 0x3034
2004
+
#define QCH_CON_LHM_AXI_G_ETR_HSI0_QCH 0x3038
2005
+
#define QCH_CON_LHM_AXI_P_AOCHSI0_QCH 0x303c
2006
+
#define QCH_CON_LHM_AXI_P_HSI0_QCH 0x3040
2007
+
#define QCH_CON_LHS_ACEL_D_HSI0_QCH 0x3044
2008
+
#define QCH_CON_LHS_AXI_D_HSI0AOC_QCH 0x3048
2009
+
#define QCH_CON_PPMU_HSI0_AOC_QCH 0x304c
2010
+
#define QCH_CON_PPMU_HSI0_BUS0_QCH 0x3050
2011
+
#define QCH_CON_SSMT_USB_QCH 0x3054
2012
+
#define QCH_CON_SYSMMU_USB_QCH 0x3058
2013
+
#define QCH_CON_SYSREG_HSI0_QCH 0x305c
2014
+
#define QCH_CON_UASC_HSI0_CTRL_QCH 0x3060
2015
+
#define QCH_CON_UASC_HSI0_LINK_QCH 0x3064
2016
+
#define QCH_CON_USB31DRD_QCH_APB 0x3068
2017
+
#define QCH_CON_USB31DRD_QCH_DBG 0x306c
2018
+
#define QCH_CON_USB31DRD_QCH_PCS 0x3070
2019
+
#define QCH_CON_USB31DRD_QCH_SLV_CTRL 0x3074
2020
+
#define QCH_CON_USB31DRD_QCH_SLV_LINK 0x3078
2021
+
#define QUEUE_CTRL_REG_BLK_HSI0_CMU_HSI0 0x3c00
2022
+
2023
+
static const unsigned long hsi0_clk_regs[] __initconst = {
2024
+
PLL_LOCKTIME_PLL_USB,
2025
+
PLL_CON0_PLL_USB,
2026
+
PLL_CON1_PLL_USB,
2027
+
PLL_CON2_PLL_USB,
2028
+
PLL_CON3_PLL_USB,
2029
+
PLL_CON4_PLL_USB,
2030
+
PLL_CON0_MUX_CLKCMU_HSI0_ALT_USER,
2031
+
PLL_CON1_MUX_CLKCMU_HSI0_ALT_USER,
2032
+
PLL_CON0_MUX_CLKCMU_HSI0_BUS_USER,
2033
+
PLL_CON1_MUX_CLKCMU_HSI0_BUS_USER,
2034
+
PLL_CON0_MUX_CLKCMU_HSI0_DPGTC_USER,
2035
+
PLL_CON1_MUX_CLKCMU_HSI0_DPGTC_USER,
2036
+
PLL_CON0_MUX_CLKCMU_HSI0_TCXO_USER,
2037
+
PLL_CON1_MUX_CLKCMU_HSI0_TCXO_USER,
2038
+
PLL_CON0_MUX_CLKCMU_HSI0_USB20_USER,
2039
+
PLL_CON1_MUX_CLKCMU_HSI0_USB20_USER,
2040
+
PLL_CON0_MUX_CLKCMU_HSI0_USB31DRD_USER,
2041
+
PLL_CON1_MUX_CLKCMU_HSI0_USB31DRD_USER,
2042
+
PLL_CON0_MUX_CLKCMU_HSI0_USPDPDBG_USER,
2043
+
PLL_CON1_MUX_CLKCMU_HSI0_USPDPDBG_USER,
2044
+
HSI0_CMU_HSI0_CONTROLLER_OPTION,
2045
+
CLKOUT_CON_BLK_HSI0_CMU_HSI0_CLKOUT0,
2046
+
CLK_CON_MUX_MUX_CLK_HSI0_BUS,
2047
+
CLK_CON_MUX_MUX_CLK_HSI0_USB20_REF,
2048
+
CLK_CON_MUX_MUX_CLK_HSI0_USB31DRD,
2049
+
CLK_CON_DIV_DIV_CLK_HSI0_USB31DRD,
2050
+
CLK_CON_GAT_CLK_BLK_HSI0_UID_HSI0_CMU_HSI0_IPCLKPORT_PCLK,
2051
+
CLK_CON_GAT_CLK_BLK_HSI0_UID_USB31DRD_IPCLKPORT_I_USB31DRD_SUSPEND_CLK_26,
2052
+
CLK_CON_GAT_CLK_HSI0_ALT,
2053
+
CLK_CON_GAT_GOUT_BLK_HSI0_UID_DP_LINK_IPCLKPORT_I_DP_GTC_CLK,
2054
+
CLK_CON_GAT_GOUT_BLK_HSI0_UID_DP_LINK_IPCLKPORT_I_PCLK,
2055
+
CLK_CON_GAT_GOUT_BLK_HSI0_UID_D_TZPC_HSI0_IPCLKPORT_PCLK,
2056
+
CLK_CON_GAT_GOUT_BLK_HSI0_UID_ETR_MIU_IPCLKPORT_I_ACLK,
2057
+
CLK_CON_GAT_GOUT_BLK_HSI0_UID_ETR_MIU_IPCLKPORT_I_PCLK,
2058
+
CLK_CON_GAT_GOUT_BLK_HSI0_UID_GPC_HSI0_IPCLKPORT_PCLK,
2059
+
CLK_CON_GAT_GOUT_BLK_HSI0_UID_LHM_AXI_G_ETR_HSI0_IPCLKPORT_I_CLK,
2060
+
CLK_CON_GAT_GOUT_BLK_HSI0_UID_LHM_AXI_P_AOCHSI0_IPCLKPORT_I_CLK,
2061
+
CLK_CON_GAT_GOUT_BLK_HSI0_UID_LHM_AXI_P_HSI0_IPCLKPORT_I_CLK,
2062
+
CLK_CON_GAT_GOUT_BLK_HSI0_UID_LHS_ACEL_D_HSI0_IPCLKPORT_I_CLK,
2063
+
CLK_CON_GAT_GOUT_BLK_HSI0_UID_LHS_AXI_D_HSI0AOC_IPCLKPORT_I_CLK,
2064
+
CLK_CON_GAT_GOUT_BLK_HSI0_UID_PPMU_HSI0_AOC_IPCLKPORT_ACLK,
2065
+
CLK_CON_GAT_GOUT_BLK_HSI0_UID_PPMU_HSI0_AOC_IPCLKPORT_PCLK,
2066
+
CLK_CON_GAT_GOUT_BLK_HSI0_UID_PPMU_HSI0_BUS0_IPCLKPORT_ACLK,
2067
+
CLK_CON_GAT_GOUT_BLK_HSI0_UID_PPMU_HSI0_BUS0_IPCLKPORT_PCLK,
2068
+
CLK_CON_GAT_GOUT_BLK_HSI0_UID_RSTNSYNC_CLK_HSI0_BUS_IPCLKPORT_CLK,
2069
+
CLK_CON_GAT_GOUT_BLK_HSI0_UID_SSMT_USB_IPCLKPORT_ACLK,
2070
+
CLK_CON_GAT_GOUT_BLK_HSI0_UID_SSMT_USB_IPCLKPORT_PCLK,
2071
+
CLK_CON_GAT_GOUT_BLK_HSI0_UID_SYSMMU_USB_IPCLKPORT_CLK_S2,
2072
+
CLK_CON_GAT_GOUT_BLK_HSI0_UID_SYSREG_HSI0_IPCLKPORT_PCLK,
2073
+
CLK_CON_GAT_GOUT_BLK_HSI0_UID_UASC_HSI0_CTRL_IPCLKPORT_ACLK,
2074
+
CLK_CON_GAT_GOUT_BLK_HSI0_UID_UASC_HSI0_CTRL_IPCLKPORT_PCLK,
2075
+
CLK_CON_GAT_GOUT_BLK_HSI0_UID_UASC_HSI0_LINK_IPCLKPORT_ACLK,
2076
+
CLK_CON_GAT_GOUT_BLK_HSI0_UID_UASC_HSI0_LINK_IPCLKPORT_PCLK,
2077
+
CLK_CON_GAT_GOUT_BLK_HSI0_UID_USB31DRD_IPCLKPORT_ACLK_PHYCTRL,
2078
+
CLK_CON_GAT_GOUT_BLK_HSI0_UID_USB31DRD_IPCLKPORT_BUS_CLK_EARLY,
2079
+
CLK_CON_GAT_GOUT_BLK_HSI0_UID_USB31DRD_IPCLKPORT_I_USB20_PHY_REFCLK_26,
2080
+
CLK_CON_GAT_GOUT_BLK_HSI0_UID_USB31DRD_IPCLKPORT_I_USB31DRD_REF_CLK_40,
2081
+
CLK_CON_GAT_GOUT_BLK_HSI0_UID_USB31DRD_IPCLKPORT_I_USBDPPHY_REF_SOC_PLL,
2082
+
CLK_CON_GAT_GOUT_BLK_HSI0_UID_USB31DRD_IPCLKPORT_I_USBDPPHY_SCL_APB_PCLK,
2083
+
CLK_CON_GAT_GOUT_BLK_HSI0_UID_USB31DRD_IPCLKPORT_I_USBPCS_APB_CLK,
2084
+
CLK_CON_GAT_GOUT_BLK_HSI0_UID_USB31DRD_IPCLKPORT_USBDPPHY_I_ACLK,
2085
+
CLK_CON_GAT_GOUT_BLK_HSI0_UID_USB31DRD_IPCLKPORT_USBDPPHY_UDBG_I_APB_PCLK,
2086
+
CLK_CON_GAT_GOUT_BLK_HSI0_UID_XIU_D0_HSI0_IPCLKPORT_ACLK,
2087
+
CLK_CON_GAT_GOUT_BLK_HSI0_UID_XIU_D1_HSI0_IPCLKPORT_ACLK,
2088
+
CLK_CON_GAT_GOUT_BLK_HSI0_UID_XIU_P_HSI0_IPCLKPORT_ACLK,
2089
+
DMYQCH_CON_USB31DRD_QCH,
2090
+
DMYQCH_CON_USB31DRD_QCH_REF,
2091
+
PCH_CON_LHM_AXI_G_ETR_HSI0_PCH,
2092
+
PCH_CON_LHM_AXI_P_AOCHSI0_PCH,
2093
+
PCH_CON_LHM_AXI_P_HSI0_PCH,
2094
+
PCH_CON_LHS_ACEL_D_HSI0_PCH,
2095
+
PCH_CON_LHS_AXI_D_HSI0AOC_PCH,
2096
+
QCH_CON_DP_LINK_QCH_GTC_CLK,
2097
+
QCH_CON_DP_LINK_QCH_PCLK,
2098
+
QCH_CON_D_TZPC_HSI0_QCH,
2099
+
QCH_CON_ETR_MIU_QCH_ACLK,
2100
+
QCH_CON_ETR_MIU_QCH_PCLK,
2101
+
QCH_CON_GPC_HSI0_QCH,
2102
+
QCH_CON_HSI0_CMU_HSI0_QCH,
2103
+
QCH_CON_LHM_AXI_G_ETR_HSI0_QCH,
2104
+
QCH_CON_LHM_AXI_P_AOCHSI0_QCH,
2105
+
QCH_CON_LHM_AXI_P_HSI0_QCH,
2106
+
QCH_CON_LHS_ACEL_D_HSI0_QCH,
2107
+
QCH_CON_LHS_AXI_D_HSI0AOC_QCH,
2108
+
QCH_CON_PPMU_HSI0_AOC_QCH,
2109
+
QCH_CON_PPMU_HSI0_BUS0_QCH,
2110
+
QCH_CON_SSMT_USB_QCH,
2111
+
QCH_CON_SYSMMU_USB_QCH,
2112
+
QCH_CON_SYSREG_HSI0_QCH,
2113
+
QCH_CON_UASC_HSI0_CTRL_QCH,
2114
+
QCH_CON_UASC_HSI0_LINK_QCH,
2115
+
QCH_CON_USB31DRD_QCH_APB,
2116
+
QCH_CON_USB31DRD_QCH_DBG,
2117
+
QCH_CON_USB31DRD_QCH_PCS,
2118
+
QCH_CON_USB31DRD_QCH_SLV_CTRL,
2119
+
QCH_CON_USB31DRD_QCH_SLV_LINK,
2120
+
QUEUE_CTRL_REG_BLK_HSI0_CMU_HSI0,
2121
+
};
2122
+
2123
+
/* List of parent clocks for Muxes in CMU_HSI0 */
2124
+
PNAME(mout_pll_usb_p) = { "oscclk", "fout_usb_pll" };
2125
+
PNAME(mout_hsi0_alt_user_p) = { "oscclk",
2126
+
"gout_hsi0_clk_hsi0_alt" };
2127
+
PNAME(mout_hsi0_bus_user_p) = { "oscclk", "dout_cmu_hsi0_bus" };
2128
+
PNAME(mout_hsi0_dpgtc_user_p) = { "oscclk", "dout_cmu_hsi0_dpgtc" };
2129
+
PNAME(mout_hsi0_tcxo_user_p) = { "oscclk", "tcxo_hsi1_hsi0" };
2130
+
PNAME(mout_hsi0_usb20_user_p) = { "oscclk", "usb20phy_phy_clock" };
2131
+
PNAME(mout_hsi0_usb31drd_user_p) = { "oscclk",
2132
+
"dout_cmu_hsi0_usb31drd" };
2133
+
PNAME(mout_hsi0_usbdpdbg_user_p) = { "oscclk",
2134
+
"dout_cmu_hsi0_usbdpdbg" };
2135
+
PNAME(mout_hsi0_bus_p) = { "mout_hsi0_bus_user",
2136
+
"mout_hsi0_alt_user" };
2137
+
PNAME(mout_hsi0_usb20_ref_p) = { "fout_usb_pll",
2138
+
"mout_hsi0_tcxo_user" };
2139
+
PNAME(mout_hsi0_usb31drd_p) = { "fout_usb_pll",
2140
+
"mout_hsi0_usb31drd_user",
2141
+
"dout_hsi0_usb31drd",
2142
+
"fout_usb_pll" };
2143
+
2144
+
static const struct samsung_pll_rate_table cmu_hsi0_usb_pll_rates[] __initconst = {
2145
+
PLL_35XX_RATE(24576000, 19200000, 150, 6, 5),
2146
+
{ /* sentinel */ }
2147
+
};
2148
+
2149
+
static const struct samsung_pll_clock cmu_hsi0_pll_clks[] __initconst = {
2150
+
PLL(pll_0518x, CLK_FOUT_USB_PLL, "fout_usb_pll", "oscclk",
2151
+
PLL_LOCKTIME_PLL_USB, PLL_CON3_PLL_USB,
2152
+
cmu_hsi0_usb_pll_rates),
2153
+
};
2154
+
2155
+
static const struct samsung_mux_clock hsi0_mux_clks[] __initconst = {
2156
+
MUX(CLK_MOUT_PLL_USB,
2157
+
"mout_pll_usb", mout_pll_usb_p,
2158
+
PLL_CON0_PLL_USB, 4, 1),
2159
+
MUX(CLK_MOUT_HSI0_ALT_USER,
2160
+
"mout_hsi0_alt_user", mout_hsi0_alt_user_p,
2161
+
PLL_CON0_MUX_CLKCMU_HSI0_ALT_USER, 4, 1),
2162
+
MUX(CLK_MOUT_HSI0_BUS_USER,
2163
+
"mout_hsi0_bus_user", mout_hsi0_bus_user_p,
2164
+
PLL_CON0_MUX_CLKCMU_HSI0_BUS_USER, 4, 1),
2165
+
MUX(CLK_MOUT_HSI0_DPGTC_USER,
2166
+
"mout_hsi0_dpgtc_user", mout_hsi0_dpgtc_user_p,
2167
+
PLL_CON0_MUX_CLKCMU_HSI0_DPGTC_USER, 4, 1),
2168
+
MUX(CLK_MOUT_HSI0_TCXO_USER,
2169
+
"mout_hsi0_tcxo_user", mout_hsi0_tcxo_user_p,
2170
+
PLL_CON0_MUX_CLKCMU_HSI0_TCXO_USER, 4, 1),
2171
+
MUX(CLK_MOUT_HSI0_USB20_USER,
2172
+
"mout_hsi0_usb20_user", mout_hsi0_usb20_user_p,
2173
+
PLL_CON0_MUX_CLKCMU_HSI0_USB20_USER, 4, 1),
2174
+
MUX(CLK_MOUT_HSI0_USB31DRD_USER,
2175
+
"mout_hsi0_usb31drd_user", mout_hsi0_usb31drd_user_p,
2176
+
PLL_CON0_MUX_CLKCMU_HSI0_USB31DRD_USER, 4, 1),
2177
+
MUX(CLK_MOUT_HSI0_USBDPDBG_USER,
2178
+
"mout_hsi0_usbdpdbg_user", mout_hsi0_usbdpdbg_user_p,
2179
+
PLL_CON0_MUX_CLKCMU_HSI0_USPDPDBG_USER, 4, 1),
2180
+
MUX(CLK_MOUT_HSI0_BUS,
2181
+
"mout_hsi0_bus", mout_hsi0_bus_p,
2182
+
CLK_CON_MUX_MUX_CLK_HSI0_BUS, 0, 1),
2183
+
MUX(CLK_MOUT_HSI0_USB20_REF,
2184
+
"mout_hsi0_usb20_ref", mout_hsi0_usb20_ref_p,
2185
+
CLK_CON_MUX_MUX_CLK_HSI0_USB20_REF, 0, 1),
2186
+
MUX(CLK_MOUT_HSI0_USB31DRD,
2187
+
"mout_hsi0_usb31drd", mout_hsi0_usb31drd_p,
2188
+
CLK_CON_MUX_MUX_CLK_HSI0_USB31DRD, 0, 2),
2189
+
};
2190
+
2191
+
static const struct samsung_div_clock hsi0_div_clks[] __initconst = {
2192
+
DIV(CLK_DOUT_HSI0_USB31DRD,
2193
+
"dout_hsi0_usb31drd", "mout_hsi0_usb20_user",
2194
+
CLK_CON_DIV_DIV_CLK_HSI0_USB31DRD, 0, 3),
2195
+
};
2196
+
2197
+
static const struct samsung_gate_clock hsi0_gate_clks[] __initconst = {
2198
+
/* TODO: should have a driver for this */
2199
+
GATE(CLK_GOUT_HSI0_PCLK,
2200
+
"gout_hsi0_hsi0_pclk", "mout_hsi0_bus",
2201
+
CLK_CON_GAT_CLK_BLK_HSI0_UID_HSI0_CMU_HSI0_IPCLKPORT_PCLK,
2202
+
21, CLK_IGNORE_UNUSED, 0),
2203
+
GATE(CLK_GOUT_HSI0_USB31DRD_I_USB31DRD_SUSPEND_CLK_26,
2204
+
"gout_hsi0_usb31drd_i_usb31drd_suspend_clk_26",
2205
+
"mout_hsi0_usb20_ref",
2206
+
CLK_CON_GAT_CLK_BLK_HSI0_UID_USB31DRD_IPCLKPORT_I_USB31DRD_SUSPEND_CLK_26,
2207
+
21, 0, 0),
2208
+
GATE(CLK_GOUT_HSI0_CLK_HSI0_ALT,
2209
+
"gout_hsi0_clk_hsi0_alt", "ioclk_clk_hsi0_alt",
2210
+
CLK_CON_GAT_CLK_HSI0_ALT, 21, 0, 0),
2211
+
GATE(CLK_GOUT_HSI0_DP_LINK_I_DP_GTC_CLK,
2212
+
"gout_hsi0_dp_link_i_dp_gtc_clk", "mout_hsi0_dpgtc_user",
2213
+
CLK_CON_GAT_GOUT_BLK_HSI0_UID_DP_LINK_IPCLKPORT_I_DP_GTC_CLK,
2214
+
21, 0, 0),
2215
+
GATE(CLK_GOUT_HSI0_DP_LINK_I_PCLK,
2216
+
"gout_hsi0_dp_link_i_pclk", "mout_hsi0_bus",
2217
+
CLK_CON_GAT_GOUT_BLK_HSI0_UID_DP_LINK_IPCLKPORT_I_PCLK, 21, 0, 0),
2218
+
GATE(CLK_GOUT_HSI0_D_TZPC_HSI0_PCLK,
2219
+
"gout_hsi0_d_tzpc_hsi0_pclk", "mout_hsi0_bus",
2220
+
CLK_CON_GAT_GOUT_BLK_HSI0_UID_D_TZPC_HSI0_IPCLKPORT_PCLK,
2221
+
21, 0, 0),
2222
+
GATE(CLK_GOUT_HSI0_ETR_MIU_I_ACLK,
2223
+
"gout_hsi0_etr_miu_i_aclk", "mout_hsi0_bus",
2224
+
CLK_CON_GAT_GOUT_BLK_HSI0_UID_ETR_MIU_IPCLKPORT_I_ACLK, 21, 0, 0),
2225
+
GATE(CLK_GOUT_HSI0_ETR_MIU_I_PCLK,
2226
+
"gout_hsi0_etr_miu_i_pclk", "mout_hsi0_bus",
2227
+
CLK_CON_GAT_GOUT_BLK_HSI0_UID_ETR_MIU_IPCLKPORT_I_PCLK, 21, 0, 0),
2228
+
GATE(CLK_GOUT_HSI0_GPC_HSI0_PCLK,
2229
+
"gout_hsi0_gpc_hsi0_pclk", "mout_hsi0_bus",
2230
+
CLK_CON_GAT_GOUT_BLK_HSI0_UID_GPC_HSI0_IPCLKPORT_PCLK, 21, 0, 0),
2231
+
GATE(CLK_GOUT_HSI0_LHM_AXI_G_ETR_HSI0_I_CLK,
2232
+
"gout_hsi0_lhm_axi_g_etr_hsi0_i_clk", "mout_hsi0_bus",
2233
+
CLK_CON_GAT_GOUT_BLK_HSI0_UID_LHM_AXI_G_ETR_HSI0_IPCLKPORT_I_CLK,
2234
+
21, 0, 0),
2235
+
GATE(CLK_GOUT_HSI0_LHM_AXI_P_AOCHSI0_I_CLK,
2236
+
"gout_hsi0_lhm_axi_p_aochsi0_i_clk", "mout_hsi0_bus",
2237
+
CLK_CON_GAT_GOUT_BLK_HSI0_UID_LHM_AXI_P_AOCHSI0_IPCLKPORT_I_CLK,
2238
+
21, 0, 0),
2239
+
/* TODO: should have a driver for this */
2240
+
GATE(CLK_GOUT_HSI0_LHM_AXI_P_HSI0_I_CLK,
2241
+
"gout_hsi0_lhm_axi_p_hsi0_i_clk", "mout_hsi0_bus",
2242
+
CLK_CON_GAT_GOUT_BLK_HSI0_UID_LHM_AXI_P_HSI0_IPCLKPORT_I_CLK,
2243
+
21, CLK_IGNORE_UNUSED, 0),
2244
+
/* TODO: should have a driver for this */
2245
+
GATE(CLK_GOUT_HSI0_LHS_ACEL_D_HSI0_I_CLK,
2246
+
"gout_hsi0_lhs_acel_d_hsi0_i_clk", "mout_hsi0_bus",
2247
+
CLK_CON_GAT_GOUT_BLK_HSI0_UID_LHS_ACEL_D_HSI0_IPCLKPORT_I_CLK,
2248
+
21, CLK_IGNORE_UNUSED, 0),
2249
+
GATE(CLK_GOUT_HSI0_LHS_AXI_D_HSI0AOC_I_CLK,
2250
+
"gout_hsi0_lhs_axi_d_hsi0aoc_i_clk", "mout_hsi0_bus",
2251
+
CLK_CON_GAT_GOUT_BLK_HSI0_UID_LHS_AXI_D_HSI0AOC_IPCLKPORT_I_CLK,
2252
+
21, 0, 0),
2253
+
GATE(CLK_GOUT_HSI0_PPMU_HSI0_AOC_ACLK,
2254
+
"gout_hsi0_ppmu_hsi0_aoc_aclk", "mout_hsi0_bus",
2255
+
CLK_CON_GAT_GOUT_BLK_HSI0_UID_PPMU_HSI0_AOC_IPCLKPORT_ACLK,
2256
+
21, 0, 0),
2257
+
GATE(CLK_GOUT_HSI0_PPMU_HSI0_AOC_PCLK,
2258
+
"gout_hsi0_ppmu_hsi0_aoc_pclk", "mout_hsi0_bus",
2259
+
CLK_CON_GAT_GOUT_BLK_HSI0_UID_PPMU_HSI0_AOC_IPCLKPORT_PCLK,
2260
+
21, 0, 0),
2261
+
GATE(CLK_GOUT_HSI0_PPMU_HSI0_BUS0_ACLK,
2262
+
"gout_hsi0_ppmu_hsi0_bus0_aclk", "mout_hsi0_bus",
2263
+
CLK_CON_GAT_GOUT_BLK_HSI0_UID_PPMU_HSI0_BUS0_IPCLKPORT_ACLK,
2264
+
21, 0, 0),
2265
+
GATE(CLK_GOUT_HSI0_PPMU_HSI0_BUS0_PCLK,
2266
+
"gout_hsi0_ppmu_hsi0_bus0_pclk", "mout_hsi0_bus",
2267
+
CLK_CON_GAT_GOUT_BLK_HSI0_UID_PPMU_HSI0_BUS0_IPCLKPORT_PCLK,
2268
+
21, 0, 0),
2269
+
GATE(CLK_GOUT_HSI0_CLK_HSI0_BUS_CLK,
2270
+
"gout_hsi0_clk_hsi0_bus_clk", "mout_hsi0_bus",
2271
+
CLK_CON_GAT_GOUT_BLK_HSI0_UID_RSTNSYNC_CLK_HSI0_BUS_IPCLKPORT_CLK,
2272
+
21, 0, 0),
2273
+
/* TODO: should have a driver for this */
2274
+
GATE(CLK_GOUT_HSI0_SSMT_USB_ACLK,
2275
+
"gout_hsi0_ssmt_usb_aclk", "mout_hsi0_bus",
2276
+
CLK_CON_GAT_GOUT_BLK_HSI0_UID_SSMT_USB_IPCLKPORT_ACLK,
2277
+
21, CLK_IGNORE_UNUSED, 0),
2278
+
/* TODO: should have a driver for this */
2279
+
GATE(CLK_GOUT_HSI0_SSMT_USB_PCLK,
2280
+
"gout_hsi0_ssmt_usb_pclk", "mout_hsi0_bus",
2281
+
CLK_CON_GAT_GOUT_BLK_HSI0_UID_SSMT_USB_IPCLKPORT_PCLK,
2282
+
21, CLK_IGNORE_UNUSED, 0),
2283
+
/* TODO: should have a driver for this */
2284
+
GATE(CLK_GOUT_HSI0_SYSMMU_USB_CLK_S2,
2285
+
"gout_hsi0_sysmmu_usb_clk_s2", "mout_hsi0_bus",
2286
+
CLK_CON_GAT_GOUT_BLK_HSI0_UID_SYSMMU_USB_IPCLKPORT_CLK_S2,
2287
+
21, CLK_IGNORE_UNUSED, 0),
2288
+
GATE(CLK_GOUT_HSI0_SYSREG_HSI0_PCLK,
2289
+
"gout_hsi0_sysreg_hsi0_pclk", "mout_hsi0_bus",
2290
+
CLK_CON_GAT_GOUT_BLK_HSI0_UID_SYSREG_HSI0_IPCLKPORT_PCLK,
2291
+
21, 0, 0),
2292
+
GATE(CLK_GOUT_HSI0_UASC_HSI0_CTRL_ACLK,
2293
+
"gout_hsi0_uasc_hsi0_ctrl_aclk", "mout_hsi0_bus",
2294
+
CLK_CON_GAT_GOUT_BLK_HSI0_UID_UASC_HSI0_CTRL_IPCLKPORT_ACLK,
2295
+
21, 0, 0),
2296
+
GATE(CLK_GOUT_HSI0_UASC_HSI0_CTRL_PCLK,
2297
+
"gout_hsi0_uasc_hsi0_ctrl_pclk", "mout_hsi0_bus",
2298
+
CLK_CON_GAT_GOUT_BLK_HSI0_UID_UASC_HSI0_CTRL_IPCLKPORT_PCLK,
2299
+
21, 0, 0),
2300
+
GATE(CLK_GOUT_HSI0_UASC_HSI0_LINK_ACLK,
2301
+
"gout_hsi0_uasc_hsi0_link_aclk", "mout_hsi0_bus",
2302
+
CLK_CON_GAT_GOUT_BLK_HSI0_UID_UASC_HSI0_LINK_IPCLKPORT_ACLK,
2303
+
21, 0, 0),
2304
+
GATE(CLK_GOUT_HSI0_UASC_HSI0_LINK_PCLK,
2305
+
"gout_hsi0_uasc_hsi0_link_pclk", "mout_hsi0_bus",
2306
+
CLK_CON_GAT_GOUT_BLK_HSI0_UID_UASC_HSI0_LINK_IPCLKPORT_PCLK,
2307
+
21, 0, 0),
2308
+
GATE(CLK_GOUT_HSI0_USB31DRD_ACLK_PHYCTRL,
2309
+
"gout_hsi0_usb31drd_aclk_phyctrl", "mout_hsi0_bus",
2310
+
CLK_CON_GAT_GOUT_BLK_HSI0_UID_USB31DRD_IPCLKPORT_ACLK_PHYCTRL,
2311
+
21, 0, 0),
2312
+
GATE(CLK_GOUT_HSI0_USB31DRD_BUS_CLK_EARLY,
2313
+
"gout_hsi0_usb31drd_bus_clk_early", "mout_hsi0_bus",
2314
+
CLK_CON_GAT_GOUT_BLK_HSI0_UID_USB31DRD_IPCLKPORT_BUS_CLK_EARLY,
2315
+
21, 0, 0),
2316
+
GATE(CLK_GOUT_HSI0_USB31DRD_I_USB20_PHY_REFCLK_26,
2317
+
"gout_hsi0_usb31drd_i_usb20_phy_refclk_26", "mout_hsi0_usb20_ref",
2318
+
CLK_CON_GAT_GOUT_BLK_HSI0_UID_USB31DRD_IPCLKPORT_I_USB20_PHY_REFCLK_26,
2319
+
21, 0, 0),
2320
+
GATE(CLK_GOUT_HSI0_USB31DRD_I_USB31DRD_REF_CLK_40,
2321
+
"gout_hsi0_usb31drd_i_usb31drd_ref_clk_40", "mout_hsi0_usb31drd",
2322
+
CLK_CON_GAT_GOUT_BLK_HSI0_UID_USB31DRD_IPCLKPORT_I_USB31DRD_REF_CLK_40,
2323
+
21, 0, 0),
2324
+
GATE(CLK_GOUT_HSI0_USB31DRD_I_USBDPPHY_REF_SOC_PLL,
2325
+
"gout_hsi0_usb31drd_i_usbdpphy_ref_soc_pll",
2326
+
"mout_hsi0_usbdpdbg_user",
2327
+
CLK_CON_GAT_GOUT_BLK_HSI0_UID_USB31DRD_IPCLKPORT_I_USBDPPHY_REF_SOC_PLL,
2328
+
21, 0, 0),
2329
+
GATE(CLK_GOUT_HSI0_USB31DRD_I_USBDPPHY_SCL_APB_PCLK,
2330
+
"gout_hsi0_usb31drd_i_usbdpphy_scl_apb_pclk", "mout_hsi0_bus",
2331
+
CLK_CON_GAT_GOUT_BLK_HSI0_UID_USB31DRD_IPCLKPORT_I_USBDPPHY_SCL_APB_PCLK,
2332
+
21, 0, 0),
2333
+
GATE(CLK_GOUT_HSI0_USB31DRD_I_USBPCS_APB_CLK,
2334
+
"gout_hsi0_usb31drd_i_usbpcs_apb_clk", "mout_hsi0_bus",
2335
+
CLK_CON_GAT_GOUT_BLK_HSI0_UID_USB31DRD_IPCLKPORT_I_USBPCS_APB_CLK,
2336
+
21, 0, 0),
2337
+
GATE(CLK_GOUT_HSI0_USB31DRD_USBDPPHY_I_ACLK,
2338
+
"gout_hsi0_usb31drd_usbdpphy_i_aclk", "mout_hsi0_bus",
2339
+
CLK_CON_GAT_GOUT_BLK_HSI0_UID_USB31DRD_IPCLKPORT_USBDPPHY_I_ACLK,
2340
+
21, 0, 0),
2341
+
GATE(CLK_GOUT_HSI0_USB31DRD_USBDPPHY_UDBG_I_APB_PCLK,
2342
+
"gout_hsi0_usb31drd_usbdpphy_udbg_i_apb_pclk", "mout_hsi0_bus",
2343
+
CLK_CON_GAT_GOUT_BLK_HSI0_UID_USB31DRD_IPCLKPORT_USBDPPHY_UDBG_I_APB_PCLK,
2344
+
21, 0, 0),
2345
+
/* TODO: should have a driver for this */
2346
+
GATE(CLK_GOUT_HSI0_XIU_D0_HSI0_ACLK,
2347
+
"gout_hsi0_xiu_d0_hsi0_aclk", "mout_hsi0_bus",
2348
+
CLK_CON_GAT_GOUT_BLK_HSI0_UID_XIU_D0_HSI0_IPCLKPORT_ACLK,
2349
+
21, CLK_IGNORE_UNUSED, 0),
2350
+
/* TODO: should have a driver for this */
2351
+
GATE(CLK_GOUT_HSI0_XIU_D1_HSI0_ACLK,
2352
+
"gout_hsi0_xiu_d1_hsi0_aclk", "mout_hsi0_bus",
2353
+
CLK_CON_GAT_GOUT_BLK_HSI0_UID_XIU_D1_HSI0_IPCLKPORT_ACLK,
2354
+
21, CLK_IGNORE_UNUSED, 0),
2355
+
/* TODO: should have a driver for this */
2356
+
GATE(CLK_GOUT_HSI0_XIU_P_HSI0_ACLK,
2357
+
"gout_hsi0_xiu_p_hsi0_aclk", "mout_hsi0_bus",
2358
+
CLK_CON_GAT_GOUT_BLK_HSI0_UID_XIU_P_HSI0_IPCLKPORT_ACLK,
2359
+
21, CLK_IGNORE_UNUSED, 0),
2360
+
};
2361
+
2362
+
static const struct samsung_fixed_rate_clock hsi0_fixed_clks[] __initconst = {
2363
+
FRATE(0, "tcxo_hsi1_hsi0", NULL, 0, 26000000),
2364
+
FRATE(0, "usb20phy_phy_clock", NULL, 0, 120000000),
2365
+
/* until we implement APMGSA */
2366
+
FRATE(0, "ioclk_clk_hsi0_alt", NULL, 0, 213000000),
2367
+
};
2368
+
2369
+
static const struct samsung_cmu_info hsi0_cmu_info __initconst = {
2370
+
.pll_clks = cmu_hsi0_pll_clks,
2371
+
.nr_pll_clks = ARRAY_SIZE(cmu_hsi0_pll_clks),
2372
+
.mux_clks = hsi0_mux_clks,
2373
+
.nr_mux_clks = ARRAY_SIZE(hsi0_mux_clks),
2374
+
.div_clks = hsi0_div_clks,
2375
+
.nr_div_clks = ARRAY_SIZE(hsi0_div_clks),
2376
+
.gate_clks = hsi0_gate_clks,
2377
+
.nr_gate_clks = ARRAY_SIZE(hsi0_gate_clks),
2378
+
.fixed_clks = hsi0_fixed_clks,
2379
+
.nr_fixed_clks = ARRAY_SIZE(hsi0_fixed_clks),
2380
+
.nr_clk_ids = CLKS_NR_HSI0,
2381
+
.clk_regs = hsi0_clk_regs,
2382
+
.nr_clk_regs = ARRAY_SIZE(hsi0_clk_regs),
2383
+
.clk_name = "bus",
2384
+
};
2385
+
2386
+
/* ---- CMU_HSI2 ------------------------------------------------------------ */
2387
+
2388
+
/* Register Offset definitions for CMU_HSI2 (0x14400000) */
2389
+
#define PLL_CON0_MUX_CLKCMU_HSI2_BUS_USER 0x0600
2390
+
#define PLL_CON1_MUX_CLKCMU_HSI2_BUS_USER 0x0604
2391
+
#define PLL_CON0_MUX_CLKCMU_HSI2_MMC_CARD_USER 0x0610
2392
+
#define PLL_CON1_MUX_CLKCMU_HSI2_MMC_CARD_USER 0x0614
2393
+
#define PLL_CON0_MUX_CLKCMU_HSI2_PCIE_USER 0x0620
2394
+
#define PLL_CON1_MUX_CLKCMU_HSI2_PCIE_USER 0x0624
2395
+
#define PLL_CON0_MUX_CLKCMU_HSI2_UFS_EMBD_USER 0x0630
2396
+
#define PLL_CON1_MUX_CLKCMU_HSI2_UFS_EMBD_USER 0x0634
2397
+
#define HSI2_CMU_HSI2_CONTROLLER_OPTION 0x0800
2398
+
#define CLKOUT_CON_BLK_HSI2_CMU_HSI2_CLKOUT0 0x0810
2399
+
#define CLK_CON_GAT_CLK_BLK_HSI2_UID_PCIE_GEN4_1_IPCLKPORT_PCIE_003_PCIE_SUB_CTRL_INST_0_PHY_REFCLK_IN 0x2000
2400
+
#define CLK_CON_GAT_CLK_BLK_HSI2_UID_PCIE_GEN4_1_IPCLKPORT_PCIE_004_PCIE_SUB_CTRL_INST_0_PHY_REFCLK_IN 0x2004
2401
+
#define CLK_CON_GAT_CLK_BLK_HSI2_UID_SSMT_PCIE_IA_GEN4A_1_IPCLKPORT_ACLK 0x2008
2402
+
#define CLK_CON_GAT_CLK_BLK_HSI2_UID_SSMT_PCIE_IA_GEN4A_1_IPCLKPORT_PCLK 0x200c
2403
+
#define CLK_CON_GAT_CLK_BLK_HSI2_UID_SSMT_PCIE_IA_GEN4B_1_IPCLKPORT_ACLK 0x2010
2404
+
#define CLK_CON_GAT_CLK_BLK_HSI2_UID_SSMT_PCIE_IA_GEN4B_1_IPCLKPORT_PCLK 0x2014
2405
+
#define CLK_CON_GAT_GOUT_BLK_HSI2_UID_D_TZPC_HSI2_IPCLKPORT_PCLK 0x201c
2406
+
#define CLK_CON_GAT_GOUT_BLK_HSI2_UID_GPC_HSI2_IPCLKPORT_PCLK 0x2020
2407
+
#define CLK_CON_GAT_GOUT_BLK_HSI2_UID_GPIO_HSI2_IPCLKPORT_PCLK 0x2024
2408
+
#define CLK_CON_GAT_GOUT_BLK_HSI2_UID_HSI2_CMU_HSI2_IPCLKPORT_PCLK 0x2028
2409
+
#define CLK_CON_GAT_GOUT_BLK_HSI2_UID_LHM_AXI_P_HSI2_IPCLKPORT_I_CLK 0x202c
2410
+
#define CLK_CON_GAT_GOUT_BLK_HSI2_UID_LHS_ACEL_D_HSI2_IPCLKPORT_I_CLK 0x2030
2411
+
#define CLK_CON_GAT_GOUT_BLK_HSI2_UID_MMC_CARD_IPCLKPORT_I_ACLK 0x2034
2412
+
#define CLK_CON_GAT_GOUT_BLK_HSI2_UID_MMC_CARD_IPCLKPORT_SDCLKIN 0x2038
2413
+
#define CLK_CON_GAT_GOUT_BLK_HSI2_UID_PCIE_GEN4_1_IPCLKPORT_PCIE_003_G4X2_DWC_PCIE_CTL_INST_0_DBI_ACLK_UG 0x203c
2414
+
#define CLK_CON_GAT_GOUT_BLK_HSI2_UID_PCIE_GEN4_1_IPCLKPORT_PCIE_003_G4X2_DWC_PCIE_CTL_INST_0_MSTR_ACLK_UG 0x2040
2415
+
#define CLK_CON_GAT_GOUT_BLK_HSI2_UID_PCIE_GEN4_1_IPCLKPORT_PCIE_003_G4X2_DWC_PCIE_CTL_INST_0_SLV_ACLK_UG 0x2044
2416
+
#define CLK_CON_GAT_GOUT_BLK_HSI2_UID_PCIE_GEN4_1_IPCLKPORT_PCIE_003_PCIE_SUB_CTRL_INST_0_I_DRIVER_APB_CLK 0x2048
2417
+
#define CLK_CON_GAT_GOUT_BLK_HSI2_UID_PCIE_GEN4_1_IPCLKPORT_PCIE_004_G4X1_DWC_PCIE_CTL_INST_0_DBI_ACLK_UG 0x204c
2418
+
#define CLK_CON_GAT_GOUT_BLK_HSI2_UID_PCIE_GEN4_1_IPCLKPORT_PCIE_004_G4X1_DWC_PCIE_CTL_INST_0_MSTR_ACLK_UG 0x2050
2419
+
#define CLK_CON_GAT_GOUT_BLK_HSI2_UID_PCIE_GEN4_1_IPCLKPORT_PCIE_004_G4X1_DWC_PCIE_CTL_INST_0_SLV_ACLK_UG 0x2054
2420
+
#define CLK_CON_GAT_GOUT_BLK_HSI2_UID_PCIE_GEN4_1_IPCLKPORT_PCIE_004_PCIE_SUB_CTRL_INST_0_I_DRIVER_APB_CLK 0x2058
2421
+
#define CLK_CON_GAT_GOUT_BLK_HSI2_UID_PCIE_GEN4_1_IPCLKPORT_PCS_PMA_INST_0_PHY_UDBG_I_APB_PCLK 0x205c
2422
+
#define CLK_CON_GAT_GOUT_BLK_HSI2_UID_PCIE_GEN4_1_IPCLKPORT_PCS_PMA_INST_0_PIPE_PAL_PCIE_INST_0_I_APB_PCLK 0x2060
2423
+
#define CLK_CON_GAT_GOUT_BLK_HSI2_UID_PCIE_GEN4_1_IPCLKPORT_PCS_PMA_INST_0_SF_PCIEPHY210X2_LN05LPE_QCH_TM_WRAPPER_INST_0_I_APB_PCLK 0x2064
2424
+
#define CLK_CON_GAT_GOUT_BLK_HSI2_UID_PCIE_IA_GEN4A_1_IPCLKPORT_I_CLK 0x2068
2425
+
#define CLK_CON_GAT_GOUT_BLK_HSI2_UID_PCIE_IA_GEN4B_1_IPCLKPORT_I_CLK 0x206c
2426
+
#define CLK_CON_GAT_GOUT_BLK_HSI2_UID_PPMU_HSI2_IPCLKPORT_ACLK 0x2070
2427
+
#define CLK_CON_GAT_GOUT_BLK_HSI2_UID_PPMU_HSI2_IPCLKPORT_PCLK 0x2074
2428
+
#define CLK_CON_GAT_GOUT_BLK_HSI2_UID_QE_MMC_CARD_HSI2_IPCLKPORT_ACLK 0x2078
2429
+
#define CLK_CON_GAT_GOUT_BLK_HSI2_UID_QE_MMC_CARD_HSI2_IPCLKPORT_PCLK 0x207c
2430
+
#define CLK_CON_GAT_GOUT_BLK_HSI2_UID_QE_PCIE_GEN4A_HSI2_IPCLKPORT_ACLK 0x2080
2431
+
#define CLK_CON_GAT_GOUT_BLK_HSI2_UID_QE_PCIE_GEN4A_HSI2_IPCLKPORT_PCLK 0x2084
2432
+
#define CLK_CON_GAT_GOUT_BLK_HSI2_UID_QE_PCIE_GEN4B_HSI2_IPCLKPORT_ACLK 0x2088
2433
+
#define CLK_CON_GAT_GOUT_BLK_HSI2_UID_QE_PCIE_GEN4B_HSI2_IPCLKPORT_PCLK 0x208c
2434
+
#define CLK_CON_GAT_GOUT_BLK_HSI2_UID_QE_UFS_EMBD_HSI2_IPCLKPORT_ACLK 0x2090
2435
+
#define CLK_CON_GAT_GOUT_BLK_HSI2_UID_QE_UFS_EMBD_HSI2_IPCLKPORT_PCLK 0x2094
2436
+
#define CLK_CON_GAT_GOUT_BLK_HSI2_UID_RSTNSYNC_CLK_HSI2_BUS_IPCLKPORT_CLK 0x2098
2437
+
#define CLK_CON_GAT_GOUT_BLK_HSI2_UID_RSTNSYNC_CLK_HSI2_OSCCLK_IPCLKPORT_CLK 0x209c
2438
+
#define CLK_CON_GAT_GOUT_BLK_HSI2_UID_SSMT_HSI2_IPCLKPORT_ACLK 0x20a0
2439
+
#define CLK_CON_GAT_GOUT_BLK_HSI2_UID_SSMT_HSI2_IPCLKPORT_PCLK 0x20a4
2440
+
#define CLK_CON_GAT_GOUT_BLK_HSI2_UID_SYSMMU_HSI2_IPCLKPORT_CLK_S2 0x20a8
2441
+
#define CLK_CON_GAT_GOUT_BLK_HSI2_UID_SYSREG_HSI2_IPCLKPORT_PCLK 0x20ac
2442
+
#define CLK_CON_GAT_GOUT_BLK_HSI2_UID_UASC_PCIE_GEN4A_DBI_1_IPCLKPORT_ACLK 0x20b0
2443
+
#define CLK_CON_GAT_GOUT_BLK_HSI2_UID_UASC_PCIE_GEN4A_DBI_1_IPCLKPORT_PCLK 0x20b4
2444
+
#define CLK_CON_GAT_GOUT_BLK_HSI2_UID_UASC_PCIE_GEN4A_SLV_1_IPCLKPORT_ACLK 0x20b8
2445
+
#define CLK_CON_GAT_GOUT_BLK_HSI2_UID_UASC_PCIE_GEN4A_SLV_1_IPCLKPORT_PCLK 0x20bc
2446
+
#define CLK_CON_GAT_GOUT_BLK_HSI2_UID_UASC_PCIE_GEN4B_DBI_1_IPCLKPORT_ACLK 0x20c0
2447
+
#define CLK_CON_GAT_GOUT_BLK_HSI2_UID_UASC_PCIE_GEN4B_DBI_1_IPCLKPORT_PCLK 0x20c4
2448
+
#define CLK_CON_GAT_GOUT_BLK_HSI2_UID_UASC_PCIE_GEN4B_SLV_1_IPCLKPORT_ACLK 0x20c8
2449
+
#define CLK_CON_GAT_GOUT_BLK_HSI2_UID_UASC_PCIE_GEN4B_SLV_1_IPCLKPORT_PCLK 0x20cc
2450
+
#define CLK_CON_GAT_GOUT_BLK_HSI2_UID_UFS_EMBD_IPCLKPORT_I_ACLK 0x20d0
2451
+
#define CLK_CON_GAT_GOUT_BLK_HSI2_UID_UFS_EMBD_IPCLKPORT_I_CLK_UNIPRO 0x20d4
2452
+
#define CLK_CON_GAT_GOUT_BLK_HSI2_UID_UFS_EMBD_IPCLKPORT_I_FMP_CLK 0x20d8
2453
+
#define CLK_CON_GAT_GOUT_BLK_HSI2_UID_XIU_D_HSI2_IPCLKPORT_ACLK 0x20dc
2454
+
#define CLK_CON_GAT_GOUT_BLK_HSI2_UID_XIU_P_HSI2_IPCLKPORT_ACLK 0x20e0
2455
+
#define DMYQCH_CON_PCIE_GEN4_1_QCH_SCLK_1 0x3000
2456
+
#define PCH_CON_LHM_AXI_P_HSI2_PCH 0x3008
2457
+
#define PCH_CON_LHS_ACEL_D_HSI2_PCH 0x300c
2458
+
#define QCH_CON_D_TZPC_HSI2_QCH 0x3010
2459
+
#define QCH_CON_GPC_HSI2_QCH 0x3014
2460
+
#define QCH_CON_GPIO_HSI2_QCH 0x3018
2461
+
#define QCH_CON_HSI2_CMU_HSI2_QCH 0x301c
2462
+
#define QCH_CON_LHM_AXI_P_HSI2_QCH 0x3020
2463
+
#define QCH_CON_LHS_ACEL_D_HSI2_QCH 0x3024
2464
+
#define QCH_CON_MMC_CARD_QCH 0x3028
2465
+
#define QCH_CON_PCIE_GEN4_1_QCH_APB_1 0x302c
2466
+
#define QCH_CON_PCIE_GEN4_1_QCH_APB_2 0x3030
2467
+
#define QCH_CON_PCIE_GEN4_1_QCH_AXI_1 0x3034
2468
+
#define QCH_CON_PCIE_GEN4_1_QCH_AXI_2 0x3038
2469
+
#define QCH_CON_PCIE_GEN4_1_QCH_DBG_1 0x303c
2470
+
#define QCH_CON_PCIE_GEN4_1_QCH_DBG_2 0x3040
2471
+
#define QCH_CON_PCIE_GEN4_1_QCH_PCS_APB 0x3044
2472
+
#define QCH_CON_PCIE_GEN4_1_QCH_PMA_APB 0x3048
2473
+
#define QCH_CON_PCIE_GEN4_1_QCH_UDBG 0x304c
2474
+
#define QCH_CON_PCIE_IA_GEN4A_1_QCH 0x3050
2475
+
#define QCH_CON_PCIE_IA_GEN4B_1_QCH 0x3054
2476
+
#define QCH_CON_PPMU_HSI2_QCH 0x3058
2477
+
#define QCH_CON_QE_MMC_CARD_HSI2_QCH 0x305c
2478
+
#define QCH_CON_QE_PCIE_GEN4A_HSI2_QCH 0x3060
2479
+
#define QCH_CON_QE_PCIE_GEN4B_HSI2_QCH 0x3064
2480
+
#define QCH_CON_QE_UFS_EMBD_HSI2_QCH 0x3068
2481
+
#define QCH_CON_SSMT_HSI2_QCH 0x306c
2482
+
#define QCH_CON_SSMT_PCIE_IA_GEN4A_1_QCH 0x3070
2483
+
#define QCH_CON_SSMT_PCIE_IA_GEN4B_1_QCH 0x3074
2484
+
#define QCH_CON_SYSMMU_HSI2_QCH 0x3078
2485
+
#define QCH_CON_SYSREG_HSI2_QCH 0x307c
2486
+
#define QCH_CON_UASC_PCIE_GEN4A_DBI_1_QCH 0x3080
2487
+
#define QCH_CON_UASC_PCIE_GEN4A_SLV_1_QCH 0x3084
2488
+
#define QCH_CON_UASC_PCIE_GEN4B_DBI_1_QCH 0x3088
2489
+
#define QCH_CON_UASC_PCIE_GEN4B_SLV_1_QCH 0x308c
2490
+
#define QCH_CON_UFS_EMBD_QCH 0x3090
2491
+
#define QCH_CON_UFS_EMBD_QCH_FMP 0x3094
2492
+
#define QUEUE_CTRL_REG_BLK_HSI2_CMU_HSI2 0x3c00
2493
+
2494
+
static const unsigned long cmu_hsi2_clk_regs[] __initconst = {
2495
+
PLL_CON0_MUX_CLKCMU_HSI2_BUS_USER,
2496
+
PLL_CON1_MUX_CLKCMU_HSI2_BUS_USER,
2497
+
PLL_CON0_MUX_CLKCMU_HSI2_MMC_CARD_USER,
2498
+
PLL_CON1_MUX_CLKCMU_HSI2_MMC_CARD_USER,
2499
+
PLL_CON0_MUX_CLKCMU_HSI2_PCIE_USER,
2500
+
PLL_CON1_MUX_CLKCMU_HSI2_PCIE_USER,
2501
+
PLL_CON0_MUX_CLKCMU_HSI2_UFS_EMBD_USER,
2502
+
PLL_CON1_MUX_CLKCMU_HSI2_UFS_EMBD_USER,
2503
+
HSI2_CMU_HSI2_CONTROLLER_OPTION,
2504
+
CLKOUT_CON_BLK_HSI2_CMU_HSI2_CLKOUT0,
2505
+
CLK_CON_GAT_CLK_BLK_HSI2_UID_PCIE_GEN4_1_IPCLKPORT_PCIE_003_PCIE_SUB_CTRL_INST_0_PHY_REFCLK_IN,
2506
+
CLK_CON_GAT_CLK_BLK_HSI2_UID_PCIE_GEN4_1_IPCLKPORT_PCIE_004_PCIE_SUB_CTRL_INST_0_PHY_REFCLK_IN,
2507
+
CLK_CON_GAT_CLK_BLK_HSI2_UID_SSMT_PCIE_IA_GEN4A_1_IPCLKPORT_ACLK,
2508
+
CLK_CON_GAT_CLK_BLK_HSI2_UID_SSMT_PCIE_IA_GEN4A_1_IPCLKPORT_PCLK,
2509
+
CLK_CON_GAT_CLK_BLK_HSI2_UID_SSMT_PCIE_IA_GEN4B_1_IPCLKPORT_ACLK,
2510
+
CLK_CON_GAT_CLK_BLK_HSI2_UID_SSMT_PCIE_IA_GEN4B_1_IPCLKPORT_PCLK,
2511
+
CLK_CON_GAT_GOUT_BLK_HSI2_UID_D_TZPC_HSI2_IPCLKPORT_PCLK,
2512
+
CLK_CON_GAT_GOUT_BLK_HSI2_UID_GPC_HSI2_IPCLKPORT_PCLK,
2513
+
CLK_CON_GAT_GOUT_BLK_HSI2_UID_GPIO_HSI2_IPCLKPORT_PCLK,
2514
+
CLK_CON_GAT_GOUT_BLK_HSI2_UID_HSI2_CMU_HSI2_IPCLKPORT_PCLK,
2515
+
CLK_CON_GAT_GOUT_BLK_HSI2_UID_LHM_AXI_P_HSI2_IPCLKPORT_I_CLK,
2516
+
CLK_CON_GAT_GOUT_BLK_HSI2_UID_LHS_ACEL_D_HSI2_IPCLKPORT_I_CLK,
2517
+
CLK_CON_GAT_GOUT_BLK_HSI2_UID_MMC_CARD_IPCLKPORT_I_ACLK,
2518
+
CLK_CON_GAT_GOUT_BLK_HSI2_UID_MMC_CARD_IPCLKPORT_SDCLKIN,
2519
+
CLK_CON_GAT_GOUT_BLK_HSI2_UID_PCIE_GEN4_1_IPCLKPORT_PCIE_003_G4X2_DWC_PCIE_CTL_INST_0_DBI_ACLK_UG,
2520
+
CLK_CON_GAT_GOUT_BLK_HSI2_UID_PCIE_GEN4_1_IPCLKPORT_PCIE_003_G4X2_DWC_PCIE_CTL_INST_0_MSTR_ACLK_UG,
2521
+
CLK_CON_GAT_GOUT_BLK_HSI2_UID_PCIE_GEN4_1_IPCLKPORT_PCIE_003_G4X2_DWC_PCIE_CTL_INST_0_SLV_ACLK_UG,
2522
+
CLK_CON_GAT_GOUT_BLK_HSI2_UID_PCIE_GEN4_1_IPCLKPORT_PCIE_003_PCIE_SUB_CTRL_INST_0_I_DRIVER_APB_CLK,
2523
+
CLK_CON_GAT_GOUT_BLK_HSI2_UID_PCIE_GEN4_1_IPCLKPORT_PCIE_004_G4X1_DWC_PCIE_CTL_INST_0_DBI_ACLK_UG,
2524
+
CLK_CON_GAT_GOUT_BLK_HSI2_UID_PCIE_GEN4_1_IPCLKPORT_PCIE_004_G4X1_DWC_PCIE_CTL_INST_0_MSTR_ACLK_UG,
2525
+
CLK_CON_GAT_GOUT_BLK_HSI2_UID_PCIE_GEN4_1_IPCLKPORT_PCIE_004_G4X1_DWC_PCIE_CTL_INST_0_SLV_ACLK_UG,
2526
+
CLK_CON_GAT_GOUT_BLK_HSI2_UID_PCIE_GEN4_1_IPCLKPORT_PCIE_004_PCIE_SUB_CTRL_INST_0_I_DRIVER_APB_CLK,
2527
+
CLK_CON_GAT_GOUT_BLK_HSI2_UID_PCIE_GEN4_1_IPCLKPORT_PCS_PMA_INST_0_PHY_UDBG_I_APB_PCLK,
2528
+
CLK_CON_GAT_GOUT_BLK_HSI2_UID_PCIE_GEN4_1_IPCLKPORT_PCS_PMA_INST_0_PIPE_PAL_PCIE_INST_0_I_APB_PCLK,
2529
+
CLK_CON_GAT_GOUT_BLK_HSI2_UID_PCIE_GEN4_1_IPCLKPORT_PCS_PMA_INST_0_SF_PCIEPHY210X2_LN05LPE_QCH_TM_WRAPPER_INST_0_I_APB_PCLK,
2530
+
CLK_CON_GAT_GOUT_BLK_HSI2_UID_PCIE_IA_GEN4A_1_IPCLKPORT_I_CLK,
2531
+
CLK_CON_GAT_GOUT_BLK_HSI2_UID_PCIE_IA_GEN4B_1_IPCLKPORT_I_CLK,
2532
+
CLK_CON_GAT_GOUT_BLK_HSI2_UID_PPMU_HSI2_IPCLKPORT_ACLK,
2533
+
CLK_CON_GAT_GOUT_BLK_HSI2_UID_PPMU_HSI2_IPCLKPORT_PCLK,
2534
+
CLK_CON_GAT_GOUT_BLK_HSI2_UID_QE_MMC_CARD_HSI2_IPCLKPORT_ACLK,
2535
+
CLK_CON_GAT_GOUT_BLK_HSI2_UID_QE_MMC_CARD_HSI2_IPCLKPORT_PCLK,
2536
+
CLK_CON_GAT_GOUT_BLK_HSI2_UID_QE_PCIE_GEN4A_HSI2_IPCLKPORT_ACLK,
2537
+
CLK_CON_GAT_GOUT_BLK_HSI2_UID_QE_PCIE_GEN4A_HSI2_IPCLKPORT_PCLK,
2538
+
CLK_CON_GAT_GOUT_BLK_HSI2_UID_QE_PCIE_GEN4B_HSI2_IPCLKPORT_ACLK,
2539
+
CLK_CON_GAT_GOUT_BLK_HSI2_UID_QE_PCIE_GEN4B_HSI2_IPCLKPORT_PCLK,
2540
+
CLK_CON_GAT_GOUT_BLK_HSI2_UID_QE_UFS_EMBD_HSI2_IPCLKPORT_ACLK,
2541
+
CLK_CON_GAT_GOUT_BLK_HSI2_UID_QE_UFS_EMBD_HSI2_IPCLKPORT_PCLK,
2542
+
CLK_CON_GAT_GOUT_BLK_HSI2_UID_RSTNSYNC_CLK_HSI2_BUS_IPCLKPORT_CLK,
2543
+
CLK_CON_GAT_GOUT_BLK_HSI2_UID_RSTNSYNC_CLK_HSI2_OSCCLK_IPCLKPORT_CLK,
2544
+
CLK_CON_GAT_GOUT_BLK_HSI2_UID_SSMT_HSI2_IPCLKPORT_ACLK,
2545
+
CLK_CON_GAT_GOUT_BLK_HSI2_UID_SSMT_HSI2_IPCLKPORT_PCLK,
2546
+
CLK_CON_GAT_GOUT_BLK_HSI2_UID_SYSMMU_HSI2_IPCLKPORT_CLK_S2,
2547
+
CLK_CON_GAT_GOUT_BLK_HSI2_UID_SYSREG_HSI2_IPCLKPORT_PCLK,
2548
+
CLK_CON_GAT_GOUT_BLK_HSI2_UID_UASC_PCIE_GEN4A_DBI_1_IPCLKPORT_ACLK,
2549
+
CLK_CON_GAT_GOUT_BLK_HSI2_UID_UASC_PCIE_GEN4A_DBI_1_IPCLKPORT_PCLK,
2550
+
CLK_CON_GAT_GOUT_BLK_HSI2_UID_UASC_PCIE_GEN4A_SLV_1_IPCLKPORT_ACLK,
2551
+
CLK_CON_GAT_GOUT_BLK_HSI2_UID_UASC_PCIE_GEN4A_SLV_1_IPCLKPORT_PCLK,
2552
+
CLK_CON_GAT_GOUT_BLK_HSI2_UID_UASC_PCIE_GEN4B_DBI_1_IPCLKPORT_ACLK,
2553
+
CLK_CON_GAT_GOUT_BLK_HSI2_UID_UASC_PCIE_GEN4B_DBI_1_IPCLKPORT_PCLK,
2554
+
CLK_CON_GAT_GOUT_BLK_HSI2_UID_UASC_PCIE_GEN4B_SLV_1_IPCLKPORT_ACLK,
2555
+
CLK_CON_GAT_GOUT_BLK_HSI2_UID_UASC_PCIE_GEN4B_SLV_1_IPCLKPORT_PCLK,
2556
+
CLK_CON_GAT_GOUT_BLK_HSI2_UID_UFS_EMBD_IPCLKPORT_I_ACLK,
2557
+
CLK_CON_GAT_GOUT_BLK_HSI2_UID_UFS_EMBD_IPCLKPORT_I_CLK_UNIPRO,
2558
+
CLK_CON_GAT_GOUT_BLK_HSI2_UID_UFS_EMBD_IPCLKPORT_I_FMP_CLK,
2559
+
CLK_CON_GAT_GOUT_BLK_HSI2_UID_XIU_D_HSI2_IPCLKPORT_ACLK,
2560
+
CLK_CON_GAT_GOUT_BLK_HSI2_UID_XIU_P_HSI2_IPCLKPORT_ACLK,
2561
+
DMYQCH_CON_PCIE_GEN4_1_QCH_SCLK_1,
2562
+
PCH_CON_LHM_AXI_P_HSI2_PCH,
2563
+
PCH_CON_LHS_ACEL_D_HSI2_PCH,
2564
+
QCH_CON_D_TZPC_HSI2_QCH,
2565
+
QCH_CON_GPC_HSI2_QCH,
2566
+
QCH_CON_GPIO_HSI2_QCH,
2567
+
QCH_CON_HSI2_CMU_HSI2_QCH,
2568
+
QCH_CON_LHM_AXI_P_HSI2_QCH,
2569
+
QCH_CON_LHS_ACEL_D_HSI2_QCH,
2570
+
QCH_CON_MMC_CARD_QCH,
2571
+
QCH_CON_PCIE_GEN4_1_QCH_APB_1,
2572
+
QCH_CON_PCIE_GEN4_1_QCH_APB_2,
2573
+
QCH_CON_PCIE_GEN4_1_QCH_AXI_1,
2574
+
QCH_CON_PCIE_GEN4_1_QCH_AXI_2,
2575
+
QCH_CON_PCIE_GEN4_1_QCH_DBG_1,
2576
+
QCH_CON_PCIE_GEN4_1_QCH_DBG_2,
2577
+
QCH_CON_PCIE_GEN4_1_QCH_PCS_APB,
2578
+
QCH_CON_PCIE_GEN4_1_QCH_PMA_APB,
2579
+
QCH_CON_PCIE_GEN4_1_QCH_UDBG,
2580
+
QCH_CON_PCIE_IA_GEN4A_1_QCH,
2581
+
QCH_CON_PCIE_IA_GEN4B_1_QCH,
2582
+
QCH_CON_PPMU_HSI2_QCH,
2583
+
QCH_CON_QE_MMC_CARD_HSI2_QCH,
2584
+
QCH_CON_QE_PCIE_GEN4A_HSI2_QCH,
2585
+
QCH_CON_QE_PCIE_GEN4B_HSI2_QCH,
2586
+
QCH_CON_QE_UFS_EMBD_HSI2_QCH,
2587
+
QCH_CON_SSMT_HSI2_QCH,
2588
+
QCH_CON_SSMT_PCIE_IA_GEN4A_1_QCH,
2589
+
QCH_CON_SSMT_PCIE_IA_GEN4B_1_QCH,
2590
+
QCH_CON_SYSMMU_HSI2_QCH,
2591
+
QCH_CON_SYSREG_HSI2_QCH,
2592
+
QCH_CON_UASC_PCIE_GEN4A_DBI_1_QCH,
2593
+
QCH_CON_UASC_PCIE_GEN4A_SLV_1_QCH,
2594
+
QCH_CON_UASC_PCIE_GEN4B_DBI_1_QCH,
2595
+
QCH_CON_UASC_PCIE_GEN4B_SLV_1_QCH,
2596
+
QCH_CON_UFS_EMBD_QCH,
2597
+
QCH_CON_UFS_EMBD_QCH_FMP,
2598
+
QUEUE_CTRL_REG_BLK_HSI2_CMU_HSI2,
2599
+
};
2600
+
2601
+
PNAME(mout_hsi2_bus_user_p) = { "oscclk", "dout_cmu_hsi2_bus" };
2602
+
PNAME(mout_hsi2_mmc_card_user_p) = { "oscclk", "dout_cmu_hsi2_mmc_card" };
2603
+
PNAME(mout_hsi2_pcie_user_p) = { "oscclk", "dout_cmu_hsi2_pcie" };
2604
+
PNAME(mout_hsi2_ufs_embd_user_p) = { "oscclk", "dout_cmu_hsi2_ufs_embd" };
2605
+
2606
+
static const struct samsung_mux_clock hsi2_mux_clks[] __initconst = {
2607
+
MUX(CLK_MOUT_HSI2_BUS_USER, "mout_hsi2_bus_user", mout_hsi2_bus_user_p,
2608
+
PLL_CON0_MUX_CLKCMU_HSI2_BUS_USER, 4, 1),
2609
+
MUX(CLK_MOUT_HSI2_MMC_CARD_USER, "mout_hsi2_mmc_card_user",
2610
+
mout_hsi2_mmc_card_user_p, PLL_CON0_MUX_CLKCMU_HSI2_MMC_CARD_USER,
2611
+
4, 1),
2612
+
MUX(CLK_MOUT_HSI2_PCIE_USER, "mout_hsi2_pcie_user",
2613
+
mout_hsi2_pcie_user_p, PLL_CON0_MUX_CLKCMU_HSI2_PCIE_USER,
2614
+
4, 1),
2615
+
MUX(CLK_MOUT_HSI2_UFS_EMBD_USER, "mout_hsi2_ufs_embd_user",
2616
+
mout_hsi2_ufs_embd_user_p, PLL_CON0_MUX_CLKCMU_HSI2_UFS_EMBD_USER,
2617
+
4, 1),
2618
+
};
2619
+
2620
+
static const struct samsung_gate_clock hsi2_gate_clks[] __initconst = {
2621
+
GATE(CLK_GOUT_HSI2_PCIE_GEN4_1_PCIE_003_PHY_REFCLK_IN,
2622
+
"gout_hsi2_pcie_gen4_1_pcie_003_phy_refclk_in",
2623
+
"mout_hsi2_pcie_user",
2624
+
CLK_CON_GAT_CLK_BLK_HSI2_UID_PCIE_GEN4_1_IPCLKPORT_PCIE_003_PCIE_SUB_CTRL_INST_0_PHY_REFCLK_IN,
2625
+
21, 0, 0),
2626
+
GATE(CLK_GOUT_HSI2_PCIE_GEN4_1_PCIE_004_PHY_REFCLK_IN,
2627
+
"gout_hsi2_pcie_gen4_1_pcie_004_phy_refclk_in",
2628
+
"mout_hsi2_pcie_user",
2629
+
CLK_CON_GAT_CLK_BLK_HSI2_UID_PCIE_GEN4_1_IPCLKPORT_PCIE_004_PCIE_SUB_CTRL_INST_0_PHY_REFCLK_IN,
2630
+
21, 0, 0),
2631
+
GATE(CLK_GOUT_HSI2_SSMT_PCIE_IA_GEN4A_1_ACLK,
2632
+
"gout_hsi2_ssmt_pcie_ia_gen4a_1_aclk", "mout_hsi2_bus_user",
2633
+
CLK_CON_GAT_CLK_BLK_HSI2_UID_SSMT_PCIE_IA_GEN4A_1_IPCLKPORT_ACLK,
2634
+
21, 0, 0),
2635
+
GATE(CLK_GOUT_HSI2_SSMT_PCIE_IA_GEN4A_1_PCLK,
2636
+
"gout_hsi2_ssmt_pcie_ia_gen4a_1_pclk", "mout_hsi2_bus_user",
2637
+
CLK_CON_GAT_CLK_BLK_HSI2_UID_SSMT_PCIE_IA_GEN4A_1_IPCLKPORT_PCLK,
2638
+
21, 0, 0),
2639
+
GATE(CLK_GOUT_HSI2_SSMT_PCIE_IA_GEN4B_1_ACLK,
2640
+
"gout_hsi2_ssmt_pcie_ia_gen4b_1_aclk", "mout_hsi2_bus_user",
2641
+
CLK_CON_GAT_CLK_BLK_HSI2_UID_SSMT_PCIE_IA_GEN4B_1_IPCLKPORT_ACLK,
2642
+
21, 0, 0),
2643
+
GATE(CLK_GOUT_HSI2_SSMT_PCIE_IA_GEN4B_1_PCLK,
2644
+
"gout_hsi2_ssmt_pcie_ia_gen4b_1_pclk", "mout_hsi2_bus_user",
2645
+
CLK_CON_GAT_CLK_BLK_HSI2_UID_SSMT_PCIE_IA_GEN4B_1_IPCLKPORT_PCLK,
2646
+
21, 0, 0),
2647
+
GATE(CLK_GOUT_HSI2_D_TZPC_HSI2_PCLK,
2648
+
"gout_hsi2_d_tzpc_hsi2_pclk", "mout_hsi2_bus_user",
2649
+
CLK_CON_GAT_GOUT_BLK_HSI2_UID_D_TZPC_HSI2_IPCLKPORT_PCLK,
2650
+
21, 0, 0),
2651
+
GATE(CLK_GOUT_HSI2_GPC_HSI2_PCLK,
2652
+
"gout_hsi2_gpc_hsi2_pclk", "mout_hsi2_bus_user",
2653
+
CLK_CON_GAT_GOUT_BLK_HSI2_UID_GPC_HSI2_IPCLKPORT_PCLK, 21, 0, 0),
2654
+
GATE(CLK_GOUT_HSI2_GPIO_HSI2_PCLK,
2655
+
"gout_hsi2_gpio_hsi2_pclk", "mout_hsi2_bus_user",
2656
+
CLK_CON_GAT_GOUT_BLK_HSI2_UID_GPIO_HSI2_IPCLKPORT_PCLK, 21,
2657
+
CLK_IGNORE_UNUSED, 0),
2658
+
/* Disabling this clock makes the system hang. Mark the clock as critical. */
2659
+
GATE(CLK_GOUT_HSI2_HSI2_CMU_HSI2_PCLK,
2660
+
"gout_hsi2_hsi2_cmu_hsi2_pclk", "mout_hsi2_bus_user",
2661
+
CLK_CON_GAT_GOUT_BLK_HSI2_UID_HSI2_CMU_HSI2_IPCLKPORT_PCLK,
2662
+
21, CLK_IS_CRITICAL, 0),
2663
+
/* Disabling this clock makes the system hang. Mark the clock as critical. */
2664
+
GATE(CLK_GOUT_HSI2_LHM_AXI_P_HSI2_I_CLK,
2665
+
"gout_hsi2_lhm_axi_p_hsi2_i_clk", "mout_hsi2_bus_user",
2666
+
CLK_CON_GAT_GOUT_BLK_HSI2_UID_LHM_AXI_P_HSI2_IPCLKPORT_I_CLK,
2667
+
21, CLK_IS_CRITICAL, 0),
2668
+
/* TODO: should have a driver for this */
2669
+
GATE(CLK_GOUT_HSI2_LHS_ACEL_D_HSI2_I_CLK,
2670
+
"gout_hsi2_lhs_acel_d_hsi2_i_clk", "mout_hsi2_bus_user",
2671
+
CLK_CON_GAT_GOUT_BLK_HSI2_UID_LHS_ACEL_D_HSI2_IPCLKPORT_I_CLK,
2672
+
21, CLK_IGNORE_UNUSED, 0),
2673
+
GATE(CLK_GOUT_HSI2_MMC_CARD_I_ACLK,
2674
+
"gout_hsi2_mmc_card_i_aclk", "mout_hsi2_bus_user",
2675
+
CLK_CON_GAT_GOUT_BLK_HSI2_UID_MMC_CARD_IPCLKPORT_I_ACLK,
2676
+
21, 0, 0),
2677
+
GATE(CLK_GOUT_HSI2_MMC_CARD_SDCLKIN,
2678
+
"gout_hsi2_mmc_card_sdclkin", "mout_hsi2_mmc_card_user",
2679
+
CLK_CON_GAT_GOUT_BLK_HSI2_UID_MMC_CARD_IPCLKPORT_SDCLKIN,
2680
+
21, 0, 0),
2681
+
GATE(CLK_GOUT_HSI2_PCIE_GEN4_1_PCIE_003_DBI_ACLK_UG,
2682
+
"gout_hsi2_pcie_gen4_1_pcie_003_dbi_aclk_ug", "mout_hsi2_bus_user",
2683
+
CLK_CON_GAT_GOUT_BLK_HSI2_UID_PCIE_GEN4_1_IPCLKPORT_PCIE_003_G4X2_DWC_PCIE_CTL_INST_0_DBI_ACLK_UG,
2684
+
21, 0, 0),
2685
+
GATE(CLK_GOUT_HSI2_PCIE_GEN4_1_PCIE_003_MSTR_ACLK_UG,
2686
+
"gout_hsi2_pcie_gen4_1_pcie_003_mstr_aclk_ug",
2687
+
"mout_hsi2_bus_user",
2688
+
CLK_CON_GAT_GOUT_BLK_HSI2_UID_PCIE_GEN4_1_IPCLKPORT_PCIE_003_G4X2_DWC_PCIE_CTL_INST_0_MSTR_ACLK_UG,
2689
+
21, 0, 0),
2690
+
GATE(CLK_GOUT_HSI2_PCIE_GEN4_1_PCIE_003_SLV_ACLK_UG,
2691
+
"gout_hsi2_pcie_gen4_1_pcie_003_slv_aclk_ug", "mout_hsi2_bus_user",
2692
+
CLK_CON_GAT_GOUT_BLK_HSI2_UID_PCIE_GEN4_1_IPCLKPORT_PCIE_003_G4X2_DWC_PCIE_CTL_INST_0_SLV_ACLK_UG,
2693
+
21, 0, 0),
2694
+
GATE(CLK_GOUT_HSI2_PCIE_GEN4_1_PCIE_003_I_DRIVER_APB_CLK,
2695
+
"gout_hsi2_pcie_gen4_1_pcie_003_i_driver_apb_clk",
2696
+
"mout_hsi2_bus_user",
2697
+
CLK_CON_GAT_GOUT_BLK_HSI2_UID_PCIE_GEN4_1_IPCLKPORT_PCIE_003_PCIE_SUB_CTRL_INST_0_I_DRIVER_APB_CLK,
2698
+
21, 0, 0),
2699
+
GATE(CLK_GOUT_HSI2_PCIE_GEN4_1_PCIE_004_DBI_ACLK_UG,
2700
+
"gout_hsi2_pcie_gen4_1_pcie_004_dbi_aclk_ug", "mout_hsi2_bus_user",
2701
+
CLK_CON_GAT_GOUT_BLK_HSI2_UID_PCIE_GEN4_1_IPCLKPORT_PCIE_004_G4X1_DWC_PCIE_CTL_INST_0_DBI_ACLK_UG,
2702
+
21, 0, 0),
2703
+
GATE(CLK_GOUT_HSI2_PCIE_GEN4_1_PCIE_004_MSTR_ACLK_UG,
2704
+
"gout_hsi2_pcie_gen4_1_pcie_004_mstr_aclk_ug",
2705
+
"mout_hsi2_bus_user",
2706
+
CLK_CON_GAT_GOUT_BLK_HSI2_UID_PCIE_GEN4_1_IPCLKPORT_PCIE_004_G4X1_DWC_PCIE_CTL_INST_0_MSTR_ACLK_UG,
2707
+
21, 0, 0),
2708
+
GATE(CLK_GOUT_HSI2_PCIE_GEN4_1_PCIE_004_SLV_ACLK_UG,
2709
+
"gout_hsi2_pcie_gen4_1_pcie_004_slv_aclk_ug", "mout_hsi2_bus_user",
2710
+
CLK_CON_GAT_GOUT_BLK_HSI2_UID_PCIE_GEN4_1_IPCLKPORT_PCIE_004_G4X1_DWC_PCIE_CTL_INST_0_SLV_ACLK_UG,
2711
+
21, 0, 0),
2712
+
GATE(CLK_GOUT_HSI2_PCIE_GEN4_1_PCIE_004_I_DRIVER_APB_CLK,
2713
+
"gout_hsi2_pcie_gen4_1_pcie_004_i_driver_apb_clk",
2714
+
"mout_hsi2_bus_user",
2715
+
CLK_CON_GAT_GOUT_BLK_HSI2_UID_PCIE_GEN4_1_IPCLKPORT_PCIE_004_PCIE_SUB_CTRL_INST_0_I_DRIVER_APB_CLK,
2716
+
21, 0, 0),
2717
+
GATE(CLK_GOUT_HSI2_PCIE_GEN4_1_PCS_PMA_PHY_UDBG_I_APB_PCLK,
2718
+
"gout_hsi2_pcie_gen4_1_pcs_pma_phy_udbg_i_apb_pclk",
2719
+
"mout_hsi2_bus_user",
2720
+
CLK_CON_GAT_GOUT_BLK_HSI2_UID_PCIE_GEN4_1_IPCLKPORT_PCS_PMA_INST_0_PHY_UDBG_I_APB_PCLK,
2721
+
21, 0, 0),
2722
+
GATE(CLK_GOUT_HSI2_PCIE_GEN4_1_PCS_PMA_PIPE_PAL_PCIE_I_APB_PCLK,
2723
+
"gout_hsi2_pcie_gen4_1_pcs_pma_pipe_pal_pcie_i_apb_pclk",
2724
+
"mout_hsi2_bus_user",
2725
+
CLK_CON_GAT_GOUT_BLK_HSI2_UID_PCIE_GEN4_1_IPCLKPORT_PCS_PMA_INST_0_PIPE_PAL_PCIE_INST_0_I_APB_PCLK,
2726
+
21, 0, 0),
2727
+
GATE(CLK_GOUT_HSI2_PCIE_GEN4_1_PCS_PMA_PCIEPHY210X2_QCH_I_APB_PCLK,
2728
+
"gout_hsi2_pcie_gen4_1_pcs_pma_pciephy210x2_qch_i_apb_pclk",
2729
+
"mout_hsi2_bus_user",
2730
+
CLK_CON_GAT_GOUT_BLK_HSI2_UID_PCIE_GEN4_1_IPCLKPORT_PCS_PMA_INST_0_SF_PCIEPHY210X2_LN05LPE_QCH_TM_WRAPPER_INST_0_I_APB_PCLK,
2731
+
21, 0, 0),
2732
+
GATE(CLK_GOUT_HSI2_PCIE_IA_GEN4A_1_I_CLK,
2733
+
"gout_hsi2_pcie_ia_gen4a_1_i_clk", "mout_hsi2_bus_user",
2734
+
CLK_CON_GAT_GOUT_BLK_HSI2_UID_PCIE_IA_GEN4A_1_IPCLKPORT_I_CLK,
2735
+
21, 0, 0),
2736
+
GATE(CLK_GOUT_HSI2_PCIE_IA_GEN4B_1_I_CLK,
2737
+
"gout_hsi2_pcie_ia_gen4b_1_i_clk", "mout_hsi2_bus_user",
2738
+
CLK_CON_GAT_GOUT_BLK_HSI2_UID_PCIE_IA_GEN4B_1_IPCLKPORT_I_CLK,
2739
+
21, 0, 0),
2740
+
GATE(CLK_GOUT_HSI2_PPMU_HSI2_ACLK,
2741
+
"gout_hsi2_ppmu_hsi2_aclk", "mout_hsi2_bus_user",
2742
+
CLK_CON_GAT_GOUT_BLK_HSI2_UID_PPMU_HSI2_IPCLKPORT_ACLK,
2743
+
21, 0, 0),
2744
+
GATE(CLK_GOUT_HSI2_PPMU_HSI2_PCLK,
2745
+
"gout_hsi2_ppmu_hsi2_pclk", "mout_hsi2_bus_user",
2746
+
CLK_CON_GAT_GOUT_BLK_HSI2_UID_PPMU_HSI2_IPCLKPORT_PCLK,
2747
+
21, 0, 0),
2748
+
GATE(CLK_GOUT_HSI2_QE_MMC_CARD_HSI2_ACLK,
2749
+
"gout_hsi2_qe_mmc_card_hsi2_aclk", "mout_hsi2_bus_user",
2750
+
CLK_CON_GAT_GOUT_BLK_HSI2_UID_QE_MMC_CARD_HSI2_IPCLKPORT_ACLK,
2751
+
21, 0, 0),
2752
+
GATE(CLK_GOUT_HSI2_QE_MMC_CARD_HSI2_PCLK,
2753
+
"gout_hsi2_qe_mmc_card_hsi2_pclk", "mout_hsi2_bus_user",
2754
+
CLK_CON_GAT_GOUT_BLK_HSI2_UID_QE_MMC_CARD_HSI2_IPCLKPORT_PCLK,
2755
+
21, 0, 0),
2756
+
GATE(CLK_GOUT_HSI2_QE_PCIE_GEN4A_HSI2_ACLK,
2757
+
"gout_hsi2_qe_pcie_gen4a_hsi2_aclk", "mout_hsi2_bus_user",
2758
+
CLK_CON_GAT_GOUT_BLK_HSI2_UID_QE_PCIE_GEN4A_HSI2_IPCLKPORT_ACLK,
2759
+
21, 0, 0),
2760
+
GATE(CLK_GOUT_HSI2_QE_PCIE_GEN4A_HSI2_PCLK,
2761
+
"gout_hsi2_qe_pcie_gen4a_hsi2_pclk", "mout_hsi2_bus_user",
2762
+
CLK_CON_GAT_GOUT_BLK_HSI2_UID_QE_PCIE_GEN4A_HSI2_IPCLKPORT_PCLK,
2763
+
21, 0, 0),
2764
+
GATE(CLK_GOUT_HSI2_QE_PCIE_GEN4B_HSI2_ACLK,
2765
+
"gout_hsi2_qe_pcie_gen4b_hsi2_aclk", "mout_hsi2_bus_user",
2766
+
CLK_CON_GAT_GOUT_BLK_HSI2_UID_QE_PCIE_GEN4B_HSI2_IPCLKPORT_ACLK,
2767
+
21, 0, 0),
2768
+
GATE(CLK_GOUT_HSI2_QE_PCIE_GEN4B_HSI2_PCLK,
2769
+
"gout_hsi2_qe_pcie_gen4b_hsi2_pclk", "mout_hsi2_bus_user",
2770
+
CLK_CON_GAT_GOUT_BLK_HSI2_UID_QE_PCIE_GEN4B_HSI2_IPCLKPORT_PCLK,
2771
+
21, 0, 0),
2772
+
GATE(CLK_GOUT_HSI2_QE_UFS_EMBD_HSI2_ACLK,
2773
+
"gout_hsi2_qe_ufs_embd_hsi2_aclk", "mout_hsi2_bus_user",
2774
+
CLK_CON_GAT_GOUT_BLK_HSI2_UID_QE_UFS_EMBD_HSI2_IPCLKPORT_ACLK,
2775
+
21, 0, 0),
2776
+
GATE(CLK_GOUT_HSI2_QE_UFS_EMBD_HSI2_PCLK,
2777
+
"gout_hsi2_qe_ufs_embd_hsi2_pclk", "mout_hsi2_bus_user",
2778
+
CLK_CON_GAT_GOUT_BLK_HSI2_UID_QE_UFS_EMBD_HSI2_IPCLKPORT_PCLK,
2779
+
21, 0, 0),
2780
+
GATE(CLK_GOUT_HSI2_CLK_HSI2_BUS_CLK,
2781
+
"gout_hsi2_clk_hsi2_bus_clk", "mout_hsi2_bus_user",
2782
+
CLK_CON_GAT_GOUT_BLK_HSI2_UID_RSTNSYNC_CLK_HSI2_BUS_IPCLKPORT_CLK,
2783
+
21, CLK_IS_CRITICAL, 0),
2784
+
GATE(CLK_GOUT_HSI2_CLK_HSI2_OSCCLK_CLK,
2785
+
"gout_hsi2_clk_hsi2_oscclk_clk", "oscclk",
2786
+
CLK_CON_GAT_GOUT_BLK_HSI2_UID_RSTNSYNC_CLK_HSI2_OSCCLK_IPCLKPORT_CLK,
2787
+
21, 0, 0),
2788
+
/* TODO: should have a driver for this */
2789
+
GATE(CLK_GOUT_HSI2_SSMT_HSI2_ACLK,
2790
+
"gout_hsi2_ssmt_hsi2_aclk", "mout_hsi2_bus_user",
2791
+
CLK_CON_GAT_GOUT_BLK_HSI2_UID_SSMT_HSI2_IPCLKPORT_ACLK,
2792
+
21, CLK_IGNORE_UNUSED, 0),
2793
+
/* TODO: should have a driver for this */
2794
+
GATE(CLK_GOUT_HSI2_SSMT_HSI2_PCLK,
2795
+
"gout_hsi2_ssmt_hsi2_pclk", "mout_hsi2_bus_user",
2796
+
CLK_CON_GAT_GOUT_BLK_HSI2_UID_SSMT_HSI2_IPCLKPORT_PCLK,
2797
+
21, CLK_IGNORE_UNUSED, 0),
2798
+
/* TODO: should have a driver for this */
2799
+
GATE(CLK_GOUT_HSI2_SYSMMU_HSI2_CLK_S2,
2800
+
"gout_hsi2_sysmmu_hsi2_clk_s2", "mout_hsi2_bus_user",
2801
+
CLK_CON_GAT_GOUT_BLK_HSI2_UID_SYSMMU_HSI2_IPCLKPORT_CLK_S2,
2802
+
21, CLK_IGNORE_UNUSED, 0),
2803
+
GATE(CLK_GOUT_HSI2_SYSREG_HSI2_PCLK,
2804
+
"gout_hsi2_sysreg_hsi2_pclk", "mout_hsi2_bus_user",
2805
+
CLK_CON_GAT_GOUT_BLK_HSI2_UID_SYSREG_HSI2_IPCLKPORT_PCLK,
2806
+
21, 0, 0),
2807
+
GATE(CLK_GOUT_HSI2_UASC_PCIE_GEN4A_DBI_1_ACLK,
2808
+
"gout_hsi2_uasc_pcie_gen4a_dbi_1_aclk", "mout_hsi2_bus_user",
2809
+
CLK_CON_GAT_GOUT_BLK_HSI2_UID_UASC_PCIE_GEN4A_DBI_1_IPCLKPORT_ACLK,
2810
+
21, 0, 0),
2811
+
GATE(CLK_GOUT_HSI2_UASC_PCIE_GEN4A_DBI_1_PCLK,
2812
+
"gout_hsi2_uasc_pcie_gen4a_dbi_1_pclk", "mout_hsi2_bus_user",
2813
+
CLK_CON_GAT_GOUT_BLK_HSI2_UID_UASC_PCIE_GEN4A_DBI_1_IPCLKPORT_PCLK,
2814
+
21, 0, 0),
2815
+
GATE(CLK_GOUT_HSI2_UASC_PCIE_GEN4A_SLV_1_ACLK,
2816
+
"gout_hsi2_uasc_pcie_gen4a_slv_1_aclk", "mout_hsi2_bus_user",
2817
+
CLK_CON_GAT_GOUT_BLK_HSI2_UID_UASC_PCIE_GEN4A_SLV_1_IPCLKPORT_ACLK,
2818
+
21, 0, 0),
2819
+
GATE(CLK_GOUT_HSI2_UASC_PCIE_GEN4A_SLV_1_PCLK,
2820
+
"gout_hsi2_uasc_pcie_gen4a_slv_1_pclk", "mout_hsi2_bus_user",
2821
+
CLK_CON_GAT_GOUT_BLK_HSI2_UID_UASC_PCIE_GEN4A_SLV_1_IPCLKPORT_PCLK,
2822
+
21, 0, 0),
2823
+
GATE(CLK_GOUT_HSI2_UASC_PCIE_GEN4B_DBI_1_ACLK,
2824
+
"gout_hsi2_uasc_pcie_gen4b_dbi_1_aclk", "mout_hsi2_bus_user",
2825
+
CLK_CON_GAT_GOUT_BLK_HSI2_UID_UASC_PCIE_GEN4B_DBI_1_IPCLKPORT_ACLK,
2826
+
21, 0, 0),
2827
+
GATE(CLK_GOUT_HSI2_UASC_PCIE_GEN4B_DBI_1_PCLK,
2828
+
"gout_hsi2_uasc_pcie_gen4b_dbi_1_pclk", "mout_hsi2_bus_user",
2829
+
CLK_CON_GAT_GOUT_BLK_HSI2_UID_UASC_PCIE_GEN4B_DBI_1_IPCLKPORT_PCLK,
2830
+
21, 0, 0),
2831
+
GATE(CLK_GOUT_HSI2_UASC_PCIE_GEN4B_SLV_1_ACLK,
2832
+
"gout_hsi2_uasc_pcie_gen4b_slv_1_aclk", "mout_hsi2_bus_user",
2833
+
CLK_CON_GAT_GOUT_BLK_HSI2_UID_UASC_PCIE_GEN4B_SLV_1_IPCLKPORT_ACLK,
2834
+
21, 0, 0),
2835
+
GATE(CLK_GOUT_HSI2_UASC_PCIE_GEN4B_SLV_1_PCLK,
2836
+
"gout_hsi2_uasc_pcie_gen4b_slv_1_pclk", "mout_hsi2_bus_user",
2837
+
CLK_CON_GAT_GOUT_BLK_HSI2_UID_UASC_PCIE_GEN4B_SLV_1_IPCLKPORT_PCLK,
2838
+
21, 0, 0),
2839
+
GATE(CLK_GOUT_HSI2_UFS_EMBD_I_ACLK,
2840
+
"gout_hsi2_ufs_embd_i_aclk", "mout_hsi2_bus_user",
2841
+
CLK_CON_GAT_GOUT_BLK_HSI2_UID_UFS_EMBD_IPCLKPORT_I_ACLK,
2842
+
21, 0, 0),
2843
+
GATE(CLK_GOUT_HSI2_UFS_EMBD_I_CLK_UNIPRO,
2844
+
"gout_hsi2_ufs_embd_i_clk_unipro", "mout_hsi2_ufs_embd_user",
2845
+
CLK_CON_GAT_GOUT_BLK_HSI2_UID_UFS_EMBD_IPCLKPORT_I_CLK_UNIPRO,
2846
+
21, 0, 0),
2847
+
GATE(CLK_GOUT_HSI2_UFS_EMBD_I_FMP_CLK,
2848
+
"gout_hsi2_ufs_embd_i_fmp_clk", "mout_hsi2_bus_user",
2849
+
CLK_CON_GAT_GOUT_BLK_HSI2_UID_UFS_EMBD_IPCLKPORT_I_FMP_CLK,
2850
+
21, 0, 0),
2851
+
/* TODO: should have a driver for this */
2852
+
GATE(CLK_GOUT_HSI2_XIU_D_HSI2_ACLK,
2853
+
"gout_hsi2_xiu_d_hsi2_aclk", "mout_hsi2_bus_user",
2854
+
CLK_CON_GAT_GOUT_BLK_HSI2_UID_XIU_D_HSI2_IPCLKPORT_ACLK,
2855
+
21, CLK_IGNORE_UNUSED, 0),
2856
+
/* TODO: should have a driver for this */
2857
+
GATE(CLK_GOUT_HSI2_XIU_P_HSI2_ACLK,
2858
+
"gout_hsi2_xiu_p_hsi2_aclk", "mout_hsi2_bus_user",
2859
+
CLK_CON_GAT_GOUT_BLK_HSI2_UID_XIU_P_HSI2_IPCLKPORT_ACLK,
2860
+
21, CLK_IGNORE_UNUSED, 0),
2861
+
};
2862
+
2863
+
static const struct samsung_cmu_info hsi2_cmu_info __initconst = {
2864
+
.mux_clks = hsi2_mux_clks,
2865
+
.nr_mux_clks = ARRAY_SIZE(hsi2_mux_clks),
2866
+
.gate_clks = hsi2_gate_clks,
2867
+
.nr_gate_clks = ARRAY_SIZE(hsi2_gate_clks),
2868
+
.nr_clk_ids = CLKS_NR_HSI2,
2869
+
.clk_regs = cmu_hsi2_clk_regs,
2870
+
.nr_clk_regs = ARRAY_SIZE(cmu_hsi2_clk_regs),
2871
+
.clk_name = "bus",
1923
2872
};
1924
2873
1925
2874
/* ---- CMU_MISC ------------------------------------------------------------ */
···
3718
2763
MUX(CLK_MOUT_PERIC0_USI0_UART_USER,
3719
2764
"mout_peric0_usi0_uart_user", mout_peric0_usi0_uart_user_p,
3720
2765
PLL_CON0_MUX_CLKCMU_PERIC0_USI0_UART_USER, 4, 1),
3721
-
MUX(CLK_MOUT_PERIC0_USI14_USI_USER,
3722
-
"mout_peric0_usi14_usi_user", mout_peric0_usi_usi_user_p,
3723
-
PLL_CON0_MUX_CLKCMU_PERIC0_USI14_USI_USER, 4, 1),
3724
-
MUX(CLK_MOUT_PERIC0_USI1_USI_USER,
3725
-
"mout_peric0_usi1_usi_user", mout_peric0_usi_usi_user_p,
3726
-
PLL_CON0_MUX_CLKCMU_PERIC0_USI1_USI_USER, 4, 1),
3727
-
MUX(CLK_MOUT_PERIC0_USI2_USI_USER,
3728
-
"mout_peric0_usi2_usi_user", mout_peric0_usi_usi_user_p,
3729
-
PLL_CON0_MUX_CLKCMU_PERIC0_USI2_USI_USER, 4, 1),
3730
-
MUX(CLK_MOUT_PERIC0_USI3_USI_USER,
3731
-
"mout_peric0_usi3_usi_user", mout_peric0_usi_usi_user_p,
3732
-
PLL_CON0_MUX_CLKCMU_PERIC0_USI3_USI_USER, 4, 1),
3733
-
MUX(CLK_MOUT_PERIC0_USI4_USI_USER,
3734
-
"mout_peric0_usi4_usi_user", mout_peric0_usi_usi_user_p,
3735
-
PLL_CON0_MUX_CLKCMU_PERIC0_USI4_USI_USER, 4, 1),
3736
-
MUX(CLK_MOUT_PERIC0_USI5_USI_USER,
3737
-
"mout_peric0_usi5_usi_user", mout_peric0_usi_usi_user_p,
3738
-
PLL_CON0_MUX_CLKCMU_PERIC0_USI5_USI_USER, 4, 1),
3739
-
MUX(CLK_MOUT_PERIC0_USI6_USI_USER,
3740
-
"mout_peric0_usi6_usi_user", mout_peric0_usi_usi_user_p,
3741
-
PLL_CON0_MUX_CLKCMU_PERIC0_USI6_USI_USER, 4, 1),
3742
-
MUX(CLK_MOUT_PERIC0_USI7_USI_USER,
3743
-
"mout_peric0_usi7_usi_user", mout_peric0_usi_usi_user_p,
3744
-
PLL_CON0_MUX_CLKCMU_PERIC0_USI7_USI_USER, 4, 1),
3745
-
MUX(CLK_MOUT_PERIC0_USI8_USI_USER,
3746
-
"mout_peric0_usi8_usi_user", mout_peric0_usi_usi_user_p,
3747
-
PLL_CON0_MUX_CLKCMU_PERIC0_USI8_USI_USER, 4, 1),
2766
+
nMUX(CLK_MOUT_PERIC0_USI14_USI_USER,
2767
+
"mout_peric0_usi14_usi_user", mout_peric0_usi_usi_user_p,
2768
+
PLL_CON0_MUX_CLKCMU_PERIC0_USI14_USI_USER, 4, 1),
2769
+
nMUX(CLK_MOUT_PERIC0_USI1_USI_USER,
2770
+
"mout_peric0_usi1_usi_user", mout_peric0_usi_usi_user_p,
2771
+
PLL_CON0_MUX_CLKCMU_PERIC0_USI1_USI_USER, 4, 1),
2772
+
nMUX(CLK_MOUT_PERIC0_USI2_USI_USER,
2773
+
"mout_peric0_usi2_usi_user", mout_peric0_usi_usi_user_p,
2774
+
PLL_CON0_MUX_CLKCMU_PERIC0_USI2_USI_USER, 4, 1),
2775
+
nMUX(CLK_MOUT_PERIC0_USI3_USI_USER,
2776
+
"mout_peric0_usi3_usi_user", mout_peric0_usi_usi_user_p,
2777
+
PLL_CON0_MUX_CLKCMU_PERIC0_USI3_USI_USER, 4, 1),
2778
+
nMUX(CLK_MOUT_PERIC0_USI4_USI_USER,
2779
+
"mout_peric0_usi4_usi_user", mout_peric0_usi_usi_user_p,
2780
+
PLL_CON0_MUX_CLKCMU_PERIC0_USI4_USI_USER, 4, 1),
2781
+
nMUX(CLK_MOUT_PERIC0_USI5_USI_USER,
2782
+
"mout_peric0_usi5_usi_user", mout_peric0_usi_usi_user_p,
2783
+
PLL_CON0_MUX_CLKCMU_PERIC0_USI5_USI_USER, 4, 1),
2784
+
nMUX(CLK_MOUT_PERIC0_USI6_USI_USER,
2785
+
"mout_peric0_usi6_usi_user", mout_peric0_usi_usi_user_p,
2786
+
PLL_CON0_MUX_CLKCMU_PERIC0_USI6_USI_USER, 4, 1),
2787
+
nMUX(CLK_MOUT_PERIC0_USI7_USI_USER,
2788
+
"mout_peric0_usi7_usi_user", mout_peric0_usi_usi_user_p,
2789
+
PLL_CON0_MUX_CLKCMU_PERIC0_USI7_USI_USER, 4, 1),
2790
+
nMUX(CLK_MOUT_PERIC0_USI8_USI_USER,
2791
+
"mout_peric0_usi8_usi_user", mout_peric0_usi_usi_user_p,
2792
+
PLL_CON0_MUX_CLKCMU_PERIC0_USI8_USI_USER, 4, 1),
3748
2793
};
3749
2794
3750
2795
static const struct samsung_div_clock peric0_div_clks[] __initconst = {
···
3753
2798
DIV(CLK_DOUT_PERIC0_USI0_UART,
3754
2799
"dout_peric0_usi0_uart", "mout_peric0_usi0_uart_user",
3755
2800
CLK_CON_DIV_DIV_CLK_PERIC0_USI0_UART, 0, 4),
3756
-
DIV(CLK_DOUT_PERIC0_USI14_USI,
3757
-
"dout_peric0_usi14_usi", "mout_peric0_usi14_usi_user",
3758
-
CLK_CON_DIV_DIV_CLK_PERIC0_USI14_USI, 0, 4),
3759
-
DIV(CLK_DOUT_PERIC0_USI1_USI,
3760
-
"dout_peric0_usi1_usi", "mout_peric0_usi1_usi_user",
3761
-
CLK_CON_DIV_DIV_CLK_PERIC0_USI1_USI, 0, 4),
3762
-
DIV(CLK_DOUT_PERIC0_USI2_USI,
3763
-
"dout_peric0_usi2_usi", "mout_peric0_usi2_usi_user",
3764
-
CLK_CON_DIV_DIV_CLK_PERIC0_USI2_USI, 0, 4),
3765
-
DIV(CLK_DOUT_PERIC0_USI3_USI,
3766
-
"dout_peric0_usi3_usi", "mout_peric0_usi3_usi_user",
3767
-
CLK_CON_DIV_DIV_CLK_PERIC0_USI3_USI, 0, 4),
3768
-
DIV(CLK_DOUT_PERIC0_USI4_USI,
3769
-
"dout_peric0_usi4_usi", "mout_peric0_usi4_usi_user",
3770
-
CLK_CON_DIV_DIV_CLK_PERIC0_USI4_USI, 0, 4),
3771
-
DIV(CLK_DOUT_PERIC0_USI5_USI,
3772
-
"dout_peric0_usi5_usi", "mout_peric0_usi5_usi_user",
3773
-
CLK_CON_DIV_DIV_CLK_PERIC0_USI5_USI, 0, 4),
3774
-
DIV(CLK_DOUT_PERIC0_USI6_USI,
3775
-
"dout_peric0_usi6_usi", "mout_peric0_usi6_usi_user",
3776
-
CLK_CON_DIV_DIV_CLK_PERIC0_USI6_USI, 0, 4),
3777
-
DIV(CLK_DOUT_PERIC0_USI7_USI,
3778
-
"dout_peric0_usi7_usi", "mout_peric0_usi7_usi_user",
3779
-
CLK_CON_DIV_DIV_CLK_PERIC0_USI7_USI, 0, 4),
3780
-
DIV(CLK_DOUT_PERIC0_USI8_USI,
3781
-
"dout_peric0_usi8_usi", "mout_peric0_usi8_usi_user",
3782
-
CLK_CON_DIV_DIV_CLK_PERIC0_USI8_USI, 0, 4),
2801
+
DIV_F(CLK_DOUT_PERIC0_USI14_USI,
2802
+
"dout_peric0_usi14_usi", "mout_peric0_usi14_usi_user",
2803
+
CLK_CON_DIV_DIV_CLK_PERIC0_USI14_USI, 0, 4,
2804
+
CLK_SET_RATE_PARENT, 0),
2805
+
DIV_F(CLK_DOUT_PERIC0_USI1_USI,
2806
+
"dout_peric0_usi1_usi", "mout_peric0_usi1_usi_user",
2807
+
CLK_CON_DIV_DIV_CLK_PERIC0_USI1_USI, 0, 4,
2808
+
CLK_SET_RATE_PARENT, 0),
2809
+
DIV_F(CLK_DOUT_PERIC0_USI2_USI,
2810
+
"dout_peric0_usi2_usi", "mout_peric0_usi2_usi_user",
2811
+
CLK_CON_DIV_DIV_CLK_PERIC0_USI2_USI, 0, 4,
2812
+
CLK_SET_RATE_PARENT, 0),
2813
+
DIV_F(CLK_DOUT_PERIC0_USI3_USI,
2814
+
"dout_peric0_usi3_usi", "mout_peric0_usi3_usi_user",
2815
+
CLK_CON_DIV_DIV_CLK_PERIC0_USI3_USI, 0, 4,
2816
+
CLK_SET_RATE_PARENT, 0),
2817
+
DIV_F(CLK_DOUT_PERIC0_USI4_USI,
2818
+
"dout_peric0_usi4_usi", "mout_peric0_usi4_usi_user",
2819
+
CLK_CON_DIV_DIV_CLK_PERIC0_USI4_USI, 0, 4,
2820
+
CLK_SET_RATE_PARENT, 0),
2821
+
DIV_F(CLK_DOUT_PERIC0_USI5_USI,
2822
+
"dout_peric0_usi5_usi", "mout_peric0_usi5_usi_user",
2823
+
CLK_CON_DIV_DIV_CLK_PERIC0_USI5_USI, 0, 4,
2824
+
CLK_SET_RATE_PARENT, 0),
2825
+
DIV_F(CLK_DOUT_PERIC0_USI6_USI,
2826
+
"dout_peric0_usi6_usi", "mout_peric0_usi6_usi_user",
2827
+
CLK_CON_DIV_DIV_CLK_PERIC0_USI6_USI, 0, 4,
2828
+
CLK_SET_RATE_PARENT, 0),
2829
+
DIV_F(CLK_DOUT_PERIC0_USI7_USI,
2830
+
"dout_peric0_usi7_usi", "mout_peric0_usi7_usi_user",
2831
+
CLK_CON_DIV_DIV_CLK_PERIC0_USI7_USI, 0, 4,
2832
+
CLK_SET_RATE_PARENT, 0),
2833
+
DIV_F(CLK_DOUT_PERIC0_USI8_USI,
2834
+
"dout_peric0_usi8_usi", "mout_peric0_usi8_usi_user",
2835
+
CLK_CON_DIV_DIV_CLK_PERIC0_USI8_USI, 0, 4,
2836
+
CLK_SET_RATE_PARENT, 0),
3783
2837
};
3784
2838
3785
2839
static const struct samsung_gate_clock peric0_gate_clks[] __initconst = {
···
3821
2857
GATE(CLK_GOUT_PERIC0_PERIC0_TOP0_IPCLK_0,
3822
2858
"gout_peric0_peric0_top0_ipclk_0", "dout_peric0_usi1_usi",
3823
2859
CLK_CON_GAT_GOUT_BLK_PERIC0_UID_PERIC0_TOP0_IPCLKPORT_IPCLK_0,
3824
-
21, 0, 0),
2860
+
21, CLK_SET_RATE_PARENT, 0),
3825
2861
GATE(CLK_GOUT_PERIC0_PERIC0_TOP0_IPCLK_1,
3826
2862
"gout_peric0_peric0_top0_ipclk_1", "dout_peric0_usi2_usi",
3827
2863
CLK_CON_GAT_GOUT_BLK_PERIC0_UID_PERIC0_TOP0_IPCLKPORT_IPCLK_1,
3828
-
21, 0, 0),
2864
+
21, CLK_SET_RATE_PARENT, 0),
3829
2865
GATE(CLK_GOUT_PERIC0_PERIC0_TOP0_IPCLK_10,
3830
2866
"gout_peric0_peric0_top0_ipclk_10", "dout_peric0_i3c",
3831
2867
CLK_CON_GAT_GOUT_BLK_PERIC0_UID_PERIC0_TOP0_IPCLKPORT_IPCLK_10,
···
3853
2889
GATE(CLK_GOUT_PERIC0_PERIC0_TOP0_IPCLK_2,
3854
2890
"gout_peric0_peric0_top0_ipclk_2", "dout_peric0_usi3_usi",
3855
2891
CLK_CON_GAT_GOUT_BLK_PERIC0_UID_PERIC0_TOP0_IPCLKPORT_IPCLK_2,
3856
-
21, 0, 0),
2892
+
21, CLK_SET_RATE_PARENT, 0),
3857
2893
GATE(CLK_GOUT_PERIC0_PERIC0_TOP0_IPCLK_3,
3858
2894
"gout_peric0_peric0_top0_ipclk_3", "dout_peric0_usi4_usi",
3859
2895
CLK_CON_GAT_GOUT_BLK_PERIC0_UID_PERIC0_TOP0_IPCLKPORT_IPCLK_3,
3860
-
21, 0, 0),
2896
+
21, CLK_SET_RATE_PARENT, 0),
3861
2897
GATE(CLK_GOUT_PERIC0_PERIC0_TOP0_IPCLK_4,
3862
2898
"gout_peric0_peric0_top0_ipclk_4", "dout_peric0_usi5_usi",
3863
2899
CLK_CON_GAT_GOUT_BLK_PERIC0_UID_PERIC0_TOP0_IPCLKPORT_IPCLK_4,
3864
-
21, 0, 0),
2900
+
21, CLK_SET_RATE_PARENT, 0),
3865
2901
GATE(CLK_GOUT_PERIC0_PERIC0_TOP0_IPCLK_5,
3866
2902
"gout_peric0_peric0_top0_ipclk_5", "dout_peric0_usi6_usi",
3867
2903
CLK_CON_GAT_GOUT_BLK_PERIC0_UID_PERIC0_TOP0_IPCLKPORT_IPCLK_5,
3868
-
21, 0, 0),
2904
+
21, CLK_SET_RATE_PARENT, 0),
3869
2905
GATE(CLK_GOUT_PERIC0_PERIC0_TOP0_IPCLK_6,
3870
2906
"gout_peric0_peric0_top0_ipclk_6", "dout_peric0_usi7_usi",
3871
2907
CLK_CON_GAT_GOUT_BLK_PERIC0_UID_PERIC0_TOP0_IPCLKPORT_IPCLK_6,
3872
-
21, 0, 0),
2908
+
21, CLK_SET_RATE_PARENT, 0),
3873
2909
GATE(CLK_GOUT_PERIC0_PERIC0_TOP0_IPCLK_7,
3874
2910
"gout_peric0_peric0_top0_ipclk_7", "dout_peric0_usi8_usi",
3875
2911
CLK_CON_GAT_GOUT_BLK_PERIC0_UID_PERIC0_TOP0_IPCLKPORT_IPCLK_7,
3876
-
21, 0, 0),
2912
+
21, CLK_SET_RATE_PARENT, 0),
3877
2913
GATE(CLK_GOUT_PERIC0_PERIC0_TOP0_IPCLK_8,
3878
2914
"gout_peric0_peric0_top0_ipclk_8", "dout_peric0_i3c",
3879
2915
CLK_CON_GAT_GOUT_BLK_PERIC0_UID_PERIC0_TOP0_IPCLKPORT_IPCLK_8,
···
3954
2990
GATE(CLK_GOUT_PERIC0_PERIC0_TOP1_IPCLK_2,
3955
2991
"gout_peric0_peric0_top1_ipclk_2", "dout_peric0_usi14_usi",
3956
2992
CLK_CON_GAT_GOUT_BLK_PERIC0_UID_PERIC0_TOP1_IPCLKPORT_IPCLK_2,
3957
-
21, 0, 0),
2993
+
21, CLK_SET_RATE_PARENT, 0),
3958
2994
/* Disabling this clock makes the system hang. Mark the clock as critical. */
3959
2995
GATE(CLK_GOUT_PERIC0_PERIC0_TOP1_PCLK_0,
3960
2996
"gout_peric0_peric0_top1_pclk_0", "mout_peric0_bus_user",
···
4194
3230
MUX(CLK_MOUT_PERIC1_I3C_USER,
4195
3231
"mout_peric1_i3c_user", mout_peric1_nonbususer_p,
4196
3232
PLL_CON0_MUX_CLKCMU_PERIC1_I3C_USER, 4, 1),
4197
-
MUX(CLK_MOUT_PERIC1_USI0_USI_USER,
4198
-
"mout_peric1_usi0_usi_user", mout_peric1_nonbususer_p,
4199
-
PLL_CON0_MUX_CLKCMU_PERIC1_USI0_USI_USER, 4, 1),
4200
-
MUX(CLK_MOUT_PERIC1_USI10_USI_USER,
4201
-
"mout_peric1_usi10_usi_user", mout_peric1_nonbususer_p,
4202
-
PLL_CON0_MUX_CLKCMU_PERIC1_USI10_USI_USER, 4, 1),
4203
-
MUX(CLK_MOUT_PERIC1_USI11_USI_USER,
4204
-
"mout_peric1_usi11_usi_user", mout_peric1_nonbususer_p,
4205
-
PLL_CON0_MUX_CLKCMU_PERIC1_USI11_USI_USER, 4, 1),
4206
-
MUX(CLK_MOUT_PERIC1_USI12_USI_USER,
4207
-
"mout_peric1_usi12_usi_user", mout_peric1_nonbususer_p,
4208
-
PLL_CON0_MUX_CLKCMU_PERIC1_USI12_USI_USER, 4, 1),
4209
-
MUX(CLK_MOUT_PERIC1_USI13_USI_USER,
4210
-
"mout_peric1_usi13_usi_user", mout_peric1_nonbususer_p,
4211
-
PLL_CON0_MUX_CLKCMU_PERIC1_USI13_USI_USER, 4, 1),
4212
-
MUX(CLK_MOUT_PERIC1_USI9_USI_USER,
4213
-
"mout_peric1_usi9_usi_user", mout_peric1_nonbususer_p,
4214
-
PLL_CON0_MUX_CLKCMU_PERIC1_USI9_USI_USER, 4, 1),
3233
+
nMUX(CLK_MOUT_PERIC1_USI0_USI_USER,
3234
+
"mout_peric1_usi0_usi_user", mout_peric1_nonbususer_p,
3235
+
PLL_CON0_MUX_CLKCMU_PERIC1_USI0_USI_USER, 4, 1),
3236
+
nMUX(CLK_MOUT_PERIC1_USI10_USI_USER,
3237
+
"mout_peric1_usi10_usi_user", mout_peric1_nonbususer_p,
3238
+
PLL_CON0_MUX_CLKCMU_PERIC1_USI10_USI_USER, 4, 1),
3239
+
nMUX(CLK_MOUT_PERIC1_USI11_USI_USER,
3240
+
"mout_peric1_usi11_usi_user", mout_peric1_nonbususer_p,
3241
+
PLL_CON0_MUX_CLKCMU_PERIC1_USI11_USI_USER, 4, 1),
3242
+
nMUX(CLK_MOUT_PERIC1_USI12_USI_USER,
3243
+
"mout_peric1_usi12_usi_user", mout_peric1_nonbususer_p,
3244
+
PLL_CON0_MUX_CLKCMU_PERIC1_USI12_USI_USER, 4, 1),
3245
+
nMUX(CLK_MOUT_PERIC1_USI13_USI_USER,
3246
+
"mout_peric1_usi13_usi_user", mout_peric1_nonbususer_p,
3247
+
PLL_CON0_MUX_CLKCMU_PERIC1_USI13_USI_USER, 4, 1),
3248
+
nMUX(CLK_MOUT_PERIC1_USI9_USI_USER,
3249
+
"mout_peric1_usi9_usi_user", mout_peric1_nonbususer_p,
3250
+
PLL_CON0_MUX_CLKCMU_PERIC1_USI9_USI_USER, 4, 1),
4215
3251
};
4216
3252
4217
3253
static const struct samsung_div_clock peric1_div_clks[] __initconst = {
4218
3254
DIV(CLK_DOUT_PERIC1_I3C, "dout_peric1_i3c", "mout_peric1_i3c_user",
4219
3255
CLK_CON_DIV_DIV_CLK_PERIC1_I3C, 0, 4),
4220
-
DIV(CLK_DOUT_PERIC1_USI0_USI,
4221
-
"dout_peric1_usi0_usi", "mout_peric1_usi0_usi_user",
4222
-
CLK_CON_DIV_DIV_CLK_PERIC1_USI0_USI, 0, 4),
4223
-
DIV(CLK_DOUT_PERIC1_USI10_USI,
4224
-
"dout_peric1_usi10_usi", "mout_peric1_usi10_usi_user",
4225
-
CLK_CON_DIV_DIV_CLK_PERIC1_USI10_USI, 0, 4),
4226
-
DIV(CLK_DOUT_PERIC1_USI11_USI,
4227
-
"dout_peric1_usi11_usi", "mout_peric1_usi11_usi_user",
4228
-
CLK_CON_DIV_DIV_CLK_PERIC1_USI11_USI, 0, 4),
4229
-
DIV(CLK_DOUT_PERIC1_USI12_USI,
4230
-
"dout_peric1_usi12_usi", "mout_peric1_usi12_usi_user",
4231
-
CLK_CON_DIV_DIV_CLK_PERIC1_USI12_USI, 0, 4),
4232
-
DIV(CLK_DOUT_PERIC1_USI13_USI,
4233
-
"dout_peric1_usi13_usi", "mout_peric1_usi13_usi_user",
4234
-
CLK_CON_DIV_DIV_CLK_PERIC1_USI13_USI, 0, 4),
4235
-
DIV(CLK_DOUT_PERIC1_USI9_USI,
4236
-
"dout_peric1_usi9_usi", "mout_peric1_usi9_usi_user",
4237
-
CLK_CON_DIV_DIV_CLK_PERIC1_USI9_USI, 0, 4),
3256
+
DIV_F(CLK_DOUT_PERIC1_USI0_USI,
3257
+
"dout_peric1_usi0_usi", "mout_peric1_usi0_usi_user",
3258
+
CLK_CON_DIV_DIV_CLK_PERIC1_USI0_USI, 0, 4,
3259
+
CLK_SET_RATE_PARENT, 0),
3260
+
DIV_F(CLK_DOUT_PERIC1_USI10_USI,
3261
+
"dout_peric1_usi10_usi", "mout_peric1_usi10_usi_user",
3262
+
CLK_CON_DIV_DIV_CLK_PERIC1_USI10_USI, 0, 4,
3263
+
CLK_SET_RATE_PARENT, 0),
3264
+
DIV_F(CLK_DOUT_PERIC1_USI11_USI,
3265
+
"dout_peric1_usi11_usi", "mout_peric1_usi11_usi_user",
3266
+
CLK_CON_DIV_DIV_CLK_PERIC1_USI11_USI, 0, 4,
3267
+
CLK_SET_RATE_PARENT, 0),
3268
+
DIV_F(CLK_DOUT_PERIC1_USI12_USI,
3269
+
"dout_peric1_usi12_usi", "mout_peric1_usi12_usi_user",
3270
+
CLK_CON_DIV_DIV_CLK_PERIC1_USI12_USI, 0, 4,
3271
+
CLK_SET_RATE_PARENT, 0),
3272
+
DIV_F(CLK_DOUT_PERIC1_USI13_USI,
3273
+
"dout_peric1_usi13_usi", "mout_peric1_usi13_usi_user",
3274
+
CLK_CON_DIV_DIV_CLK_PERIC1_USI13_USI, 0, 4,
3275
+
CLK_SET_RATE_PARENT, 0),
3276
+
DIV_F(CLK_DOUT_PERIC1_USI9_USI,
3277
+
"dout_peric1_usi9_usi", "mout_peric1_usi9_usi_user",
3278
+
CLK_CON_DIV_DIV_CLK_PERIC1_USI9_USI, 0, 4,
3279
+
CLK_SET_RATE_PARENT, 0),
4238
3280
};
4239
3281
4240
3282
static const struct samsung_gate_clock peric1_gate_clks[] __initconst = {
···
4275
3305
GATE(CLK_GOUT_PERIC1_PERIC1_TOP0_IPCLK_1,
4276
3306
"gout_peric1_peric1_top0_ipclk_1", "dout_peric1_usi0_usi",
4277
3307
CLK_CON_GAT_GOUT_BLK_PERIC1_UID_PERIC1_TOP0_IPCLKPORT_IPCLK_1,
4278
-
21, 0, 0),
3308
+
21, CLK_SET_RATE_PARENT, 0),
4279
3309
GATE(CLK_GOUT_PERIC1_PERIC1_TOP0_IPCLK_2,
4280
3310
"gout_peric1_peric1_top0_ipclk_2", "dout_peric1_usi9_usi",
4281
3311
CLK_CON_GAT_GOUT_BLK_PERIC1_UID_PERIC1_TOP0_IPCLKPORT_IPCLK_2,
4282
-
21, 0, 0),
3312
+
21, CLK_SET_RATE_PARENT, 0),
4283
3313
GATE(CLK_GOUT_PERIC1_PERIC1_TOP0_IPCLK_3,
4284
3314
"gout_peric1_peric1_top0_ipclk_3", "dout_peric1_usi10_usi",
4285
3315
CLK_CON_GAT_GOUT_BLK_PERIC1_UID_PERIC1_TOP0_IPCLKPORT_IPCLK_3,
4286
-
21, 0, 0),
3316
+
21, CLK_SET_RATE_PARENT, 0),
4287
3317
GATE(CLK_GOUT_PERIC1_PERIC1_TOP0_IPCLK_4,
4288
3318
"gout_peric1_peric1_top0_ipclk_4", "dout_peric1_usi11_usi",
4289
3319
CLK_CON_GAT_GOUT_BLK_PERIC1_UID_PERIC1_TOP0_IPCLKPORT_IPCLK_4,
4290
-
21, 0, 0),
3320
+
21, CLK_SET_RATE_PARENT, 0),
4291
3321
GATE(CLK_GOUT_PERIC1_PERIC1_TOP0_IPCLK_5,
4292
3322
"gout_peric1_peric1_top0_ipclk_5", "dout_peric1_usi12_usi",
4293
3323
CLK_CON_GAT_GOUT_BLK_PERIC1_UID_PERIC1_TOP0_IPCLKPORT_IPCLK_5,
4294
-
21, 0, 0),
3324
+
21, CLK_SET_RATE_PARENT, 0),
4295
3325
GATE(CLK_GOUT_PERIC1_PERIC1_TOP0_IPCLK_6,
4296
3326
"gout_peric1_peric1_top0_ipclk_6", "dout_peric1_usi13_usi",
4297
3327
CLK_CON_GAT_GOUT_BLK_PERIC1_UID_PERIC1_TOP0_IPCLKPORT_IPCLK_6,
4298
-
21, 0, 0),
3328
+
21, CLK_SET_RATE_PARENT, 0),
4299
3329
GATE(CLK_GOUT_PERIC1_PERIC1_TOP0_IPCLK_8,
4300
3330
"gout_peric1_peric1_top0_ipclk_8", "dout_peric1_i3c",
4301
3331
CLK_CON_GAT_GOUT_BLK_PERIC1_UID_PERIC1_TOP0_IPCLKPORT_IPCLK_8,
···
4396
3426
{
4397
3427
.compatible = "google,gs101-cmu-apm",
4398
3428
.data = &apm_cmu_info,
3429
+
}, {
3430
+
.compatible = "google,gs101-cmu-hsi0",
3431
+
.data = &hsi0_cmu_info,
3432
+
}, {
3433
+
.compatible = "google,gs101-cmu-hsi2",
3434
+
.data = &hsi2_cmu_info,
4399
3435
}, {
4400
3436
.compatible = "google,gs101-cmu-peric0",
4401
3437
.data = &peric0_cmu_info,
+1
-10
drivers/clk/samsung/clk.c
+1
-10
drivers/clk/samsung/clk.c
···
139
139
unsigned int nr_clk)
140
140
{
141
141
struct clk_hw *clk_hw;
142
-
unsigned int idx, ret;
142
+
unsigned int idx;
143
143
144
144
for (idx = 0; idx < nr_clk; idx++, list++) {
145
145
clk_hw = clk_hw_register_fixed_rate(ctx->dev, list->name,
···
151
151
}
152
152
153
153
samsung_clk_add_lookup(ctx, clk_hw, list->id);
154
-
155
-
/*
156
-
* Unconditionally add a clock lookup for the fixed rate clocks.
157
-
* There are not many of these on any of Samsung platforms.
158
-
*/
159
-
ret = clk_hw_register_clkdev(clk_hw, list->name, NULL);
160
-
if (ret)
161
-
pr_err("%s: failed to register clock lookup for %s",
162
-
__func__, list->name);
163
154
}
164
155
}
165
156
+13
-2
drivers/clk/samsung/clk.h
+13
-2
drivers/clk/samsung/clk.h
···
133
133
.name = cname, \
134
134
.parent_names = pnames, \
135
135
.num_parents = ARRAY_SIZE(pnames), \
136
-
.flags = (f) | CLK_SET_RATE_NO_REPARENT, \
136
+
.flags = f, \
137
137
.offset = o, \
138
138
.shift = s, \
139
139
.width = w, \
···
141
141
}
142
142
143
143
#define MUX(_id, cname, pnames, o, s, w) \
144
-
__MUX(_id, cname, pnames, o, s, w, 0, 0)
144
+
__MUX(_id, cname, pnames, o, s, w, CLK_SET_RATE_NO_REPARENT, 0)
145
145
146
146
#define MUX_F(_id, cname, pnames, o, s, w, f, mf) \
147
+
__MUX(_id, cname, pnames, o, s, w, (f) | CLK_SET_RATE_NO_REPARENT, mf)
148
+
149
+
/* Used by MUX clocks where reparenting on clock rate change is allowed. */
150
+
#define nMUX(_id, cname, pnames, o, s, w) \
151
+
__MUX(_id, cname, pnames, o, s, w, 0, 0)
152
+
153
+
#define nMUX_F(_id, cname, pnames, o, s, w, f, mf) \
147
154
__MUX(_id, cname, pnames, o, s, w, f, mf)
148
155
149
156
/**
···
337
330
* @suspend_regs: list of clock registers to set before suspend
338
331
* @nr_suspend_regs: count of clock registers in @suspend_regs
339
332
* @clk_name: name of the parent clock needed for CMU register access
333
+
* @manual_plls: Enable manual control for PLL clocks
340
334
*/
341
335
struct samsung_cmu_info {
342
336
const struct samsung_pll_clock *pll_clks;
···
362
354
const struct samsung_clk_reg_dump *suspend_regs;
363
355
unsigned int nr_suspend_regs;
364
356
const char *clk_name;
357
+
358
+
/* ARM64 Exynos CMUs */
359
+
bool manual_plls;
365
360
};
366
361
367
362
struct samsung_clk_provider *samsung_clk_init(struct device *dev,
+11
drivers/clk/sophgo/Kconfig
+11
drivers/clk/sophgo/Kconfig
···
1
+
# SPDX-License-Identifier: GPL-2.0
2
+
# common clock support for SOPHGO SoC family.
3
+
4
+
config CLK_SOPHGO_CV1800
5
+
tristate "Support for the Sophgo CV1800 series SoCs clock controller"
6
+
depends on ARCH_SOPHGO || COMPILE_TEST
7
+
help
8
+
This driver supports clock controller of Sophgo CV18XX series SoC.
9
+
The driver require a 25MHz Oscillator to function generate clock.
10
+
It includes PLLs, common clock function and some vendor clock for
11
+
IPs of CV18XX series SoC
+7
drivers/clk/sophgo/Makefile
+7
drivers/clk/sophgo/Makefile
+1537
drivers/clk/sophgo/clk-cv1800.c
+1537
drivers/clk/sophgo/clk-cv1800.c
···
1
+
// SPDX-License-Identifier: GPL-2.0
2
+
/*
3
+
* Copyright (C) 2023 Inochi Amaoto <inochiama@outlook.com>
4
+
*/
5
+
6
+
#include <linux/module.h>
7
+
#include <linux/clk-provider.h>
8
+
#include <linux/platform_device.h>
9
+
#include <linux/io.h>
10
+
#include <linux/spinlock.h>
11
+
12
+
#include "clk-cv1800.h"
13
+
14
+
#include "clk-cv18xx-common.h"
15
+
#include "clk-cv18xx-ip.h"
16
+
#include "clk-cv18xx-pll.h"
17
+
18
+
struct cv1800_clk_ctrl;
19
+
20
+
struct cv1800_clk_desc {
21
+
struct clk_hw_onecell_data *clks_data;
22
+
23
+
int (*pre_init)(struct device *dev, void __iomem *base,
24
+
struct cv1800_clk_ctrl *ctrl,
25
+
const struct cv1800_clk_desc *desc);
26
+
};
27
+
28
+
struct cv1800_clk_ctrl {
29
+
const struct cv1800_clk_desc *desc;
30
+
spinlock_t lock;
31
+
};
32
+
33
+
#define CV1800_DIV_FLAG \
34
+
(CLK_DIVIDER_ONE_BASED | CLK_DIVIDER_ROUND_CLOSEST)
35
+
static const struct clk_parent_data osc_parents[] = {
36
+
{ .index = 0 },
37
+
};
38
+
39
+
static const struct cv1800_clk_pll_limit pll_limits[] = {
40
+
{
41
+
.pre_div = _CV1800_PLL_LIMIT(1, 127),
42
+
.div = _CV1800_PLL_LIMIT(6, 127),
43
+
.post_div = _CV1800_PLL_LIMIT(1, 127),
44
+
.ictrl = _CV1800_PLL_LIMIT(0, 7),
45
+
.mode = _CV1800_PLL_LIMIT(0, 3),
46
+
},
47
+
{
48
+
.pre_div = _CV1800_PLL_LIMIT(1, 127),
49
+
.div = _CV1800_PLL_LIMIT(6, 127),
50
+
.post_div = _CV1800_PLL_LIMIT(1, 127),
51
+
.ictrl = _CV1800_PLL_LIMIT(0, 7),
52
+
.mode = _CV1800_PLL_LIMIT(0, 3),
53
+
},
54
+
};
55
+
56
+
static CV1800_INTEGRAL_PLL(clk_fpll, osc_parents,
57
+
REG_FPLL_CSR,
58
+
REG_PLL_G6_CTRL, 8,
59
+
REG_PLL_G6_STATUS, 2,
60
+
pll_limits,
61
+
CLK_IS_CRITICAL);
62
+
63
+
static CV1800_INTEGRAL_PLL(clk_mipimpll, osc_parents,
64
+
REG_MIPIMPLL_CSR,
65
+
REG_PLL_G2_CTRL, 0,
66
+
REG_PLL_G2_STATUS, 0,
67
+
pll_limits,
68
+
CLK_IS_CRITICAL);
69
+
70
+
static const struct clk_parent_data clk_mipimpll_parents[] = {
71
+
{ .hw = &clk_mipimpll.common.hw },
72
+
};
73
+
static const struct clk_parent_data clk_bypass_mipimpll_parents[] = {
74
+
{ .index = 0 },
75
+
{ .hw = &clk_mipimpll.common.hw },
76
+
};
77
+
static const struct clk_parent_data clk_bypass_fpll_parents[] = {
78
+
{ .index = 0 },
79
+
{ .hw = &clk_fpll.common.hw },
80
+
};
81
+
82
+
static struct cv1800_clk_pll_synthesizer clk_mpll_synthesizer = {
83
+
.en = CV1800_CLK_BIT(REG_PLL_G6_SSC_SYN_CTRL, 2),
84
+
.clk_half = CV1800_CLK_BIT(REG_PLL_G6_SSC_SYN_CTRL, 0),
85
+
.ctrl = REG_MPLL_SSC_SYN_CTRL,
86
+
.set = REG_MPLL_SSC_SYN_SET,
87
+
};
88
+
static CV1800_FACTIONAL_PLL(clk_mpll, clk_bypass_mipimpll_parents,
89
+
REG_MPLL_CSR,
90
+
REG_PLL_G6_CTRL, 0,
91
+
REG_PLL_G6_STATUS, 0,
92
+
pll_limits,
93
+
&clk_mpll_synthesizer,
94
+
CLK_IS_CRITICAL);
95
+
96
+
static struct cv1800_clk_pll_synthesizer clk_tpll_synthesizer = {
97
+
.en = CV1800_CLK_BIT(REG_PLL_G6_SSC_SYN_CTRL, 3),
98
+
.clk_half = CV1800_CLK_BIT(REG_PLL_G6_SSC_SYN_CTRL, 0),
99
+
.ctrl = REG_TPLL_SSC_SYN_CTRL,
100
+
.set = REG_TPLL_SSC_SYN_SET,
101
+
};
102
+
static CV1800_FACTIONAL_PLL(clk_tpll, clk_bypass_mipimpll_parents,
103
+
REG_TPLL_CSR,
104
+
REG_PLL_G6_CTRL, 4,
105
+
REG_PLL_G6_STATUS, 1,
106
+
pll_limits,
107
+
&clk_tpll_synthesizer,
108
+
CLK_IS_CRITICAL);
109
+
110
+
static struct cv1800_clk_pll_synthesizer clk_a0pll_synthesizer = {
111
+
.en = CV1800_CLK_BIT(REG_PLL_G2_SSC_SYN_CTRL, 2),
112
+
.clk_half = CV1800_CLK_BIT(REG_PLL_G2_SSC_SYN_CTRL, 0),
113
+
.ctrl = REG_A0PLL_SSC_SYN_CTRL,
114
+
.set = REG_A0PLL_SSC_SYN_SET,
115
+
};
116
+
static CV1800_FACTIONAL_PLL(clk_a0pll, clk_bypass_mipimpll_parents,
117
+
REG_A0PLL_CSR,
118
+
REG_PLL_G2_CTRL, 4,
119
+
REG_PLL_G2_STATUS, 1,
120
+
pll_limits,
121
+
&clk_a0pll_synthesizer,
122
+
CLK_IS_CRITICAL);
123
+
124
+
static struct cv1800_clk_pll_synthesizer clk_disppll_synthesizer = {
125
+
.en = CV1800_CLK_BIT(REG_PLL_G2_SSC_SYN_CTRL, 3),
126
+
.clk_half = CV1800_CLK_BIT(REG_PLL_G2_SSC_SYN_CTRL, 0),
127
+
.ctrl = REG_DISPPLL_SSC_SYN_CTRL,
128
+
.set = REG_DISPPLL_SSC_SYN_SET,
129
+
};
130
+
static CV1800_FACTIONAL_PLL(clk_disppll, clk_bypass_mipimpll_parents,
131
+
REG_DISPPLL_CSR,
132
+
REG_PLL_G2_CTRL, 8,
133
+
REG_PLL_G2_STATUS, 2,
134
+
pll_limits,
135
+
&clk_disppll_synthesizer,
136
+
CLK_IS_CRITICAL);
137
+
138
+
static struct cv1800_clk_pll_synthesizer clk_cam0pll_synthesizer = {
139
+
.en = CV1800_CLK_BIT(REG_PLL_G2_SSC_SYN_CTRL, 4),
140
+
.clk_half = CV1800_CLK_BIT(REG_PLL_G2_SSC_SYN_CTRL, 0),
141
+
.ctrl = REG_CAM0PLL_SSC_SYN_CTRL,
142
+
.set = REG_CAM0PLL_SSC_SYN_SET,
143
+
};
144
+
static CV1800_FACTIONAL_PLL(clk_cam0pll, clk_bypass_mipimpll_parents,
145
+
REG_CAM0PLL_CSR,
146
+
REG_PLL_G2_CTRL, 12,
147
+
REG_PLL_G2_STATUS, 3,
148
+
pll_limits,
149
+
&clk_cam0pll_synthesizer,
150
+
CLK_IGNORE_UNUSED);
151
+
152
+
static struct cv1800_clk_pll_synthesizer clk_cam1pll_synthesizer = {
153
+
.en = CV1800_CLK_BIT(REG_PLL_G2_SSC_SYN_CTRL, 5),
154
+
.clk_half = CV1800_CLK_BIT(REG_PLL_G2_SSC_SYN_CTRL, 0),
155
+
.ctrl = REG_CAM1PLL_SSC_SYN_CTRL,
156
+
.set = REG_CAM1PLL_SSC_SYN_SET,
157
+
};
158
+
static CV1800_FACTIONAL_PLL(clk_cam1pll, clk_bypass_mipimpll_parents,
159
+
REG_CAM1PLL_CSR,
160
+
REG_PLL_G2_CTRL, 16,
161
+
REG_PLL_G2_STATUS, 4,
162
+
pll_limits,
163
+
&clk_cam1pll_synthesizer,
164
+
CLK_IS_CRITICAL);
165
+
166
+
static const struct clk_parent_data clk_cam0pll_parents[] = {
167
+
{ .hw = &clk_cam0pll.common.hw },
168
+
};
169
+
170
+
/* G2D */
171
+
static CV1800_FIXED_DIV(clk_cam0pll_d2, clk_cam0pll_parents,
172
+
REG_CAM0PLL_CLK_CSR, 1,
173
+
2,
174
+
CLK_SET_RATE_PARENT | CLK_IGNORE_UNUSED);
175
+
static CV1800_FIXED_DIV(clk_cam0pll_d3, clk_cam0pll_parents,
176
+
REG_CAM0PLL_CLK_CSR, 2,
177
+
3,
178
+
CLK_SET_RATE_PARENT | CLK_IGNORE_UNUSED);
179
+
static CV1800_FIXED_DIV(clk_mipimpll_d3, clk_mipimpll_parents,
180
+
REG_MIPIMPLL_CLK_CSR, 2,
181
+
3,
182
+
CLK_SET_RATE_PARENT | CLK_IGNORE_UNUSED);
183
+
184
+
/* TPU */
185
+
static const struct clk_parent_data clk_tpu_parents[] = {
186
+
{ .index = 0 },
187
+
{ .hw = &clk_tpll.common.hw },
188
+
{ .hw = &clk_a0pll.common.hw },
189
+
{ .hw = &clk_mipimpll.common.hw },
190
+
{ .hw = &clk_fpll.common.hw },
191
+
};
192
+
193
+
static CV1800_BYPASS_MUX(clk_tpu, clk_tpu_parents,
194
+
REG_CLK_EN_0, 4,
195
+
REG_DIV_CLK_TPU, 16, 4, 3, CV1800_DIV_FLAG,
196
+
REG_DIV_CLK_TPU, 8, 2,
197
+
REG_CLK_BYP_0, 3,
198
+
0);
199
+
static CV1800_GATE(clk_tpu_fab, clk_mipimpll_parents,
200
+
REG_CLK_EN_0, 5,
201
+
0);
202
+
203
+
/* FABRIC_AXI6 */
204
+
static CV1800_BYPASS_DIV(clk_axi6, clk_bypass_fpll_parents,
205
+
REG_CLK_EN_2, 2,
206
+
REG_DIV_CLK_AXI6, 16, 4, 15, CV1800_DIV_FLAG,
207
+
REG_CLK_BYP_0, 20,
208
+
CLK_IS_CRITICAL);
209
+
210
+
static const struct clk_parent_data clk_axi6_bus_parents[] = {
211
+
{ .hw = &clk_axi6.div.common.hw },
212
+
};
213
+
static const struct clk_parent_data clk_bypass_axi6_bus_parents[] = {
214
+
{ .index = 0 },
215
+
{ .hw = &clk_axi6.div.common.hw },
216
+
};
217
+
218
+
/* FABRIC_AXI4 */
219
+
static const struct clk_parent_data clk_axi4_parents[] = {
220
+
{ .index = 0 },
221
+
{ .hw = &clk_fpll.common.hw },
222
+
{ .hw = &clk_disppll.common.hw },
223
+
};
224
+
225
+
static CV1800_BYPASS_MUX(clk_axi4, clk_axi4_parents,
226
+
REG_CLK_EN_2, 1,
227
+
REG_DIV_CLK_AXI4, 16, 4, 5, CV1800_DIV_FLAG,
228
+
REG_DIV_CLK_AXI4, 8, 2,
229
+
REG_CLK_BYP_0, 19,
230
+
CLK_IS_CRITICAL);
231
+
232
+
static const struct clk_parent_data clk_axi4_bus_parents[] = {
233
+
{ .hw = &clk_axi4.mux.common.hw },
234
+
};
235
+
236
+
/* XTAL_MISC */
237
+
static CV1800_GATE(clk_xtal_misc, osc_parents,
238
+
REG_CLK_EN_0, 14,
239
+
CLK_IS_CRITICAL);
240
+
241
+
static const struct clk_parent_data clk_timer_parents[] = {
242
+
{ .hw = &clk_xtal_misc.common.hw },
243
+
};
244
+
245
+
/* TOP */
246
+
static const struct clk_parent_data clk_cam0_200_parents[] = {
247
+
{ .index = 0 },
248
+
{ .index = 0 },
249
+
{ .hw = &clk_disppll.common.hw },
250
+
};
251
+
252
+
static CV1800_BYPASS_MUX(clk_cam0_200, clk_cam0_200_parents,
253
+
REG_CLK_EN_1, 13,
254
+
REG_DIV_CLK_CAM0_200, 16, 4, 1, CV1800_DIV_FLAG,
255
+
REG_DIV_CLK_CAM0_200, 8, 2,
256
+
REG_CLK_BYP_0, 16,
257
+
CLK_IS_CRITICAL);
258
+
static CV1800_DIV(clk_1m, osc_parents,
259
+
REG_CLK_EN_3, 5,
260
+
REG_DIV_CLK_1M, 16, 6, 25, CV1800_DIV_FLAG,
261
+
CLK_IS_CRITICAL);
262
+
static CV1800_GATE(clk_pm, clk_axi6_bus_parents,
263
+
REG_CLK_EN_3, 8,
264
+
CLK_IS_CRITICAL);
265
+
static CV1800_GATE(clk_timer0, clk_timer_parents,
266
+
REG_CLK_EN_3, 9,
267
+
CLK_IS_CRITICAL);
268
+
static CV1800_GATE(clk_timer1, clk_timer_parents,
269
+
REG_CLK_EN_3, 10,
270
+
CLK_IS_CRITICAL);
271
+
static CV1800_GATE(clk_timer2, clk_timer_parents,
272
+
REG_CLK_EN_3, 11,
273
+
CLK_IS_CRITICAL);
274
+
static CV1800_GATE(clk_timer3, clk_timer_parents,
275
+
REG_CLK_EN_3, 12,
276
+
CLK_IS_CRITICAL);
277
+
static CV1800_GATE(clk_timer4, clk_timer_parents,
278
+
REG_CLK_EN_3, 13,
279
+
CLK_IS_CRITICAL);
280
+
static CV1800_GATE(clk_timer5, clk_timer_parents,
281
+
REG_CLK_EN_3, 14,
282
+
CLK_IS_CRITICAL);
283
+
static CV1800_GATE(clk_timer6, clk_timer_parents,
284
+
REG_CLK_EN_3, 15,
285
+
CLK_IS_CRITICAL);
286
+
static CV1800_GATE(clk_timer7, clk_timer_parents,
287
+
REG_CLK_EN_3, 16,
288
+
CLK_IS_CRITICAL);
289
+
290
+
static const struct clk_parent_data clk_parents_1m[] = {
291
+
{ .hw = &clk_1m.common.hw },
292
+
};
293
+
static const struct clk_parent_data clk_uart_parents[] = {
294
+
{ .hw = &clk_cam0_200.mux.common.hw },
295
+
};
296
+
297
+
/* AHB ROM */
298
+
static CV1800_GATE(clk_ahb_rom, clk_axi4_bus_parents,
299
+
REG_CLK_EN_0, 6,
300
+
0);
301
+
302
+
/* RTC */
303
+
static CV1800_GATE(clk_rtc_25m, osc_parents,
304
+
REG_CLK_EN_0, 8,
305
+
CLK_IS_CRITICAL);
306
+
static CV1800_BYPASS_DIV(clk_src_rtc_sys_0, clk_bypass_fpll_parents,
307
+
REG_CLK_EN_4, 6,
308
+
REG_DIV_CLK_RTCSYS_SRC_0, 16, 4, 5, CV1800_DIV_FLAG,
309
+
REG_CLK_BYP_1, 5,
310
+
CLK_IS_CRITICAL);
311
+
312
+
/* TEMPSEN */
313
+
static CV1800_GATE(clk_tempsen, osc_parents,
314
+
REG_CLK_EN_0, 9,
315
+
0);
316
+
317
+
/* SARADC */
318
+
static CV1800_GATE(clk_saradc, osc_parents,
319
+
REG_CLK_EN_0, 10,
320
+
0);
321
+
322
+
/* EFUSE */
323
+
static CV1800_GATE(clk_efuse, osc_parents,
324
+
REG_CLK_EN_0, 11,
325
+
0);
326
+
static CV1800_GATE(clk_apb_efuse, osc_parents,
327
+
REG_CLK_EN_0, 12,
328
+
0);
329
+
330
+
/* WDT */
331
+
static CV1800_GATE(clk_apb_wdt, osc_parents,
332
+
REG_CLK_EN_1, 7,
333
+
CLK_IS_CRITICAL);
334
+
335
+
/* WGN */
336
+
static CV1800_GATE(clk_wgn, osc_parents,
337
+
REG_CLK_EN_3, 22,
338
+
0);
339
+
static CV1800_GATE(clk_wgn0, osc_parents,
340
+
REG_CLK_EN_3, 23,
341
+
0);
342
+
static CV1800_GATE(clk_wgn1, osc_parents,
343
+
REG_CLK_EN_3, 24,
344
+
0);
345
+
static CV1800_GATE(clk_wgn2, osc_parents,
346
+
REG_CLK_EN_3, 25,
347
+
0);
348
+
349
+
/* KEYSCAN */
350
+
static CV1800_GATE(clk_keyscan, osc_parents,
351
+
REG_CLK_EN_3, 26,
352
+
0);
353
+
354
+
/* EMMC */
355
+
static CV1800_GATE(clk_axi4_emmc, clk_axi4_bus_parents,
356
+
REG_CLK_EN_0, 15,
357
+
0);
358
+
static CV1800_BYPASS_MUX(clk_emmc, clk_axi4_parents,
359
+
REG_CLK_EN_0, 16,
360
+
REG_DIV_CLK_EMMC, 16, 5, 15, CV1800_DIV_FLAG,
361
+
REG_DIV_CLK_EMMC, 8, 2,
362
+
REG_CLK_BYP_0, 5,
363
+
0);
364
+
static CV1800_DIV(clk_emmc_100k, clk_parents_1m,
365
+
REG_CLK_EN_0, 17,
366
+
REG_DIV_CLK_EMMC_100K, 16, 8, 10, CV1800_DIV_FLAG,
367
+
0);
368
+
369
+
/* SD */
370
+
static CV1800_GATE(clk_axi4_sd0, clk_axi4_bus_parents,
371
+
REG_CLK_EN_0, 18,
372
+
0);
373
+
static CV1800_BYPASS_MUX(clk_sd0, clk_axi4_parents,
374
+
REG_CLK_EN_0, 19,
375
+
REG_DIV_CLK_SD0, 16, 5, 15, CV1800_DIV_FLAG,
376
+
REG_DIV_CLK_SD0, 8, 2,
377
+
REG_CLK_BYP_0, 6,
378
+
0);
379
+
static CV1800_DIV(clk_sd0_100k, clk_parents_1m,
380
+
REG_CLK_EN_0, 20,
381
+
REG_DIV_CLK_SD0_100K, 16, 8, 10, CV1800_DIV_FLAG,
382
+
0);
383
+
static CV1800_GATE(clk_axi4_sd1, clk_axi4_bus_parents,
384
+
REG_CLK_EN_0, 21,
385
+
0);
386
+
static CV1800_BYPASS_MUX(clk_sd1, clk_axi4_parents,
387
+
REG_CLK_EN_0, 22,
388
+
REG_DIV_CLK_SD1, 16, 5, 15, CV1800_DIV_FLAG,
389
+
REG_DIV_CLK_SD1, 8, 2,
390
+
REG_CLK_BYP_0, 7,
391
+
0);
392
+
static CV1800_DIV(clk_sd1_100k, clk_parents_1m,
393
+
REG_CLK_EN_0, 23,
394
+
REG_DIV_CLK_SD1_100K, 16, 8, 10, CV1800_DIV_FLAG,
395
+
0);
396
+
397
+
/* SPI NAND */
398
+
static CV1800_BYPASS_MUX(clk_spi_nand, clk_axi4_parents,
399
+
REG_CLK_EN_0, 24,
400
+
REG_DIV_CLK_SPI_NAND, 16, 5, 8, CV1800_DIV_FLAG,
401
+
REG_DIV_CLK_SPI_NAND, 8, 2,
402
+
REG_CLK_BYP_0, 8,
403
+
0);
404
+
405
+
/* GPIO */
406
+
static CV1800_DIV(clk_gpio_db, clk_parents_1m,
407
+
REG_CLK_EN_0, 31,
408
+
REG_DIV_CLK_GPIO_DB, 16, 16, 10, CV1800_DIV_FLAG,
409
+
CLK_IS_CRITICAL);
410
+
static CV1800_GATE(clk_apb_gpio, clk_axi6_bus_parents,
411
+
REG_CLK_EN_0, 29,
412
+
CLK_IS_CRITICAL);
413
+
static CV1800_GATE(clk_apb_gpio_intr, clk_axi6_bus_parents,
414
+
REG_CLK_EN_0, 30,
415
+
CLK_IS_CRITICAL);
416
+
417
+
/* ETH */
418
+
static CV1800_BYPASS_DIV(clk_eth0_500m, clk_bypass_fpll_parents,
419
+
REG_CLK_EN_0, 25,
420
+
REG_DIV_CLK_GPIO_DB, 16, 4, 3, CV1800_DIV_FLAG,
421
+
REG_CLK_BYP_0, 9,
422
+
0);
423
+
static CV1800_GATE(clk_axi4_eth0, clk_axi4_bus_parents,
424
+
REG_CLK_EN_0, 26,
425
+
0);
426
+
static CV1800_BYPASS_DIV(clk_eth1_500m, clk_bypass_fpll_parents,
427
+
REG_CLK_EN_0, 27,
428
+
REG_DIV_CLK_GPIO_DB, 16, 4, 3, CV1800_DIV_FLAG,
429
+
REG_CLK_BYP_0, 10,
430
+
0);
431
+
static CV1800_GATE(clk_axi4_eth1, clk_axi4_bus_parents,
432
+
REG_CLK_EN_0, 28,
433
+
0);
434
+
435
+
/* SF */
436
+
static CV1800_GATE(clk_ahb_sf, clk_axi4_bus_parents,
437
+
REG_CLK_EN_1, 0,
438
+
0);
439
+
static CV1800_GATE(clk_ahb_sf1, clk_axi4_bus_parents,
440
+
REG_CLK_EN_3, 27,
441
+
0);
442
+
443
+
/* AUDSRC */
444
+
static CV1800_ACLK(clk_a24m, clk_mipimpll_parents,
445
+
REG_APLL_FRAC_DIV_CTRL, 0,
446
+
REG_APLL_FRAC_DIV_CTRL, 3,
447
+
REG_APLL_FRAC_DIV_CTRL, 1,
448
+
REG_APLL_FRAC_DIV_CTRL, 2,
449
+
REG_APLL_FRAC_DIV_M, 0, 22, CV1800_DIV_FLAG,
450
+
REG_APLL_FRAC_DIV_N, 0, 22, CV1800_DIV_FLAG,
451
+
24576000,
452
+
0);
453
+
454
+
static const struct clk_parent_data clk_aud_parents[] = {
455
+
{ .index = 0 },
456
+
{ .hw = &clk_a0pll.common.hw },
457
+
{ .hw = &clk_a24m.common.hw },
458
+
};
459
+
460
+
static CV1800_BYPASS_MUX(clk_audsrc, clk_aud_parents,
461
+
REG_CLK_EN_4, 1,
462
+
REG_DIV_CLK_AUDSRC, 16, 8, 18, CV1800_DIV_FLAG,
463
+
REG_DIV_CLK_AUDSRC, 8, 2,
464
+
REG_CLK_BYP_1, 2,
465
+
0);
466
+
static CV1800_GATE(clk_apb_audsrc, clk_axi4_bus_parents,
467
+
REG_CLK_EN_4, 2,
468
+
0);
469
+
470
+
/* SDMA */
471
+
static CV1800_GATE(clk_sdma_axi, clk_axi4_bus_parents,
472
+
REG_CLK_EN_1, 1,
473
+
0);
474
+
static CV1800_BYPASS_MUX(clk_sdma_aud0, clk_aud_parents,
475
+
REG_CLK_EN_1, 2,
476
+
REG_DIV_CLK_SDMA_AUD0, 16, 8, 18, CV1800_DIV_FLAG,
477
+
REG_DIV_CLK_SDMA_AUD0, 8, 2,
478
+
REG_CLK_BYP_0, 11,
479
+
0);
480
+
static CV1800_BYPASS_MUX(clk_sdma_aud1, clk_aud_parents,
481
+
REG_CLK_EN_1, 3,
482
+
REG_DIV_CLK_SDMA_AUD1, 16, 8, 18, CV1800_DIV_FLAG,
483
+
REG_DIV_CLK_SDMA_AUD1, 8, 2,
484
+
REG_CLK_BYP_0, 12,
485
+
0);
486
+
static CV1800_BYPASS_MUX(clk_sdma_aud2, clk_aud_parents,
487
+
REG_CLK_EN_1, 3,
488
+
REG_DIV_CLK_SDMA_AUD2, 16, 8, 18, CV1800_DIV_FLAG,
489
+
REG_DIV_CLK_SDMA_AUD2, 8, 2,
490
+
REG_CLK_BYP_0, 13,
491
+
0);
492
+
static CV1800_BYPASS_MUX(clk_sdma_aud3, clk_aud_parents,
493
+
REG_CLK_EN_1, 3,
494
+
REG_DIV_CLK_SDMA_AUD3, 16, 8, 18, CV1800_DIV_FLAG,
495
+
REG_DIV_CLK_SDMA_AUD3, 8, 2,
496
+
REG_CLK_BYP_0, 14,
497
+
0);
498
+
499
+
/* SPI */
500
+
static CV1800_GATE(clk_apb_spi0, clk_axi4_bus_parents,
501
+
REG_CLK_EN_1, 9,
502
+
0);
503
+
static CV1800_GATE(clk_apb_spi1, clk_axi4_bus_parents,
504
+
REG_CLK_EN_1, 10,
505
+
0);
506
+
static CV1800_GATE(clk_apb_spi2, clk_axi4_bus_parents,
507
+
REG_CLK_EN_1, 11,
508
+
0);
509
+
static CV1800_GATE(clk_apb_spi3, clk_axi4_bus_parents,
510
+
REG_CLK_EN_1, 12,
511
+
0);
512
+
static CV1800_BYPASS_DIV(clk_spi, clk_bypass_fpll_parents,
513
+
REG_CLK_EN_3, 6,
514
+
REG_DIV_CLK_SPI, 16, 6, 8, CV1800_DIV_FLAG,
515
+
REG_CLK_BYP_0, 30,
516
+
0);
517
+
518
+
/* UART */
519
+
static CV1800_GATE(clk_uart0, clk_uart_parents,
520
+
REG_CLK_EN_1, 14,
521
+
CLK_IS_CRITICAL);
522
+
static CV1800_GATE(clk_apb_uart0, clk_axi4_bus_parents,
523
+
REG_CLK_EN_1, 15,
524
+
CLK_IS_CRITICAL);
525
+
static CV1800_GATE(clk_uart1, clk_uart_parents,
526
+
REG_CLK_EN_1, 16,
527
+
0);
528
+
static CV1800_GATE(clk_apb_uart1, clk_axi4_bus_parents,
529
+
REG_CLK_EN_1, 17,
530
+
0);
531
+
static CV1800_GATE(clk_uart2, clk_uart_parents,
532
+
REG_CLK_EN_1, 18,
533
+
0);
534
+
static CV1800_GATE(clk_apb_uart2, clk_axi4_bus_parents,
535
+
REG_CLK_EN_1, 19,
536
+
0);
537
+
static CV1800_GATE(clk_uart3, clk_uart_parents,
538
+
REG_CLK_EN_1, 20,
539
+
0);
540
+
static CV1800_GATE(clk_apb_uart3, clk_axi4_bus_parents,
541
+
REG_CLK_EN_1, 21,
542
+
0);
543
+
static CV1800_GATE(clk_uart4, clk_uart_parents,
544
+
REG_CLK_EN_1, 22,
545
+
0);
546
+
static CV1800_GATE(clk_apb_uart4, clk_axi4_bus_parents,
547
+
REG_CLK_EN_1, 23,
548
+
0);
549
+
550
+
/* I2S */
551
+
static CV1800_GATE(clk_apb_i2s0, clk_axi4_bus_parents,
552
+
REG_CLK_EN_1, 24,
553
+
0);
554
+
static CV1800_GATE(clk_apb_i2s1, clk_axi4_bus_parents,
555
+
REG_CLK_EN_1, 25,
556
+
0);
557
+
static CV1800_GATE(clk_apb_i2s2, clk_axi4_bus_parents,
558
+
REG_CLK_EN_1, 26,
559
+
0);
560
+
static CV1800_GATE(clk_apb_i2s3, clk_axi4_bus_parents,
561
+
REG_CLK_EN_1, 27,
562
+
0);
563
+
564
+
/* DEBUG */
565
+
static CV1800_GATE(clk_debug, osc_parents,
566
+
REG_CLK_EN_0, 13,
567
+
CLK_IS_CRITICAL);
568
+
static CV1800_BYPASS_DIV(clk_ap_debug, clk_bypass_fpll_parents,
569
+
REG_CLK_EN_4, 5,
570
+
REG_DIV_CLK_AP_DEBUG, 16, 4, 5, CV1800_DIV_FLAG,
571
+
REG_CLK_BYP_1, 4,
572
+
CLK_IS_CRITICAL);
573
+
574
+
/* DDR */
575
+
static CV1800_GATE(clk_ddr_axi_reg, clk_axi6_bus_parents,
576
+
REG_CLK_EN_0, 7,
577
+
CLK_IS_CRITICAL);
578
+
579
+
/* I2C */
580
+
static CV1800_GATE(clk_apb_i2c, clk_axi4_bus_parents,
581
+
REG_CLK_EN_1, 6,
582
+
0);
583
+
static CV1800_BYPASS_DIV(clk_i2c, clk_bypass_axi6_bus_parents,
584
+
REG_CLK_EN_3, 7,
585
+
REG_DIV_CLK_I2C, 16, 4, 1, CV1800_DIV_FLAG,
586
+
REG_CLK_BYP_0, 31,
587
+
0);
588
+
static CV1800_GATE(clk_apb_i2c0, clk_axi4_bus_parents,
589
+
REG_CLK_EN_3, 17,
590
+
0);
591
+
static CV1800_GATE(clk_apb_i2c1, clk_axi4_bus_parents,
592
+
REG_CLK_EN_3, 18,
593
+
0);
594
+
static CV1800_GATE(clk_apb_i2c2, clk_axi4_bus_parents,
595
+
REG_CLK_EN_3, 19,
596
+
0);
597
+
static CV1800_GATE(clk_apb_i2c3, clk_axi4_bus_parents,
598
+
REG_CLK_EN_3, 20,
599
+
0);
600
+
static CV1800_GATE(clk_apb_i2c4, clk_axi4_bus_parents,
601
+
REG_CLK_EN_3, 21,
602
+
0);
603
+
604
+
/* USB */
605
+
static CV1800_GATE(clk_axi4_usb, clk_axi4_bus_parents,
606
+
REG_CLK_EN_1, 28,
607
+
0);
608
+
static CV1800_GATE(clk_apb_usb, clk_axi4_bus_parents,
609
+
REG_CLK_EN_1, 29,
610
+
0);
611
+
static CV1800_BYPASS_FIXED_DIV(clk_usb_125m, clk_bypass_fpll_parents,
612
+
REG_CLK_EN_1, 30,
613
+
12,
614
+
REG_CLK_BYP_0, 17,
615
+
CLK_SET_RATE_PARENT);
616
+
static CV1800_FIXED_DIV(clk_usb_33k, clk_parents_1m,
617
+
REG_CLK_EN_1, 31,
618
+
3,
619
+
0);
620
+
static CV1800_BYPASS_FIXED_DIV(clk_usb_12m, clk_bypass_fpll_parents,
621
+
REG_CLK_EN_2, 0,
622
+
125,
623
+
REG_CLK_BYP_0, 18,
624
+
CLK_SET_RATE_PARENT);
625
+
626
+
/* VIP SYS */
627
+
static const struct clk_parent_data clk_vip_sys_parents[] = {
628
+
{ .index = 0 },
629
+
{ .hw = &clk_mipimpll.common.hw },
630
+
{ .hw = &clk_cam0pll.common.hw },
631
+
{ .hw = &clk_disppll.common.hw },
632
+
{ .hw = &clk_fpll.common.hw },
633
+
};
634
+
static const struct clk_parent_data clk_disp_vip_parents[] = {
635
+
{ .index = 0 },
636
+
{ .hw = &clk_disppll.common.hw },
637
+
};
638
+
639
+
static CV1800_BYPASS_DIV(clk_dsi_esc, clk_bypass_axi6_bus_parents,
640
+
REG_CLK_EN_2, 3,
641
+
REG_DIV_CLK_DSI_ESC, 16, 4, 5, CV1800_DIV_FLAG,
642
+
REG_CLK_BYP_0, 21,
643
+
0);
644
+
static CV1800_BYPASS_MUX(clk_axi_vip, clk_vip_sys_parents,
645
+
REG_CLK_EN_2, 4,
646
+
REG_DIV_CLK_AXI_VIP, 16, 4, 3, CV1800_DIV_FLAG,
647
+
REG_DIV_CLK_AXI_VIP, 8, 2,
648
+
REG_CLK_BYP_0, 22,
649
+
0);
650
+
651
+
static const struct clk_parent_data clk_axi_vip_bus_parents[] = {
652
+
{ .hw = &clk_axi_vip.mux.common.hw },
653
+
};
654
+
655
+
static CV1800_BYPASS_MUX(clk_src_vip_sys_0, clk_vip_sys_parents,
656
+
REG_CLK_EN_2, 5,
657
+
REG_DIV_CLK_SRC_VIP_SYS_0, 16, 4, 6, CV1800_DIV_FLAG,
658
+
REG_DIV_CLK_SRC_VIP_SYS_0, 8, 2,
659
+
REG_CLK_BYP_0, 23,
660
+
0);
661
+
static CV1800_BYPASS_MUX(clk_src_vip_sys_1, clk_vip_sys_parents,
662
+
REG_CLK_EN_2, 6,
663
+
REG_DIV_CLK_SRC_VIP_SYS_1, 16, 4, 6, CV1800_DIV_FLAG,
664
+
REG_DIV_CLK_SRC_VIP_SYS_1, 8, 2,
665
+
REG_CLK_BYP_0, 24,
666
+
0);
667
+
static CV1800_BYPASS_DIV(clk_disp_src_vip, clk_disp_vip_parents,
668
+
REG_CLK_EN_2, 7,
669
+
REG_DIV_CLK_DISP_SRC_VIP, 16, 4, 8, CV1800_DIV_FLAG,
670
+
REG_CLK_BYP_0, 25,
671
+
0);
672
+
static CV1800_BYPASS_MUX(clk_src_vip_sys_2, clk_vip_sys_parents,
673
+
REG_CLK_EN_3, 29,
674
+
REG_DIV_CLK_SRC_VIP_SYS_2, 16, 4, 2, CV1800_DIV_FLAG,
675
+
REG_DIV_CLK_SRC_VIP_SYS_2, 8, 2,
676
+
REG_CLK_BYP_1, 1,
677
+
0);
678
+
static CV1800_GATE(clk_csi_mac0_vip, clk_axi_vip_bus_parents,
679
+
REG_CLK_EN_2, 18,
680
+
0);
681
+
static CV1800_GATE(clk_csi_mac1_vip, clk_axi_vip_bus_parents,
682
+
REG_CLK_EN_2, 19,
683
+
0);
684
+
static CV1800_GATE(clk_isp_top_vip, clk_axi_vip_bus_parents,
685
+
REG_CLK_EN_2, 20,
686
+
0);
687
+
static CV1800_GATE(clk_img_d_vip, clk_axi_vip_bus_parents,
688
+
REG_CLK_EN_2, 21,
689
+
0);
690
+
static CV1800_GATE(clk_img_v_vip, clk_axi_vip_bus_parents,
691
+
REG_CLK_EN_2, 22,
692
+
0);
693
+
static CV1800_GATE(clk_sc_top_vip, clk_axi_vip_bus_parents,
694
+
REG_CLK_EN_2, 23,
695
+
0);
696
+
static CV1800_GATE(clk_sc_d_vip, clk_axi_vip_bus_parents,
697
+
REG_CLK_EN_2, 24,
698
+
0);
699
+
static CV1800_GATE(clk_sc_v1_vip, clk_axi_vip_bus_parents,
700
+
REG_CLK_EN_2, 25,
701
+
0);
702
+
static CV1800_GATE(clk_sc_v2_vip, clk_axi_vip_bus_parents,
703
+
REG_CLK_EN_2, 26,
704
+
0);
705
+
static CV1800_GATE(clk_sc_v3_vip, clk_axi_vip_bus_parents,
706
+
REG_CLK_EN_2, 27,
707
+
0);
708
+
static CV1800_GATE(clk_dwa_vip, clk_axi_vip_bus_parents,
709
+
REG_CLK_EN_2, 28,
710
+
0);
711
+
static CV1800_GATE(clk_bt_vip, clk_axi_vip_bus_parents,
712
+
REG_CLK_EN_2, 29,
713
+
0);
714
+
static CV1800_GATE(clk_disp_vip, clk_axi_vip_bus_parents,
715
+
REG_CLK_EN_2, 30,
716
+
0);
717
+
static CV1800_GATE(clk_dsi_mac_vip, clk_axi_vip_bus_parents,
718
+
REG_CLK_EN_2, 31,
719
+
0);
720
+
static CV1800_GATE(clk_lvds0_vip, clk_axi_vip_bus_parents,
721
+
REG_CLK_EN_3, 0,
722
+
0);
723
+
static CV1800_GATE(clk_lvds1_vip, clk_axi_vip_bus_parents,
724
+
REG_CLK_EN_3, 1,
725
+
0);
726
+
static CV1800_GATE(clk_csi0_rx_vip, clk_axi_vip_bus_parents,
727
+
REG_CLK_EN_3, 2,
728
+
0);
729
+
static CV1800_GATE(clk_csi1_rx_vip, clk_axi_vip_bus_parents,
730
+
REG_CLK_EN_3, 3,
731
+
0);
732
+
static CV1800_GATE(clk_pad_vi_vip, clk_axi_vip_bus_parents,
733
+
REG_CLK_EN_3, 4,
734
+
0);
735
+
static CV1800_GATE(clk_pad_vi1_vip, clk_axi_vip_bus_parents,
736
+
REG_CLK_EN_3, 30,
737
+
0);
738
+
static CV1800_GATE(clk_cfg_reg_vip, clk_axi6_bus_parents,
739
+
REG_CLK_EN_3, 31,
740
+
0);
741
+
static CV1800_GATE(clk_pad_vi2_vip, clk_axi_vip_bus_parents,
742
+
REG_CLK_EN_4, 7,
743
+
0);
744
+
static CV1800_GATE(clk_csi_be_vip, clk_axi_vip_bus_parents,
745
+
REG_CLK_EN_4, 8,
746
+
0);
747
+
static CV1800_GATE(clk_vip_ip0, clk_axi_vip_bus_parents,
748
+
REG_CLK_EN_4, 9,
749
+
0);
750
+
static CV1800_GATE(clk_vip_ip1, clk_axi_vip_bus_parents,
751
+
REG_CLK_EN_4, 10,
752
+
0);
753
+
static CV1800_GATE(clk_vip_ip2, clk_axi_vip_bus_parents,
754
+
REG_CLK_EN_4, 11,
755
+
0);
756
+
static CV1800_GATE(clk_vip_ip3, clk_axi_vip_bus_parents,
757
+
REG_CLK_EN_4, 12,
758
+
0);
759
+
static CV1800_BYPASS_MUX(clk_src_vip_sys_3, clk_vip_sys_parents,
760
+
REG_CLK_EN_4, 15,
761
+
REG_DIV_CLK_SRC_VIP_SYS_3, 16, 4, 2, CV1800_DIV_FLAG,
762
+
REG_DIV_CLK_SRC_VIP_SYS_3, 8, 2,
763
+
REG_CLK_BYP_1, 8,
764
+
0);
765
+
static CV1800_BYPASS_MUX(clk_src_vip_sys_4, clk_vip_sys_parents,
766
+
REG_CLK_EN_4, 16,
767
+
REG_DIV_CLK_SRC_VIP_SYS_4, 16, 4, 3, CV1800_DIV_FLAG,
768
+
REG_DIV_CLK_SRC_VIP_SYS_4, 8, 2,
769
+
REG_CLK_BYP_1, 9,
770
+
0);
771
+
static CV1800_GATE(clk_ive_vip, clk_axi_vip_bus_parents,
772
+
REG_CLK_EN_4, 17,
773
+
0);
774
+
static CV1800_GATE(clk_raw_vip, clk_axi_vip_bus_parents,
775
+
REG_CLK_EN_4, 18,
776
+
0);
777
+
static CV1800_GATE(clk_osdc_vip, clk_axi_vip_bus_parents,
778
+
REG_CLK_EN_4, 19,
779
+
0);
780
+
static CV1800_GATE(clk_csi_mac2_vip, clk_axi_vip_bus_parents,
781
+
REG_CLK_EN_4, 20,
782
+
0);
783
+
static CV1800_GATE(clk_cam0_vip, clk_axi_vip_bus_parents,
784
+
REG_CLK_EN_4, 21,
785
+
0);
786
+
787
+
/* CAM OUT */
788
+
static const struct clk_parent_data clk_cam_parents[] = {
789
+
{ .hw = &clk_cam0pll.common.hw },
790
+
{ .hw = &clk_cam0pll_d2.common.hw },
791
+
{ .hw = &clk_cam0pll_d3.common.hw },
792
+
{ .hw = &clk_mipimpll_d3.common.hw },
793
+
};
794
+
795
+
static CV1800_MUX(clk_cam0, clk_cam_parents,
796
+
REG_CLK_EN_2, 16,
797
+
REG_CLK_CAM0_SRC_DIV, 16, 6, 0, CV1800_DIV_FLAG,
798
+
REG_CLK_CAM0_SRC_DIV, 8, 2,
799
+
CLK_IGNORE_UNUSED);
800
+
static CV1800_MUX(clk_cam1, clk_cam_parents,
801
+
REG_CLK_EN_2, 17,
802
+
REG_CLK_CAM1_SRC_DIV, 16, 6, 0, CV1800_DIV_FLAG,
803
+
REG_CLK_CAM1_SRC_DIV, 8, 2,
804
+
CLK_IGNORE_UNUSED);
805
+
806
+
/* VIDEO SUBSYS */
807
+
static const struct clk_parent_data clk_axi_video_codec_parents[] = {
808
+
{ .index = 0 },
809
+
{ .hw = &clk_a0pll.common.hw },
810
+
{ .hw = &clk_mipimpll.common.hw },
811
+
{ .hw = &clk_cam1pll.common.hw },
812
+
{ .hw = &clk_fpll.common.hw },
813
+
};
814
+
static const struct clk_parent_data clk_vc_src0_parents[] = {
815
+
{ .index = 0 },
816
+
{ .hw = &clk_disppll.common.hw },
817
+
{ .hw = &clk_mipimpll.common.hw },
818
+
{ .hw = &clk_cam1pll.common.hw },
819
+
{ .hw = &clk_fpll.common.hw },
820
+
};
821
+
static const struct clk_parent_data clk_vc_src1_parents[] = {
822
+
{ .index = 0 },
823
+
{ .hw = &clk_cam1pll.common.hw },
824
+
};
825
+
826
+
static CV1800_BYPASS_MUX(clk_axi_video_codec, clk_axi_video_codec_parents,
827
+
REG_CLK_EN_2, 8,
828
+
REG_DIV_CLK_AXI_VIDEO_CODEC, 16, 4, 2, CV1800_DIV_FLAG,
829
+
REG_DIV_CLK_AXI_VIDEO_CODEC, 8, 2,
830
+
REG_CLK_BYP_0, 26,
831
+
0);
832
+
833
+
static const struct clk_parent_data clk_axi_video_codec_bus_parents[] = {
834
+
{ .hw = &clk_axi_video_codec.mux.common.hw },
835
+
};
836
+
837
+
static CV1800_BYPASS_MUX(clk_vc_src0, clk_vc_src0_parents,
838
+
REG_CLK_EN_2, 9,
839
+
REG_DIV_CLK_VC_SRC0, 16, 4, 2, CV1800_DIV_FLAG,
840
+
REG_DIV_CLK_VC_SRC0, 8, 2,
841
+
REG_CLK_BYP_0, 27,
842
+
0);
843
+
844
+
static CV1800_GATE(clk_h264c, clk_axi_video_codec_bus_parents,
845
+
REG_CLK_EN_2, 10,
846
+
0);
847
+
static CV1800_GATE(clk_h265c, clk_axi_video_codec_bus_parents,
848
+
REG_CLK_EN_2, 11,
849
+
0);
850
+
static CV1800_GATE(clk_jpeg, clk_axi_video_codec_bus_parents,
851
+
REG_CLK_EN_2, 12,
852
+
CLK_IGNORE_UNUSED);
853
+
static CV1800_GATE(clk_apb_jpeg, clk_axi6_bus_parents,
854
+
REG_CLK_EN_2, 13,
855
+
CLK_IGNORE_UNUSED);
856
+
static CV1800_GATE(clk_apb_h264c, clk_axi6_bus_parents,
857
+
REG_CLK_EN_2, 14,
858
+
0);
859
+
static CV1800_GATE(clk_apb_h265c, clk_axi6_bus_parents,
860
+
REG_CLK_EN_2, 15,
861
+
0);
862
+
static CV1800_BYPASS_FIXED_DIV(clk_vc_src1, clk_vc_src1_parents,
863
+
REG_CLK_EN_3, 28,
864
+
2,
865
+
REG_CLK_BYP_1, 0,
866
+
CLK_SET_RATE_PARENT);
867
+
static CV1800_BYPASS_FIXED_DIV(clk_vc_src2, clk_bypass_fpll_parents,
868
+
REG_CLK_EN_4, 3,
869
+
3,
870
+
REG_CLK_BYP_1, 3,
871
+
CLK_SET_RATE_PARENT);
872
+
873
+
/* VC SYS */
874
+
static CV1800_GATE(clk_cfg_reg_vc, clk_axi6_bus_parents,
875
+
REG_CLK_EN_4, 0,
876
+
CLK_IGNORE_UNUSED);
877
+
878
+
/* PWM */
879
+
static CV1800_BYPASS_MUX(clk_pwm_src, clk_axi4_parents,
880
+
REG_CLK_EN_4, 4,
881
+
REG_DIV_CLK_PWM_SRC_0, 16, 6, 10, CV1800_DIV_FLAG,
882
+
REG_DIV_CLK_PWM_SRC_0, 8, 2,
883
+
REG_CLK_BYP_0, 15,
884
+
CLK_IS_CRITICAL);
885
+
886
+
static const struct clk_parent_data clk_pwm_parents[] = {
887
+
{ .hw = &clk_pwm_src.mux.common.hw },
888
+
};
889
+
890
+
static CV1800_GATE(clk_pwm, clk_pwm_parents,
891
+
REG_CLK_EN_1, 8,
892
+
CLK_IS_CRITICAL);
893
+
894
+
/* C906 */
895
+
static const struct clk_parent_data clk_c906_0_parents[] = {
896
+
{ .index = 0 },
897
+
{ .hw = &clk_tpll.common.hw },
898
+
{ .hw = &clk_a0pll.common.hw },
899
+
{ .hw = &clk_mipimpll.common.hw },
900
+
{ .hw = &clk_mpll.common.hw },
901
+
{ .hw = &clk_fpll.common.hw },
902
+
};
903
+
static const struct clk_parent_data clk_c906_1_parents[] = {
904
+
{ .index = 0 },
905
+
{ .hw = &clk_tpll.common.hw },
906
+
{ .hw = &clk_a0pll.common.hw },
907
+
{ .hw = &clk_disppll.common.hw },
908
+
{ .hw = &clk_mpll.common.hw },
909
+
{ .hw = &clk_fpll.common.hw },
910
+
};
911
+
912
+
static const s8 clk_c906_parent2sel[] = {
913
+
-1, /* osc */
914
+
0, /* mux 0: clk_tpll(c906_0), clk_tpll(c906_1) */
915
+
0, /* mux 0: clk_a0pll(c906_0), clk_a0pll(c906_1) */
916
+
0, /* mux 0: clk_mipimpll(c906_0), clk_disppll(c906_1) */
917
+
0, /* mux 0: clk_mpll(c906_0), clk_mpll(c906_1) */
918
+
1 /* mux 1: clk_fpll(c906_0), clk_fpll(c906_1) */
919
+
};
920
+
921
+
static const u8 clk_c906_sel2parent[2][4] = {
922
+
[0] = {
923
+
1,
924
+
2,
925
+
3,
926
+
4
927
+
},
928
+
[1] = {
929
+
5,
930
+
5,
931
+
5,
932
+
5
933
+
},
934
+
};
935
+
936
+
static CV1800_MMUX(clk_c906_0, clk_c906_0_parents,
937
+
REG_CLK_EN_4, 13,
938
+
REG_DIV_CLK_C906_0_0, 16, 4, 1, CV1800_DIV_FLAG,
939
+
REG_DIV_CLK_C906_0_1, 16, 4, 2, CV1800_DIV_FLAG,
940
+
REG_DIV_CLK_C906_0_0, 8, 2,
941
+
REG_DIV_CLK_C906_0_1, 8, 2,
942
+
REG_CLK_BYP_1, 6,
943
+
REG_CLK_SEL_0, 23,
944
+
clk_c906_parent2sel,
945
+
clk_c906_sel2parent[0], clk_c906_sel2parent[1],
946
+
CLK_IS_CRITICAL | CLK_GET_RATE_NOCACHE);
947
+
static CV1800_MMUX(clk_c906_1, clk_c906_1_parents,
948
+
REG_CLK_EN_4, 14,
949
+
REG_DIV_CLK_C906_1_0, 16, 4, 2, CV1800_DIV_FLAG,
950
+
REG_DIV_CLK_C906_1_1, 16, 4, 3, CV1800_DIV_FLAG,
951
+
REG_DIV_CLK_C906_1_0, 8, 2,
952
+
REG_DIV_CLK_C906_1_1, 8, 2,
953
+
REG_CLK_BYP_1, 7,
954
+
REG_CLK_SEL_0, 24,
955
+
clk_c906_parent2sel,
956
+
clk_c906_sel2parent[0], clk_c906_sel2parent[1],
957
+
CLK_IS_CRITICAL | CLK_GET_RATE_NOCACHE);
958
+
959
+
/* A53 */
960
+
static CV1800_BYPASS_DIV(clk_cpu_axi0, clk_axi4_parents,
961
+
REG_CLK_EN_0, 1,
962
+
REG_DIV_CLK_CPU_AXI0, 16, 4, 3, CV1800_DIV_FLAG,
963
+
REG_CLK_BYP_0, 1,
964
+
CLK_IS_CRITICAL);
965
+
static CV1800_BYPASS_DIV(clk_cpu_gic, clk_bypass_fpll_parents,
966
+
REG_CLK_EN_0, 2,
967
+
REG_DIV_CLK_CPU_GIC, 16, 4, 5, CV1800_DIV_FLAG,
968
+
REG_CLK_BYP_0, 2,
969
+
CLK_IS_CRITICAL);
970
+
static CV1800_GATE(clk_xtal_ap, osc_parents,
971
+
REG_CLK_EN_0, 3,
972
+
CLK_IS_CRITICAL);
973
+
974
+
static const struct clk_parent_data clk_a53_parents[] = {
975
+
{ .index = 0 },
976
+
{ .hw = &clk_tpll.common.hw },
977
+
{ .hw = &clk_a0pll.common.hw },
978
+
{ .hw = &clk_mipimpll.common.hw },
979
+
{ .hw = &clk_mpll.common.hw },
980
+
{ .hw = &clk_fpll.common.hw },
981
+
};
982
+
983
+
static const s8 clk_a53_parent2sel[] = {
984
+
-1, /* osc */
985
+
0, /* mux 0: clk_tpll */
986
+
0, /* mux 0: clk_a0pll */
987
+
0, /* mux 0: clk_mipimpll */
988
+
0, /* mux 0: clk_mpll */
989
+
1 /* mux 1: clk_fpll */
990
+
};
991
+
992
+
static const u8 clk_a53_sel2parent[2][4] = {
993
+
[0] = {
994
+
1,
995
+
2,
996
+
3,
997
+
4
998
+
},
999
+
[1] = {
1000
+
5,
1001
+
5,
1002
+
5,
1003
+
5
1004
+
},
1005
+
};
1006
+
1007
+
/*
1008
+
* Clock for A53 cpu in the CV18XX/SG200X series.
1009
+
* For CV180X and CV181X series, this clock is not used, but can not
1010
+
* be set to bypass mode, or the SoC will hang.
1011
+
*/
1012
+
static CV1800_MMUX(clk_a53, clk_a53_parents,
1013
+
REG_CLK_EN_0, 0,
1014
+
REG_DIV_CLK_A53_0, 16, 4, 1, CV1800_DIV_FLAG,
1015
+
REG_DIV_CLK_A53_1, 16, 4, 2, CV1800_DIV_FLAG,
1016
+
REG_DIV_CLK_A53_0, 8, 2,
1017
+
REG_DIV_CLK_A53_1, 8, 2,
1018
+
REG_CLK_BYP_0, 0,
1019
+
REG_CLK_SEL_0, 0,
1020
+
clk_a53_parent2sel,
1021
+
clk_a53_sel2parent[0], clk_a53_sel2parent[1],
1022
+
CLK_IS_CRITICAL | CLK_GET_RATE_NOCACHE);
1023
+
1024
+
static struct clk_hw_onecell_data cv1800_hw_clks = {
1025
+
.num = CV1800_CLK_MAX,
1026
+
.hws = {
1027
+
[CLK_MPLL] = &clk_mpll.common.hw,
1028
+
[CLK_TPLL] = &clk_tpll.common.hw,
1029
+
[CLK_FPLL] = &clk_fpll.common.hw,
1030
+
[CLK_MIPIMPLL] = &clk_mipimpll.common.hw,
1031
+
[CLK_A0PLL] = &clk_a0pll.common.hw,
1032
+
[CLK_DISPPLL] = &clk_disppll.common.hw,
1033
+
[CLK_CAM0PLL] = &clk_cam0pll.common.hw,
1034
+
[CLK_CAM1PLL] = &clk_cam1pll.common.hw,
1035
+
1036
+
[CLK_MIPIMPLL_D3] = &clk_mipimpll_d3.common.hw,
1037
+
[CLK_CAM0PLL_D2] = &clk_cam0pll_d2.common.hw,
1038
+
[CLK_CAM0PLL_D3] = &clk_cam0pll_d3.common.hw,
1039
+
1040
+
[CLK_TPU] = &clk_tpu.mux.common.hw,
1041
+
[CLK_TPU_FAB] = &clk_tpu_fab.common.hw,
1042
+
[CLK_AHB_ROM] = &clk_ahb_rom.common.hw,
1043
+
[CLK_DDR_AXI_REG] = &clk_ddr_axi_reg.common.hw,
1044
+
[CLK_RTC_25M] = &clk_rtc_25m.common.hw,
1045
+
[CLK_SRC_RTC_SYS_0] = &clk_src_rtc_sys_0.div.common.hw,
1046
+
[CLK_TEMPSEN] = &clk_tempsen.common.hw,
1047
+
[CLK_SARADC] = &clk_saradc.common.hw,
1048
+
[CLK_EFUSE] = &clk_efuse.common.hw,
1049
+
[CLK_APB_EFUSE] = &clk_apb_efuse.common.hw,
1050
+
[CLK_DEBUG] = &clk_debug.common.hw,
1051
+
[CLK_AP_DEBUG] = &clk_ap_debug.div.common.hw,
1052
+
[CLK_XTAL_MISC] = &clk_xtal_misc.common.hw,
1053
+
[CLK_AXI4_EMMC] = &clk_axi4_emmc.common.hw,
1054
+
[CLK_EMMC] = &clk_emmc.mux.common.hw,
1055
+
[CLK_EMMC_100K] = &clk_emmc_100k.common.hw,
1056
+
[CLK_AXI4_SD0] = &clk_axi4_sd0.common.hw,
1057
+
[CLK_SD0] = &clk_sd0.mux.common.hw,
1058
+
[CLK_SD0_100K] = &clk_sd0_100k.common.hw,
1059
+
[CLK_AXI4_SD1] = &clk_axi4_sd1.common.hw,
1060
+
[CLK_SD1] = &clk_sd1.mux.common.hw,
1061
+
[CLK_SD1_100K] = &clk_sd1_100k.common.hw,
1062
+
[CLK_SPI_NAND] = &clk_spi_nand.mux.common.hw,
1063
+
[CLK_ETH0_500M] = &clk_eth0_500m.div.common.hw,
1064
+
[CLK_AXI4_ETH0] = &clk_axi4_eth0.common.hw,
1065
+
[CLK_ETH1_500M] = &clk_eth1_500m.div.common.hw,
1066
+
[CLK_AXI4_ETH1] = &clk_axi4_eth1.common.hw,
1067
+
[CLK_APB_GPIO] = &clk_apb_gpio.common.hw,
1068
+
[CLK_APB_GPIO_INTR] = &clk_apb_gpio_intr.common.hw,
1069
+
[CLK_GPIO_DB] = &clk_gpio_db.common.hw,
1070
+
[CLK_AHB_SF] = &clk_ahb_sf.common.hw,
1071
+
[CLK_AHB_SF1] = &clk_ahb_sf1.common.hw,
1072
+
[CLK_A24M] = &clk_a24m.common.hw,
1073
+
[CLK_AUDSRC] = &clk_audsrc.mux.common.hw,
1074
+
[CLK_APB_AUDSRC] = &clk_apb_audsrc.common.hw,
1075
+
[CLK_SDMA_AXI] = &clk_sdma_axi.common.hw,
1076
+
[CLK_SDMA_AUD0] = &clk_sdma_aud0.mux.common.hw,
1077
+
[CLK_SDMA_AUD1] = &clk_sdma_aud1.mux.common.hw,
1078
+
[CLK_SDMA_AUD2] = &clk_sdma_aud2.mux.common.hw,
1079
+
[CLK_SDMA_AUD3] = &clk_sdma_aud3.mux.common.hw,
1080
+
[CLK_I2C] = &clk_i2c.div.common.hw,
1081
+
[CLK_APB_I2C] = &clk_apb_i2c.common.hw,
1082
+
[CLK_APB_I2C0] = &clk_apb_i2c0.common.hw,
1083
+
[CLK_APB_I2C1] = &clk_apb_i2c1.common.hw,
1084
+
[CLK_APB_I2C2] = &clk_apb_i2c2.common.hw,
1085
+
[CLK_APB_I2C3] = &clk_apb_i2c3.common.hw,
1086
+
[CLK_APB_I2C4] = &clk_apb_i2c4.common.hw,
1087
+
[CLK_APB_WDT] = &clk_apb_wdt.common.hw,
1088
+
[CLK_PWM_SRC] = &clk_pwm_src.mux.common.hw,
1089
+
[CLK_PWM] = &clk_pwm.common.hw,
1090
+
[CLK_SPI] = &clk_spi.div.common.hw,
1091
+
[CLK_APB_SPI0] = &clk_apb_spi0.common.hw,
1092
+
[CLK_APB_SPI1] = &clk_apb_spi1.common.hw,
1093
+
[CLK_APB_SPI2] = &clk_apb_spi2.common.hw,
1094
+
[CLK_APB_SPI3] = &clk_apb_spi3.common.hw,
1095
+
[CLK_1M] = &clk_1m.common.hw,
1096
+
[CLK_CAM0_200] = &clk_cam0_200.mux.common.hw,
1097
+
[CLK_PM] = &clk_pm.common.hw,
1098
+
[CLK_TIMER0] = &clk_timer0.common.hw,
1099
+
[CLK_TIMER1] = &clk_timer1.common.hw,
1100
+
[CLK_TIMER2] = &clk_timer2.common.hw,
1101
+
[CLK_TIMER3] = &clk_timer3.common.hw,
1102
+
[CLK_TIMER4] = &clk_timer4.common.hw,
1103
+
[CLK_TIMER5] = &clk_timer5.common.hw,
1104
+
[CLK_TIMER6] = &clk_timer6.common.hw,
1105
+
[CLK_TIMER7] = &clk_timer7.common.hw,
1106
+
[CLK_UART0] = &clk_uart0.common.hw,
1107
+
[CLK_APB_UART0] = &clk_apb_uart0.common.hw,
1108
+
[CLK_UART1] = &clk_uart1.common.hw,
1109
+
[CLK_APB_UART1] = &clk_apb_uart1.common.hw,
1110
+
[CLK_UART2] = &clk_uart2.common.hw,
1111
+
[CLK_APB_UART2] = &clk_apb_uart2.common.hw,
1112
+
[CLK_UART3] = &clk_uart3.common.hw,
1113
+
[CLK_APB_UART3] = &clk_apb_uart3.common.hw,
1114
+
[CLK_UART4] = &clk_uart4.common.hw,
1115
+
[CLK_APB_UART4] = &clk_apb_uart4.common.hw,
1116
+
[CLK_APB_I2S0] = &clk_apb_i2s0.common.hw,
1117
+
[CLK_APB_I2S1] = &clk_apb_i2s1.common.hw,
1118
+
[CLK_APB_I2S2] = &clk_apb_i2s2.common.hw,
1119
+
[CLK_APB_I2S3] = &clk_apb_i2s3.common.hw,
1120
+
[CLK_AXI4_USB] = &clk_axi4_usb.common.hw,
1121
+
[CLK_APB_USB] = &clk_apb_usb.common.hw,
1122
+
[CLK_USB_125M] = &clk_usb_125m.div.common.hw,
1123
+
[CLK_USB_33K] = &clk_usb_33k.common.hw,
1124
+
[CLK_USB_12M] = &clk_usb_12m.div.common.hw,
1125
+
[CLK_AXI4] = &clk_axi4.mux.common.hw,
1126
+
[CLK_AXI6] = &clk_axi6.div.common.hw,
1127
+
[CLK_DSI_ESC] = &clk_dsi_esc.div.common.hw,
1128
+
[CLK_AXI_VIP] = &clk_axi_vip.mux.common.hw,
1129
+
[CLK_SRC_VIP_SYS_0] = &clk_src_vip_sys_0.mux.common.hw,
1130
+
[CLK_SRC_VIP_SYS_1] = &clk_src_vip_sys_1.mux.common.hw,
1131
+
[CLK_SRC_VIP_SYS_2] = &clk_src_vip_sys_2.mux.common.hw,
1132
+
[CLK_SRC_VIP_SYS_3] = &clk_src_vip_sys_3.mux.common.hw,
1133
+
[CLK_SRC_VIP_SYS_4] = &clk_src_vip_sys_4.mux.common.hw,
1134
+
[CLK_CSI_BE_VIP] = &clk_csi_be_vip.common.hw,
1135
+
[CLK_CSI_MAC0_VIP] = &clk_csi_mac0_vip.common.hw,
1136
+
[CLK_CSI_MAC1_VIP] = &clk_csi_mac1_vip.common.hw,
1137
+
[CLK_CSI_MAC2_VIP] = &clk_csi_mac2_vip.common.hw,
1138
+
[CLK_CSI0_RX_VIP] = &clk_csi0_rx_vip.common.hw,
1139
+
[CLK_CSI1_RX_VIP] = &clk_csi1_rx_vip.common.hw,
1140
+
[CLK_ISP_TOP_VIP] = &clk_isp_top_vip.common.hw,
1141
+
[CLK_IMG_D_VIP] = &clk_img_d_vip.common.hw,
1142
+
[CLK_IMG_V_VIP] = &clk_img_v_vip.common.hw,
1143
+
[CLK_SC_TOP_VIP] = &clk_sc_top_vip.common.hw,
1144
+
[CLK_SC_D_VIP] = &clk_sc_d_vip.common.hw,
1145
+
[CLK_SC_V1_VIP] = &clk_sc_v1_vip.common.hw,
1146
+
[CLK_SC_V2_VIP] = &clk_sc_v2_vip.common.hw,
1147
+
[CLK_SC_V3_VIP] = &clk_sc_v3_vip.common.hw,
1148
+
[CLK_DWA_VIP] = &clk_dwa_vip.common.hw,
1149
+
[CLK_BT_VIP] = &clk_bt_vip.common.hw,
1150
+
[CLK_DISP_VIP] = &clk_disp_vip.common.hw,
1151
+
[CLK_DSI_MAC_VIP] = &clk_dsi_mac_vip.common.hw,
1152
+
[CLK_LVDS0_VIP] = &clk_lvds0_vip.common.hw,
1153
+
[CLK_LVDS1_VIP] = &clk_lvds1_vip.common.hw,
1154
+
[CLK_PAD_VI_VIP] = &clk_pad_vi_vip.common.hw,
1155
+
[CLK_PAD_VI1_VIP] = &clk_pad_vi1_vip.common.hw,
1156
+
[CLK_PAD_VI2_VIP] = &clk_pad_vi2_vip.common.hw,
1157
+
[CLK_CFG_REG_VIP] = &clk_cfg_reg_vip.common.hw,
1158
+
[CLK_VIP_IP0] = &clk_vip_ip0.common.hw,
1159
+
[CLK_VIP_IP1] = &clk_vip_ip1.common.hw,
1160
+
[CLK_VIP_IP2] = &clk_vip_ip2.common.hw,
1161
+
[CLK_VIP_IP3] = &clk_vip_ip3.common.hw,
1162
+
[CLK_IVE_VIP] = &clk_ive_vip.common.hw,
1163
+
[CLK_RAW_VIP] = &clk_raw_vip.common.hw,
1164
+
[CLK_OSDC_VIP] = &clk_osdc_vip.common.hw,
1165
+
[CLK_CAM0_VIP] = &clk_cam0_vip.common.hw,
1166
+
[CLK_AXI_VIDEO_CODEC] = &clk_axi_video_codec.mux.common.hw,
1167
+
[CLK_VC_SRC0] = &clk_vc_src0.mux.common.hw,
1168
+
[CLK_VC_SRC1] = &clk_vc_src1.div.common.hw,
1169
+
[CLK_VC_SRC2] = &clk_vc_src2.div.common.hw,
1170
+
[CLK_H264C] = &clk_h264c.common.hw,
1171
+
[CLK_APB_H264C] = &clk_apb_h264c.common.hw,
1172
+
[CLK_H265C] = &clk_h265c.common.hw,
1173
+
[CLK_APB_H265C] = &clk_apb_h265c.common.hw,
1174
+
[CLK_JPEG] = &clk_jpeg.common.hw,
1175
+
[CLK_APB_JPEG] = &clk_apb_jpeg.common.hw,
1176
+
[CLK_CAM0] = &clk_cam0.common.hw,
1177
+
[CLK_CAM1] = &clk_cam1.common.hw,
1178
+
[CLK_WGN] = &clk_wgn.common.hw,
1179
+
[CLK_WGN0] = &clk_wgn0.common.hw,
1180
+
[CLK_WGN1] = &clk_wgn1.common.hw,
1181
+
[CLK_WGN2] = &clk_wgn2.common.hw,
1182
+
[CLK_KEYSCAN] = &clk_keyscan.common.hw,
1183
+
[CLK_CFG_REG_VC] = &clk_cfg_reg_vc.common.hw,
1184
+
[CLK_C906_0] = &clk_c906_0.common.hw,
1185
+
[CLK_C906_1] = &clk_c906_1.common.hw,
1186
+
[CLK_A53] = &clk_a53.common.hw,
1187
+
[CLK_CPU_AXI0] = &clk_cpu_axi0.div.common.hw,
1188
+
[CLK_CPU_GIC] = &clk_cpu_gic.div.common.hw,
1189
+
[CLK_XTAL_AP] = &clk_xtal_ap.common.hw,
1190
+
},
1191
+
};
1192
+
1193
+
static void cv18xx_clk_disable_auto_pd(void __iomem *base)
1194
+
{
1195
+
static const u16 CV1800_PD_CLK[] = {
1196
+
REG_MIPIMPLL_CLK_CSR,
1197
+
REG_A0PLL_CLK_CSR,
1198
+
REG_DISPPLL_CLK_CSR,
1199
+
REG_CAM0PLL_CLK_CSR,
1200
+
REG_CAM1PLL_CLK_CSR,
1201
+
};
1202
+
1203
+
u32 val;
1204
+
int i;
1205
+
1206
+
/* disable auto power down */
1207
+
for (i = 0; i < ARRAY_SIZE(CV1800_PD_CLK); i++) {
1208
+
u32 reg = CV1800_PD_CLK[i];
1209
+
1210
+
val = readl(base + reg);
1211
+
val |= GENMASK(12, 9);
1212
+
val &= ~BIT(8);
1213
+
writel(val, base + reg);
1214
+
}
1215
+
}
1216
+
1217
+
static void cv18xx_clk_disable_a53(void __iomem *base)
1218
+
{
1219
+
u32 val = readl(base + REG_CLK_BYP_0);
1220
+
1221
+
/* Set bypass clock for clk_a53 */
1222
+
val |= BIT(0);
1223
+
1224
+
/* Set bypass clock for clk_cpu_axi0 */
1225
+
val |= BIT(1);
1226
+
1227
+
/* Set bypass clock for clk_cpu_gic */
1228
+
val |= BIT(2);
1229
+
1230
+
writel(val, base + REG_CLK_BYP_0);
1231
+
}
1232
+
1233
+
static int cv1800_pre_init(struct device *dev, void __iomem *base,
1234
+
struct cv1800_clk_ctrl *ctrl,
1235
+
const struct cv1800_clk_desc *desc)
1236
+
{
1237
+
u32 val = readl(base + REG_CLK_EN_2);
1238
+
1239
+
/* disable unsupported clk_disp_src_vip */
1240
+
val &= ~BIT(7);
1241
+
1242
+
writel(val, base + REG_CLK_EN_2);
1243
+
1244
+
cv18xx_clk_disable_a53(base);
1245
+
cv18xx_clk_disable_auto_pd(base);
1246
+
1247
+
return 0;
1248
+
}
1249
+
1250
+
static const struct cv1800_clk_desc cv1800_desc = {
1251
+
.clks_data = &cv1800_hw_clks,
1252
+
.pre_init = cv1800_pre_init,
1253
+
};
1254
+
1255
+
static struct clk_hw_onecell_data cv1810_hw_clks = {
1256
+
.num = CV1810_CLK_MAX,
1257
+
.hws = {
1258
+
[CLK_MPLL] = &clk_mpll.common.hw,
1259
+
[CLK_TPLL] = &clk_tpll.common.hw,
1260
+
[CLK_FPLL] = &clk_fpll.common.hw,
1261
+
[CLK_MIPIMPLL] = &clk_mipimpll.common.hw,
1262
+
[CLK_A0PLL] = &clk_a0pll.common.hw,
1263
+
[CLK_DISPPLL] = &clk_disppll.common.hw,
1264
+
[CLK_CAM0PLL] = &clk_cam0pll.common.hw,
1265
+
[CLK_CAM1PLL] = &clk_cam1pll.common.hw,
1266
+
1267
+
[CLK_MIPIMPLL_D3] = &clk_mipimpll_d3.common.hw,
1268
+
[CLK_CAM0PLL_D2] = &clk_cam0pll_d2.common.hw,
1269
+
[CLK_CAM0PLL_D3] = &clk_cam0pll_d3.common.hw,
1270
+
1271
+
[CLK_TPU] = &clk_tpu.mux.common.hw,
1272
+
[CLK_TPU_FAB] = &clk_tpu_fab.common.hw,
1273
+
[CLK_AHB_ROM] = &clk_ahb_rom.common.hw,
1274
+
[CLK_DDR_AXI_REG] = &clk_ddr_axi_reg.common.hw,
1275
+
[CLK_RTC_25M] = &clk_rtc_25m.common.hw,
1276
+
[CLK_SRC_RTC_SYS_0] = &clk_src_rtc_sys_0.div.common.hw,
1277
+
[CLK_TEMPSEN] = &clk_tempsen.common.hw,
1278
+
[CLK_SARADC] = &clk_saradc.common.hw,
1279
+
[CLK_EFUSE] = &clk_efuse.common.hw,
1280
+
[CLK_APB_EFUSE] = &clk_apb_efuse.common.hw,
1281
+
[CLK_DEBUG] = &clk_debug.common.hw,
1282
+
[CLK_AP_DEBUG] = &clk_ap_debug.div.common.hw,
1283
+
[CLK_XTAL_MISC] = &clk_xtal_misc.common.hw,
1284
+
[CLK_AXI4_EMMC] = &clk_axi4_emmc.common.hw,
1285
+
[CLK_EMMC] = &clk_emmc.mux.common.hw,
1286
+
[CLK_EMMC_100K] = &clk_emmc_100k.common.hw,
1287
+
[CLK_AXI4_SD0] = &clk_axi4_sd0.common.hw,
1288
+
[CLK_SD0] = &clk_sd0.mux.common.hw,
1289
+
[CLK_SD0_100K] = &clk_sd0_100k.common.hw,
1290
+
[CLK_AXI4_SD1] = &clk_axi4_sd1.common.hw,
1291
+
[CLK_SD1] = &clk_sd1.mux.common.hw,
1292
+
[CLK_SD1_100K] = &clk_sd1_100k.common.hw,
1293
+
[CLK_SPI_NAND] = &clk_spi_nand.mux.common.hw,
1294
+
[CLK_ETH0_500M] = &clk_eth0_500m.div.common.hw,
1295
+
[CLK_AXI4_ETH0] = &clk_axi4_eth0.common.hw,
1296
+
[CLK_ETH1_500M] = &clk_eth1_500m.div.common.hw,
1297
+
[CLK_AXI4_ETH1] = &clk_axi4_eth1.common.hw,
1298
+
[CLK_APB_GPIO] = &clk_apb_gpio.common.hw,
1299
+
[CLK_APB_GPIO_INTR] = &clk_apb_gpio_intr.common.hw,
1300
+
[CLK_GPIO_DB] = &clk_gpio_db.common.hw,
1301
+
[CLK_AHB_SF] = &clk_ahb_sf.common.hw,
1302
+
[CLK_AHB_SF1] = &clk_ahb_sf1.common.hw,
1303
+
[CLK_A24M] = &clk_a24m.common.hw,
1304
+
[CLK_AUDSRC] = &clk_audsrc.mux.common.hw,
1305
+
[CLK_APB_AUDSRC] = &clk_apb_audsrc.common.hw,
1306
+
[CLK_SDMA_AXI] = &clk_sdma_axi.common.hw,
1307
+
[CLK_SDMA_AUD0] = &clk_sdma_aud0.mux.common.hw,
1308
+
[CLK_SDMA_AUD1] = &clk_sdma_aud1.mux.common.hw,
1309
+
[CLK_SDMA_AUD2] = &clk_sdma_aud2.mux.common.hw,
1310
+
[CLK_SDMA_AUD3] = &clk_sdma_aud3.mux.common.hw,
1311
+
[CLK_I2C] = &clk_i2c.div.common.hw,
1312
+
[CLK_APB_I2C] = &clk_apb_i2c.common.hw,
1313
+
[CLK_APB_I2C0] = &clk_apb_i2c0.common.hw,
1314
+
[CLK_APB_I2C1] = &clk_apb_i2c1.common.hw,
1315
+
[CLK_APB_I2C2] = &clk_apb_i2c2.common.hw,
1316
+
[CLK_APB_I2C3] = &clk_apb_i2c3.common.hw,
1317
+
[CLK_APB_I2C4] = &clk_apb_i2c4.common.hw,
1318
+
[CLK_APB_WDT] = &clk_apb_wdt.common.hw,
1319
+
[CLK_PWM_SRC] = &clk_pwm_src.mux.common.hw,
1320
+
[CLK_PWM] = &clk_pwm.common.hw,
1321
+
[CLK_SPI] = &clk_spi.div.common.hw,
1322
+
[CLK_APB_SPI0] = &clk_apb_spi0.common.hw,
1323
+
[CLK_APB_SPI1] = &clk_apb_spi1.common.hw,
1324
+
[CLK_APB_SPI2] = &clk_apb_spi2.common.hw,
1325
+
[CLK_APB_SPI3] = &clk_apb_spi3.common.hw,
1326
+
[CLK_1M] = &clk_1m.common.hw,
1327
+
[CLK_CAM0_200] = &clk_cam0_200.mux.common.hw,
1328
+
[CLK_PM] = &clk_pm.common.hw,
1329
+
[CLK_TIMER0] = &clk_timer0.common.hw,
1330
+
[CLK_TIMER1] = &clk_timer1.common.hw,
1331
+
[CLK_TIMER2] = &clk_timer2.common.hw,
1332
+
[CLK_TIMER3] = &clk_timer3.common.hw,
1333
+
[CLK_TIMER4] = &clk_timer4.common.hw,
1334
+
[CLK_TIMER5] = &clk_timer5.common.hw,
1335
+
[CLK_TIMER6] = &clk_timer6.common.hw,
1336
+
[CLK_TIMER7] = &clk_timer7.common.hw,
1337
+
[CLK_UART0] = &clk_uart0.common.hw,
1338
+
[CLK_APB_UART0] = &clk_apb_uart0.common.hw,
1339
+
[CLK_UART1] = &clk_uart1.common.hw,
1340
+
[CLK_APB_UART1] = &clk_apb_uart1.common.hw,
1341
+
[CLK_UART2] = &clk_uart2.common.hw,
1342
+
[CLK_APB_UART2] = &clk_apb_uart2.common.hw,
1343
+
[CLK_UART3] = &clk_uart3.common.hw,
1344
+
[CLK_APB_UART3] = &clk_apb_uart3.common.hw,
1345
+
[CLK_UART4] = &clk_uart4.common.hw,
1346
+
[CLK_APB_UART4] = &clk_apb_uart4.common.hw,
1347
+
[CLK_APB_I2S0] = &clk_apb_i2s0.common.hw,
1348
+
[CLK_APB_I2S1] = &clk_apb_i2s1.common.hw,
1349
+
[CLK_APB_I2S2] = &clk_apb_i2s2.common.hw,
1350
+
[CLK_APB_I2S3] = &clk_apb_i2s3.common.hw,
1351
+
[CLK_AXI4_USB] = &clk_axi4_usb.common.hw,
1352
+
[CLK_APB_USB] = &clk_apb_usb.common.hw,
1353
+
[CLK_USB_125M] = &clk_usb_125m.div.common.hw,
1354
+
[CLK_USB_33K] = &clk_usb_33k.common.hw,
1355
+
[CLK_USB_12M] = &clk_usb_12m.div.common.hw,
1356
+
[CLK_AXI4] = &clk_axi4.mux.common.hw,
1357
+
[CLK_AXI6] = &clk_axi6.div.common.hw,
1358
+
[CLK_DSI_ESC] = &clk_dsi_esc.div.common.hw,
1359
+
[CLK_AXI_VIP] = &clk_axi_vip.mux.common.hw,
1360
+
[CLK_SRC_VIP_SYS_0] = &clk_src_vip_sys_0.mux.common.hw,
1361
+
[CLK_SRC_VIP_SYS_1] = &clk_src_vip_sys_1.mux.common.hw,
1362
+
[CLK_SRC_VIP_SYS_2] = &clk_src_vip_sys_2.mux.common.hw,
1363
+
[CLK_SRC_VIP_SYS_3] = &clk_src_vip_sys_3.mux.common.hw,
1364
+
[CLK_SRC_VIP_SYS_4] = &clk_src_vip_sys_4.mux.common.hw,
1365
+
[CLK_CSI_BE_VIP] = &clk_csi_be_vip.common.hw,
1366
+
[CLK_CSI_MAC0_VIP] = &clk_csi_mac0_vip.common.hw,
1367
+
[CLK_CSI_MAC1_VIP] = &clk_csi_mac1_vip.common.hw,
1368
+
[CLK_CSI_MAC2_VIP] = &clk_csi_mac2_vip.common.hw,
1369
+
[CLK_CSI0_RX_VIP] = &clk_csi0_rx_vip.common.hw,
1370
+
[CLK_CSI1_RX_VIP] = &clk_csi1_rx_vip.common.hw,
1371
+
[CLK_ISP_TOP_VIP] = &clk_isp_top_vip.common.hw,
1372
+
[CLK_IMG_D_VIP] = &clk_img_d_vip.common.hw,
1373
+
[CLK_IMG_V_VIP] = &clk_img_v_vip.common.hw,
1374
+
[CLK_SC_TOP_VIP] = &clk_sc_top_vip.common.hw,
1375
+
[CLK_SC_D_VIP] = &clk_sc_d_vip.common.hw,
1376
+
[CLK_SC_V1_VIP] = &clk_sc_v1_vip.common.hw,
1377
+
[CLK_SC_V2_VIP] = &clk_sc_v2_vip.common.hw,
1378
+
[CLK_SC_V3_VIP] = &clk_sc_v3_vip.common.hw,
1379
+
[CLK_DWA_VIP] = &clk_dwa_vip.common.hw,
1380
+
[CLK_BT_VIP] = &clk_bt_vip.common.hw,
1381
+
[CLK_DISP_VIP] = &clk_disp_vip.common.hw,
1382
+
[CLK_DSI_MAC_VIP] = &clk_dsi_mac_vip.common.hw,
1383
+
[CLK_LVDS0_VIP] = &clk_lvds0_vip.common.hw,
1384
+
[CLK_LVDS1_VIP] = &clk_lvds1_vip.common.hw,
1385
+
[CLK_PAD_VI_VIP] = &clk_pad_vi_vip.common.hw,
1386
+
[CLK_PAD_VI1_VIP] = &clk_pad_vi1_vip.common.hw,
1387
+
[CLK_PAD_VI2_VIP] = &clk_pad_vi2_vip.common.hw,
1388
+
[CLK_CFG_REG_VIP] = &clk_cfg_reg_vip.common.hw,
1389
+
[CLK_VIP_IP0] = &clk_vip_ip0.common.hw,
1390
+
[CLK_VIP_IP1] = &clk_vip_ip1.common.hw,
1391
+
[CLK_VIP_IP2] = &clk_vip_ip2.common.hw,
1392
+
[CLK_VIP_IP3] = &clk_vip_ip3.common.hw,
1393
+
[CLK_IVE_VIP] = &clk_ive_vip.common.hw,
1394
+
[CLK_RAW_VIP] = &clk_raw_vip.common.hw,
1395
+
[CLK_OSDC_VIP] = &clk_osdc_vip.common.hw,
1396
+
[CLK_CAM0_VIP] = &clk_cam0_vip.common.hw,
1397
+
[CLK_AXI_VIDEO_CODEC] = &clk_axi_video_codec.mux.common.hw,
1398
+
[CLK_VC_SRC0] = &clk_vc_src0.mux.common.hw,
1399
+
[CLK_VC_SRC1] = &clk_vc_src1.div.common.hw,
1400
+
[CLK_VC_SRC2] = &clk_vc_src2.div.common.hw,
1401
+
[CLK_H264C] = &clk_h264c.common.hw,
1402
+
[CLK_APB_H264C] = &clk_apb_h264c.common.hw,
1403
+
[CLK_H265C] = &clk_h265c.common.hw,
1404
+
[CLK_APB_H265C] = &clk_apb_h265c.common.hw,
1405
+
[CLK_JPEG] = &clk_jpeg.common.hw,
1406
+
[CLK_APB_JPEG] = &clk_apb_jpeg.common.hw,
1407
+
[CLK_CAM0] = &clk_cam0.common.hw,
1408
+
[CLK_CAM1] = &clk_cam1.common.hw,
1409
+
[CLK_WGN] = &clk_wgn.common.hw,
1410
+
[CLK_WGN0] = &clk_wgn0.common.hw,
1411
+
[CLK_WGN1] = &clk_wgn1.common.hw,
1412
+
[CLK_WGN2] = &clk_wgn2.common.hw,
1413
+
[CLK_KEYSCAN] = &clk_keyscan.common.hw,
1414
+
[CLK_CFG_REG_VC] = &clk_cfg_reg_vc.common.hw,
1415
+
[CLK_C906_0] = &clk_c906_0.common.hw,
1416
+
[CLK_C906_1] = &clk_c906_1.common.hw,
1417
+
[CLK_A53] = &clk_a53.common.hw,
1418
+
[CLK_CPU_AXI0] = &clk_cpu_axi0.div.common.hw,
1419
+
[CLK_CPU_GIC] = &clk_cpu_gic.div.common.hw,
1420
+
[CLK_XTAL_AP] = &clk_xtal_ap.common.hw,
1421
+
[CLK_DISP_SRC_VIP] = &clk_disp_src_vip.div.common.hw,
1422
+
},
1423
+
};
1424
+
1425
+
static int cv1810_pre_init(struct device *dev, void __iomem *base,
1426
+
struct cv1800_clk_ctrl *ctrl,
1427
+
const struct cv1800_clk_desc *desc)
1428
+
{
1429
+
cv18xx_clk_disable_a53(base);
1430
+
cv18xx_clk_disable_auto_pd(base);
1431
+
1432
+
return 0;
1433
+
}
1434
+
1435
+
static const struct cv1800_clk_desc cv1810_desc = {
1436
+
.clks_data = &cv1810_hw_clks,
1437
+
.pre_init = cv1810_pre_init,
1438
+
};
1439
+
1440
+
static int sg2000_pre_init(struct device *dev, void __iomem *base,
1441
+
struct cv1800_clk_ctrl *ctrl,
1442
+
const struct cv1800_clk_desc *desc)
1443
+
{
1444
+
cv18xx_clk_disable_auto_pd(base);
1445
+
1446
+
return 0;
1447
+
}
1448
+
1449
+
static const struct cv1800_clk_desc sg2000_desc = {
1450
+
.clks_data = &cv1810_hw_clks,
1451
+
.pre_init = sg2000_pre_init,
1452
+
};
1453
+
1454
+
static int cv1800_clk_init_ctrl(struct device *dev, void __iomem *reg,
1455
+
struct cv1800_clk_ctrl *ctrl,
1456
+
const struct cv1800_clk_desc *desc)
1457
+
{
1458
+
int i, ret;
1459
+
1460
+
ctrl->desc = desc;
1461
+
spin_lock_init(&ctrl->lock);
1462
+
1463
+
for (i = 0; i < desc->clks_data->num; i++) {
1464
+
struct clk_hw *hw = desc->clks_data->hws[i];
1465
+
struct cv1800_clk_common *common;
1466
+
const char *name;
1467
+
1468
+
if (!hw)
1469
+
continue;
1470
+
1471
+
name = hw->init->name;
1472
+
1473
+
common = hw_to_cv1800_clk_common(hw);
1474
+
common->base = reg;
1475
+
common->lock = &ctrl->lock;
1476
+
1477
+
ret = devm_clk_hw_register(dev, hw);
1478
+
if (ret) {
1479
+
dev_err(dev, "Couldn't register clock %d - %s\n",
1480
+
i, name);
1481
+
return ret;
1482
+
}
1483
+
}
1484
+
1485
+
return devm_of_clk_add_hw_provider(dev, of_clk_hw_onecell_get,
1486
+
desc->clks_data);
1487
+
}
1488
+
1489
+
static int cv1800_clk_probe(struct platform_device *pdev)
1490
+
{
1491
+
struct device *dev = &pdev->dev;
1492
+
void __iomem *reg;
1493
+
int ret;
1494
+
const struct cv1800_clk_desc *desc;
1495
+
struct cv1800_clk_ctrl *ctrl;
1496
+
1497
+
reg = devm_platform_ioremap_resource(pdev, 0);
1498
+
if (IS_ERR(reg))
1499
+
return PTR_ERR(reg);
1500
+
1501
+
desc = device_get_match_data(dev);
1502
+
if (!desc) {
1503
+
dev_err(dev, "no match data for platform\n");
1504
+
return -EINVAL;
1505
+
}
1506
+
1507
+
ctrl = devm_kzalloc(dev, sizeof(*ctrl), GFP_KERNEL);
1508
+
if (!ctrl)
1509
+
return -ENOMEM;
1510
+
1511
+
if (desc->pre_init) {
1512
+
ret = desc->pre_init(dev, reg, ctrl, desc);
1513
+
if (ret)
1514
+
return ret;
1515
+
}
1516
+
1517
+
return cv1800_clk_init_ctrl(dev, reg, ctrl, desc);
1518
+
}
1519
+
1520
+
static const struct of_device_id cv1800_clk_ids[] = {
1521
+
{ .compatible = "sophgo,cv1800-clk", .data = &cv1800_desc },
1522
+
{ .compatible = "sophgo,cv1810-clk", .data = &cv1810_desc },
1523
+
{ .compatible = "sophgo,sg2000-clk", .data = &sg2000_desc },
1524
+
{ }
1525
+
};
1526
+
MODULE_DEVICE_TABLE(of, cv1800_clk_ids);
1527
+
1528
+
static struct platform_driver cv1800_clk_driver = {
1529
+
.probe = cv1800_clk_probe,
1530
+
.driver = {
1531
+
.name = "cv1800-clk",
1532
+
.suppress_bind_attrs = true,
1533
+
.of_match_table = cv1800_clk_ids,
1534
+
},
1535
+
};
1536
+
module_platform_driver(cv1800_clk_driver);
1537
+
MODULE_LICENSE("GPL");
+123
drivers/clk/sophgo/clk-cv1800.h
+123
drivers/clk/sophgo/clk-cv1800.h
···
1
+
/* SPDX-License-Identifier: GPL-2.0 */
2
+
/*
3
+
* Copyright (C) 2023 Inochi Amaoto <inochiama@outlook.com>
4
+
*/
5
+
6
+
#ifndef _CLK_SOPHGO_CV1800_H_
7
+
#define _CLK_SOPHGO_CV1800_H_
8
+
9
+
#include <dt-bindings/clock/sophgo,cv1800.h>
10
+
11
+
#define CV1800_CLK_MAX (CLK_XTAL_AP + 1)
12
+
#define CV1810_CLK_MAX (CLK_DISP_SRC_VIP + 1)
13
+
14
+
#define REG_PLL_G2_CTRL 0x800
15
+
#define REG_PLL_G2_STATUS 0x804
16
+
#define REG_MIPIMPLL_CSR 0x808
17
+
#define REG_A0PLL_CSR 0x80C
18
+
#define REG_DISPPLL_CSR 0x810
19
+
#define REG_CAM0PLL_CSR 0x814
20
+
#define REG_CAM1PLL_CSR 0x818
21
+
#define REG_PLL_G2_SSC_SYN_CTRL 0x840
22
+
#define REG_A0PLL_SSC_SYN_CTRL 0x850
23
+
#define REG_A0PLL_SSC_SYN_SET 0x854
24
+
#define REG_A0PLL_SSC_SYN_SPAN 0x858
25
+
#define REG_A0PLL_SSC_SYN_STEP 0x85C
26
+
#define REG_DISPPLL_SSC_SYN_CTRL 0x860
27
+
#define REG_DISPPLL_SSC_SYN_SET 0x864
28
+
#define REG_DISPPLL_SSC_SYN_SPAN 0x868
29
+
#define REG_DISPPLL_SSC_SYN_STEP 0x86C
30
+
#define REG_CAM0PLL_SSC_SYN_CTRL 0x870
31
+
#define REG_CAM0PLL_SSC_SYN_SET 0x874
32
+
#define REG_CAM0PLL_SSC_SYN_SPAN 0x878
33
+
#define REG_CAM0PLL_SSC_SYN_STEP 0x87C
34
+
#define REG_CAM1PLL_SSC_SYN_CTRL 0x880
35
+
#define REG_CAM1PLL_SSC_SYN_SET 0x884
36
+
#define REG_CAM1PLL_SSC_SYN_SPAN 0x888
37
+
#define REG_CAM1PLL_SSC_SYN_STEP 0x88C
38
+
#define REG_APLL_FRAC_DIV_CTRL 0x890
39
+
#define REG_APLL_FRAC_DIV_M 0x894
40
+
#define REG_APLL_FRAC_DIV_N 0x898
41
+
#define REG_MIPIMPLL_CLK_CSR 0x8A0
42
+
#define REG_A0PLL_CLK_CSR 0x8A4
43
+
#define REG_DISPPLL_CLK_CSR 0x8A8
44
+
#define REG_CAM0PLL_CLK_CSR 0x8AC
45
+
#define REG_CAM1PLL_CLK_CSR 0x8B0
46
+
#define REG_CLK_CAM0_SRC_DIV 0x8C0
47
+
#define REG_CLK_CAM1_SRC_DIV 0x8C4
48
+
49
+
/* top_pll_g6 */
50
+
#define REG_PLL_G6_CTRL 0x900
51
+
#define REG_PLL_G6_STATUS 0x904
52
+
#define REG_MPLL_CSR 0x908
53
+
#define REG_TPLL_CSR 0x90C
54
+
#define REG_FPLL_CSR 0x910
55
+
#define REG_PLL_G6_SSC_SYN_CTRL 0x940
56
+
#define REG_DPLL_SSC_SYN_CTRL 0x950
57
+
#define REG_DPLL_SSC_SYN_SET 0x954
58
+
#define REG_DPLL_SSC_SYN_SPAN 0x958
59
+
#define REG_DPLL_SSC_SYN_STEP 0x95C
60
+
#define REG_MPLL_SSC_SYN_CTRL 0x960
61
+
#define REG_MPLL_SSC_SYN_SET 0x964
62
+
#define REG_MPLL_SSC_SYN_SPAN 0x968
63
+
#define REG_MPLL_SSC_SYN_STEP 0x96C
64
+
#define REG_TPLL_SSC_SYN_CTRL 0x970
65
+
#define REG_TPLL_SSC_SYN_SET 0x974
66
+
#define REG_TPLL_SSC_SYN_SPAN 0x978
67
+
#define REG_TPLL_SSC_SYN_STEP 0x97C
68
+
69
+
/* clkgen */
70
+
#define REG_CLK_EN_0 0x000
71
+
#define REG_CLK_EN_1 0x004
72
+
#define REG_CLK_EN_2 0x008
73
+
#define REG_CLK_EN_3 0x00C
74
+
#define REG_CLK_EN_4 0x010
75
+
#define REG_CLK_SEL_0 0x020
76
+
#define REG_CLK_BYP_0 0x030
77
+
#define REG_CLK_BYP_1 0x034
78
+
79
+
#define REG_DIV_CLK_A53_0 0x040
80
+
#define REG_DIV_CLK_A53_1 0x044
81
+
#define REG_DIV_CLK_CPU_AXI0 0x048
82
+
#define REG_DIV_CLK_CPU_GIC 0x050
83
+
#define REG_DIV_CLK_TPU 0x054
84
+
#define REG_DIV_CLK_EMMC 0x064
85
+
#define REG_DIV_CLK_EMMC_100K 0x06C
86
+
#define REG_DIV_CLK_SD0 0x070
87
+
#define REG_DIV_CLK_SD0_100K 0x078
88
+
#define REG_DIV_CLK_SD1 0x07C
89
+
#define REG_DIV_CLK_SD1_100K 0x084
90
+
#define REG_DIV_CLK_SPI_NAND 0x088
91
+
#define REG_DIV_CLK_ETH0_500M 0x08C
92
+
#define REG_DIV_CLK_ETH1_500M 0x090
93
+
#define REG_DIV_CLK_GPIO_DB 0x094
94
+
#define REG_DIV_CLK_SDMA_AUD0 0x098
95
+
#define REG_DIV_CLK_SDMA_AUD1 0x09C
96
+
#define REG_DIV_CLK_SDMA_AUD2 0x0A0
97
+
#define REG_DIV_CLK_SDMA_AUD3 0x0A4
98
+
#define REG_DIV_CLK_CAM0_200 0x0A8
99
+
#define REG_DIV_CLK_AXI4 0x0B8
100
+
#define REG_DIV_CLK_AXI6 0x0BC
101
+
#define REG_DIV_CLK_DSI_ESC 0x0C4
102
+
#define REG_DIV_CLK_AXI_VIP 0x0C8
103
+
#define REG_DIV_CLK_SRC_VIP_SYS_0 0x0D0
104
+
#define REG_DIV_CLK_SRC_VIP_SYS_1 0x0D8
105
+
#define REG_DIV_CLK_DISP_SRC_VIP 0x0E0
106
+
#define REG_DIV_CLK_AXI_VIDEO_CODEC 0x0E4
107
+
#define REG_DIV_CLK_VC_SRC0 0x0EC
108
+
#define REG_DIV_CLK_1M 0x0FC
109
+
#define REG_DIV_CLK_SPI 0x100
110
+
#define REG_DIV_CLK_I2C 0x104
111
+
#define REG_DIV_CLK_SRC_VIP_SYS_2 0x110
112
+
#define REG_DIV_CLK_AUDSRC 0x118
113
+
#define REG_DIV_CLK_PWM_SRC_0 0x120
114
+
#define REG_DIV_CLK_AP_DEBUG 0x128
115
+
#define REG_DIV_CLK_RTCSYS_SRC_0 0x12C
116
+
#define REG_DIV_CLK_C906_0_0 0x130
117
+
#define REG_DIV_CLK_C906_0_1 0x134
118
+
#define REG_DIV_CLK_C906_1_0 0x138
119
+
#define REG_DIV_CLK_C906_1_1 0x13C
120
+
#define REG_DIV_CLK_SRC_VIP_SYS_3 0x140
121
+
#define REG_DIV_CLK_SRC_VIP_SYS_4 0x144
122
+
123
+
#endif /* _CLK_SOPHGO_CV1800_H_ */
+66
drivers/clk/sophgo/clk-cv18xx-common.c
+66
drivers/clk/sophgo/clk-cv18xx-common.c
···
1
+
// SPDX-License-Identifier: GPL-2.0
2
+
/*
3
+
* Copyright (C) 2023 Inochi Amaoto <inochiama@outlook.com>
4
+
*/
5
+
6
+
#include <linux/io.h>
7
+
#include <linux/iopoll.h>
8
+
#include <linux/spinlock.h>
9
+
#include <linux/bug.h>
10
+
11
+
#include "clk-cv18xx-common.h"
12
+
13
+
int cv1800_clk_setbit(struct cv1800_clk_common *common,
14
+
struct cv1800_clk_regbit *field)
15
+
{
16
+
u32 mask = BIT(field->shift);
17
+
u32 value;
18
+
unsigned long flags;
19
+
20
+
spin_lock_irqsave(common->lock, flags);
21
+
22
+
value = readl(common->base + field->reg);
23
+
writel(value | mask, common->base + field->reg);
24
+
25
+
spin_unlock_irqrestore(common->lock, flags);
26
+
27
+
return 0;
28
+
}
29
+
30
+
int cv1800_clk_clearbit(struct cv1800_clk_common *common,
31
+
struct cv1800_clk_regbit *field)
32
+
{
33
+
u32 mask = BIT(field->shift);
34
+
u32 value;
35
+
unsigned long flags;
36
+
37
+
spin_lock_irqsave(common->lock, flags);
38
+
39
+
value = readl(common->base + field->reg);
40
+
writel(value & ~mask, common->base + field->reg);
41
+
42
+
spin_unlock_irqrestore(common->lock, flags);
43
+
44
+
return 0;
45
+
}
46
+
47
+
int cv1800_clk_checkbit(struct cv1800_clk_common *common,
48
+
struct cv1800_clk_regbit *field)
49
+
{
50
+
return readl(common->base + field->reg) & BIT(field->shift);
51
+
}
52
+
53
+
#define PLL_LOCK_TIMEOUT_US (200 * 1000)
54
+
55
+
void cv1800_clk_wait_for_lock(struct cv1800_clk_common *common,
56
+
u32 reg, u32 lock)
57
+
{
58
+
void __iomem *addr = common->base + reg;
59
+
u32 regval;
60
+
61
+
if (!lock)
62
+
return;
63
+
64
+
WARN_ON(readl_relaxed_poll_timeout(addr, regval, regval & lock,
65
+
100, PLL_LOCK_TIMEOUT_US));
66
+
}
+81
drivers/clk/sophgo/clk-cv18xx-common.h
+81
drivers/clk/sophgo/clk-cv18xx-common.h
···
1
+
/* SPDX-License-Identifier: GPL-2.0 */
2
+
/*
3
+
* Copyright (C) 2023 Inochi Amaoto <inochiama@outlook.com>
4
+
*/
5
+
6
+
#ifndef _CLK_SOPHGO_CV18XX_IP_H_
7
+
#define _CLK_SOPHGO_CV18XX_IP_H_
8
+
9
+
#include <linux/compiler.h>
10
+
#include <linux/clk-provider.h>
11
+
#include <linux/bitfield.h>
12
+
13
+
struct cv1800_clk_common {
14
+
void __iomem *base;
15
+
spinlock_t *lock;
16
+
struct clk_hw hw;
17
+
unsigned long features;
18
+
};
19
+
20
+
#define CV1800_CLK_COMMON(_name, _parents, _op, _flags) \
21
+
{ \
22
+
.hw.init = CLK_HW_INIT_PARENTS_DATA(_name, _parents, \
23
+
_op, _flags), \
24
+
}
25
+
26
+
static inline struct cv1800_clk_common *
27
+
hw_to_cv1800_clk_common(struct clk_hw *hw)
28
+
{
29
+
return container_of(hw, struct cv1800_clk_common, hw);
30
+
}
31
+
32
+
struct cv1800_clk_regbit {
33
+
u16 reg;
34
+
s8 shift;
35
+
};
36
+
37
+
struct cv1800_clk_regfield {
38
+
u16 reg;
39
+
u8 shift;
40
+
u8 width;
41
+
s16 initval;
42
+
unsigned long flags;
43
+
};
44
+
45
+
#define CV1800_CLK_BIT(_reg, _shift) \
46
+
{ \
47
+
.reg = _reg, \
48
+
.shift = _shift, \
49
+
}
50
+
51
+
#define CV1800_CLK_REG(_reg, _shift, _width, _initval, _flags) \
52
+
{ \
53
+
.reg = _reg, \
54
+
.shift = _shift, \
55
+
.width = _width, \
56
+
.initval = _initval, \
57
+
.flags = _flags, \
58
+
}
59
+
60
+
#define cv1800_clk_regfield_genmask(_reg) \
61
+
GENMASK((_reg)->shift + (_reg)->width - 1, (_reg)->shift)
62
+
#define cv1800_clk_regfield_get(_val, _reg) \
63
+
(((_val) >> (_reg)->shift) & GENMASK((_reg)->width - 1, 0))
64
+
#define cv1800_clk_regfield_set(_val, _new, _reg) \
65
+
(((_val) & ~cv1800_clk_regfield_genmask((_reg))) | \
66
+
(((_new) & GENMASK((_reg)->width - 1, 0)) << (_reg)->shift))
67
+
68
+
#define _CV1800_SET_FIELD(_reg, _val, _field) \
69
+
(((_reg) & ~(_field)) | FIELD_PREP((_field), (_val)))
70
+
71
+
int cv1800_clk_setbit(struct cv1800_clk_common *common,
72
+
struct cv1800_clk_regbit *field);
73
+
int cv1800_clk_clearbit(struct cv1800_clk_common *common,
74
+
struct cv1800_clk_regbit *field);
75
+
int cv1800_clk_checkbit(struct cv1800_clk_common *common,
76
+
struct cv1800_clk_regbit *field);
77
+
78
+
void cv1800_clk_wait_for_lock(struct cv1800_clk_common *common,
79
+
u32 reg, u32 lock);
80
+
81
+
#endif // _CLK_SOPHGO_CV18XX_IP_H_
+887
drivers/clk/sophgo/clk-cv18xx-ip.c
+887
drivers/clk/sophgo/clk-cv18xx-ip.c
···
1
+
// SPDX-License-Identifier: GPL-2.0
2
+
/*
3
+
* Copyright (C) 2023 Inochi Amaoto <inochiama@outlook.com>
4
+
*/
5
+
6
+
#include <linux/clk-provider.h>
7
+
#include <linux/io.h>
8
+
#include <linux/gcd.h>
9
+
#include <linux/spinlock.h>
10
+
11
+
#include "clk-cv18xx-ip.h"
12
+
13
+
/* GATE */
14
+
static inline struct cv1800_clk_gate *hw_to_cv1800_clk_gate(struct clk_hw *hw)
15
+
{
16
+
struct cv1800_clk_common *common = hw_to_cv1800_clk_common(hw);
17
+
18
+
return container_of(common, struct cv1800_clk_gate, common);
19
+
}
20
+
21
+
static int gate_enable(struct clk_hw *hw)
22
+
{
23
+
struct cv1800_clk_gate *gate = hw_to_cv1800_clk_gate(hw);
24
+
25
+
return cv1800_clk_setbit(&gate->common, &gate->gate);
26
+
}
27
+
28
+
static void gate_disable(struct clk_hw *hw)
29
+
{
30
+
struct cv1800_clk_gate *gate = hw_to_cv1800_clk_gate(hw);
31
+
32
+
cv1800_clk_clearbit(&gate->common, &gate->gate);
33
+
}
34
+
35
+
static int gate_is_enabled(struct clk_hw *hw)
36
+
{
37
+
struct cv1800_clk_gate *gate = hw_to_cv1800_clk_gate(hw);
38
+
39
+
return cv1800_clk_checkbit(&gate->common, &gate->gate);
40
+
}
41
+
42
+
static unsigned long gate_recalc_rate(struct clk_hw *hw,
43
+
unsigned long parent_rate)
44
+
{
45
+
return parent_rate;
46
+
}
47
+
48
+
static long gate_round_rate(struct clk_hw *hw, unsigned long rate,
49
+
unsigned long *parent_rate)
50
+
{
51
+
return *parent_rate;
52
+
}
53
+
54
+
static int gate_set_rate(struct clk_hw *hw, unsigned long rate,
55
+
unsigned long parent_rate)
56
+
{
57
+
return 0;
58
+
}
59
+
60
+
const struct clk_ops cv1800_clk_gate_ops = {
61
+
.disable = gate_disable,
62
+
.enable = gate_enable,
63
+
.is_enabled = gate_is_enabled,
64
+
65
+
.recalc_rate = gate_recalc_rate,
66
+
.round_rate = gate_round_rate,
67
+
.set_rate = gate_set_rate,
68
+
};
69
+
70
+
/* DIV */
71
+
#define _DIV_EN_CLK_DIV_FACTOR_FIELD BIT(3)
72
+
73
+
#define DIV_GET_EN_CLK_DIV_FACTOR(_reg) \
74
+
FIELD_GET(_DIV_EN_CLK_DIV_FACTOR_FIELD, _reg)
75
+
76
+
#define DIV_SET_EN_DIV_FACTOR(_reg) \
77
+
_CV1800_SET_FIELD(_reg, 1, _DIV_EN_CLK_DIV_FACTOR_FIELD)
78
+
79
+
static inline struct cv1800_clk_div *hw_to_cv1800_clk_div(struct clk_hw *hw)
80
+
{
81
+
struct cv1800_clk_common *common = hw_to_cv1800_clk_common(hw);
82
+
83
+
return container_of(common, struct cv1800_clk_div, common);
84
+
}
85
+
86
+
static int div_enable(struct clk_hw *hw)
87
+
{
88
+
struct cv1800_clk_div *div = hw_to_cv1800_clk_div(hw);
89
+
90
+
return cv1800_clk_setbit(&div->common, &div->gate);
91
+
}
92
+
93
+
static void div_disable(struct clk_hw *hw)
94
+
{
95
+
struct cv1800_clk_div *div = hw_to_cv1800_clk_div(hw);
96
+
97
+
cv1800_clk_clearbit(&div->common, &div->gate);
98
+
}
99
+
100
+
static int div_is_enabled(struct clk_hw *hw)
101
+
{
102
+
struct cv1800_clk_div *div = hw_to_cv1800_clk_div(hw);
103
+
104
+
return cv1800_clk_checkbit(&div->common, &div->gate);
105
+
}
106
+
107
+
static int div_helper_set_rate(struct cv1800_clk_common *common,
108
+
struct cv1800_clk_regfield *div,
109
+
unsigned long val)
110
+
{
111
+
unsigned long flags;
112
+
u32 reg;
113
+
114
+
if (div->width == 0)
115
+
return 0;
116
+
117
+
spin_lock_irqsave(common->lock, flags);
118
+
119
+
reg = readl(common->base + div->reg);
120
+
reg = cv1800_clk_regfield_set(reg, val, div);
121
+
if (div->initval > 0)
122
+
reg = DIV_SET_EN_DIV_FACTOR(reg);
123
+
124
+
writel(reg, common->base + div->reg);
125
+
126
+
spin_unlock_irqrestore(common->lock, flags);
127
+
128
+
return 0;
129
+
}
130
+
131
+
static u32 div_helper_get_clockdiv(struct cv1800_clk_common *common,
132
+
struct cv1800_clk_regfield *div)
133
+
{
134
+
u32 clockdiv = 1;
135
+
u32 reg;
136
+
137
+
if (!div || div->initval < 0 || (div->width == 0 && div->initval <= 0))
138
+
return 1;
139
+
140
+
if (div->width == 0 && div->initval > 0)
141
+
return div->initval;
142
+
143
+
reg = readl(common->base + div->reg);
144
+
145
+
if (div->initval == 0 || DIV_GET_EN_CLK_DIV_FACTOR(reg))
146
+
clockdiv = cv1800_clk_regfield_get(reg, div);
147
+
else if (div->initval > 0)
148
+
clockdiv = div->initval;
149
+
150
+
return clockdiv;
151
+
}
152
+
153
+
static u32 div_helper_round_rate(struct cv1800_clk_regfield *div,
154
+
struct clk_hw *hw, struct clk_hw *parent,
155
+
unsigned long rate, unsigned long *prate)
156
+
{
157
+
if (div->width == 0) {
158
+
if (div->initval <= 0)
159
+
return DIV_ROUND_UP_ULL(*prate, 1);
160
+
else
161
+
return DIV_ROUND_UP_ULL(*prate, div->initval);
162
+
}
163
+
164
+
return divider_round_rate_parent(hw, parent, rate, prate, NULL,
165
+
div->width, div->flags);
166
+
}
167
+
168
+
static long div_round_rate(struct clk_hw *parent, unsigned long *parent_rate,
169
+
unsigned long rate, int id, void *data)
170
+
{
171
+
struct cv1800_clk_div *div = data;
172
+
173
+
return div_helper_round_rate(&div->div, &div->common.hw, parent,
174
+
rate, parent_rate);
175
+
}
176
+
177
+
static bool div_is_better_rate(struct cv1800_clk_common *common,
178
+
unsigned long target, unsigned long now,
179
+
unsigned long best)
180
+
{
181
+
if (common->features & CLK_DIVIDER_ROUND_CLOSEST)
182
+
return abs_diff(target, now) < abs_diff(target, best);
183
+
184
+
return now <= target && now > best;
185
+
}
186
+
187
+
static int mux_helper_determine_rate(struct cv1800_clk_common *common,
188
+
struct clk_rate_request *req,
189
+
long (*round)(struct clk_hw *,
190
+
unsigned long *,
191
+
unsigned long,
192
+
int,
193
+
void *),
194
+
void *data)
195
+
{
196
+
unsigned long best_parent_rate = 0, best_rate = 0;
197
+
struct clk_hw *best_parent, *hw = &common->hw;
198
+
unsigned int i;
199
+
200
+
if (clk_hw_get_flags(hw) & CLK_SET_RATE_NO_REPARENT) {
201
+
unsigned long adj_parent_rate;
202
+
203
+
best_parent = clk_hw_get_parent(hw);
204
+
best_parent_rate = clk_hw_get_rate(best_parent);
205
+
206
+
best_rate = round(best_parent, &adj_parent_rate,
207
+
req->rate, -1, data);
208
+
209
+
goto find;
210
+
}
211
+
212
+
for (i = 0; i < clk_hw_get_num_parents(hw); i++) {
213
+
unsigned long tmp_rate, parent_rate;
214
+
struct clk_hw *parent;
215
+
216
+
parent = clk_hw_get_parent_by_index(hw, i);
217
+
if (!parent)
218
+
continue;
219
+
220
+
parent_rate = clk_hw_get_rate(parent);
221
+
222
+
tmp_rate = round(parent, &parent_rate, req->rate, i, data);
223
+
224
+
if (tmp_rate == req->rate) {
225
+
best_parent = parent;
226
+
best_parent_rate = parent_rate;
227
+
best_rate = tmp_rate;
228
+
goto find;
229
+
}
230
+
231
+
if (div_is_better_rate(common, req->rate,
232
+
tmp_rate, best_rate)) {
233
+
best_parent = parent;
234
+
best_parent_rate = parent_rate;
235
+
best_rate = tmp_rate;
236
+
}
237
+
}
238
+
239
+
if (best_rate == 0)
240
+
return -EINVAL;
241
+
242
+
find:
243
+
req->best_parent_hw = best_parent;
244
+
req->best_parent_rate = best_parent_rate;
245
+
req->rate = best_rate;
246
+
return 0;
247
+
}
248
+
249
+
static int div_determine_rate(struct clk_hw *hw,
250
+
struct clk_rate_request *req)
251
+
{
252
+
struct cv1800_clk_div *div = hw_to_cv1800_clk_div(hw);
253
+
254
+
return mux_helper_determine_rate(&div->common, req,
255
+
div_round_rate, div);
256
+
}
257
+
258
+
static unsigned long div_recalc_rate(struct clk_hw *hw,
259
+
unsigned long parent_rate)
260
+
{
261
+
struct cv1800_clk_div *div = hw_to_cv1800_clk_div(hw);
262
+
unsigned long val;
263
+
264
+
val = div_helper_get_clockdiv(&div->common, &div->div);
265
+
if (val == 0)
266
+
return 0;
267
+
268
+
return divider_recalc_rate(hw, parent_rate, val, NULL,
269
+
div->div.flags, div->div.width);
270
+
}
271
+
272
+
static int div_set_rate(struct clk_hw *hw, unsigned long rate,
273
+
unsigned long parent_rate)
274
+
{
275
+
struct cv1800_clk_div *div = hw_to_cv1800_clk_div(hw);
276
+
unsigned long val;
277
+
278
+
val = divider_get_val(rate, parent_rate, NULL,
279
+
div->div.width, div->div.flags);
280
+
281
+
return div_helper_set_rate(&div->common, &div->div, val);
282
+
}
283
+
284
+
const struct clk_ops cv1800_clk_div_ops = {
285
+
.disable = div_disable,
286
+
.enable = div_enable,
287
+
.is_enabled = div_is_enabled,
288
+
289
+
.determine_rate = div_determine_rate,
290
+
.recalc_rate = div_recalc_rate,
291
+
.set_rate = div_set_rate,
292
+
};
293
+
294
+
static inline struct cv1800_clk_bypass_div *
295
+
hw_to_cv1800_clk_bypass_div(struct clk_hw *hw)
296
+
{
297
+
struct cv1800_clk_div *div = hw_to_cv1800_clk_div(hw);
298
+
299
+
return container_of(div, struct cv1800_clk_bypass_div, div);
300
+
}
301
+
302
+
static long bypass_div_round_rate(struct clk_hw *parent,
303
+
unsigned long *parent_rate,
304
+
unsigned long rate, int id, void *data)
305
+
{
306
+
struct cv1800_clk_bypass_div *div = data;
307
+
308
+
if (id == -1) {
309
+
if (cv1800_clk_checkbit(&div->div.common, &div->bypass))
310
+
return *parent_rate;
311
+
else
312
+
return div_round_rate(parent, parent_rate, rate,
313
+
-1, &div->div);
314
+
}
315
+
316
+
if (id == 0)
317
+
return *parent_rate;
318
+
319
+
return div_round_rate(parent, parent_rate, rate, id - 1, &div->div);
320
+
}
321
+
322
+
static int bypass_div_determine_rate(struct clk_hw *hw,
323
+
struct clk_rate_request *req)
324
+
{
325
+
struct cv1800_clk_bypass_div *div = hw_to_cv1800_clk_bypass_div(hw);
326
+
327
+
return mux_helper_determine_rate(&div->div.common, req,
328
+
bypass_div_round_rate, div);
329
+
}
330
+
331
+
static unsigned long bypass_div_recalc_rate(struct clk_hw *hw,
332
+
unsigned long parent_rate)
333
+
{
334
+
struct cv1800_clk_bypass_div *div = hw_to_cv1800_clk_bypass_div(hw);
335
+
336
+
if (cv1800_clk_checkbit(&div->div.common, &div->bypass))
337
+
return parent_rate;
338
+
339
+
return div_recalc_rate(hw, parent_rate);
340
+
}
341
+
342
+
static int bypass_div_set_rate(struct clk_hw *hw, unsigned long rate,
343
+
unsigned long parent_rate)
344
+
{
345
+
struct cv1800_clk_bypass_div *div = hw_to_cv1800_clk_bypass_div(hw);
346
+
347
+
if (cv1800_clk_checkbit(&div->div.common, &div->bypass))
348
+
return 0;
349
+
350
+
return div_set_rate(hw, rate, parent_rate);
351
+
}
352
+
353
+
static u8 bypass_div_get_parent(struct clk_hw *hw)
354
+
{
355
+
struct cv1800_clk_bypass_div *div = hw_to_cv1800_clk_bypass_div(hw);
356
+
357
+
if (cv1800_clk_checkbit(&div->div.common, &div->bypass))
358
+
return 0;
359
+
360
+
return 1;
361
+
}
362
+
363
+
static int bypass_div_set_parent(struct clk_hw *hw, u8 index)
364
+
{
365
+
struct cv1800_clk_bypass_div *div = hw_to_cv1800_clk_bypass_div(hw);
366
+
367
+
if (index)
368
+
return cv1800_clk_clearbit(&div->div.common, &div->bypass);
369
+
370
+
return cv1800_clk_setbit(&div->div.common, &div->bypass);
371
+
}
372
+
373
+
const struct clk_ops cv1800_clk_bypass_div_ops = {
374
+
.disable = div_disable,
375
+
.enable = div_enable,
376
+
.is_enabled = div_is_enabled,
377
+
378
+
.determine_rate = bypass_div_determine_rate,
379
+
.recalc_rate = bypass_div_recalc_rate,
380
+
.set_rate = bypass_div_set_rate,
381
+
382
+
.set_parent = bypass_div_set_parent,
383
+
.get_parent = bypass_div_get_parent,
384
+
};
385
+
386
+
/* MUX */
387
+
static inline struct cv1800_clk_mux *hw_to_cv1800_clk_mux(struct clk_hw *hw)
388
+
{
389
+
struct cv1800_clk_common *common = hw_to_cv1800_clk_common(hw);
390
+
391
+
return container_of(common, struct cv1800_clk_mux, common);
392
+
}
393
+
394
+
static int mux_enable(struct clk_hw *hw)
395
+
{
396
+
struct cv1800_clk_mux *mux = hw_to_cv1800_clk_mux(hw);
397
+
398
+
return cv1800_clk_setbit(&mux->common, &mux->gate);
399
+
}
400
+
401
+
static void mux_disable(struct clk_hw *hw)
402
+
{
403
+
struct cv1800_clk_mux *mux = hw_to_cv1800_clk_mux(hw);
404
+
405
+
cv1800_clk_clearbit(&mux->common, &mux->gate);
406
+
}
407
+
408
+
static int mux_is_enabled(struct clk_hw *hw)
409
+
{
410
+
struct cv1800_clk_mux *mux = hw_to_cv1800_clk_mux(hw);
411
+
412
+
return cv1800_clk_checkbit(&mux->common, &mux->gate);
413
+
}
414
+
415
+
static long mux_round_rate(struct clk_hw *parent, unsigned long *parent_rate,
416
+
unsigned long rate, int id, void *data)
417
+
{
418
+
struct cv1800_clk_mux *mux = data;
419
+
420
+
return div_helper_round_rate(&mux->div, &mux->common.hw, parent,
421
+
rate, parent_rate);
422
+
}
423
+
424
+
static int mux_determine_rate(struct clk_hw *hw,
425
+
struct clk_rate_request *req)
426
+
{
427
+
struct cv1800_clk_mux *mux = hw_to_cv1800_clk_mux(hw);
428
+
429
+
return mux_helper_determine_rate(&mux->common, req,
430
+
mux_round_rate, mux);
431
+
}
432
+
433
+
static unsigned long mux_recalc_rate(struct clk_hw *hw,
434
+
unsigned long parent_rate)
435
+
{
436
+
struct cv1800_clk_mux *mux = hw_to_cv1800_clk_mux(hw);
437
+
unsigned long val;
438
+
439
+
val = div_helper_get_clockdiv(&mux->common, &mux->div);
440
+
if (val == 0)
441
+
return 0;
442
+
443
+
return divider_recalc_rate(hw, parent_rate, val, NULL,
444
+
mux->div.flags, mux->div.width);
445
+
}
446
+
447
+
static int mux_set_rate(struct clk_hw *hw, unsigned long rate,
448
+
unsigned long parent_rate)
449
+
{
450
+
struct cv1800_clk_mux *mux = hw_to_cv1800_clk_mux(hw);
451
+
unsigned long val;
452
+
453
+
val = divider_get_val(rate, parent_rate, NULL,
454
+
mux->div.width, mux->div.flags);
455
+
456
+
return div_helper_set_rate(&mux->common, &mux->div, val);
457
+
}
458
+
459
+
static u8 mux_get_parent(struct clk_hw *hw)
460
+
{
461
+
struct cv1800_clk_mux *mux = hw_to_cv1800_clk_mux(hw);
462
+
u32 reg = readl(mux->common.base + mux->mux.reg);
463
+
464
+
return cv1800_clk_regfield_get(reg, &mux->mux);
465
+
}
466
+
467
+
static int _mux_set_parent(struct cv1800_clk_mux *mux, u8 index)
468
+
{
469
+
u32 reg;
470
+
471
+
reg = readl(mux->common.base + mux->mux.reg);
472
+
reg = cv1800_clk_regfield_set(reg, index, &mux->mux);
473
+
writel(reg, mux->common.base + mux->mux.reg);
474
+
475
+
return 0;
476
+
}
477
+
478
+
static int mux_set_parent(struct clk_hw *hw, u8 index)
479
+
{
480
+
struct cv1800_clk_mux *mux = hw_to_cv1800_clk_mux(hw);
481
+
unsigned long flags;
482
+
483
+
spin_lock_irqsave(mux->common.lock, flags);
484
+
485
+
_mux_set_parent(mux, index);
486
+
487
+
spin_unlock_irqrestore(mux->common.lock, flags);
488
+
489
+
return 0;
490
+
}
491
+
492
+
const struct clk_ops cv1800_clk_mux_ops = {
493
+
.disable = mux_disable,
494
+
.enable = mux_enable,
495
+
.is_enabled = mux_is_enabled,
496
+
497
+
.determine_rate = mux_determine_rate,
498
+
.recalc_rate = mux_recalc_rate,
499
+
.set_rate = mux_set_rate,
500
+
501
+
.set_parent = mux_set_parent,
502
+
.get_parent = mux_get_parent,
503
+
};
504
+
505
+
static inline struct cv1800_clk_bypass_mux *
506
+
hw_to_cv1800_clk_bypass_mux(struct clk_hw *hw)
507
+
{
508
+
struct cv1800_clk_mux *mux = hw_to_cv1800_clk_mux(hw);
509
+
510
+
return container_of(mux, struct cv1800_clk_bypass_mux, mux);
511
+
}
512
+
513
+
static long bypass_mux_round_rate(struct clk_hw *parent,
514
+
unsigned long *parent_rate,
515
+
unsigned long rate, int id, void *data)
516
+
{
517
+
struct cv1800_clk_bypass_mux *mux = data;
518
+
519
+
if (id == -1) {
520
+
if (cv1800_clk_checkbit(&mux->mux.common, &mux->bypass))
521
+
return *parent_rate;
522
+
else
523
+
return mux_round_rate(parent, parent_rate, rate,
524
+
-1, &mux->mux);
525
+
}
526
+
527
+
if (id == 0)
528
+
return *parent_rate;
529
+
530
+
return mux_round_rate(parent, parent_rate, rate, id - 1, &mux->mux);
531
+
}
532
+
533
+
static int bypass_mux_determine_rate(struct clk_hw *hw,
534
+
struct clk_rate_request *req)
535
+
{
536
+
struct cv1800_clk_bypass_mux *mux = hw_to_cv1800_clk_bypass_mux(hw);
537
+
538
+
return mux_helper_determine_rate(&mux->mux.common, req,
539
+
bypass_mux_round_rate, mux);
540
+
}
541
+
542
+
static unsigned long bypass_mux_recalc_rate(struct clk_hw *hw,
543
+
unsigned long parent_rate)
544
+
{
545
+
struct cv1800_clk_bypass_mux *mux = hw_to_cv1800_clk_bypass_mux(hw);
546
+
547
+
if (cv1800_clk_checkbit(&mux->mux.common, &mux->bypass))
548
+
return parent_rate;
549
+
550
+
return mux_recalc_rate(hw, parent_rate);
551
+
}
552
+
553
+
static int bypass_mux_set_rate(struct clk_hw *hw, unsigned long rate,
554
+
unsigned long parent_rate)
555
+
{
556
+
struct cv1800_clk_bypass_mux *mux = hw_to_cv1800_clk_bypass_mux(hw);
557
+
558
+
if (cv1800_clk_checkbit(&mux->mux.common, &mux->bypass))
559
+
return 0;
560
+
561
+
return mux_set_rate(hw, rate, parent_rate);
562
+
}
563
+
564
+
static u8 bypass_mux_get_parent(struct clk_hw *hw)
565
+
{
566
+
struct cv1800_clk_bypass_mux *mux = hw_to_cv1800_clk_bypass_mux(hw);
567
+
568
+
if (cv1800_clk_checkbit(&mux->mux.common, &mux->bypass))
569
+
return 0;
570
+
571
+
return mux_get_parent(hw) + 1;
572
+
}
573
+
574
+
static int bypass_mux_set_parent(struct clk_hw *hw, u8 index)
575
+
{
576
+
struct cv1800_clk_bypass_mux *mux = hw_to_cv1800_clk_bypass_mux(hw);
577
+
578
+
if (index == 0)
579
+
return cv1800_clk_setbit(&mux->mux.common, &mux->bypass);
580
+
581
+
return cv1800_clk_clearbit(&mux->mux.common, &mux->bypass);
582
+
}
583
+
584
+
const struct clk_ops cv1800_clk_bypass_mux_ops = {
585
+
.disable = mux_disable,
586
+
.enable = mux_enable,
587
+
.is_enabled = mux_is_enabled,
588
+
589
+
.determine_rate = bypass_mux_determine_rate,
590
+
.recalc_rate = bypass_mux_recalc_rate,
591
+
.set_rate = bypass_mux_set_rate,
592
+
593
+
.set_parent = bypass_mux_set_parent,
594
+
.get_parent = bypass_mux_get_parent,
595
+
};
596
+
597
+
/* MMUX */
598
+
static inline struct cv1800_clk_mmux *hw_to_cv1800_clk_mmux(struct clk_hw *hw)
599
+
{
600
+
struct cv1800_clk_common *common = hw_to_cv1800_clk_common(hw);
601
+
602
+
return container_of(common, struct cv1800_clk_mmux, common);
603
+
}
604
+
605
+
static u8 mmux_get_parent_id(struct cv1800_clk_mmux *mmux)
606
+
{
607
+
struct clk_hw *hw = &mmux->common.hw;
608
+
struct clk_hw *parent = clk_hw_get_parent(hw);
609
+
unsigned int i;
610
+
611
+
for (i = 0; i < clk_hw_get_num_parents(hw); i++) {
612
+
if (parent == clk_hw_get_parent_by_index(hw, i))
613
+
return i;
614
+
}
615
+
616
+
unreachable();
617
+
}
618
+
619
+
static int mmux_enable(struct clk_hw *hw)
620
+
{
621
+
struct cv1800_clk_mmux *mmux = hw_to_cv1800_clk_mmux(hw);
622
+
623
+
return cv1800_clk_setbit(&mmux->common, &mmux->gate);
624
+
}
625
+
626
+
static void mmux_disable(struct clk_hw *hw)
627
+
{
628
+
struct cv1800_clk_mmux *mmux = hw_to_cv1800_clk_mmux(hw);
629
+
630
+
cv1800_clk_clearbit(&mmux->common, &mmux->gate);
631
+
}
632
+
633
+
static int mmux_is_enabled(struct clk_hw *hw)
634
+
{
635
+
struct cv1800_clk_mmux *mmux = hw_to_cv1800_clk_mmux(hw);
636
+
637
+
return cv1800_clk_checkbit(&mmux->common, &mmux->gate);
638
+
}
639
+
640
+
static long mmux_round_rate(struct clk_hw *parent, unsigned long *parent_rate,
641
+
unsigned long rate, int id, void *data)
642
+
{
643
+
struct cv1800_clk_mmux *mmux = data;
644
+
s8 div_id;
645
+
646
+
if (id == -1) {
647
+
if (cv1800_clk_checkbit(&mmux->common, &mmux->bypass))
648
+
return *parent_rate;
649
+
650
+
id = mmux_get_parent_id(mmux);
651
+
}
652
+
653
+
div_id = mmux->parent2sel[id];
654
+
655
+
if (div_id < 0)
656
+
return *parent_rate;
657
+
658
+
return div_helper_round_rate(&mmux->div[div_id],
659
+
&mmux->common.hw, parent,
660
+
rate, parent_rate);
661
+
}
662
+
663
+
static int mmux_determine_rate(struct clk_hw *hw,
664
+
struct clk_rate_request *req)
665
+
{
666
+
struct cv1800_clk_mmux *mmux = hw_to_cv1800_clk_mmux(hw);
667
+
668
+
return mux_helper_determine_rate(&mmux->common, req,
669
+
mmux_round_rate, mmux);
670
+
}
671
+
672
+
static unsigned long mmux_recalc_rate(struct clk_hw *hw,
673
+
unsigned long parent_rate)
674
+
{
675
+
struct cv1800_clk_mmux *mmux = hw_to_cv1800_clk_mmux(hw);
676
+
unsigned long val;
677
+
struct cv1800_clk_regfield *div;
678
+
679
+
if (cv1800_clk_checkbit(&mmux->common, &mmux->bypass))
680
+
return parent_rate;
681
+
682
+
if (cv1800_clk_checkbit(&mmux->common, &mmux->clk_sel))
683
+
div = &mmux->div[0];
684
+
else
685
+
div = &mmux->div[1];
686
+
687
+
val = div_helper_get_clockdiv(&mmux->common, div);
688
+
if (val == 0)
689
+
return 0;
690
+
691
+
return divider_recalc_rate(hw, parent_rate, val, NULL,
692
+
div->flags, div->width);
693
+
}
694
+
695
+
static int mmux_set_rate(struct clk_hw *hw, unsigned long rate,
696
+
unsigned long parent_rate)
697
+
{
698
+
struct cv1800_clk_mmux *mmux = hw_to_cv1800_clk_mmux(hw);
699
+
struct cv1800_clk_regfield *div;
700
+
unsigned long val;
701
+
702
+
if (cv1800_clk_checkbit(&mmux->common, &mmux->bypass))
703
+
return parent_rate;
704
+
705
+
if (cv1800_clk_checkbit(&mmux->common, &mmux->clk_sel))
706
+
div = &mmux->div[0];
707
+
else
708
+
div = &mmux->div[1];
709
+
710
+
val = divider_get_val(rate, parent_rate, NULL,
711
+
div->width, div->flags);
712
+
713
+
return div_helper_set_rate(&mmux->common, div, val);
714
+
}
715
+
716
+
static u8 mmux_get_parent(struct clk_hw *hw)
717
+
{
718
+
struct cv1800_clk_mmux *mmux = hw_to_cv1800_clk_mmux(hw);
719
+
struct cv1800_clk_regfield *mux;
720
+
u32 reg;
721
+
s8 clk_sel;
722
+
723
+
if (cv1800_clk_checkbit(&mmux->common, &mmux->bypass))
724
+
return 0;
725
+
726
+
if (cv1800_clk_checkbit(&mmux->common, &mmux->clk_sel))
727
+
clk_sel = 0;
728
+
else
729
+
clk_sel = 1;
730
+
mux = &mmux->mux[clk_sel];
731
+
732
+
reg = readl(mmux->common.base + mux->reg);
733
+
734
+
return mmux->sel2parent[clk_sel][cv1800_clk_regfield_get(reg, mux)];
735
+
}
736
+
737
+
static int mmux_set_parent(struct clk_hw *hw, u8 index)
738
+
{
739
+
struct cv1800_clk_mmux *mmux = hw_to_cv1800_clk_mmux(hw);
740
+
struct cv1800_clk_regfield *mux;
741
+
unsigned long flags;
742
+
u32 reg;
743
+
s8 clk_sel = mmux->parent2sel[index];
744
+
745
+
if (index == 0 || clk_sel == -1) {
746
+
cv1800_clk_setbit(&mmux->common, &mmux->bypass);
747
+
goto release;
748
+
}
749
+
750
+
cv1800_clk_clearbit(&mmux->common, &mmux->bypass);
751
+
752
+
if (clk_sel)
753
+
cv1800_clk_clearbit(&mmux->common, &mmux->clk_sel);
754
+
else
755
+
cv1800_clk_setbit(&mmux->common, &mmux->clk_sel);
756
+
757
+
spin_lock_irqsave(mmux->common.lock, flags);
758
+
759
+
mux = &mmux->mux[clk_sel];
760
+
reg = readl(mmux->common.base + mux->reg);
761
+
reg = cv1800_clk_regfield_set(reg, index, mux);
762
+
763
+
writel(reg, mmux->common.base + mux->reg);
764
+
765
+
spin_unlock_irqrestore(mmux->common.lock, flags);
766
+
767
+
release:
768
+
return 0;
769
+
}
770
+
771
+
const struct clk_ops cv1800_clk_mmux_ops = {
772
+
.disable = mmux_disable,
773
+
.enable = mmux_enable,
774
+
.is_enabled = mmux_is_enabled,
775
+
776
+
.determine_rate = mmux_determine_rate,
777
+
.recalc_rate = mmux_recalc_rate,
778
+
.set_rate = mmux_set_rate,
779
+
780
+
.set_parent = mmux_set_parent,
781
+
.get_parent = mmux_get_parent,
782
+
};
783
+
784
+
/* AUDIO CLK */
785
+
static inline struct cv1800_clk_audio *
786
+
hw_to_cv1800_clk_audio(struct clk_hw *hw)
787
+
{
788
+
struct cv1800_clk_common *common = hw_to_cv1800_clk_common(hw);
789
+
790
+
return container_of(common, struct cv1800_clk_audio, common);
791
+
}
792
+
793
+
static int aclk_enable(struct clk_hw *hw)
794
+
{
795
+
struct cv1800_clk_audio *aclk = hw_to_cv1800_clk_audio(hw);
796
+
797
+
cv1800_clk_setbit(&aclk->common, &aclk->src_en);
798
+
return cv1800_clk_setbit(&aclk->common, &aclk->output_en);
799
+
}
800
+
801
+
static void aclk_disable(struct clk_hw *hw)
802
+
{
803
+
struct cv1800_clk_audio *aclk = hw_to_cv1800_clk_audio(hw);
804
+
805
+
cv1800_clk_clearbit(&aclk->common, &aclk->output_en);
806
+
cv1800_clk_clearbit(&aclk->common, &aclk->src_en);
807
+
}
808
+
809
+
static int aclk_is_enabled(struct clk_hw *hw)
810
+
{
811
+
struct cv1800_clk_audio *aclk = hw_to_cv1800_clk_audio(hw);
812
+
813
+
return cv1800_clk_checkbit(&aclk->common, &aclk->output_en);
814
+
}
815
+
816
+
static int aclk_determine_rate(struct clk_hw *hw,
817
+
struct clk_rate_request *req)
818
+
{
819
+
struct cv1800_clk_audio *aclk = hw_to_cv1800_clk_audio(hw);
820
+
821
+
req->rate = aclk->target_rate;
822
+
823
+
return 0;
824
+
}
825
+
826
+
static unsigned long aclk_recalc_rate(struct clk_hw *hw,
827
+
unsigned long parent_rate)
828
+
{
829
+
struct cv1800_clk_audio *aclk = hw_to_cv1800_clk_audio(hw);
830
+
u64 rate = parent_rate;
831
+
u64 factor = 2;
832
+
u32 regval;
833
+
834
+
if (!cv1800_clk_checkbit(&aclk->common, &aclk->div_en))
835
+
return 0;
836
+
837
+
regval = readl(aclk->common.base + aclk->m.reg);
838
+
factor *= cv1800_clk_regfield_get(regval, &aclk->m);
839
+
840
+
regval = readl(aclk->common.base + aclk->n.reg);
841
+
rate *= cv1800_clk_regfield_get(regval, &aclk->n);
842
+
843
+
return DIV64_U64_ROUND_UP(rate, factor);
844
+
}
845
+
846
+
static void aclk_determine_mn(unsigned long parent_rate, unsigned long rate,
847
+
u32 *m, u32 *n)
848
+
{
849
+
u32 tm = parent_rate / 2;
850
+
u32 tn = rate;
851
+
u32 tcommon = gcd(tm, tn);
852
+
*m = tm / tcommon;
853
+
*n = tn / tcommon;
854
+
}
855
+
856
+
static int aclk_set_rate(struct clk_hw *hw, unsigned long rate,
857
+
unsigned long parent_rate)
858
+
{
859
+
struct cv1800_clk_audio *aclk = hw_to_cv1800_clk_audio(hw);
860
+
unsigned long flags;
861
+
u32 m, n;
862
+
863
+
aclk_determine_mn(parent_rate, rate,
864
+
&m, &n);
865
+
866
+
spin_lock_irqsave(aclk->common.lock, flags);
867
+
868
+
writel(m, aclk->common.base + aclk->m.reg);
869
+
writel(n, aclk->common.base + aclk->n.reg);
870
+
871
+
cv1800_clk_setbit(&aclk->common, &aclk->div_en);
872
+
cv1800_clk_setbit(&aclk->common, &aclk->div_up);
873
+
874
+
spin_unlock_irqrestore(aclk->common.lock, flags);
875
+
876
+
return 0;
877
+
}
878
+
879
+
const struct clk_ops cv1800_clk_audio_ops = {
880
+
.disable = aclk_disable,
881
+
.enable = aclk_enable,
882
+
.is_enabled = aclk_is_enabled,
883
+
884
+
.determine_rate = aclk_determine_rate,
885
+
.recalc_rate = aclk_recalc_rate,
886
+
.set_rate = aclk_set_rate,
887
+
};
+261
drivers/clk/sophgo/clk-cv18xx-ip.h
+261
drivers/clk/sophgo/clk-cv18xx-ip.h
···
1
+
/* SPDX-License-Identifier: GPL-2.0 */
2
+
/*
3
+
* Copyright (C) 2023 Inochi Amaoto <inochiama@outlook.com>
4
+
*/
5
+
6
+
#ifndef _CLK_SOPHGO_CV1800_IP_H_
7
+
#define _CLK_SOPHGO_CV1800_IP_H_
8
+
9
+
#include "clk-cv18xx-common.h"
10
+
11
+
struct cv1800_clk_gate {
12
+
struct cv1800_clk_common common;
13
+
struct cv1800_clk_regbit gate;
14
+
};
15
+
16
+
struct cv1800_clk_div_data {
17
+
u32 reg;
18
+
u32 mask;
19
+
u32 width;
20
+
u32 init;
21
+
u32 flags;
22
+
};
23
+
24
+
struct cv1800_clk_div {
25
+
struct cv1800_clk_common common;
26
+
struct cv1800_clk_regbit gate;
27
+
struct cv1800_clk_regfield div;
28
+
};
29
+
30
+
struct cv1800_clk_bypass_div {
31
+
struct cv1800_clk_div div;
32
+
struct cv1800_clk_regbit bypass;
33
+
};
34
+
35
+
struct cv1800_clk_mux {
36
+
struct cv1800_clk_common common;
37
+
struct cv1800_clk_regbit gate;
38
+
struct cv1800_clk_regfield div;
39
+
struct cv1800_clk_regfield mux;
40
+
};
41
+
42
+
struct cv1800_clk_bypass_mux {
43
+
struct cv1800_clk_mux mux;
44
+
struct cv1800_clk_regbit bypass;
45
+
};
46
+
47
+
struct cv1800_clk_mmux {
48
+
struct cv1800_clk_common common;
49
+
struct cv1800_clk_regbit gate;
50
+
struct cv1800_clk_regfield div[2];
51
+
struct cv1800_clk_regfield mux[2];
52
+
struct cv1800_clk_regbit bypass;
53
+
struct cv1800_clk_regbit clk_sel;
54
+
const s8 *parent2sel;
55
+
const u8 *sel2parent[2];
56
+
};
57
+
58
+
struct cv1800_clk_audio {
59
+
struct cv1800_clk_common common;
60
+
struct cv1800_clk_regbit src_en;
61
+
struct cv1800_clk_regbit output_en;
62
+
struct cv1800_clk_regbit div_en;
63
+
struct cv1800_clk_regbit div_up;
64
+
struct cv1800_clk_regfield m;
65
+
struct cv1800_clk_regfield n;
66
+
u32 target_rate;
67
+
};
68
+
69
+
#define CV1800_GATE(_name, _parent, _gate_reg, _gate_shift, _flags) \
70
+
struct cv1800_clk_gate _name = { \
71
+
.common = CV1800_CLK_COMMON(#_name, _parent, \
72
+
&cv1800_clk_gate_ops, \
73
+
_flags), \
74
+
.gate = CV1800_CLK_BIT(_gate_reg, _gate_shift), \
75
+
}
76
+
77
+
#define _CV1800_DIV(_name, _parent, _gate_reg, _gate_shift, \
78
+
_div_reg, _div_shift, _div_width, _div_init, \
79
+
_div_flag, _ops, _flags) \
80
+
{ \
81
+
.common = CV1800_CLK_COMMON(#_name, _parent, \
82
+
_ops, _flags), \
83
+
.gate = CV1800_CLK_BIT(_gate_reg, \
84
+
_gate_shift), \
85
+
.div = CV1800_CLK_REG(_div_reg, _div_shift, \
86
+
_div_width, _div_init, \
87
+
_div_flag), \
88
+
}
89
+
90
+
#define _CV1800_FIXED_DIV_FLAG \
91
+
(CLK_DIVIDER_ONE_BASED | CLK_DIVIDER_ROUND_CLOSEST)
92
+
93
+
#define _CV1800_FIXED_DIV(_name, _parent, _gate_reg, _gate_shift, \
94
+
_fix_div, _ops, _flags) \
95
+
{ \
96
+
.common = CV1800_CLK_COMMON(#_name, _parent, \
97
+
_ops, _flags), \
98
+
.gate = CV1800_CLK_BIT(_gate_reg, \
99
+
_gate_shift), \
100
+
.div = CV1800_CLK_REG(0, 0, 0, \
101
+
_fix_div, \
102
+
_CV1800_FIXED_DIV_FLAG),\
103
+
}
104
+
105
+
#define CV1800_DIV(_name, _parent, _gate_reg, _gate_shift, \
106
+
_div_reg, _div_shift, _div_width, _div_init, \
107
+
_div_flag, _flags) \
108
+
struct cv1800_clk_div _name = \
109
+
_CV1800_DIV(_name, _parent, _gate_reg, _gate_shift, \
110
+
_div_reg, _div_shift, _div_width, _div_init,\
111
+
_div_flag, &cv1800_clk_div_ops, _flags)
112
+
113
+
#define CV1800_BYPASS_DIV(_name, _parent, _gate_reg, _gate_shift, \
114
+
_div_reg, _div_shift, _div_width, _div_init, \
115
+
_div_flag, _bypass_reg, _bypass_shift, _flags)\
116
+
struct cv1800_clk_bypass_div _name = { \
117
+
.div = _CV1800_DIV(_name, _parent, \
118
+
_gate_reg, _gate_shift, \
119
+
_div_reg, _div_shift, \
120
+
_div_width, _div_init, _div_flag, \
121
+
&cv1800_clk_bypass_div_ops, \
122
+
_flags), \
123
+
.bypass = CV1800_CLK_BIT(_bypass_reg, _bypass_shift), \
124
+
}
125
+
126
+
#define CV1800_FIXED_DIV(_name, _parent, _gate_reg, _gate_shift, \
127
+
_fix_div, _flags) \
128
+
struct cv1800_clk_div _name = \
129
+
_CV1800_FIXED_DIV(_name, _parent, \
130
+
_gate_reg, _gate_shift, \
131
+
_fix_div, \
132
+
&cv1800_clk_div_ops, _flags) \
133
+
134
+
#define CV1800_BYPASS_FIXED_DIV(_name, _parent, _gate_reg, _gate_shift, \
135
+
_fix_div, _bypass_reg, _bypass_shift, \
136
+
_flags) \
137
+
struct cv1800_clk_bypass_div _name = { \
138
+
.div = _CV1800_FIXED_DIV(_name, _parent, \
139
+
_gate_reg, _gate_shift, \
140
+
_fix_div, \
141
+
&cv1800_clk_bypass_div_ops, \
142
+
_flags), \
143
+
.bypass = CV1800_CLK_BIT(_bypass_reg, _bypass_shift), \
144
+
}
145
+
146
+
#define _CV1800_MUX(_name, _parent, _gate_reg, _gate_shift, \
147
+
_div_reg, _div_shift, _div_width, _div_init, \
148
+
_div_flag, \
149
+
_mux_reg, _mux_shift, _mux_width, \
150
+
_ops, _flags) \
151
+
{ \
152
+
.common = CV1800_CLK_COMMON(#_name, _parent, \
153
+
_ops, _flags), \
154
+
.gate = CV1800_CLK_BIT(_gate_reg, \
155
+
_gate_shift), \
156
+
.div = CV1800_CLK_REG(_div_reg, _div_shift, \
157
+
_div_width, _div_init, \
158
+
_div_flag), \
159
+
.mux = CV1800_CLK_REG(_mux_reg, _mux_shift, \
160
+
_mux_width, 0, 0), \
161
+
}
162
+
163
+
#define CV1800_MUX(_name, _parent, _gate_reg, _gate_shift, \
164
+
_div_reg, _div_shift, _div_width, _div_init, \
165
+
_div_flag, \
166
+
_mux_reg, _mux_shift, _mux_width, _flags) \
167
+
struct cv1800_clk_mux _name = \
168
+
_CV1800_MUX(_name, _parent, _gate_reg, _gate_shift, \
169
+
_div_reg, _div_shift, _div_width, _div_init,\
170
+
_div_flag, _mux_reg, _mux_shift, _mux_width,\
171
+
&cv1800_clk_mux_ops, _flags)
172
+
173
+
#define CV1800_BYPASS_MUX(_name, _parent, _gate_reg, _gate_shift, \
174
+
_div_reg, _div_shift, _div_width, _div_init, \
175
+
_div_flag, \
176
+
_mux_reg, _mux_shift, _mux_width, \
177
+
_bypass_reg, _bypass_shift, _flags) \
178
+
struct cv1800_clk_bypass_mux _name = { \
179
+
.mux = _CV1800_MUX(_name, _parent, \
180
+
_gate_reg, _gate_shift, \
181
+
_div_reg, _div_shift, _div_width, \
182
+
_div_init, _div_flag, \
183
+
_mux_reg, _mux_shift, _mux_width, \
184
+
&cv1800_clk_bypass_mux_ops, \
185
+
_flags), \
186
+
.bypass = CV1800_CLK_BIT(_bypass_reg, _bypass_shift), \
187
+
}
188
+
189
+
#define CV1800_MMUX(_name, _parent, _gate_reg, _gate_shift, \
190
+
_div0_reg, _div0_shift, _div0_width, _div0_init, \
191
+
_div0_flag, \
192
+
_div1_reg, _div1_shift, _div1_width, _div1_init, \
193
+
_div1_flag, \
194
+
_mux0_reg, _mux0_shift, _mux0_width, \
195
+
_mux1_reg, _mux1_shift, _mux1_width, \
196
+
_bypass_reg, _bypass_shift, \
197
+
_clk_sel_reg, _clk_sel_shift, \
198
+
_parent2sel, _sel2parent0, _sel2parent1, _flags) \
199
+
struct cv1800_clk_mmux _name = { \
200
+
.common = CV1800_CLK_COMMON(#_name, _parent, \
201
+
&cv1800_clk_mmux_ops,\
202
+
_flags), \
203
+
.gate = CV1800_CLK_BIT(_gate_reg, _gate_shift),\
204
+
.div = { \
205
+
CV1800_CLK_REG(_div0_reg, _div0_shift, \
206
+
_div0_width, _div0_init, \
207
+
_div0_flag), \
208
+
CV1800_CLK_REG(_div1_reg, _div1_shift, \
209
+
_div1_width, _div1_init, \
210
+
_div1_flag), \
211
+
}, \
212
+
.mux = { \
213
+
CV1800_CLK_REG(_mux0_reg, _mux0_shift, \
214
+
_mux0_width, 0, 0), \
215
+
CV1800_CLK_REG(_mux1_reg, _mux1_shift, \
216
+
_mux1_width, 0, 0), \
217
+
}, \
218
+
.bypass = CV1800_CLK_BIT(_bypass_reg, \
219
+
_bypass_shift), \
220
+
.clk_sel = CV1800_CLK_BIT(_clk_sel_reg, \
221
+
_clk_sel_shift), \
222
+
.parent2sel = _parent2sel, \
223
+
.sel2parent = { _sel2parent0, _sel2parent1 }, \
224
+
}
225
+
226
+
#define CV1800_ACLK(_name, _parent, \
227
+
_src_en_reg, _src_en_reg_shift, \
228
+
_output_en_reg, _output_en_shift, \
229
+
_div_en_reg, _div_en_reg_shift, \
230
+
_div_up_reg, _div_up_reg_shift, \
231
+
_m_reg, _m_shift, _m_width, _m_flag, \
232
+
_n_reg, _n_shift, _n_width, _n_flag, \
233
+
_target_rate, _flags) \
234
+
struct cv1800_clk_audio _name = { \
235
+
.common = CV1800_CLK_COMMON(#_name, _parent, \
236
+
&cv1800_clk_audio_ops,\
237
+
_flags), \
238
+
.src_en = CV1800_CLK_BIT(_src_en_reg, \
239
+
_src_en_reg_shift), \
240
+
.output_en = CV1800_CLK_BIT(_output_en_reg, \
241
+
_output_en_shift), \
242
+
.div_en = CV1800_CLK_BIT(_div_en_reg, \
243
+
_div_en_reg_shift), \
244
+
.div_up = CV1800_CLK_BIT(_div_up_reg, \
245
+
_div_up_reg_shift), \
246
+
.m = CV1800_CLK_REG(_m_reg, _m_shift, \
247
+
_m_width, 0, _m_flag), \
248
+
.n = CV1800_CLK_REG(_n_reg, _n_shift, \
249
+
_n_width, 0, _n_flag), \
250
+
.target_rate = _target_rate, \
251
+
}
252
+
253
+
extern const struct clk_ops cv1800_clk_gate_ops;
254
+
extern const struct clk_ops cv1800_clk_div_ops;
255
+
extern const struct clk_ops cv1800_clk_bypass_div_ops;
256
+
extern const struct clk_ops cv1800_clk_mux_ops;
257
+
extern const struct clk_ops cv1800_clk_bypass_mux_ops;
258
+
extern const struct clk_ops cv1800_clk_mmux_ops;
259
+
extern const struct clk_ops cv1800_clk_audio_ops;
260
+
261
+
#endif // _CLK_SOPHGO_CV1800_IP_H_
+419
drivers/clk/sophgo/clk-cv18xx-pll.c
+419
drivers/clk/sophgo/clk-cv18xx-pll.c
···
1
+
// SPDX-License-Identifier: GPL-2.0
2
+
/*
3
+
* Copyright (C) 2023 Inochi Amaoto <inochiama@outlook.com>
4
+
*/
5
+
6
+
#include <linux/clk-provider.h>
7
+
#include <linux/io.h>
8
+
#include <linux/limits.h>
9
+
#include <linux/spinlock.h>
10
+
11
+
#include "clk-cv18xx-pll.h"
12
+
13
+
static inline struct cv1800_clk_pll *hw_to_cv1800_clk_pll(struct clk_hw *hw)
14
+
{
15
+
struct cv1800_clk_common *common = hw_to_cv1800_clk_common(hw);
16
+
17
+
return container_of(common, struct cv1800_clk_pll, common);
18
+
}
19
+
20
+
static unsigned long ipll_calc_rate(unsigned long parent_rate,
21
+
unsigned long pre_div_sel,
22
+
unsigned long div_sel,
23
+
unsigned long post_div_sel)
24
+
{
25
+
uint64_t rate = parent_rate;
26
+
27
+
rate *= div_sel;
28
+
do_div(rate, pre_div_sel * post_div_sel);
29
+
30
+
return rate;
31
+
}
32
+
33
+
static unsigned long ipll_recalc_rate(struct clk_hw *hw,
34
+
unsigned long parent_rate)
35
+
{
36
+
struct cv1800_clk_pll *pll = hw_to_cv1800_clk_pll(hw);
37
+
u32 value;
38
+
39
+
value = readl(pll->common.base + pll->pll_reg);
40
+
41
+
return ipll_calc_rate(parent_rate,
42
+
PLL_GET_PRE_DIV_SEL(value),
43
+
PLL_GET_DIV_SEL(value),
44
+
PLL_GET_POST_DIV_SEL(value));
45
+
}
46
+
47
+
static int ipll_find_rate(const struct cv1800_clk_pll_limit *limit,
48
+
unsigned long prate, unsigned long *rate,
49
+
u32 *value)
50
+
{
51
+
unsigned long best_rate = 0;
52
+
unsigned long trate = *rate;
53
+
unsigned long pre_div_sel = 0, div_sel = 0, post_div_sel = 0;
54
+
unsigned long pre, div, post;
55
+
u32 detected = *value;
56
+
unsigned long tmp;
57
+
58
+
for_each_pll_limit_range(pre, &limit->pre_div) {
59
+
for_each_pll_limit_range(div, &limit->div) {
60
+
for_each_pll_limit_range(post, &limit->post_div) {
61
+
tmp = ipll_calc_rate(prate, pre, div, post);
62
+
63
+
if (tmp > trate)
64
+
continue;
65
+
66
+
if ((trate - tmp) < (trate - best_rate)) {
67
+
best_rate = tmp;
68
+
pre_div_sel = pre;
69
+
div_sel = div;
70
+
post_div_sel = post;
71
+
}
72
+
}
73
+
}
74
+
}
75
+
76
+
if (best_rate) {
77
+
detected = PLL_SET_PRE_DIV_SEL(detected, pre_div_sel);
78
+
detected = PLL_SET_POST_DIV_SEL(detected, post_div_sel);
79
+
detected = PLL_SET_DIV_SEL(detected, div_sel);
80
+
*value = detected;
81
+
*rate = best_rate;
82
+
return 0;
83
+
}
84
+
85
+
return -EINVAL;
86
+
}
87
+
88
+
static int ipll_determine_rate(struct clk_hw *hw, struct clk_rate_request *req)
89
+
{
90
+
u32 val;
91
+
struct cv1800_clk_pll *pll = hw_to_cv1800_clk_pll(hw);
92
+
93
+
return ipll_find_rate(pll->pll_limit, req->best_parent_rate,
94
+
&req->rate, &val);
95
+
}
96
+
97
+
static void pll_get_mode_ctrl(unsigned long div_sel,
98
+
bool (*mode_ctrl_check)(unsigned long,
99
+
unsigned long,
100
+
unsigned long),
101
+
const struct cv1800_clk_pll_limit *limit,
102
+
u32 *value)
103
+
{
104
+
unsigned long ictrl = 0, mode = 0;
105
+
u32 detected = *value;
106
+
107
+
for_each_pll_limit_range(mode, &limit->mode) {
108
+
for_each_pll_limit_range(ictrl, &limit->ictrl) {
109
+
if (mode_ctrl_check(div_sel, ictrl, mode)) {
110
+
detected = PLL_SET_SEL_MODE(detected, mode);
111
+
detected = PLL_SET_ICTRL(detected, ictrl);
112
+
*value = detected;
113
+
return;
114
+
}
115
+
}
116
+
}
117
+
}
118
+
119
+
static bool ipll_check_mode_ctrl_restrict(unsigned long div_sel,
120
+
unsigned long ictrl,
121
+
unsigned long mode)
122
+
{
123
+
unsigned long left_rest = 20 * div_sel;
124
+
unsigned long right_rest = 35 * div_sel;
125
+
unsigned long test = 184 * (1 + mode) * (1 + ictrl) / 2;
126
+
127
+
return test > left_rest && test <= right_rest;
128
+
}
129
+
130
+
static int ipll_set_rate(struct clk_hw *hw, unsigned long rate,
131
+
unsigned long parent_rate)
132
+
{
133
+
u32 regval, detected = 0;
134
+
unsigned long flags;
135
+
struct cv1800_clk_pll *pll = hw_to_cv1800_clk_pll(hw);
136
+
137
+
ipll_find_rate(pll->pll_limit, parent_rate, &rate, &detected);
138
+
pll_get_mode_ctrl(PLL_GET_DIV_SEL(detected),
139
+
ipll_check_mode_ctrl_restrict,
140
+
pll->pll_limit, &detected);
141
+
142
+
spin_lock_irqsave(pll->common.lock, flags);
143
+
144
+
regval = readl(pll->common.base + pll->pll_reg);
145
+
regval = PLL_COPY_REG(regval, detected);
146
+
147
+
writel(regval, pll->common.base + pll->pll_reg);
148
+
149
+
spin_unlock_irqrestore(pll->common.lock, flags);
150
+
151
+
cv1800_clk_wait_for_lock(&pll->common, pll->pll_status.reg,
152
+
BIT(pll->pll_status.shift));
153
+
154
+
return 0;
155
+
}
156
+
157
+
static int pll_enable(struct clk_hw *hw)
158
+
{
159
+
struct cv1800_clk_pll *pll = hw_to_cv1800_clk_pll(hw);
160
+
161
+
return cv1800_clk_clearbit(&pll->common, &pll->pll_pwd);
162
+
}
163
+
164
+
static void pll_disable(struct clk_hw *hw)
165
+
{
166
+
struct cv1800_clk_pll *pll = hw_to_cv1800_clk_pll(hw);
167
+
168
+
cv1800_clk_setbit(&pll->common, &pll->pll_pwd);
169
+
}
170
+
171
+
static int pll_is_enable(struct clk_hw *hw)
172
+
{
173
+
struct cv1800_clk_pll *pll = hw_to_cv1800_clk_pll(hw);
174
+
175
+
return cv1800_clk_checkbit(&pll->common, &pll->pll_pwd) == 0;
176
+
}
177
+
178
+
const struct clk_ops cv1800_clk_ipll_ops = {
179
+
.disable = pll_disable,
180
+
.enable = pll_enable,
181
+
.is_enabled = pll_is_enable,
182
+
183
+
.recalc_rate = ipll_recalc_rate,
184
+
.determine_rate = ipll_determine_rate,
185
+
.set_rate = ipll_set_rate,
186
+
};
187
+
188
+
#define PLL_SYN_FACTOR_DOT_POS 26
189
+
#define PLL_SYN_FACTOR_MINIMUM ((4 << PLL_SYN_FACTOR_DOT_POS) + 1)
190
+
191
+
static bool fpll_is_factional_mode(struct cv1800_clk_pll *pll)
192
+
{
193
+
return cv1800_clk_checkbit(&pll->common, &pll->pll_syn->en);
194
+
}
195
+
196
+
static unsigned long fpll_calc_rate(unsigned long parent_rate,
197
+
unsigned long pre_div_sel,
198
+
unsigned long div_sel,
199
+
unsigned long post_div_sel,
200
+
unsigned long ssc_syn_set,
201
+
bool is_full_parent)
202
+
{
203
+
u64 dividend = parent_rate * div_sel;
204
+
u64 factor = ssc_syn_set * pre_div_sel * post_div_sel;
205
+
unsigned long rate;
206
+
207
+
dividend <<= PLL_SYN_FACTOR_DOT_POS - 1;
208
+
rate = div64_u64_rem(dividend, factor, ÷nd);
209
+
210
+
if (is_full_parent) {
211
+
dividend <<= 1;
212
+
rate <<= 1;
213
+
}
214
+
215
+
rate += DIV64_U64_ROUND_CLOSEST(dividend, factor);
216
+
217
+
return rate;
218
+
}
219
+
220
+
static unsigned long fpll_recalc_rate(struct clk_hw *hw,
221
+
unsigned long parent_rate)
222
+
{
223
+
struct cv1800_clk_pll *pll = hw_to_cv1800_clk_pll(hw);
224
+
u32 value;
225
+
bool clk_full;
226
+
u32 syn_set;
227
+
228
+
if (!fpll_is_factional_mode(pll))
229
+
return ipll_recalc_rate(hw, parent_rate);
230
+
231
+
syn_set = readl(pll->common.base + pll->pll_syn->set);
232
+
233
+
if (syn_set == 0)
234
+
return 0;
235
+
236
+
clk_full = cv1800_clk_checkbit(&pll->common,
237
+
&pll->pll_syn->clk_half);
238
+
239
+
value = readl(pll->common.base + pll->pll_reg);
240
+
241
+
return fpll_calc_rate(parent_rate,
242
+
PLL_GET_PRE_DIV_SEL(value),
243
+
PLL_GET_DIV_SEL(value),
244
+
PLL_GET_POST_DIV_SEL(value),
245
+
syn_set, clk_full);
246
+
}
247
+
248
+
static unsigned long fpll_find_synthesizer(unsigned long parent,
249
+
unsigned long rate,
250
+
unsigned long pre_div,
251
+
unsigned long div,
252
+
unsigned long post_div,
253
+
bool is_full_parent,
254
+
u32 *ssc_syn_set)
255
+
{
256
+
u32 test_max = U32_MAX, test_min = PLL_SYN_FACTOR_MINIMUM;
257
+
unsigned long trate;
258
+
259
+
while (test_min < test_max) {
260
+
u32 tssc = (test_max + test_min) / 2;
261
+
262
+
trate = fpll_calc_rate(parent, pre_div, div, post_div,
263
+
tssc, is_full_parent);
264
+
265
+
if (trate == rate) {
266
+
test_min = tssc;
267
+
break;
268
+
}
269
+
270
+
if (trate > rate)
271
+
test_min = tssc + 1;
272
+
else
273
+
test_max = tssc - 1;
274
+
}
275
+
276
+
if (trate != 0)
277
+
*ssc_syn_set = test_min;
278
+
279
+
return trate;
280
+
}
281
+
282
+
static int fpll_find_rate(struct cv1800_clk_pll *pll,
283
+
const struct cv1800_clk_pll_limit *limit,
284
+
unsigned long prate,
285
+
unsigned long *rate,
286
+
u32 *value, u32 *ssc_syn_set)
287
+
{
288
+
unsigned long best_rate = 0;
289
+
unsigned long pre_div_sel = 0, div_sel = 0, post_div_sel = 0;
290
+
unsigned long pre, div, post;
291
+
unsigned long trate = *rate;
292
+
u32 detected = *value;
293
+
unsigned long tmp;
294
+
bool clk_full = cv1800_clk_checkbit(&pll->common,
295
+
&pll->pll_syn->clk_half);
296
+
297
+
for_each_pll_limit_range(pre, &limit->pre_div) {
298
+
for_each_pll_limit_range(post, &limit->post_div) {
299
+
for_each_pll_limit_range(div, &limit->div) {
300
+
tmp = fpll_find_synthesizer(prate, trate,
301
+
pre, div, post,
302
+
clk_full,
303
+
ssc_syn_set);
304
+
305
+
if ((trate - tmp) < (trate - best_rate)) {
306
+
best_rate = tmp;
307
+
pre_div_sel = pre;
308
+
div_sel = div;
309
+
post_div_sel = post;
310
+
}
311
+
}
312
+
}
313
+
}
314
+
315
+
if (best_rate) {
316
+
detected = PLL_SET_PRE_DIV_SEL(detected, pre_div_sel);
317
+
detected = PLL_SET_POST_DIV_SEL(detected, post_div_sel);
318
+
detected = PLL_SET_DIV_SEL(detected, div_sel);
319
+
*value = detected;
320
+
*rate = best_rate;
321
+
return 0;
322
+
}
323
+
324
+
return -EINVAL;
325
+
}
326
+
327
+
static int fpll_determine_rate(struct clk_hw *hw, struct clk_rate_request *req)
328
+
{
329
+
struct cv1800_clk_pll *pll = hw_to_cv1800_clk_pll(hw);
330
+
u32 val, ssc_syn_set;
331
+
332
+
if (!fpll_is_factional_mode(pll))
333
+
return ipll_determine_rate(hw, req);
334
+
335
+
fpll_find_rate(pll, &pll->pll_limit[2], req->best_parent_rate,
336
+
&req->rate, &val, &ssc_syn_set);
337
+
338
+
return 0;
339
+
}
340
+
341
+
static bool fpll_check_mode_ctrl_restrict(unsigned long div_sel,
342
+
unsigned long ictrl,
343
+
unsigned long mode)
344
+
{
345
+
unsigned long left_rest = 10 * div_sel;
346
+
unsigned long right_rest = 24 * div_sel;
347
+
unsigned long test = 184 * (1 + mode) * (1 + ictrl) / 2;
348
+
349
+
return test > left_rest && test <= right_rest;
350
+
}
351
+
352
+
static int fpll_set_rate(struct clk_hw *hw, unsigned long rate,
353
+
unsigned long parent_rate)
354
+
{
355
+
u32 regval;
356
+
u32 detected = 0, detected_ssc = 0;
357
+
unsigned long flags;
358
+
struct cv1800_clk_pll *pll = hw_to_cv1800_clk_pll(hw);
359
+
360
+
if (!fpll_is_factional_mode(pll))
361
+
return ipll_set_rate(hw, rate, parent_rate);
362
+
363
+
fpll_find_rate(pll, &pll->pll_limit[2], parent_rate,
364
+
&rate, &detected, &detected_ssc);
365
+
pll_get_mode_ctrl(PLL_GET_DIV_SEL(detected),
366
+
fpll_check_mode_ctrl_restrict,
367
+
pll->pll_limit, &detected);
368
+
369
+
spin_lock_irqsave(pll->common.lock, flags);
370
+
371
+
writel(detected_ssc, pll->common.base + pll->pll_syn->set);
372
+
373
+
regval = readl(pll->common.base + pll->pll_reg);
374
+
regval = PLL_COPY_REG(regval, detected);
375
+
376
+
writel(regval, pll->common.base + pll->pll_reg);
377
+
378
+
spin_unlock_irqrestore(pll->common.lock, flags);
379
+
380
+
cv1800_clk_wait_for_lock(&pll->common, pll->pll_status.reg,
381
+
BIT(pll->pll_status.shift));
382
+
383
+
return 0;
384
+
}
385
+
386
+
static u8 fpll_get_parent(struct clk_hw *hw)
387
+
{
388
+
struct cv1800_clk_pll *pll = hw_to_cv1800_clk_pll(hw);
389
+
390
+
if (fpll_is_factional_mode(pll))
391
+
return 1;
392
+
393
+
return 0;
394
+
}
395
+
396
+
static int fpll_set_parent(struct clk_hw *hw, u8 index)
397
+
{
398
+
struct cv1800_clk_pll *pll = hw_to_cv1800_clk_pll(hw);
399
+
400
+
if (index)
401
+
cv1800_clk_setbit(&pll->common, &pll->pll_syn->en);
402
+
else
403
+
cv1800_clk_clearbit(&pll->common, &pll->pll_syn->en);
404
+
405
+
return 0;
406
+
}
407
+
408
+
const struct clk_ops cv1800_clk_fpll_ops = {
409
+
.disable = pll_disable,
410
+
.enable = pll_enable,
411
+
.is_enabled = pll_is_enable,
412
+
413
+
.recalc_rate = fpll_recalc_rate,
414
+
.determine_rate = fpll_determine_rate,
415
+
.set_rate = fpll_set_rate,
416
+
417
+
.set_parent = fpll_set_parent,
418
+
.get_parent = fpll_get_parent,
419
+
};
+118
drivers/clk/sophgo/clk-cv18xx-pll.h
+118
drivers/clk/sophgo/clk-cv18xx-pll.h
···
1
+
/* SPDX-License-Identifier: GPL-2.0 */
2
+
/*
3
+
* Copyright (C) 2023 Inochi Amaoto <inochiama@outlook.com>
4
+
*/
5
+
6
+
#ifndef _CLK_SOPHGO_CV1800_PLL_H_
7
+
#define _CLK_SOPHGO_CV1800_PLL_H_
8
+
9
+
#include "clk-cv18xx-common.h"
10
+
11
+
struct cv1800_clk_pll_limit {
12
+
struct {
13
+
u8 min;
14
+
u8 max;
15
+
} pre_div, div, post_div, ictrl, mode;
16
+
};
17
+
18
+
#define _CV1800_PLL_LIMIT(_min, _max) \
19
+
{ \
20
+
.min = _min, \
21
+
.max = _max, \
22
+
} \
23
+
24
+
#define for_each_pll_limit_range(_var, _restrict) \
25
+
for (_var = (_restrict)->min; _var <= (_restrict)->max; _var++)
26
+
27
+
struct cv1800_clk_pll_synthesizer {
28
+
struct cv1800_clk_regbit en;
29
+
struct cv1800_clk_regbit clk_half;
30
+
u32 ctrl;
31
+
u32 set;
32
+
};
33
+
34
+
#define _PLL_PRE_DIV_SEL_FIELD GENMASK(6, 0)
35
+
#define _PLL_POST_DIV_SEL_FIELD GENMASK(14, 8)
36
+
#define _PLL_SEL_MODE_FIELD GENMASK(16, 15)
37
+
#define _PLL_DIV_SEL_FIELD GENMASK(23, 17)
38
+
#define _PLL_ICTRL_FIELD GENMASK(26, 24)
39
+
40
+
#define _PLL_ALL_FIELD_MASK \
41
+
(_PLL_PRE_DIV_SEL_FIELD | \
42
+
_PLL_POST_DIV_SEL_FIELD | \
43
+
_PLL_SEL_MODE_FIELD | \
44
+
_PLL_DIV_SEL_FIELD | \
45
+
_PLL_ICTRL_FIELD)
46
+
47
+
#define PLL_COPY_REG(_dest, _src) \
48
+
(((_dest) & (~_PLL_ALL_FIELD_MASK)) | ((_src) & _PLL_ALL_FIELD_MASK))
49
+
50
+
#define PLL_GET_PRE_DIV_SEL(_reg) \
51
+
FIELD_GET(_PLL_PRE_DIV_SEL_FIELD, (_reg))
52
+
#define PLL_GET_POST_DIV_SEL(_reg) \
53
+
FIELD_GET(_PLL_POST_DIV_SEL_FIELD, (_reg))
54
+
#define PLL_GET_SEL_MODE(_reg) \
55
+
FIELD_GET(_PLL_SEL_MODE_FIELD, (_reg))
56
+
#define PLL_GET_DIV_SEL(_reg) \
57
+
FIELD_GET(_PLL_DIV_SEL_FIELD, (_reg))
58
+
#define PLL_GET_ICTRL(_reg) \
59
+
FIELD_GET(_PLL_ICTRL_FIELD, (_reg))
60
+
61
+
#define PLL_SET_PRE_DIV_SEL(_reg, _val) \
62
+
_CV1800_SET_FIELD((_reg), (_val), _PLL_PRE_DIV_SEL_FIELD)
63
+
#define PLL_SET_POST_DIV_SEL(_reg, _val) \
64
+
_CV1800_SET_FIELD((_reg), (_val), _PLL_POST_DIV_SEL_FIELD)
65
+
#define PLL_SET_SEL_MODE(_reg, _val) \
66
+
_CV1800_SET_FIELD((_reg), (_val), _PLL_SEL_MODE_FIELD)
67
+
#define PLL_SET_DIV_SEL(_reg, _val) \
68
+
_CV1800_SET_FIELD((_reg), (_val), _PLL_DIV_SEL_FIELD)
69
+
#define PLL_SET_ICTRL(_reg, _val) \
70
+
_CV1800_SET_FIELD((_reg), (_val), _PLL_ICTRL_FIELD)
71
+
72
+
struct cv1800_clk_pll {
73
+
struct cv1800_clk_common common;
74
+
u32 pll_reg;
75
+
struct cv1800_clk_regbit pll_pwd;
76
+
struct cv1800_clk_regbit pll_status;
77
+
const struct cv1800_clk_pll_limit *pll_limit;
78
+
struct cv1800_clk_pll_synthesizer *pll_syn;
79
+
};
80
+
81
+
#define CV1800_INTEGRAL_PLL(_name, _parent, _pll_reg, \
82
+
_pll_pwd_reg, _pll_pwd_shift, \
83
+
_pll_status_reg, _pll_status_shift, \
84
+
_pll_limit, _flags) \
85
+
struct cv1800_clk_pll _name = { \
86
+
.common = CV1800_CLK_COMMON(#_name, _parent, \
87
+
&cv1800_clk_ipll_ops,\
88
+
_flags), \
89
+
.pll_reg = _pll_reg, \
90
+
.pll_pwd = CV1800_CLK_BIT(_pll_pwd_reg, \
91
+
_pll_pwd_shift), \
92
+
.pll_status = CV1800_CLK_BIT(_pll_status_reg, \
93
+
_pll_status_shift), \
94
+
.pll_limit = _pll_limit, \
95
+
.pll_syn = NULL, \
96
+
}
97
+
98
+
#define CV1800_FACTIONAL_PLL(_name, _parent, _pll_reg, \
99
+
_pll_pwd_reg, _pll_pwd_shift, \
100
+
_pll_status_reg, _pll_status_shift, \
101
+
_pll_limit, _pll_syn, _flags) \
102
+
struct cv1800_clk_pll _name = { \
103
+
.common = CV1800_CLK_COMMON(#_name, _parent, \
104
+
&cv1800_clk_fpll_ops,\
105
+
_flags), \
106
+
.pll_reg = _pll_reg, \
107
+
.pll_pwd = CV1800_CLK_BIT(_pll_pwd_reg, \
108
+
_pll_pwd_shift), \
109
+
.pll_status = CV1800_CLK_BIT(_pll_status_reg, \
110
+
_pll_status_shift), \
111
+
.pll_limit = _pll_limit, \
112
+
.pll_syn = _pll_syn, \
113
+
}
114
+
115
+
extern const struct clk_ops cv1800_clk_ipll_ops;
116
+
extern const struct clk_ops cv1800_clk_fpll_ops;
117
+
118
+
#endif // _CLK_SOPHGO_CV1800_PLL_H_
+7
drivers/clk/stm32/Kconfig
+7
drivers/clk/stm32/Kconfig
+1
drivers/clk/stm32/Makefile
+1
drivers/clk/stm32/Makefile
+5
-6
drivers/clk/stm32/clk-stm32-core.c
+5
-6
drivers/clk/stm32/clk-stm32-core.c
···
25
25
{
26
26
const struct stm32_rcc_match_data *data = match->data;
27
27
struct clk_hw_onecell_data *clk_data = data->hw_clks;
28
-
struct device_node *np = dev_of_node(dev);
29
28
struct clk_hw **hws;
30
29
int n, max_binding;
31
30
···
63
64
hws[cfg_clock->id] = hw;
64
65
}
65
66
66
-
return of_clk_add_hw_provider(np, of_clk_hw_onecell_get, clk_data);
67
+
return devm_of_clk_add_hw_provider(dev, of_clk_hw_onecell_get, clk_data);
67
68
}
68
69
69
70
int stm32_rcc_init(struct device *dev, const struct of_device_id *match_data,
···
637
638
mux->lock = lock;
638
639
mux->clock_data = data->clock_data;
639
640
640
-
err = clk_hw_register(dev, hw);
641
+
err = devm_clk_hw_register(dev, hw);
641
642
if (err)
642
643
return ERR_PTR(err);
643
644
···
658
659
gate->lock = lock;
659
660
gate->clock_data = data->clock_data;
660
661
661
-
err = clk_hw_register(dev, hw);
662
+
err = devm_clk_hw_register(dev, hw);
662
663
if (err)
663
664
return ERR_PTR(err);
664
665
···
679
680
div->lock = lock;
680
681
div->clock_data = data->clock_data;
681
682
682
-
err = clk_hw_register(dev, hw);
683
+
err = devm_clk_hw_register(dev, hw);
683
684
if (err)
684
685
return ERR_PTR(err);
685
686
···
700
701
composite->lock = lock;
701
702
composite->clock_data = data->clock_data;
702
703
703
-
err = clk_hw_register(dev, hw);
704
+
err = devm_clk_hw_register(dev, hw);
704
705
if (err)
705
706
return ERR_PTR(err);
706
707
+5
-67
drivers/clk/stm32/clk-stm32mp13.c
+5
-67
drivers/clk/stm32/clk-stm32mp13.c
···
1536
1536
};
1537
1537
MODULE_DEVICE_TABLE(of, stm32mp13_match_data);
1538
1538
1539
-
static int stm32mp1_rcc_init(struct device *dev)
1540
-
{
1541
-
void __iomem *rcc_base;
1542
-
int ret = -ENOMEM;
1543
-
1544
-
rcc_base = of_iomap(dev_of_node(dev), 0);
1545
-
if (!rcc_base) {
1546
-
dev_err(dev, "%pOFn: unable to map resource", dev_of_node(dev));
1547
-
goto out;
1548
-
}
1549
-
1550
-
ret = stm32_rcc_init(dev, stm32mp13_match_data, rcc_base);
1551
-
out:
1552
-
if (ret) {
1553
-
if (rcc_base)
1554
-
iounmap(rcc_base);
1555
-
1556
-
of_node_put(dev_of_node(dev));
1557
-
}
1558
-
1559
-
return ret;
1560
-
}
1561
-
1562
-
static int get_clock_deps(struct device *dev)
1563
-
{
1564
-
static const char * const clock_deps_name[] = {
1565
-
"hsi", "hse", "csi", "lsi", "lse",
1566
-
};
1567
-
size_t deps_size = sizeof(struct clk *) * ARRAY_SIZE(clock_deps_name);
1568
-
struct clk **clk_deps;
1569
-
int i;
1570
-
1571
-
clk_deps = devm_kzalloc(dev, deps_size, GFP_KERNEL);
1572
-
if (!clk_deps)
1573
-
return -ENOMEM;
1574
-
1575
-
for (i = 0; i < ARRAY_SIZE(clock_deps_name); i++) {
1576
-
struct clk *clk = of_clk_get_by_name(dev_of_node(dev),
1577
-
clock_deps_name[i]);
1578
-
1579
-
if (IS_ERR(clk)) {
1580
-
if (PTR_ERR(clk) != -EINVAL && PTR_ERR(clk) != -ENOENT)
1581
-
return PTR_ERR(clk);
1582
-
} else {
1583
-
/* Device gets a reference count on the clock */
1584
-
clk_deps[i] = devm_clk_get(dev, __clk_get_name(clk));
1585
-
clk_put(clk);
1586
-
}
1587
-
}
1588
-
1589
-
return 0;
1590
-
}
1591
-
1592
1539
static int stm32mp1_rcc_clocks_probe(struct platform_device *pdev)
1593
1540
{
1594
1541
struct device *dev = &pdev->dev;
1595
-
int ret = get_clock_deps(dev);
1542
+
void __iomem *base;
1596
1543
1597
-
if (!ret)
1598
-
ret = stm32mp1_rcc_init(dev);
1544
+
base = devm_platform_ioremap_resource(pdev, 0);
1545
+
if (WARN_ON(IS_ERR(base)))
1546
+
return PTR_ERR(base);
1599
1547
1600
-
return ret;
1601
-
}
1602
-
1603
-
static void stm32mp1_rcc_clocks_remove(struct platform_device *pdev)
1604
-
{
1605
-
struct device *dev = &pdev->dev;
1606
-
struct device_node *child, *np = dev_of_node(dev);
1607
-
1608
-
for_each_available_child_of_node(np, child)
1609
-
of_clk_del_provider(child);
1548
+
return stm32_rcc_init(dev, stm32mp13_match_data, base);
1610
1549
}
1611
1550
1612
1551
static struct platform_driver stm32mp13_rcc_clocks_driver = {
···
1554
1615
.of_match_table = stm32mp13_match_data,
1555
1616
},
1556
1617
.probe = stm32mp1_rcc_clocks_probe,
1557
-
.remove_new = stm32mp1_rcc_clocks_remove,
1558
1618
};
1559
1619
1560
1620
static int __init stm32mp13_clocks_init(void)
+1875
drivers/clk/stm32/clk-stm32mp25.c
+1875
drivers/clk/stm32/clk-stm32mp25.c
···
1
+
// SPDX-License-Identifier: GPL-2.0-only
2
+
/*
3
+
* Copyright (C) STMicroelectronics 2023 - All Rights Reserved
4
+
* Author: Gabriel Fernandez <gabriel.fernandez@foss.st.com> for STMicroelectronics.
5
+
*/
6
+
7
+
#include <linux/clk-provider.h>
8
+
#include <linux/platform_device.h>
9
+
10
+
#include "clk-stm32-core.h"
11
+
#include "reset-stm32.h"
12
+
#include "stm32mp25_rcc.h"
13
+
14
+
#include <dt-bindings/clock/st,stm32mp25-rcc.h>
15
+
#include <dt-bindings/reset/st,stm32mp25-rcc.h>
16
+
17
+
enum {
18
+
HSE,
19
+
HSI,
20
+
MSI,
21
+
LSE,
22
+
LSI,
23
+
HSE_DIV2,
24
+
ICN_HS_MCU,
25
+
ICN_LS_MCU,
26
+
ICN_SDMMC,
27
+
ICN_DDR,
28
+
ICN_DISPLAY,
29
+
ICN_HSL,
30
+
ICN_NIC,
31
+
ICN_VID,
32
+
FLEXGEN_07,
33
+
FLEXGEN_08,
34
+
FLEXGEN_09,
35
+
FLEXGEN_10,
36
+
FLEXGEN_11,
37
+
FLEXGEN_12,
38
+
FLEXGEN_13,
39
+
FLEXGEN_14,
40
+
FLEXGEN_15,
41
+
FLEXGEN_16,
42
+
FLEXGEN_17,
43
+
FLEXGEN_18,
44
+
FLEXGEN_19,
45
+
FLEXGEN_20,
46
+
FLEXGEN_21,
47
+
FLEXGEN_22,
48
+
FLEXGEN_23,
49
+
FLEXGEN_24,
50
+
FLEXGEN_25,
51
+
FLEXGEN_26,
52
+
FLEXGEN_27,
53
+
FLEXGEN_28,
54
+
FLEXGEN_29,
55
+
FLEXGEN_30,
56
+
FLEXGEN_31,
57
+
FLEXGEN_32,
58
+
FLEXGEN_33,
59
+
FLEXGEN_34,
60
+
FLEXGEN_35,
61
+
FLEXGEN_36,
62
+
FLEXGEN_37,
63
+
FLEXGEN_38,
64
+
FLEXGEN_39,
65
+
FLEXGEN_40,
66
+
FLEXGEN_41,
67
+
FLEXGEN_42,
68
+
FLEXGEN_43,
69
+
FLEXGEN_44,
70
+
FLEXGEN_45,
71
+
FLEXGEN_46,
72
+
FLEXGEN_47,
73
+
FLEXGEN_48,
74
+
FLEXGEN_49,
75
+
FLEXGEN_50,
76
+
FLEXGEN_51,
77
+
FLEXGEN_52,
78
+
FLEXGEN_53,
79
+
FLEXGEN_54,
80
+
FLEXGEN_55,
81
+
FLEXGEN_56,
82
+
FLEXGEN_57,
83
+
FLEXGEN_58,
84
+
FLEXGEN_59,
85
+
FLEXGEN_60,
86
+
FLEXGEN_61,
87
+
FLEXGEN_62,
88
+
FLEXGEN_63,
89
+
ICN_APB1,
90
+
ICN_APB2,
91
+
ICN_APB3,
92
+
ICN_APB4,
93
+
ICN_APBDBG,
94
+
TIMG1,
95
+
TIMG2,
96
+
PLL3,
97
+
DSI_TXBYTE,
98
+
};
99
+
100
+
static const struct clk_parent_data adc12_src[] = {
101
+
{ .index = FLEXGEN_46 },
102
+
{ .index = ICN_LS_MCU },
103
+
};
104
+
105
+
static const struct clk_parent_data adc3_src[] = {
106
+
{ .index = FLEXGEN_47 },
107
+
{ .index = ICN_LS_MCU },
108
+
{ .index = FLEXGEN_46 },
109
+
};
110
+
111
+
static const struct clk_parent_data usb2phy1_src[] = {
112
+
{ .index = FLEXGEN_57 },
113
+
{ .index = HSE_DIV2 },
114
+
};
115
+
116
+
static const struct clk_parent_data usb2phy2_src[] = {
117
+
{ .index = FLEXGEN_58 },
118
+
{ .index = HSE_DIV2 },
119
+
};
120
+
121
+
static const struct clk_parent_data usb3pciphy_src[] = {
122
+
{ .index = FLEXGEN_34 },
123
+
{ .index = HSE_DIV2 },
124
+
};
125
+
126
+
static struct clk_stm32_gate ck_ker_ltdc;
127
+
128
+
static const struct clk_parent_data dsiblane_src[] = {
129
+
{ .index = DSI_TXBYTE },
130
+
{ .hw = &ck_ker_ltdc.hw },
131
+
};
132
+
133
+
static const struct clk_parent_data dsiphy_src[] = {
134
+
{ .index = FLEXGEN_28 },
135
+
{ .index = HSE },
136
+
};
137
+
138
+
static const struct clk_parent_data lvdsphy_src[] = {
139
+
{ .index = FLEXGEN_32 },
140
+
{ .index = HSE },
141
+
};
142
+
143
+
static const struct clk_parent_data dts_src[] = {
144
+
{ .index = HSI },
145
+
{ .index = HSE },
146
+
{ .index = MSI },
147
+
};
148
+
149
+
static const struct clk_parent_data mco1_src[] = {
150
+
{ .index = FLEXGEN_61 },
151
+
};
152
+
153
+
static const struct clk_parent_data mco2_src[] = {
154
+
{ .index = FLEXGEN_62 },
155
+
};
156
+
157
+
enum enum_mux_cfg {
158
+
MUX_ADC12,
159
+
MUX_ADC3,
160
+
MUX_DSIBLANE,
161
+
MUX_DSIPHY,
162
+
MUX_DTS,
163
+
MUX_LVDSPHY,
164
+
MUX_MCO1,
165
+
MUX_MCO2,
166
+
MUX_USB2PHY1,
167
+
MUX_USB2PHY2,
168
+
MUX_USB3PCIEPHY,
169
+
MUX_NB
170
+
};
171
+
172
+
#define MUX_CFG(id, _offset, _shift, _witdh) \
173
+
[id] = { \
174
+
.offset = (_offset), \
175
+
.shift = (_shift), \
176
+
.width = (_witdh), \
177
+
}
178
+
179
+
static const struct stm32_mux_cfg stm32mp25_muxes[MUX_NB] = {
180
+
MUX_CFG(MUX_ADC12, RCC_ADC12CFGR, 12, 1),
181
+
MUX_CFG(MUX_ADC3, RCC_ADC3CFGR, 12, 2),
182
+
MUX_CFG(MUX_DSIBLANE, RCC_DSICFGR, 12, 1),
183
+
MUX_CFG(MUX_DSIPHY, RCC_DSICFGR, 15, 1),
184
+
MUX_CFG(MUX_DTS, RCC_DTSCFGR, 12, 2),
185
+
MUX_CFG(MUX_LVDSPHY, RCC_LVDSCFGR, 15, 1),
186
+
MUX_CFG(MUX_MCO1, RCC_MCO1CFGR, 0, 1),
187
+
MUX_CFG(MUX_MCO2, RCC_MCO2CFGR, 0, 1),
188
+
MUX_CFG(MUX_USB2PHY1, RCC_USB2PHY1CFGR, 15, 1),
189
+
MUX_CFG(MUX_USB2PHY2, RCC_USB2PHY2CFGR, 15, 1),
190
+
MUX_CFG(MUX_USB3PCIEPHY, RCC_USB3PCIEPHYCFGR, 15, 1),
191
+
};
192
+
193
+
enum enum_gate_cfg {
194
+
GATE_ADC12,
195
+
GATE_ADC3,
196
+
GATE_ADF1,
197
+
GATE_CCI,
198
+
GATE_CRC,
199
+
GATE_CRYP1,
200
+
GATE_CRYP2,
201
+
GATE_CSI,
202
+
GATE_DCMIPP,
203
+
GATE_DSI,
204
+
GATE_DTS,
205
+
GATE_ETH1,
206
+
GATE_ETH1MAC,
207
+
GATE_ETH1RX,
208
+
GATE_ETH1STP,
209
+
GATE_ETH1TX,
210
+
GATE_ETH2,
211
+
GATE_ETH2MAC,
212
+
GATE_ETH2RX,
213
+
GATE_ETH2STP,
214
+
GATE_ETH2TX,
215
+
GATE_ETHSW,
216
+
GATE_ETHSWACMCFG,
217
+
GATE_ETHSWACMMSG,
218
+
GATE_ETHSWMAC,
219
+
GATE_ETHSWREF,
220
+
GATE_FDCAN,
221
+
GATE_GPU,
222
+
GATE_HASH,
223
+
GATE_HDP,
224
+
GATE_I2C1,
225
+
GATE_I2C2,
226
+
GATE_I2C3,
227
+
GATE_I2C4,
228
+
GATE_I2C5,
229
+
GATE_I2C6,
230
+
GATE_I2C7,
231
+
GATE_I2C8,
232
+
GATE_I3C1,
233
+
GATE_I3C2,
234
+
GATE_I3C3,
235
+
GATE_I3C4,
236
+
GATE_IS2M,
237
+
GATE_IWDG1,
238
+
GATE_IWDG2,
239
+
GATE_IWDG3,
240
+
GATE_IWDG4,
241
+
GATE_IWDG5,
242
+
GATE_LPTIM1,
243
+
GATE_LPTIM2,
244
+
GATE_LPTIM3,
245
+
GATE_LPTIM4,
246
+
GATE_LPTIM5,
247
+
GATE_LPUART1,
248
+
GATE_LTDC,
249
+
GATE_LVDS,
250
+
GATE_MCO1,
251
+
GATE_MCO2,
252
+
GATE_MDF1,
253
+
GATE_OSPIIOM,
254
+
GATE_PCIE,
255
+
GATE_PKA,
256
+
GATE_RNG,
257
+
GATE_SAES,
258
+
GATE_SAI1,
259
+
GATE_SAI2,
260
+
GATE_SAI3,
261
+
GATE_SAI4,
262
+
GATE_SDMMC1,
263
+
GATE_SDMMC2,
264
+
GATE_SDMMC3,
265
+
GATE_SERC,
266
+
GATE_SPDIFRX,
267
+
GATE_SPI1,
268
+
GATE_SPI2,
269
+
GATE_SPI3,
270
+
GATE_SPI4,
271
+
GATE_SPI5,
272
+
GATE_SPI6,
273
+
GATE_SPI7,
274
+
GATE_SPI8,
275
+
GATE_TIM1,
276
+
GATE_TIM10,
277
+
GATE_TIM11,
278
+
GATE_TIM12,
279
+
GATE_TIM13,
280
+
GATE_TIM14,
281
+
GATE_TIM15,
282
+
GATE_TIM16,
283
+
GATE_TIM17,
284
+
GATE_TIM2,
285
+
GATE_TIM20,
286
+
GATE_TIM3,
287
+
GATE_TIM4,
288
+
GATE_TIM5,
289
+
GATE_TIM6,
290
+
GATE_TIM7,
291
+
GATE_TIM8,
292
+
GATE_UART4,
293
+
GATE_UART5,
294
+
GATE_UART7,
295
+
GATE_UART8,
296
+
GATE_UART9,
297
+
GATE_USART1,
298
+
GATE_USART2,
299
+
GATE_USART3,
300
+
GATE_USART6,
301
+
GATE_USBH,
302
+
GATE_USB2PHY1,
303
+
GATE_USB2PHY2,
304
+
GATE_USB3DR,
305
+
GATE_USB3PCIEPHY,
306
+
GATE_USBTC,
307
+
GATE_VDEC,
308
+
GATE_VENC,
309
+
GATE_VREF,
310
+
GATE_WWDG1,
311
+
GATE_WWDG2,
312
+
GATE_NB
313
+
};
314
+
315
+
#define GATE_CFG(id, _offset, _bit_idx, _offset_clr) \
316
+
[id] = { \
317
+
.offset = (_offset), \
318
+
.bit_idx = (_bit_idx), \
319
+
.set_clr = (_offset_clr), \
320
+
}
321
+
322
+
static const struct stm32_gate_cfg stm32mp25_gates[GATE_NB] = {
323
+
GATE_CFG(GATE_ADC12, RCC_ADC12CFGR, 1, 0),
324
+
GATE_CFG(GATE_ADC3, RCC_ADC3CFGR, 1, 0),
325
+
GATE_CFG(GATE_ADF1, RCC_ADF1CFGR, 1, 0),
326
+
GATE_CFG(GATE_CCI, RCC_CCICFGR, 1, 0),
327
+
GATE_CFG(GATE_CRC, RCC_CRCCFGR, 1, 0),
328
+
GATE_CFG(GATE_CRYP1, RCC_CRYP1CFGR, 1, 0),
329
+
GATE_CFG(GATE_CRYP2, RCC_CRYP2CFGR, 1, 0),
330
+
GATE_CFG(GATE_CSI, RCC_CSICFGR, 1, 0),
331
+
GATE_CFG(GATE_DCMIPP, RCC_DCMIPPCFGR, 1, 0),
332
+
GATE_CFG(GATE_DSI, RCC_DSICFGR, 1, 0),
333
+
GATE_CFG(GATE_DTS, RCC_DTSCFGR, 1, 0),
334
+
GATE_CFG(GATE_ETH1, RCC_ETH1CFGR, 5, 0),
335
+
GATE_CFG(GATE_ETH1MAC, RCC_ETH1CFGR, 1, 0),
336
+
GATE_CFG(GATE_ETH1RX, RCC_ETH1CFGR, 10, 0),
337
+
GATE_CFG(GATE_ETH1STP, RCC_ETH1CFGR, 4, 0),
338
+
GATE_CFG(GATE_ETH1TX, RCC_ETH1CFGR, 8, 0),
339
+
GATE_CFG(GATE_ETH2, RCC_ETH2CFGR, 5, 0),
340
+
GATE_CFG(GATE_ETH2MAC, RCC_ETH2CFGR, 1, 0),
341
+
GATE_CFG(GATE_ETH2RX, RCC_ETH2CFGR, 10, 0),
342
+
GATE_CFG(GATE_ETH2STP, RCC_ETH2CFGR, 4, 0),
343
+
GATE_CFG(GATE_ETH2TX, RCC_ETH2CFGR, 8, 0),
344
+
GATE_CFG(GATE_ETHSW, RCC_ETHSWCFGR, 5, 0),
345
+
GATE_CFG(GATE_ETHSWACMCFG, RCC_ETHSWACMCFGR, 1, 0),
346
+
GATE_CFG(GATE_ETHSWACMMSG, RCC_ETHSWACMMSGCFGR, 1, 0),
347
+
GATE_CFG(GATE_ETHSWMAC, RCC_ETHSWCFGR, 1, 0),
348
+
GATE_CFG(GATE_ETHSWREF, RCC_ETHSWCFGR, 21, 0),
349
+
GATE_CFG(GATE_FDCAN, RCC_FDCANCFGR, 1, 0),
350
+
GATE_CFG(GATE_GPU, RCC_GPUCFGR, 1, 0),
351
+
GATE_CFG(GATE_HASH, RCC_HASHCFGR, 1, 0),
352
+
GATE_CFG(GATE_HDP, RCC_HDPCFGR, 1, 0),
353
+
GATE_CFG(GATE_I2C1, RCC_I2C1CFGR, 1, 0),
354
+
GATE_CFG(GATE_I2C2, RCC_I2C2CFGR, 1, 0),
355
+
GATE_CFG(GATE_I2C3, RCC_I2C3CFGR, 1, 0),
356
+
GATE_CFG(GATE_I2C4, RCC_I2C4CFGR, 1, 0),
357
+
GATE_CFG(GATE_I2C5, RCC_I2C5CFGR, 1, 0),
358
+
GATE_CFG(GATE_I2C6, RCC_I2C6CFGR, 1, 0),
359
+
GATE_CFG(GATE_I2C7, RCC_I2C7CFGR, 1, 0),
360
+
GATE_CFG(GATE_I2C8, RCC_I2C8CFGR, 1, 0),
361
+
GATE_CFG(GATE_I3C1, RCC_I3C1CFGR, 1, 0),
362
+
GATE_CFG(GATE_I3C2, RCC_I3C2CFGR, 1, 0),
363
+
GATE_CFG(GATE_I3C3, RCC_I3C3CFGR, 1, 0),
364
+
GATE_CFG(GATE_I3C4, RCC_I3C4CFGR, 1, 0),
365
+
GATE_CFG(GATE_IS2M, RCC_IS2MCFGR, 1, 0),
366
+
GATE_CFG(GATE_IWDG1, RCC_IWDG1CFGR, 1, 0),
367
+
GATE_CFG(GATE_IWDG2, RCC_IWDG2CFGR, 1, 0),
368
+
GATE_CFG(GATE_IWDG3, RCC_IWDG3CFGR, 1, 0),
369
+
GATE_CFG(GATE_IWDG4, RCC_IWDG4CFGR, 1, 0),
370
+
GATE_CFG(GATE_IWDG5, RCC_IWDG5CFGR, 1, 0),
371
+
GATE_CFG(GATE_LPTIM1, RCC_LPTIM1CFGR, 1, 0),
372
+
GATE_CFG(GATE_LPTIM2, RCC_LPTIM2CFGR, 1, 0),
373
+
GATE_CFG(GATE_LPTIM3, RCC_LPTIM3CFGR, 1, 0),
374
+
GATE_CFG(GATE_LPTIM4, RCC_LPTIM4CFGR, 1, 0),
375
+
GATE_CFG(GATE_LPTIM5, RCC_LPTIM5CFGR, 1, 0),
376
+
GATE_CFG(GATE_LPUART1, RCC_LPUART1CFGR, 1, 0),
377
+
GATE_CFG(GATE_LTDC, RCC_LTDCCFGR, 1, 0),
378
+
GATE_CFG(GATE_LVDS, RCC_LVDSCFGR, 1, 0),
379
+
GATE_CFG(GATE_MCO1, RCC_MCO1CFGR, 8, 0),
380
+
GATE_CFG(GATE_MCO2, RCC_MCO2CFGR, 8, 0),
381
+
GATE_CFG(GATE_MDF1, RCC_MDF1CFGR, 1, 0),
382
+
GATE_CFG(GATE_OSPIIOM, RCC_OSPIIOMCFGR, 1, 0),
383
+
GATE_CFG(GATE_PCIE, RCC_PCIECFGR, 1, 0),
384
+
GATE_CFG(GATE_PKA, RCC_PKACFGR, 1, 0),
385
+
GATE_CFG(GATE_RNG, RCC_RNGCFGR, 1, 0),
386
+
GATE_CFG(GATE_SAES, RCC_SAESCFGR, 1, 0),
387
+
GATE_CFG(GATE_SAI1, RCC_SAI1CFGR, 1, 0),
388
+
GATE_CFG(GATE_SAI2, RCC_SAI2CFGR, 1, 0),
389
+
GATE_CFG(GATE_SAI3, RCC_SAI3CFGR, 1, 0),
390
+
GATE_CFG(GATE_SAI4, RCC_SAI4CFGR, 1, 0),
391
+
GATE_CFG(GATE_SDMMC1, RCC_SDMMC1CFGR, 1, 0),
392
+
GATE_CFG(GATE_SDMMC2, RCC_SDMMC2CFGR, 1, 0),
393
+
GATE_CFG(GATE_SDMMC3, RCC_SDMMC3CFGR, 1, 0),
394
+
GATE_CFG(GATE_SERC, RCC_SERCCFGR, 1, 0),
395
+
GATE_CFG(GATE_SPDIFRX, RCC_SPDIFRXCFGR, 1, 0),
396
+
GATE_CFG(GATE_SPI1, RCC_SPI1CFGR, 1, 0),
397
+
GATE_CFG(GATE_SPI2, RCC_SPI2CFGR, 1, 0),
398
+
GATE_CFG(GATE_SPI3, RCC_SPI3CFGR, 1, 0),
399
+
GATE_CFG(GATE_SPI4, RCC_SPI4CFGR, 1, 0),
400
+
GATE_CFG(GATE_SPI5, RCC_SPI5CFGR, 1, 0),
401
+
GATE_CFG(GATE_SPI6, RCC_SPI6CFGR, 1, 0),
402
+
GATE_CFG(GATE_SPI7, RCC_SPI7CFGR, 1, 0),
403
+
GATE_CFG(GATE_SPI8, RCC_SPI8CFGR, 1, 0),
404
+
GATE_CFG(GATE_TIM1, RCC_TIM1CFGR, 1, 0),
405
+
GATE_CFG(GATE_TIM10, RCC_TIM10CFGR, 1, 0),
406
+
GATE_CFG(GATE_TIM11, RCC_TIM11CFGR, 1, 0),
407
+
GATE_CFG(GATE_TIM12, RCC_TIM12CFGR, 1, 0),
408
+
GATE_CFG(GATE_TIM13, RCC_TIM13CFGR, 1, 0),
409
+
GATE_CFG(GATE_TIM14, RCC_TIM14CFGR, 1, 0),
410
+
GATE_CFG(GATE_TIM15, RCC_TIM15CFGR, 1, 0),
411
+
GATE_CFG(GATE_TIM16, RCC_TIM16CFGR, 1, 0),
412
+
GATE_CFG(GATE_TIM17, RCC_TIM17CFGR, 1, 0),
413
+
GATE_CFG(GATE_TIM2, RCC_TIM2CFGR, 1, 0),
414
+
GATE_CFG(GATE_TIM20, RCC_TIM20CFGR, 1, 0),
415
+
GATE_CFG(GATE_TIM3, RCC_TIM3CFGR, 1, 0),
416
+
GATE_CFG(GATE_TIM4, RCC_TIM4CFGR, 1, 0),
417
+
GATE_CFG(GATE_TIM5, RCC_TIM5CFGR, 1, 0),
418
+
GATE_CFG(GATE_TIM6, RCC_TIM6CFGR, 1, 0),
419
+
GATE_CFG(GATE_TIM7, RCC_TIM7CFGR, 1, 0),
420
+
GATE_CFG(GATE_TIM8, RCC_TIM8CFGR, 1, 0),
421
+
GATE_CFG(GATE_UART4, RCC_UART4CFGR, 1, 0),
422
+
GATE_CFG(GATE_UART5, RCC_UART5CFGR, 1, 0),
423
+
GATE_CFG(GATE_UART7, RCC_UART7CFGR, 1, 0),
424
+
GATE_CFG(GATE_UART8, RCC_UART8CFGR, 1, 0),
425
+
GATE_CFG(GATE_UART9, RCC_UART9CFGR, 1, 0),
426
+
GATE_CFG(GATE_USART1, RCC_USART1CFGR, 1, 0),
427
+
GATE_CFG(GATE_USART2, RCC_USART2CFGR, 1, 0),
428
+
GATE_CFG(GATE_USART3, RCC_USART3CFGR, 1, 0),
429
+
GATE_CFG(GATE_USART6, RCC_USART6CFGR, 1, 0),
430
+
GATE_CFG(GATE_USBH, RCC_USBHCFGR, 1, 0),
431
+
GATE_CFG(GATE_USB2PHY1, RCC_USB2PHY1CFGR, 1, 0),
432
+
GATE_CFG(GATE_USB2PHY2, RCC_USB2PHY2CFGR, 1, 0),
433
+
GATE_CFG(GATE_USB3DR, RCC_USB3DRCFGR, 1, 0),
434
+
GATE_CFG(GATE_USB3PCIEPHY, RCC_USB3PCIEPHYCFGR, 1, 0),
435
+
GATE_CFG(GATE_USBTC, RCC_USBTCCFGR, 1, 0),
436
+
GATE_CFG(GATE_VDEC, RCC_VDECCFGR, 1, 0),
437
+
GATE_CFG(GATE_VENC, RCC_VENCCFGR, 1, 0),
438
+
GATE_CFG(GATE_VREF, RCC_VREFCFGR, 1, 0),
439
+
GATE_CFG(GATE_WWDG1, RCC_WWDG1CFGR, 1, 0),
440
+
GATE_CFG(GATE_WWDG2, RCC_WWDG2CFGR, 1, 0),
441
+
};
442
+
443
+
#define CLK_HW_INIT_INDEX(_name, _parent, _ops, _flags) \
444
+
(&(struct clk_init_data) { \
445
+
.flags = _flags, \
446
+
.name = _name, \
447
+
.parent_data = (const struct clk_parent_data[]) { \
448
+
{ .index = _parent }, \
449
+
}, \
450
+
.num_parents = 1, \
451
+
.ops = _ops, \
452
+
})
453
+
454
+
/* ADC */
455
+
static struct clk_stm32_gate ck_icn_p_adc12 = {
456
+
.gate_id = GATE_ADC12,
457
+
.hw.init = CLK_HW_INIT_INDEX("ck_icn_p_adc12", ICN_LS_MCU, &clk_stm32_gate_ops, 0),
458
+
};
459
+
460
+
static struct clk_stm32_composite ck_ker_adc12 = {
461
+
.gate_id = GATE_ADC12,
462
+
.mux_id = MUX_ADC12,
463
+
.div_id = NO_STM32_DIV,
464
+
.hw.init = CLK_HW_INIT_PARENTS_DATA("ck_ker_adc12", adc12_src, &clk_stm32_composite_ops, 0),
465
+
};
466
+
467
+
static struct clk_stm32_gate ck_icn_p_adc3 = {
468
+
.gate_id = GATE_ADC3,
469
+
.hw.init = CLK_HW_INIT_INDEX("ck_icn_p_adc3", ICN_LS_MCU, &clk_stm32_gate_ops, 0),
470
+
};
471
+
472
+
static struct clk_stm32_composite ck_ker_adc3 = {
473
+
.gate_id = GATE_ADC3,
474
+
.mux_id = MUX_ADC3,
475
+
.div_id = NO_STM32_DIV,
476
+
.hw.init = CLK_HW_INIT_PARENTS_DATA("ck_ker_adc3", adc3_src, &clk_stm32_composite_ops, 0),
477
+
};
478
+
479
+
/* ADF */
480
+
static struct clk_stm32_gate ck_icn_p_adf1 = {
481
+
.gate_id = GATE_ADF1,
482
+
.hw.init = CLK_HW_INIT_INDEX("ck_icn_p_adf1", ICN_LS_MCU, &clk_stm32_gate_ops, 0),
483
+
};
484
+
485
+
static struct clk_stm32_gate ck_ker_adf1 = {
486
+
.gate_id = GATE_ADF1,
487
+
.hw.init = CLK_HW_INIT_INDEX("ck_ker_adf1", FLEXGEN_42, &clk_stm32_gate_ops, 0),
488
+
};
489
+
490
+
/* DCMI */
491
+
static struct clk_stm32_gate ck_icn_p_cci = {
492
+
.gate_id = GATE_CCI,
493
+
.hw.init = CLK_HW_INIT_INDEX("ck_icn_p_cci", ICN_LS_MCU, &clk_stm32_gate_ops, 0),
494
+
};
495
+
496
+
/* CSI-HOST */
497
+
static struct clk_stm32_gate ck_icn_p_csi = {
498
+
.gate_id = GATE_CSI,
499
+
.hw.init = CLK_HW_INIT_INDEX("ck_icn_p_csi", ICN_APB4, &clk_stm32_gate_ops, 0),
500
+
};
501
+
502
+
static struct clk_stm32_gate ck_ker_csi = {
503
+
.gate_id = GATE_CSI,
504
+
.hw.init = CLK_HW_INIT_INDEX("ck_ker_csi", FLEXGEN_29, &clk_stm32_gate_ops, 0),
505
+
};
506
+
507
+
static struct clk_stm32_gate ck_ker_csitxesc = {
508
+
.gate_id = GATE_CSI,
509
+
.hw.init = CLK_HW_INIT_INDEX("ck_ker_csitxesc", FLEXGEN_30, &clk_stm32_gate_ops, 0),
510
+
};
511
+
512
+
/* CSI-PHY */
513
+
static struct clk_stm32_gate ck_ker_csiphy = {
514
+
.gate_id = GATE_CSI,
515
+
.hw.init = CLK_HW_INIT_INDEX("ck_ker_csiphy", FLEXGEN_31, &clk_stm32_gate_ops, 0),
516
+
};
517
+
518
+
/* DCMIPP */
519
+
static struct clk_stm32_gate ck_icn_p_dcmipp = {
520
+
.gate_id = GATE_DCMIPP,
521
+
.hw.init = CLK_HW_INIT_INDEX("ck_icn_p_dcmipp", ICN_APB4, &clk_stm32_gate_ops, 0),
522
+
};
523
+
524
+
/* CRC */
525
+
static struct clk_stm32_gate ck_icn_p_crc = {
526
+
.gate_id = GATE_CRC,
527
+
.hw.init = CLK_HW_INIT_INDEX("ck_icn_p_crc", ICN_LS_MCU, &clk_stm32_gate_ops, 0),
528
+
};
529
+
530
+
/* CRYP */
531
+
static struct clk_stm32_gate ck_icn_p_cryp1 = {
532
+
.gate_id = GATE_CRYP1,
533
+
.hw.init = CLK_HW_INIT_INDEX("ck_icn_p_cryp1", ICN_LS_MCU, &clk_stm32_gate_ops, 0),
534
+
};
535
+
536
+
static struct clk_stm32_gate ck_icn_p_cryp2 = {
537
+
.gate_id = GATE_CRYP2,
538
+
.hw.init = CLK_HW_INIT_INDEX("ck_icn_p_cryp2", ICN_LS_MCU, &clk_stm32_gate_ops, 0),
539
+
};
540
+
541
+
/* DBG & TRACE*/
542
+
/* Trace and debug clocks are managed by SCMI */
543
+
544
+
/* LTDC */
545
+
static struct clk_stm32_gate ck_icn_p_ltdc = {
546
+
.gate_id = GATE_LTDC,
547
+
.hw.init = CLK_HW_INIT_INDEX("ck_icn_p_ltdc", ICN_APB4, &clk_stm32_gate_ops, 0),
548
+
};
549
+
550
+
static struct clk_stm32_gate ck_ker_ltdc = {
551
+
.gate_id = GATE_LTDC,
552
+
.hw.init = CLK_HW_INIT_INDEX("ck_ker_ltdc", FLEXGEN_27, &clk_stm32_gate_ops,
553
+
CLK_SET_RATE_PARENT),
554
+
};
555
+
556
+
/* DSI */
557
+
static struct clk_stm32_gate ck_icn_p_dsi = {
558
+
.gate_id = GATE_DSI,
559
+
.hw.init = CLK_HW_INIT_INDEX("ck_icn_p_dsi", ICN_APB4, &clk_stm32_gate_ops, 0),
560
+
};
561
+
562
+
static struct clk_stm32_composite clk_lanebyte = {
563
+
.gate_id = GATE_DSI,
564
+
.mux_id = MUX_DSIBLANE,
565
+
.div_id = NO_STM32_DIV,
566
+
.hw.init = CLK_HW_INIT_PARENTS_DATA("clk_lanebyte", dsiblane_src,
567
+
&clk_stm32_composite_ops, 0),
568
+
};
569
+
570
+
/* LVDS */
571
+
static struct clk_stm32_gate ck_icn_p_lvds = {
572
+
.gate_id = GATE_LVDS,
573
+
.hw.init = CLK_HW_INIT_INDEX("ck_icn_p_lvds", ICN_APB4, &clk_stm32_gate_ops, 0),
574
+
};
575
+
576
+
/* DSI PHY */
577
+
static struct clk_stm32_composite clk_phy_dsi = {
578
+
.gate_id = GATE_DSI,
579
+
.mux_id = MUX_DSIPHY,
580
+
.div_id = NO_STM32_DIV,
581
+
.hw.init = CLK_HW_INIT_PARENTS_DATA("clk_phy_dsi", dsiphy_src,
582
+
&clk_stm32_composite_ops, 0),
583
+
};
584
+
585
+
/* LVDS PHY */
586
+
static struct clk_stm32_composite ck_ker_lvdsphy = {
587
+
.gate_id = GATE_LVDS,
588
+
.mux_id = MUX_LVDSPHY,
589
+
.div_id = NO_STM32_DIV,
590
+
.hw.init = CLK_HW_INIT_PARENTS_DATA("ck_ker_lvdsphy", lvdsphy_src,
591
+
&clk_stm32_composite_ops, 0),
592
+
};
593
+
594
+
/* DTS */
595
+
static struct clk_stm32_composite ck_ker_dts = {
596
+
.gate_id = GATE_DTS,
597
+
.mux_id = MUX_DTS,
598
+
.div_id = NO_STM32_DIV,
599
+
.hw.init = CLK_HW_INIT_PARENTS_DATA("ck_ker_dts", dts_src,
600
+
&clk_stm32_composite_ops, 0),
601
+
};
602
+
603
+
/* ETHERNET */
604
+
static struct clk_stm32_gate ck_icn_p_eth1 = {
605
+
.gate_id = GATE_ETH1,
606
+
.hw.init = CLK_HW_INIT_INDEX("ck_icn_p_eth1", ICN_LS_MCU, &clk_stm32_gate_ops, 0),
607
+
};
608
+
609
+
static struct clk_stm32_gate ck_ker_eth1stp = {
610
+
.gate_id = GATE_ETH1STP,
611
+
.hw.init = CLK_HW_INIT_INDEX("ck_ker_eth1stp", ICN_LS_MCU, &clk_stm32_gate_ops, 0),
612
+
};
613
+
614
+
static struct clk_stm32_gate ck_ker_eth1 = {
615
+
.gate_id = GATE_ETH1,
616
+
.hw.init = CLK_HW_INIT_INDEX("ck_ker_eth1", FLEXGEN_54, &clk_stm32_gate_ops, 0),
617
+
};
618
+
619
+
static struct clk_stm32_gate ck_ker_eth1ptp = {
620
+
.gate_id = GATE_ETH1,
621
+
.hw.init = CLK_HW_INIT_INDEX("ck_ker_eth1ptp", FLEXGEN_56, &clk_stm32_gate_ops, 0),
622
+
};
623
+
624
+
static struct clk_stm32_gate ck_ker_eth1mac = {
625
+
.gate_id = GATE_ETH1MAC,
626
+
.hw.init = CLK_HW_INIT_INDEX("ck_ker_eth1mac", ICN_LS_MCU, &clk_stm32_gate_ops, 0),
627
+
};
628
+
629
+
static struct clk_stm32_gate ck_ker_eth1tx = {
630
+
.gate_id = GATE_ETH1TX,
631
+
.hw.init = CLK_HW_INIT_INDEX("ck_ker_eth1tx", ICN_LS_MCU, &clk_stm32_gate_ops, 0),
632
+
};
633
+
634
+
static struct clk_stm32_gate ck_ker_eth1rx = {
635
+
.gate_id = GATE_ETH1RX,
636
+
.hw.init = CLK_HW_INIT_INDEX("ck_ker_eth1rx", ICN_LS_MCU, &clk_stm32_gate_ops, 0),
637
+
};
638
+
639
+
static struct clk_stm32_gate ck_icn_p_eth2 = {
640
+
.gate_id = GATE_ETH2,
641
+
.hw.init = CLK_HW_INIT_INDEX("ck_icn_p_eth2", ICN_LS_MCU, &clk_stm32_gate_ops, 0),
642
+
};
643
+
644
+
static struct clk_stm32_gate ck_ker_eth2stp = {
645
+
.gate_id = GATE_ETH2STP,
646
+
.hw.init = CLK_HW_INIT_INDEX("ck_ker_eth2stp", ICN_LS_MCU, &clk_stm32_gate_ops, 0),
647
+
};
648
+
649
+
static struct clk_stm32_gate ck_ker_eth2 = {
650
+
.gate_id = GATE_ETH2,
651
+
.hw.init = CLK_HW_INIT_INDEX("ck_ker_eth2", FLEXGEN_55, &clk_stm32_gate_ops, 0),
652
+
};
653
+
654
+
static struct clk_stm32_gate ck_ker_eth2ptp = {
655
+
.gate_id = GATE_ETH2,
656
+
.hw.init = CLK_HW_INIT_INDEX("ck_ker_eth2ptp", FLEXGEN_56, &clk_stm32_gate_ops, 0),
657
+
};
658
+
659
+
static struct clk_stm32_gate ck_ker_eth2mac = {
660
+
.gate_id = GATE_ETH2MAC,
661
+
.hw.init = CLK_HW_INIT_INDEX("ck_ker_eth2mac", ICN_LS_MCU, &clk_stm32_gate_ops, 0),
662
+
};
663
+
664
+
static struct clk_stm32_gate ck_ker_eth2tx = {
665
+
.gate_id = GATE_ETH2TX,
666
+
.hw.init = CLK_HW_INIT_INDEX("ck_ker_eth2tx", ICN_LS_MCU, &clk_stm32_gate_ops, 0),
667
+
};
668
+
669
+
static struct clk_stm32_gate ck_ker_eth2rx = {
670
+
.gate_id = GATE_ETH2RX,
671
+
.hw.init = CLK_HW_INIT_INDEX("ck_ker_eth2rx", ICN_LS_MCU, &clk_stm32_gate_ops, 0),
672
+
};
673
+
674
+
static struct clk_stm32_gate ck_icn_p_ethsw = {
675
+
.gate_id = GATE_ETHSWMAC,
676
+
.hw.init = CLK_HW_INIT_INDEX("ck_icn_p_ethsw", ICN_LS_MCU, &clk_stm32_gate_ops, 0),
677
+
};
678
+
679
+
static struct clk_stm32_gate ck_ker_ethsw = {
680
+
.gate_id = GATE_ETHSW,
681
+
.hw.init = CLK_HW_INIT_INDEX("ck_ker_ethsw", FLEXGEN_54, &clk_stm32_gate_ops, 0),
682
+
};
683
+
684
+
static struct clk_stm32_gate ck_ker_ethswref = {
685
+
.gate_id = GATE_ETHSWREF,
686
+
.hw.init = CLK_HW_INIT_INDEX("ck_ker_ethswref", FLEXGEN_60, &clk_stm32_gate_ops, 0),
687
+
};
688
+
689
+
static struct clk_stm32_gate ck_icn_p_ethsw_acm_cfg = {
690
+
.gate_id = GATE_ETHSWACMCFG,
691
+
.hw.init = CLK_HW_INIT_INDEX("ck_icn_p_ethsw_acm_cfg", ICN_LS_MCU,
692
+
&clk_stm32_gate_ops, 0),
693
+
};
694
+
695
+
static struct clk_stm32_gate ck_icn_p_ethsw_acm_msg = {
696
+
.gate_id = GATE_ETHSWACMMSG,
697
+
.hw.init = CLK_HW_INIT_INDEX("ck_icn_p_ethsw_acm_msg", ICN_LS_MCU,
698
+
&clk_stm32_gate_ops, 0),
699
+
};
700
+
701
+
/* FDCAN */
702
+
static struct clk_stm32_gate ck_icn_p_fdcan = {
703
+
.gate_id = GATE_FDCAN,
704
+
.hw.init = CLK_HW_INIT_INDEX("ck_icn_p_fdcan", ICN_APB2, &clk_stm32_gate_ops, 0),
705
+
};
706
+
707
+
static struct clk_stm32_gate ck_ker_fdcan = {
708
+
.gate_id = GATE_FDCAN,
709
+
.hw.init = CLK_HW_INIT_INDEX("ck_ker_fdcan", FLEXGEN_26, &clk_stm32_gate_ops, 0),
710
+
};
711
+
712
+
/* GPU */
713
+
static struct clk_stm32_gate ck_icn_m_gpu = {
714
+
.gate_id = GATE_GPU,
715
+
.hw.init = CLK_HW_INIT_INDEX("ck_icn_m_gpu", FLEXGEN_59, &clk_stm32_gate_ops, 0),
716
+
};
717
+
718
+
static struct clk_stm32_gate ck_ker_gpu = {
719
+
.gate_id = GATE_GPU,
720
+
.hw.init = CLK_HW_INIT_INDEX("ck_ker_gpu", PLL3, &clk_stm32_gate_ops, 0),
721
+
};
722
+
723
+
/* HASH */
724
+
static struct clk_stm32_gate ck_icn_p_hash = {
725
+
.gate_id = GATE_HASH,
726
+
.hw.init = CLK_HW_INIT_INDEX("ck_icn_p_hash", ICN_LS_MCU, &clk_stm32_gate_ops, 0),
727
+
};
728
+
729
+
/* HDP */
730
+
static struct clk_stm32_gate ck_icn_p_hdp = {
731
+
.gate_id = GATE_HDP,
732
+
.hw.init = CLK_HW_INIT_INDEX("ck_icn_p_hdp", ICN_APB3, &clk_stm32_gate_ops, 0),
733
+
};
734
+
735
+
/* I2C */
736
+
static struct clk_stm32_gate ck_icn_p_i2c8 = {
737
+
.gate_id = GATE_I2C8,
738
+
.hw.init = CLK_HW_INIT_INDEX("ck_icn_p_i2c8", ICN_LS_MCU, &clk_stm32_gate_ops, 0),
739
+
};
740
+
741
+
static struct clk_stm32_gate ck_icn_p_i2c1 = {
742
+
.gate_id = GATE_I2C1,
743
+
.hw.init = CLK_HW_INIT_INDEX("ck_icn_p_i2c1", ICN_APB1, &clk_stm32_gate_ops, 0),
744
+
};
745
+
746
+
static struct clk_stm32_gate ck_icn_p_i2c2 = {
747
+
.gate_id = GATE_I2C2,
748
+
.hw.init = CLK_HW_INIT_INDEX("ck_icn_p_i2c2", ICN_APB1, &clk_stm32_gate_ops, 0),
749
+
};
750
+
751
+
static struct clk_stm32_gate ck_icn_p_i2c3 = {
752
+
.gate_id = GATE_I2C3,
753
+
.hw.init = CLK_HW_INIT_INDEX("ck_icn_p_i2c3", ICN_APB1, &clk_stm32_gate_ops, 0),
754
+
};
755
+
756
+
static struct clk_stm32_gate ck_icn_p_i2c4 = {
757
+
.gate_id = GATE_I2C4,
758
+
.hw.init = CLK_HW_INIT_INDEX("ck_icn_p_i2c4", ICN_APB1, &clk_stm32_gate_ops, 0),
759
+
};
760
+
761
+
static struct clk_stm32_gate ck_icn_p_i2c5 = {
762
+
.gate_id = GATE_I2C5,
763
+
.hw.init = CLK_HW_INIT_INDEX("ck_icn_p_i2c5", ICN_APB1, &clk_stm32_gate_ops, 0),
764
+
};
765
+
766
+
static struct clk_stm32_gate ck_icn_p_i2c6 = {
767
+
.gate_id = GATE_I2C6,
768
+
.hw.init = CLK_HW_INIT_INDEX("ck_icn_p_i2c6", ICN_APB1, &clk_stm32_gate_ops, 0),
769
+
};
770
+
771
+
static struct clk_stm32_gate ck_icn_p_i2c7 = {
772
+
.gate_id = GATE_I2C7,
773
+
.hw.init = CLK_HW_INIT_INDEX("ck_icn_p_i2c7", ICN_APB1, &clk_stm32_gate_ops, 0),
774
+
};
775
+
776
+
static struct clk_stm32_gate ck_ker_i2c1 = {
777
+
.gate_id = GATE_I2C1,
778
+
.hw.init = CLK_HW_INIT_INDEX("ck_ker_i2c1", FLEXGEN_12, &clk_stm32_gate_ops, 0),
779
+
};
780
+
781
+
static struct clk_stm32_gate ck_ker_i2c2 = {
782
+
.gate_id = GATE_I2C2,
783
+
.hw.init = CLK_HW_INIT_INDEX("ck_ker_i2c2", FLEXGEN_12, &clk_stm32_gate_ops, 0),
784
+
};
785
+
786
+
static struct clk_stm32_gate ck_ker_i2c3 = {
787
+
.gate_id = GATE_I2C3,
788
+
.hw.init = CLK_HW_INIT_INDEX("ck_ker_i2c3", FLEXGEN_13, &clk_stm32_gate_ops, 0),
789
+
};
790
+
791
+
static struct clk_stm32_gate ck_ker_i2c5 = {
792
+
.gate_id = GATE_I2C5,
793
+
.hw.init = CLK_HW_INIT_INDEX("ck_ker_i2c5", FLEXGEN_13, &clk_stm32_gate_ops, 0),
794
+
};
795
+
796
+
static struct clk_stm32_gate ck_ker_i2c4 = {
797
+
.gate_id = GATE_I2C4,
798
+
.hw.init = CLK_HW_INIT_INDEX("ck_ker_i2c4", FLEXGEN_14, &clk_stm32_gate_ops, 0),
799
+
};
800
+
801
+
static struct clk_stm32_gate ck_ker_i2c6 = {
802
+
.gate_id = GATE_I2C6,
803
+
.hw.init = CLK_HW_INIT_INDEX("ck_ker_i2c6", FLEXGEN_14, &clk_stm32_gate_ops, 0),
804
+
};
805
+
806
+
static struct clk_stm32_gate ck_ker_i2c7 = {
807
+
.gate_id = GATE_I2C7,
808
+
.hw.init = CLK_HW_INIT_INDEX("ck_ker_i2c7", FLEXGEN_15, &clk_stm32_gate_ops, 0),
809
+
};
810
+
811
+
static struct clk_stm32_gate ck_ker_i2c8 = {
812
+
.gate_id = GATE_I2C8,
813
+
.hw.init = CLK_HW_INIT_INDEX("ck_ker_i2c8", FLEXGEN_38, &clk_stm32_gate_ops, 0),
814
+
};
815
+
816
+
/* I3C */
817
+
static struct clk_stm32_gate ck_icn_p_i3c1 = {
818
+
.gate_id = GATE_I3C1,
819
+
.hw.init = CLK_HW_INIT_INDEX("ck_icn_p_i3c1", ICN_APB1, &clk_stm32_gate_ops, 0),
820
+
};
821
+
822
+
static struct clk_stm32_gate ck_icn_p_i3c2 = {
823
+
.gate_id = GATE_I3C2,
824
+
.hw.init = CLK_HW_INIT_INDEX("ck_icn_p_i3c2", ICN_APB1, &clk_stm32_gate_ops, 0),
825
+
};
826
+
827
+
static struct clk_stm32_gate ck_icn_p_i3c3 = {
828
+
.gate_id = GATE_I3C3,
829
+
.hw.init = CLK_HW_INIT_INDEX("ck_icn_p_i3c3", ICN_APB1, &clk_stm32_gate_ops, 0),
830
+
};
831
+
832
+
static struct clk_stm32_gate ck_icn_p_i3c4 = {
833
+
.gate_id = GATE_I3C4,
834
+
.hw.init = CLK_HW_INIT_INDEX("ck_icn_p_i3c4", ICN_LS_MCU, &clk_stm32_gate_ops, 0),
835
+
};
836
+
837
+
static struct clk_stm32_gate ck_ker_i3c1 = {
838
+
.gate_id = GATE_I3C1,
839
+
.hw.init = CLK_HW_INIT_INDEX("ck_ker_i3c1", FLEXGEN_12, &clk_stm32_gate_ops, 0),
840
+
};
841
+
842
+
static struct clk_stm32_gate ck_ker_i3c2 = {
843
+
.gate_id = GATE_I3C2,
844
+
.hw.init = CLK_HW_INIT_INDEX("ck_ker_i3c2", FLEXGEN_12, &clk_stm32_gate_ops, 0),
845
+
};
846
+
847
+
static struct clk_stm32_gate ck_ker_i3c3 = {
848
+
.gate_id = GATE_I3C3,
849
+
.hw.init = CLK_HW_INIT_INDEX("ck_ker_i3c3", FLEXGEN_13, &clk_stm32_gate_ops, 0),
850
+
};
851
+
852
+
static struct clk_stm32_gate ck_ker_i3c4 = {
853
+
.gate_id = GATE_I3C4,
854
+
.hw.init = CLK_HW_INIT_INDEX("ck_ker_i3c4", FLEXGEN_36, &clk_stm32_gate_ops, 0),
855
+
};
856
+
857
+
/* I2S */
858
+
static struct clk_stm32_gate ck_icn_p_is2m = {
859
+
.gate_id = GATE_IS2M,
860
+
.hw.init = CLK_HW_INIT_INDEX("ck_icn_p_is2m", ICN_APB3, &clk_stm32_gate_ops, 0),
861
+
};
862
+
863
+
/* IWDG */
864
+
static struct clk_stm32_gate ck_icn_p_iwdg2 = {
865
+
.gate_id = GATE_IWDG2,
866
+
.hw.init = CLK_HW_INIT_INDEX("ck_icn_p_iwdg2", ICN_APB3, &clk_stm32_gate_ops, 0),
867
+
};
868
+
869
+
static struct clk_stm32_gate ck_icn_p_iwdg3 = {
870
+
.gate_id = GATE_IWDG3,
871
+
.hw.init = CLK_HW_INIT_INDEX("ck_icn_p_iwdg3", ICN_APB3, &clk_stm32_gate_ops, 0),
872
+
};
873
+
874
+
static struct clk_stm32_gate ck_icn_p_iwdg4 = {
875
+
.gate_id = GATE_IWDG4,
876
+
.hw.init = CLK_HW_INIT_INDEX("ck_icn_p_iwdg4", ICN_APB3, &clk_stm32_gate_ops, 0),
877
+
};
878
+
879
+
static struct clk_stm32_gate ck_icn_p_iwdg5 = {
880
+
.gate_id = GATE_IWDG5,
881
+
.hw.init = CLK_HW_INIT_INDEX("ck_icn_p_iwdg5", ICN_LS_MCU, &clk_stm32_gate_ops, 0),
882
+
};
883
+
884
+
/* LPTIM */
885
+
static struct clk_stm32_gate ck_icn_p_lptim1 = {
886
+
.gate_id = GATE_LPTIM1,
887
+
.hw.init = CLK_HW_INIT_INDEX("ck_icn_p_lptim1", ICN_APB1, &clk_stm32_gate_ops, 0),
888
+
};
889
+
890
+
static struct clk_stm32_gate ck_icn_p_lptim2 = {
891
+
.gate_id = GATE_LPTIM2,
892
+
.hw.init = CLK_HW_INIT_INDEX("ck_icn_p_lptim2", ICN_APB1, &clk_stm32_gate_ops, 0),
893
+
};
894
+
895
+
static struct clk_stm32_gate ck_icn_p_lptim3 = {
896
+
.gate_id = GATE_LPTIM3,
897
+
.hw.init = CLK_HW_INIT_INDEX("ck_icn_p_lptim3", ICN_LS_MCU, &clk_stm32_gate_ops, 0),
898
+
};
899
+
900
+
static struct clk_stm32_gate ck_icn_p_lptim4 = {
901
+
.gate_id = GATE_LPTIM4,
902
+
.hw.init = CLK_HW_INIT_INDEX("ck_icn_p_lptim4", ICN_LS_MCU, &clk_stm32_gate_ops, 0),
903
+
};
904
+
905
+
static struct clk_stm32_gate ck_icn_p_lptim5 = {
906
+
.gate_id = GATE_LPTIM5,
907
+
.hw.init = CLK_HW_INIT_INDEX("ck_icn_p_lptim5", ICN_LS_MCU, &clk_stm32_gate_ops, 0),
908
+
};
909
+
910
+
static struct clk_stm32_gate ck_ker_lptim1 = {
911
+
.gate_id = GATE_LPTIM1,
912
+
.hw.init = CLK_HW_INIT_INDEX("ck_ker_lptim1", FLEXGEN_07, &clk_stm32_gate_ops, 0),
913
+
};
914
+
915
+
static struct clk_stm32_gate ck_ker_lptim2 = {
916
+
.gate_id = GATE_LPTIM2,
917
+
.hw.init = CLK_HW_INIT_INDEX("ck_ker_lptim2", FLEXGEN_07, &clk_stm32_gate_ops, 0),
918
+
};
919
+
920
+
static struct clk_stm32_gate ck_ker_lptim3 = {
921
+
.gate_id = GATE_LPTIM3,
922
+
.hw.init = CLK_HW_INIT_INDEX("ck_ker_lptim3", FLEXGEN_40, &clk_stm32_gate_ops, 0),
923
+
};
924
+
925
+
static struct clk_stm32_gate ck_ker_lptim4 = {
926
+
.gate_id = GATE_LPTIM4,
927
+
.hw.init = CLK_HW_INIT_INDEX("ck_ker_lptim4", FLEXGEN_41, &clk_stm32_gate_ops, 0),
928
+
};
929
+
930
+
static struct clk_stm32_gate ck_ker_lptim5 = {
931
+
.gate_id = GATE_LPTIM5,
932
+
.hw.init = CLK_HW_INIT_INDEX("ck_ker_lptim5", FLEXGEN_41, &clk_stm32_gate_ops, 0),
933
+
};
934
+
935
+
/* LPUART */
936
+
static struct clk_stm32_gate ck_icn_p_lpuart1 = {
937
+
.gate_id = GATE_LPUART1,
938
+
.hw.init = CLK_HW_INIT_INDEX("ck_icn_p_lpuart1", ICN_LS_MCU, &clk_stm32_gate_ops, 0),
939
+
};
940
+
941
+
static struct clk_stm32_gate ck_ker_lpuart1 = {
942
+
.gate_id = GATE_LPUART1,
943
+
.hw.init = CLK_HW_INIT_INDEX("ck_ker_lpuart1", FLEXGEN_39, &clk_stm32_gate_ops, 0),
944
+
};
945
+
946
+
/* MCO1 & MCO2 */
947
+
static struct clk_stm32_composite ck_mco1 = {
948
+
.gate_id = GATE_MCO1,
949
+
.mux_id = MUX_MCO1,
950
+
.div_id = NO_STM32_DIV,
951
+
.hw.init = CLK_HW_INIT_PARENTS_DATA("ck_mco1", mco1_src, &clk_stm32_composite_ops, 0),
952
+
};
953
+
954
+
static struct clk_stm32_composite ck_mco2 = {
955
+
.gate_id = GATE_MCO2,
956
+
.mux_id = MUX_MCO2,
957
+
.div_id = NO_STM32_DIV,
958
+
.hw.init = CLK_HW_INIT_PARENTS_DATA("ck_mco2", mco2_src, &clk_stm32_composite_ops, 0),
959
+
};
960
+
961
+
/* MDF */
962
+
static struct clk_stm32_gate ck_icn_p_mdf1 = {
963
+
.gate_id = GATE_MDF1,
964
+
.hw.init = CLK_HW_INIT_INDEX("ck_icn_p_mdf1", ICN_LS_MCU, &clk_stm32_gate_ops, 0),
965
+
};
966
+
967
+
static struct clk_stm32_gate ck_ker_mdf1 = {
968
+
.gate_id = GATE_MDF1,
969
+
.hw.init = CLK_HW_INIT_INDEX("ck_ker_mdf1", FLEXGEN_23, &clk_stm32_gate_ops, 0),
970
+
};
971
+
972
+
/* OSPI */
973
+
static struct clk_stm32_gate ck_icn_p_ospiiom = {
974
+
.gate_id = GATE_OSPIIOM,
975
+
.hw.init = CLK_HW_INIT_INDEX("ck_icn_p_ospiiom", ICN_LS_MCU, &clk_stm32_gate_ops, 0),
976
+
};
977
+
978
+
/* PCIE */
979
+
static struct clk_stm32_gate ck_icn_p_pcie = {
980
+
.gate_id = GATE_PCIE,
981
+
.hw.init = CLK_HW_INIT_INDEX("ck_icn_p_pcie", ICN_LS_MCU, &clk_stm32_gate_ops, 0),
982
+
};
983
+
984
+
/* SAI */
985
+
static struct clk_stm32_gate ck_icn_p_sai1 = {
986
+
.gate_id = GATE_SAI1,
987
+
.hw.init = CLK_HW_INIT_INDEX("ck_icn_p_sai1", ICN_APB2, &clk_stm32_gate_ops, 0),
988
+
};
989
+
990
+
static struct clk_stm32_gate ck_icn_p_sai2 = {
991
+
.gate_id = GATE_SAI2,
992
+
.hw.init = CLK_HW_INIT_INDEX("ck_icn_p_sai2", ICN_APB2, &clk_stm32_gate_ops, 0),
993
+
};
994
+
995
+
static struct clk_stm32_gate ck_icn_p_sai3 = {
996
+
.gate_id = GATE_SAI3,
997
+
.hw.init = CLK_HW_INIT_INDEX("ck_icn_p_sai3", ICN_APB2, &clk_stm32_gate_ops, 0),
998
+
};
999
+
1000
+
static struct clk_stm32_gate ck_icn_p_sai4 = {
1001
+
.gate_id = GATE_SAI4,
1002
+
.hw.init = CLK_HW_INIT_INDEX("ck_icn_p_sai4", ICN_APB2, &clk_stm32_gate_ops, 0),
1003
+
};
1004
+
1005
+
static struct clk_stm32_gate ck_ker_sai1 = {
1006
+
.gate_id = GATE_SAI1,
1007
+
.hw.init = CLK_HW_INIT_INDEX("ck_ker_sai1", FLEXGEN_23, &clk_stm32_gate_ops,
1008
+
CLK_SET_RATE_PARENT),
1009
+
};
1010
+
1011
+
static struct clk_stm32_gate ck_ker_sai2 = {
1012
+
.gate_id = GATE_SAI2,
1013
+
.hw.init = CLK_HW_INIT_INDEX("ck_ker_sai2", FLEXGEN_24, &clk_stm32_gate_ops,
1014
+
CLK_SET_RATE_PARENT),
1015
+
};
1016
+
1017
+
static struct clk_stm32_gate ck_ker_sai3 = {
1018
+
.gate_id = GATE_SAI3,
1019
+
.hw.init = CLK_HW_INIT_INDEX("ck_ker_sai3", FLEXGEN_25, &clk_stm32_gate_ops,
1020
+
CLK_SET_RATE_PARENT),
1021
+
};
1022
+
1023
+
static struct clk_stm32_gate ck_ker_sai4 = {
1024
+
.gate_id = GATE_SAI4,
1025
+
.hw.init = CLK_HW_INIT_INDEX("ck_ker_sai4", FLEXGEN_25, &clk_stm32_gate_ops,
1026
+
CLK_SET_RATE_PARENT),
1027
+
};
1028
+
1029
+
/* SDMMC */
1030
+
static struct clk_stm32_gate ck_icn_m_sdmmc1 = {
1031
+
.gate_id = GATE_SDMMC1,
1032
+
.hw.init = CLK_HW_INIT_INDEX("ck_icn_m_sdmmc1", ICN_SDMMC, &clk_stm32_gate_ops, 0),
1033
+
};
1034
+
1035
+
static struct clk_stm32_gate ck_icn_m_sdmmc2 = {
1036
+
.gate_id = GATE_SDMMC2,
1037
+
.hw.init = CLK_HW_INIT_INDEX("ck_icn_m_sdmmc2", ICN_SDMMC, &clk_stm32_gate_ops, 0),
1038
+
};
1039
+
1040
+
static struct clk_stm32_gate ck_icn_m_sdmmc3 = {
1041
+
.gate_id = GATE_SDMMC3,
1042
+
.hw.init = CLK_HW_INIT_INDEX("ck_icn_m_sdmmc3", ICN_SDMMC, &clk_stm32_gate_ops, 0),
1043
+
};
1044
+
1045
+
static struct clk_stm32_gate ck_ker_sdmmc1 = {
1046
+
.gate_id = GATE_SDMMC1,
1047
+
.hw.init = CLK_HW_INIT_INDEX("ck_ker_sdmmc1", FLEXGEN_51, &clk_stm32_gate_ops, 0),
1048
+
};
1049
+
1050
+
static struct clk_stm32_gate ck_ker_sdmmc2 = {
1051
+
.gate_id = GATE_SDMMC2,
1052
+
.hw.init = CLK_HW_INIT_INDEX("ck_ker_sdmmc2", FLEXGEN_52, &clk_stm32_gate_ops, 0),
1053
+
};
1054
+
1055
+
static struct clk_stm32_gate ck_ker_sdmmc3 = {
1056
+
.gate_id = GATE_SDMMC3,
1057
+
.hw.init = CLK_HW_INIT_INDEX("ck_ker_sdmmc3", FLEXGEN_53, &clk_stm32_gate_ops, 0),
1058
+
};
1059
+
1060
+
/* SPDIF */
1061
+
static struct clk_stm32_gate ck_icn_p_spdifrx = {
1062
+
.gate_id = GATE_SPDIFRX,
1063
+
.hw.init = CLK_HW_INIT_INDEX("ck_icn_p_spdifrx", ICN_APB1, &clk_stm32_gate_ops, 0),
1064
+
};
1065
+
1066
+
static struct clk_stm32_gate ck_ker_spdifrx = {
1067
+
.gate_id = GATE_SPDIFRX,
1068
+
.hw.init = CLK_HW_INIT_INDEX("ck_ker_spdifrx", FLEXGEN_11, &clk_stm32_gate_ops, 0),
1069
+
};
1070
+
1071
+
/* SPI */
1072
+
static struct clk_stm32_gate ck_icn_p_spi1 = {
1073
+
.gate_id = GATE_SPI1,
1074
+
.hw.init = CLK_HW_INIT_INDEX("ck_icn_p_spi1", ICN_APB2, &clk_stm32_gate_ops, 0),
1075
+
};
1076
+
1077
+
static struct clk_stm32_gate ck_icn_p_spi2 = {
1078
+
.gate_id = GATE_SPI2,
1079
+
.hw.init = CLK_HW_INIT_INDEX("ck_icn_p_spi2", ICN_APB1, &clk_stm32_gate_ops, 0),
1080
+
};
1081
+
1082
+
static struct clk_stm32_gate ck_icn_p_spi3 = {
1083
+
.gate_id = GATE_SPI3,
1084
+
.hw.init = CLK_HW_INIT_INDEX("ck_icn_p_spi3", ICN_APB1, &clk_stm32_gate_ops, 0),
1085
+
};
1086
+
1087
+
static struct clk_stm32_gate ck_icn_p_spi4 = {
1088
+
.gate_id = GATE_SPI4,
1089
+
.hw.init = CLK_HW_INIT_INDEX("ck_icn_p_spi4", ICN_APB2, &clk_stm32_gate_ops, 0),
1090
+
};
1091
+
1092
+
static struct clk_stm32_gate ck_icn_p_spi5 = {
1093
+
.gate_id = GATE_SPI5,
1094
+
.hw.init = CLK_HW_INIT_INDEX("ck_icn_p_spi5", ICN_APB2, &clk_stm32_gate_ops, 0),
1095
+
};
1096
+
1097
+
static struct clk_stm32_gate ck_icn_p_spi6 = {
1098
+
.gate_id = GATE_SPI6,
1099
+
.hw.init = CLK_HW_INIT_INDEX("ck_icn_p_spi6", ICN_APB2, &clk_stm32_gate_ops, 0),
1100
+
};
1101
+
1102
+
static struct clk_stm32_gate ck_icn_p_spi7 = {
1103
+
.gate_id = GATE_SPI7,
1104
+
.hw.init = CLK_HW_INIT_INDEX("ck_icn_p_spi7", ICN_APB2, &clk_stm32_gate_ops, 0),
1105
+
};
1106
+
1107
+
static struct clk_stm32_gate ck_icn_p_spi8 = {
1108
+
.gate_id = GATE_SPI8,
1109
+
.hw.init = CLK_HW_INIT_INDEX("ck_icn_p_spi8", ICN_LS_MCU, &clk_stm32_gate_ops, 0),
1110
+
};
1111
+
1112
+
static struct clk_stm32_gate ck_ker_spi1 = {
1113
+
.gate_id = GATE_SPI1,
1114
+
.hw.init = CLK_HW_INIT_INDEX("ck_ker_spi1", FLEXGEN_16, &clk_stm32_gate_ops,
1115
+
CLK_SET_RATE_PARENT),
1116
+
};
1117
+
1118
+
static struct clk_stm32_gate ck_ker_spi2 = {
1119
+
.gate_id = GATE_SPI2,
1120
+
.hw.init = CLK_HW_INIT_INDEX("ck_ker_spi2", FLEXGEN_10, &clk_stm32_gate_ops,
1121
+
CLK_SET_RATE_PARENT),
1122
+
};
1123
+
1124
+
static struct clk_stm32_gate ck_ker_spi3 = {
1125
+
.gate_id = GATE_SPI3,
1126
+
.hw.init = CLK_HW_INIT_INDEX("ck_ker_spi3", FLEXGEN_10, &clk_stm32_gate_ops,
1127
+
CLK_SET_RATE_PARENT),
1128
+
};
1129
+
1130
+
static struct clk_stm32_gate ck_ker_spi4 = {
1131
+
.gate_id = GATE_SPI4,
1132
+
.hw.init = CLK_HW_INIT_INDEX("ck_ker_spi4", FLEXGEN_17, &clk_stm32_gate_ops, 0),
1133
+
};
1134
+
1135
+
static struct clk_stm32_gate ck_ker_spi5 = {
1136
+
.gate_id = GATE_SPI5,
1137
+
.hw.init = CLK_HW_INIT_INDEX("ck_ker_spi5", FLEXGEN_17, &clk_stm32_gate_ops, 0),
1138
+
};
1139
+
1140
+
static struct clk_stm32_gate ck_ker_spi6 = {
1141
+
.gate_id = GATE_SPI6,
1142
+
.hw.init = CLK_HW_INIT_INDEX("ck_ker_spi6", FLEXGEN_18, &clk_stm32_gate_ops, 0),
1143
+
};
1144
+
1145
+
static struct clk_stm32_gate ck_ker_spi7 = {
1146
+
.gate_id = GATE_SPI7,
1147
+
.hw.init = CLK_HW_INIT_INDEX("ck_ker_spi7", FLEXGEN_18, &clk_stm32_gate_ops, 0),
1148
+
};
1149
+
1150
+
static struct clk_stm32_gate ck_ker_spi8 = {
1151
+
.gate_id = GATE_SPI8,
1152
+
.hw.init = CLK_HW_INIT_INDEX("ck_ker_spi8", FLEXGEN_37, &clk_stm32_gate_ops, 0),
1153
+
};
1154
+
1155
+
/* Timers */
1156
+
static struct clk_stm32_gate ck_icn_p_tim2 = {
1157
+
.gate_id = GATE_TIM2,
1158
+
.hw.init = CLK_HW_INIT_INDEX("ck_icn_p_tim2", ICN_APB1, &clk_stm32_gate_ops, 0),
1159
+
};
1160
+
1161
+
static struct clk_stm32_gate ck_icn_p_tim3 = {
1162
+
.gate_id = GATE_TIM3,
1163
+
.hw.init = CLK_HW_INIT_INDEX("ck_icn_p_tim3", ICN_APB1, &clk_stm32_gate_ops, 0),
1164
+
};
1165
+
1166
+
static struct clk_stm32_gate ck_icn_p_tim4 = {
1167
+
.gate_id = GATE_TIM4,
1168
+
.hw.init = CLK_HW_INIT_INDEX("ck_icn_p_tim4", ICN_APB1, &clk_stm32_gate_ops, 0),
1169
+
};
1170
+
1171
+
static struct clk_stm32_gate ck_icn_p_tim5 = {
1172
+
.gate_id = GATE_TIM5,
1173
+
.hw.init = CLK_HW_INIT_INDEX("ck_icn_p_tim5", ICN_APB1, &clk_stm32_gate_ops, 0),
1174
+
};
1175
+
1176
+
static struct clk_stm32_gate ck_icn_p_tim6 = {
1177
+
.gate_id = GATE_TIM6,
1178
+
.hw.init = CLK_HW_INIT_INDEX("ck_icn_p_tim6", ICN_APB1, &clk_stm32_gate_ops, 0),
1179
+
};
1180
+
1181
+
static struct clk_stm32_gate ck_icn_p_tim7 = {
1182
+
.gate_id = GATE_TIM7,
1183
+
.hw.init = CLK_HW_INIT_INDEX("ck_icn_p_tim7", ICN_APB1, &clk_stm32_gate_ops, 0),
1184
+
};
1185
+
1186
+
static struct clk_stm32_gate ck_icn_p_tim10 = {
1187
+
.gate_id = GATE_TIM10,
1188
+
.hw.init = CLK_HW_INIT_INDEX("ck_icn_p_tim10", ICN_APB1, &clk_stm32_gate_ops, 0),
1189
+
};
1190
+
1191
+
static struct clk_stm32_gate ck_icn_p_tim11 = {
1192
+
.gate_id = GATE_TIM11,
1193
+
.hw.init = CLK_HW_INIT_INDEX("ck_icn_p_tim11", ICN_APB1, &clk_stm32_gate_ops, 0),
1194
+
};
1195
+
1196
+
static struct clk_stm32_gate ck_icn_p_tim12 = {
1197
+
.gate_id = GATE_TIM12,
1198
+
.hw.init = CLK_HW_INIT_INDEX("ck_icn_p_tim12", ICN_APB1, &clk_stm32_gate_ops, 0),
1199
+
};
1200
+
1201
+
static struct clk_stm32_gate ck_icn_p_tim13 = {
1202
+
.gate_id = GATE_TIM13,
1203
+
.hw.init = CLK_HW_INIT_INDEX("ck_icn_p_tim13", ICN_APB1, &clk_stm32_gate_ops, 0),
1204
+
};
1205
+
1206
+
static struct clk_stm32_gate ck_icn_p_tim14 = {
1207
+
.gate_id = GATE_TIM14,
1208
+
.hw.init = CLK_HW_INIT_INDEX("ck_icn_p_tim14", ICN_APB1, &clk_stm32_gate_ops, 0),
1209
+
};
1210
+
1211
+
static struct clk_stm32_gate ck_icn_p_tim1 = {
1212
+
.gate_id = GATE_TIM1,
1213
+
.hw.init = CLK_HW_INIT_INDEX("ck_icn_p_tim1", ICN_APB2, &clk_stm32_gate_ops, 0),
1214
+
};
1215
+
1216
+
static struct clk_stm32_gate ck_icn_p_tim8 = {
1217
+
.gate_id = GATE_TIM8,
1218
+
.hw.init = CLK_HW_INIT_INDEX("ck_icn_p_tim8", ICN_APB2, &clk_stm32_gate_ops, 0),
1219
+
};
1220
+
1221
+
static struct clk_stm32_gate ck_icn_p_tim15 = {
1222
+
.gate_id = GATE_TIM15,
1223
+
.hw.init = CLK_HW_INIT_INDEX("ck_icn_p_tim15", ICN_APB2, &clk_stm32_gate_ops, 0),
1224
+
};
1225
+
1226
+
static struct clk_stm32_gate ck_icn_p_tim16 = {
1227
+
.gate_id = GATE_TIM16,
1228
+
.hw.init = CLK_HW_INIT_INDEX("ck_icn_p_tim16", ICN_APB2, &clk_stm32_gate_ops, 0),
1229
+
};
1230
+
1231
+
static struct clk_stm32_gate ck_icn_p_tim17 = {
1232
+
.gate_id = GATE_TIM17,
1233
+
.hw.init = CLK_HW_INIT_INDEX("ck_icn_p_tim17", ICN_APB2, &clk_stm32_gate_ops, 0),
1234
+
};
1235
+
1236
+
static struct clk_stm32_gate ck_icn_p_tim20 = {
1237
+
.gate_id = GATE_TIM20,
1238
+
.hw.init = CLK_HW_INIT_INDEX("ck_icn_p_tim20", ICN_APB2, &clk_stm32_gate_ops, 0),
1239
+
};
1240
+
1241
+
static struct clk_stm32_gate ck_ker_tim2 = {
1242
+
.gate_id = GATE_TIM2,
1243
+
.hw.init = CLK_HW_INIT_INDEX("ck_ker_tim2", TIMG1, &clk_stm32_gate_ops, 0),
1244
+
};
1245
+
1246
+
static struct clk_stm32_gate ck_ker_tim3 = {
1247
+
.gate_id = GATE_TIM3,
1248
+
.hw.init = CLK_HW_INIT_INDEX("ck_ker_tim3", TIMG1, &clk_stm32_gate_ops, 0),
1249
+
};
1250
+
1251
+
static struct clk_stm32_gate ck_ker_tim4 = {
1252
+
.gate_id = GATE_TIM4,
1253
+
.hw.init = CLK_HW_INIT_INDEX("ck_ker_tim4", TIMG1, &clk_stm32_gate_ops, 0),
1254
+
};
1255
+
1256
+
static struct clk_stm32_gate ck_ker_tim5 = {
1257
+
.gate_id = GATE_TIM5,
1258
+
.hw.init = CLK_HW_INIT_INDEX("ck_ker_tim5", TIMG1, &clk_stm32_gate_ops, 0),
1259
+
};
1260
+
1261
+
static struct clk_stm32_gate ck_ker_tim6 = {
1262
+
.gate_id = GATE_TIM6,
1263
+
.hw.init = CLK_HW_INIT_INDEX("ck_ker_tim6", TIMG1, &clk_stm32_gate_ops, 0),
1264
+
};
1265
+
1266
+
static struct clk_stm32_gate ck_ker_tim7 = {
1267
+
.gate_id = GATE_TIM7,
1268
+
.hw.init = CLK_HW_INIT_INDEX("ck_ker_tim7", TIMG1, &clk_stm32_gate_ops, 0),
1269
+
};
1270
+
1271
+
static struct clk_stm32_gate ck_ker_tim10 = {
1272
+
.gate_id = GATE_TIM10,
1273
+
.hw.init = CLK_HW_INIT_INDEX("ck_ker_tim10", TIMG1, &clk_stm32_gate_ops, 0),
1274
+
};
1275
+
1276
+
static struct clk_stm32_gate ck_ker_tim11 = {
1277
+
.gate_id = GATE_TIM11,
1278
+
.hw.init = CLK_HW_INIT_INDEX("ck_ker_tim11", TIMG1, &clk_stm32_gate_ops, 0),
1279
+
};
1280
+
1281
+
static struct clk_stm32_gate ck_ker_tim12 = {
1282
+
.gate_id = GATE_TIM12,
1283
+
.hw.init = CLK_HW_INIT_INDEX("ck_ker_tim12", TIMG1, &clk_stm32_gate_ops, 0),
1284
+
};
1285
+
1286
+
static struct clk_stm32_gate ck_ker_tim13 = {
1287
+
.gate_id = GATE_TIM13,
1288
+
.hw.init = CLK_HW_INIT_INDEX("ck_ker_tim13", TIMG1, &clk_stm32_gate_ops, 0),
1289
+
};
1290
+
1291
+
static struct clk_stm32_gate ck_ker_tim14 = {
1292
+
.gate_id = GATE_TIM14,
1293
+
.hw.init = CLK_HW_INIT_INDEX("ck_ker_tim14", TIMG1, &clk_stm32_gate_ops, 0),
1294
+
};
1295
+
1296
+
static struct clk_stm32_gate ck_ker_tim1 = {
1297
+
.gate_id = GATE_TIM1,
1298
+
.hw.init = CLK_HW_INIT_INDEX("ck_ker_tim1", TIMG2, &clk_stm32_gate_ops, 0),
1299
+
};
1300
+
1301
+
static struct clk_stm32_gate ck_ker_tim8 = {
1302
+
.gate_id = GATE_TIM8,
1303
+
.hw.init = CLK_HW_INIT_INDEX("ck_ker_tim8", TIMG2, &clk_stm32_gate_ops, 0),
1304
+
};
1305
+
1306
+
static struct clk_stm32_gate ck_ker_tim15 = {
1307
+
.gate_id = GATE_TIM15,
1308
+
.hw.init = CLK_HW_INIT_INDEX("ck_ker_tim15", TIMG2, &clk_stm32_gate_ops, 0),
1309
+
};
1310
+
1311
+
static struct clk_stm32_gate ck_ker_tim16 = {
1312
+
.gate_id = GATE_TIM16,
1313
+
.hw.init = CLK_HW_INIT_INDEX("ck_ker_tim16", TIMG2, &clk_stm32_gate_ops, 0),
1314
+
};
1315
+
1316
+
static struct clk_stm32_gate ck_ker_tim17 = {
1317
+
.gate_id = GATE_TIM17,
1318
+
.hw.init = CLK_HW_INIT_INDEX("ck_ker_tim17", TIMG2, &clk_stm32_gate_ops, 0),
1319
+
};
1320
+
1321
+
static struct clk_stm32_gate ck_ker_tim20 = {
1322
+
.gate_id = GATE_TIM20,
1323
+
.hw.init = CLK_HW_INIT_INDEX("ck_ker_tim20", TIMG2, &clk_stm32_gate_ops, 0),
1324
+
};
1325
+
1326
+
/* UART/USART */
1327
+
static struct clk_stm32_gate ck_icn_p_usart2 = {
1328
+
.gate_id = GATE_USART2,
1329
+
.hw.init = CLK_HW_INIT_INDEX("ck_icn_p_usart2", ICN_APB1, &clk_stm32_gate_ops, 0),
1330
+
};
1331
+
1332
+
static struct clk_stm32_gate ck_icn_p_usart3 = {
1333
+
.gate_id = GATE_USART3,
1334
+
.hw.init = CLK_HW_INIT_INDEX("ck_icn_p_usart3", ICN_APB1, &clk_stm32_gate_ops, 0),
1335
+
};
1336
+
1337
+
static struct clk_stm32_gate ck_icn_p_uart4 = {
1338
+
.gate_id = GATE_UART4,
1339
+
.hw.init = CLK_HW_INIT_INDEX("ck_icn_p_uart4", ICN_APB1, &clk_stm32_gate_ops, 0),
1340
+
};
1341
+
1342
+
static struct clk_stm32_gate ck_icn_p_uart5 = {
1343
+
.gate_id = GATE_UART5,
1344
+
.hw.init = CLK_HW_INIT_INDEX("ck_icn_p_uart5", ICN_APB1, &clk_stm32_gate_ops, 0),
1345
+
};
1346
+
1347
+
static struct clk_stm32_gate ck_icn_p_usart1 = {
1348
+
.gate_id = GATE_USART1,
1349
+
.hw.init = CLK_HW_INIT_INDEX("ck_icn_p_usart1", ICN_APB2, &clk_stm32_gate_ops, 0),
1350
+
};
1351
+
1352
+
static struct clk_stm32_gate ck_icn_p_usart6 = {
1353
+
.gate_id = GATE_USART6,
1354
+
.hw.init = CLK_HW_INIT_INDEX("ck_icn_p_usart6", ICN_APB2, &clk_stm32_gate_ops, 0),
1355
+
};
1356
+
1357
+
static struct clk_stm32_gate ck_icn_p_uart7 = {
1358
+
.gate_id = GATE_UART7,
1359
+
.hw.init = CLK_HW_INIT_INDEX("ck_icn_p_uart7", ICN_APB2, &clk_stm32_gate_ops, 0),
1360
+
};
1361
+
1362
+
static struct clk_stm32_gate ck_icn_p_uart8 = {
1363
+
.gate_id = GATE_UART8,
1364
+
.hw.init = CLK_HW_INIT_INDEX("ck_icn_p_uart8", ICN_APB2, &clk_stm32_gate_ops, 0),
1365
+
};
1366
+
1367
+
static struct clk_stm32_gate ck_icn_p_uart9 = {
1368
+
.gate_id = GATE_UART9,
1369
+
.hw.init = CLK_HW_INIT_INDEX("ck_icn_p_uart9", ICN_APB2, &clk_stm32_gate_ops, 0),
1370
+
};
1371
+
1372
+
static struct clk_stm32_gate ck_ker_usart2 = {
1373
+
.gate_id = GATE_USART2,
1374
+
.hw.init = CLK_HW_INIT_INDEX("ck_ker_usart2", FLEXGEN_08, &clk_stm32_gate_ops, 0),
1375
+
};
1376
+
1377
+
static struct clk_stm32_gate ck_ker_uart4 = {
1378
+
.gate_id = GATE_UART4,
1379
+
.hw.init = CLK_HW_INIT_INDEX("ck_ker_uart4", FLEXGEN_08, &clk_stm32_gate_ops, 0),
1380
+
};
1381
+
1382
+
static struct clk_stm32_gate ck_ker_usart3 = {
1383
+
.gate_id = GATE_USART3,
1384
+
.hw.init = CLK_HW_INIT_INDEX("ck_ker_usart3", FLEXGEN_09, &clk_stm32_gate_ops, 0),
1385
+
};
1386
+
1387
+
static struct clk_stm32_gate ck_ker_uart5 = {
1388
+
.gate_id = GATE_UART5,
1389
+
.hw.init = CLK_HW_INIT_INDEX("ck_ker_uart5", FLEXGEN_09, &clk_stm32_gate_ops, 0),
1390
+
};
1391
+
1392
+
static struct clk_stm32_gate ck_ker_usart1 = {
1393
+
.gate_id = GATE_USART1,
1394
+
.hw.init = CLK_HW_INIT_INDEX("ck_ker_usart1", FLEXGEN_19, &clk_stm32_gate_ops, 0),
1395
+
};
1396
+
1397
+
static struct clk_stm32_gate ck_ker_usart6 = {
1398
+
.gate_id = GATE_USART6,
1399
+
.hw.init = CLK_HW_INIT_INDEX("ck_ker_usart6", FLEXGEN_20, &clk_stm32_gate_ops, 0),
1400
+
};
1401
+
1402
+
static struct clk_stm32_gate ck_ker_uart7 = {
1403
+
.gate_id = GATE_UART7,
1404
+
.hw.init = CLK_HW_INIT_INDEX("ck_ker_uart7", FLEXGEN_21, &clk_stm32_gate_ops, 0),
1405
+
};
1406
+
1407
+
static struct clk_stm32_gate ck_ker_uart8 = {
1408
+
.gate_id = GATE_UART8,
1409
+
.hw.init = CLK_HW_INIT_INDEX("ck_ker_uart8", FLEXGEN_21, &clk_stm32_gate_ops, 0),
1410
+
};
1411
+
1412
+
static struct clk_stm32_gate ck_ker_uart9 = {
1413
+
.gate_id = GATE_UART9,
1414
+
.hw.init = CLK_HW_INIT_INDEX("ck_ker_uart9", FLEXGEN_22, &clk_stm32_gate_ops, 0),
1415
+
};
1416
+
1417
+
/* USB2PHY1 */
1418
+
static struct clk_stm32_composite ck_ker_usb2phy1 = {
1419
+
.gate_id = GATE_USB2PHY1,
1420
+
.mux_id = MUX_USB2PHY1,
1421
+
.div_id = NO_STM32_DIV,
1422
+
.hw.init = CLK_HW_INIT_PARENTS_DATA("ck_ker_usb2phy1", usb2phy1_src,
1423
+
&clk_stm32_composite_ops, 0),
1424
+
};
1425
+
1426
+
/* USB2H */
1427
+
static struct clk_stm32_gate ck_icn_m_usb2ehci = {
1428
+
.gate_id = GATE_USBH,
1429
+
.hw.init = CLK_HW_INIT_INDEX("ck_icn_m_usb2ehci", ICN_HSL, &clk_stm32_gate_ops, 0),
1430
+
};
1431
+
1432
+
static struct clk_stm32_gate ck_icn_m_usb2ohci = {
1433
+
.gate_id = GATE_USBH,
1434
+
.hw.init = CLK_HW_INIT_INDEX("ck_icn_m_usb2ohci", ICN_HSL, &clk_stm32_gate_ops, 0),
1435
+
};
1436
+
1437
+
/* USB2PHY2 */
1438
+
static struct clk_stm32_composite ck_ker_usb2phy2_en = {
1439
+
.gate_id = GATE_USB2PHY2,
1440
+
.mux_id = MUX_USB2PHY2,
1441
+
.div_id = NO_STM32_DIV,
1442
+
.hw.init = CLK_HW_INIT_PARENTS_DATA("ck_ker_usb2phy2_en", usb2phy2_src,
1443
+
&clk_stm32_composite_ops, 0),
1444
+
};
1445
+
1446
+
/* USB3 PCIe COMBOPHY */
1447
+
static struct clk_stm32_gate ck_icn_p_usb3pciephy = {
1448
+
.gate_id = GATE_USB3PCIEPHY,
1449
+
.hw.init = CLK_HW_INIT_INDEX("ck_icn_p_usb3pciephy", ICN_APB4, &clk_stm32_gate_ops, 0),
1450
+
};
1451
+
1452
+
static struct clk_stm32_composite ck_ker_usb3pciephy = {
1453
+
.gate_id = GATE_USB3PCIEPHY,
1454
+
.mux_id = MUX_USB3PCIEPHY,
1455
+
.div_id = NO_STM32_DIV,
1456
+
.hw.init = CLK_HW_INIT_PARENTS_DATA("ck_ker_usb3pciephy", usb3pciphy_src,
1457
+
&clk_stm32_composite_ops, 0),
1458
+
};
1459
+
1460
+
/* USB3 DRD */
1461
+
static struct clk_stm32_gate ck_icn_m_usb3dr = {
1462
+
.gate_id = GATE_USB3DR,
1463
+
.hw.init = CLK_HW_INIT_INDEX("ck_icn_m_usb3dr", ICN_HSL, &clk_stm32_gate_ops, 0),
1464
+
};
1465
+
1466
+
static struct clk_stm32_gate ck_ker_usb2phy2 = {
1467
+
.gate_id = GATE_USB3DR,
1468
+
.hw.init = CLK_HW_INIT_INDEX("ck_ker_usb2phy2", FLEXGEN_58, &clk_stm32_gate_ops, 0),
1469
+
};
1470
+
1471
+
/* USBTC */
1472
+
static struct clk_stm32_gate ck_icn_p_usbtc = {
1473
+
.gate_id = GATE_USBTC,
1474
+
.hw.init = CLK_HW_INIT_INDEX("ck_icn_p_usbtc", ICN_APB4, &clk_stm32_gate_ops, 0),
1475
+
};
1476
+
1477
+
static struct clk_stm32_gate ck_ker_usbtc = {
1478
+
.gate_id = GATE_USBTC,
1479
+
.hw.init = CLK_HW_INIT_INDEX("ck_ker_usbtc", FLEXGEN_35, &clk_stm32_gate_ops, 0),
1480
+
};
1481
+
1482
+
/* VDEC / VENC */
1483
+
static struct clk_stm32_gate ck_icn_p_vdec = {
1484
+
.gate_id = GATE_VDEC,
1485
+
.hw.init = CLK_HW_INIT_INDEX("ck_icn_p_vdec", ICN_APB4, &clk_stm32_gate_ops, 0),
1486
+
};
1487
+
1488
+
static struct clk_stm32_gate ck_icn_p_venc = {
1489
+
.gate_id = GATE_VENC,
1490
+
.hw.init = CLK_HW_INIT_INDEX("ck_icn_p_venc", ICN_APB4, &clk_stm32_gate_ops, 0),
1491
+
};
1492
+
1493
+
/* VREF */
1494
+
static struct clk_stm32_gate ck_icn_p_vref = {
1495
+
.gate_id = GATE_VREF,
1496
+
.hw.init = CLK_HW_INIT_INDEX("ck_icn_p_vref", ICN_APB3, &clk_stm32_gate_ops, 0),
1497
+
};
1498
+
1499
+
/* WWDG */
1500
+
static struct clk_stm32_gate ck_icn_p_wwdg1 = {
1501
+
.gate_id = GATE_WWDG1,
1502
+
.hw.init = CLK_HW_INIT_INDEX("ck_icn_p_wwdg1", ICN_APB3, &clk_stm32_gate_ops, 0),
1503
+
};
1504
+
1505
+
static struct clk_stm32_gate ck_icn_p_wwdg2 = {
1506
+
.gate_id = GATE_WWDG2,
1507
+
.hw.init = CLK_HW_INIT_INDEX("ck_icn_p_wwdg2", ICN_LS_MCU, &clk_stm32_gate_ops, 0),
1508
+
};
1509
+
1510
+
#define SECF_NONE -1
1511
+
1512
+
static const struct clock_config stm32mp25_clock_cfg[] = {
1513
+
STM32_GATE_CFG(CK_BUS_ETH1, ck_icn_p_eth1, SECF_NONE),
1514
+
STM32_GATE_CFG(CK_BUS_ETH2, ck_icn_p_eth2, SECF_NONE),
1515
+
STM32_GATE_CFG(CK_BUS_PCIE, ck_icn_p_pcie, SECF_NONE),
1516
+
STM32_GATE_CFG(CK_BUS_ETHSW, ck_icn_p_ethsw, SECF_NONE),
1517
+
STM32_GATE_CFG(CK_BUS_ADC12, ck_icn_p_adc12, SECF_NONE),
1518
+
STM32_GATE_CFG(CK_BUS_ADC3, ck_icn_p_adc3, SECF_NONE),
1519
+
STM32_GATE_CFG(CK_BUS_CCI, ck_icn_p_cci, SECF_NONE),
1520
+
STM32_GATE_CFG(CK_BUS_CRC, ck_icn_p_crc, SECF_NONE),
1521
+
STM32_GATE_CFG(CK_BUS_MDF1, ck_icn_p_mdf1, SECF_NONE),
1522
+
STM32_GATE_CFG(CK_BUS_OSPIIOM, ck_icn_p_ospiiom, SECF_NONE),
1523
+
STM32_GATE_CFG(CK_BUS_HASH, ck_icn_p_hash, SECF_NONE),
1524
+
STM32_GATE_CFG(CK_BUS_CRYP1, ck_icn_p_cryp1, SECF_NONE),
1525
+
STM32_GATE_CFG(CK_BUS_CRYP2, ck_icn_p_cryp2, SECF_NONE),
1526
+
STM32_GATE_CFG(CK_BUS_ADF1, ck_icn_p_adf1, SECF_NONE),
1527
+
STM32_GATE_CFG(CK_BUS_SPI8, ck_icn_p_spi8, SECF_NONE),
1528
+
STM32_GATE_CFG(CK_BUS_LPUART1, ck_icn_p_lpuart1, SECF_NONE),
1529
+
STM32_GATE_CFG(CK_BUS_I2C8, ck_icn_p_i2c8, SECF_NONE),
1530
+
STM32_GATE_CFG(CK_BUS_LPTIM3, ck_icn_p_lptim3, SECF_NONE),
1531
+
STM32_GATE_CFG(CK_BUS_LPTIM4, ck_icn_p_lptim4, SECF_NONE),
1532
+
STM32_GATE_CFG(CK_BUS_LPTIM5, ck_icn_p_lptim5, SECF_NONE),
1533
+
STM32_GATE_CFG(CK_BUS_IWDG5, ck_icn_p_iwdg5, SECF_NONE),
1534
+
STM32_GATE_CFG(CK_BUS_WWDG2, ck_icn_p_wwdg2, SECF_NONE),
1535
+
STM32_GATE_CFG(CK_BUS_I3C4, ck_icn_p_i3c4, SECF_NONE),
1536
+
STM32_GATE_CFG(CK_BUS_SDMMC1, ck_icn_m_sdmmc1, SECF_NONE),
1537
+
STM32_GATE_CFG(CK_BUS_SDMMC2, ck_icn_m_sdmmc2, SECF_NONE),
1538
+
STM32_GATE_CFG(CK_BUS_SDMMC3, ck_icn_m_sdmmc3, SECF_NONE),
1539
+
STM32_GATE_CFG(CK_BUS_USB2OHCI, ck_icn_m_usb2ohci, SECF_NONE),
1540
+
STM32_GATE_CFG(CK_BUS_USB2EHCI, ck_icn_m_usb2ehci, SECF_NONE),
1541
+
STM32_GATE_CFG(CK_BUS_USB3DR, ck_icn_m_usb3dr, SECF_NONE),
1542
+
STM32_GATE_CFG(CK_BUS_TIM2, ck_icn_p_tim2, SECF_NONE),
1543
+
STM32_GATE_CFG(CK_BUS_TIM3, ck_icn_p_tim3, SECF_NONE),
1544
+
STM32_GATE_CFG(CK_BUS_TIM4, ck_icn_p_tim4, SECF_NONE),
1545
+
STM32_GATE_CFG(CK_BUS_TIM5, ck_icn_p_tim5, SECF_NONE),
1546
+
STM32_GATE_CFG(CK_BUS_TIM6, ck_icn_p_tim6, SECF_NONE),
1547
+
STM32_GATE_CFG(CK_BUS_TIM7, ck_icn_p_tim7, SECF_NONE),
1548
+
STM32_GATE_CFG(CK_BUS_TIM10, ck_icn_p_tim10, SECF_NONE),
1549
+
STM32_GATE_CFG(CK_BUS_TIM11, ck_icn_p_tim11, SECF_NONE),
1550
+
STM32_GATE_CFG(CK_BUS_TIM12, ck_icn_p_tim12, SECF_NONE),
1551
+
STM32_GATE_CFG(CK_BUS_TIM13, ck_icn_p_tim13, SECF_NONE),
1552
+
STM32_GATE_CFG(CK_BUS_TIM14, ck_icn_p_tim14, SECF_NONE),
1553
+
STM32_GATE_CFG(CK_BUS_LPTIM1, ck_icn_p_lptim1, SECF_NONE),
1554
+
STM32_GATE_CFG(CK_BUS_LPTIM2, ck_icn_p_lptim2, SECF_NONE),
1555
+
STM32_GATE_CFG(CK_BUS_SPI2, ck_icn_p_spi2, SECF_NONE),
1556
+
STM32_GATE_CFG(CK_BUS_SPI3, ck_icn_p_spi3, SECF_NONE),
1557
+
STM32_GATE_CFG(CK_BUS_SPDIFRX, ck_icn_p_spdifrx, SECF_NONE),
1558
+
STM32_GATE_CFG(CK_BUS_USART2, ck_icn_p_usart2, SECF_NONE),
1559
+
STM32_GATE_CFG(CK_BUS_USART3, ck_icn_p_usart3, SECF_NONE),
1560
+
STM32_GATE_CFG(CK_BUS_UART4, ck_icn_p_uart4, SECF_NONE),
1561
+
STM32_GATE_CFG(CK_BUS_UART5, ck_icn_p_uart5, SECF_NONE),
1562
+
STM32_GATE_CFG(CK_BUS_I2C1, ck_icn_p_i2c1, SECF_NONE),
1563
+
STM32_GATE_CFG(CK_BUS_I2C2, ck_icn_p_i2c2, SECF_NONE),
1564
+
STM32_GATE_CFG(CK_BUS_I2C3, ck_icn_p_i2c3, SECF_NONE),
1565
+
STM32_GATE_CFG(CK_BUS_I2C4, ck_icn_p_i2c4, SECF_NONE),
1566
+
STM32_GATE_CFG(CK_BUS_I2C5, ck_icn_p_i2c5, SECF_NONE),
1567
+
STM32_GATE_CFG(CK_BUS_I2C6, ck_icn_p_i2c6, SECF_NONE),
1568
+
STM32_GATE_CFG(CK_BUS_I2C7, ck_icn_p_i2c7, SECF_NONE),
1569
+
STM32_GATE_CFG(CK_BUS_I3C1, ck_icn_p_i3c1, SECF_NONE),
1570
+
STM32_GATE_CFG(CK_BUS_I3C2, ck_icn_p_i3c2, SECF_NONE),
1571
+
STM32_GATE_CFG(CK_BUS_I3C3, ck_icn_p_i3c3, SECF_NONE),
1572
+
STM32_GATE_CFG(CK_BUS_TIM1, ck_icn_p_tim1, SECF_NONE),
1573
+
STM32_GATE_CFG(CK_BUS_TIM8, ck_icn_p_tim8, SECF_NONE),
1574
+
STM32_GATE_CFG(CK_BUS_TIM15, ck_icn_p_tim15, SECF_NONE),
1575
+
STM32_GATE_CFG(CK_BUS_TIM16, ck_icn_p_tim16, SECF_NONE),
1576
+
STM32_GATE_CFG(CK_BUS_TIM17, ck_icn_p_tim17, SECF_NONE),
1577
+
STM32_GATE_CFG(CK_BUS_TIM20, ck_icn_p_tim20, SECF_NONE),
1578
+
STM32_GATE_CFG(CK_BUS_SAI1, ck_icn_p_sai1, SECF_NONE),
1579
+
STM32_GATE_CFG(CK_BUS_SAI2, ck_icn_p_sai2, SECF_NONE),
1580
+
STM32_GATE_CFG(CK_BUS_SAI3, ck_icn_p_sai3, SECF_NONE),
1581
+
STM32_GATE_CFG(CK_BUS_SAI4, ck_icn_p_sai4, SECF_NONE),
1582
+
STM32_GATE_CFG(CK_BUS_USART1, ck_icn_p_usart1, SECF_NONE),
1583
+
STM32_GATE_CFG(CK_BUS_USART6, ck_icn_p_usart6, SECF_NONE),
1584
+
STM32_GATE_CFG(CK_BUS_UART7, ck_icn_p_uart7, SECF_NONE),
1585
+
STM32_GATE_CFG(CK_BUS_UART8, ck_icn_p_uart8, SECF_NONE),
1586
+
STM32_GATE_CFG(CK_BUS_UART9, ck_icn_p_uart9, SECF_NONE),
1587
+
STM32_GATE_CFG(CK_BUS_FDCAN, ck_icn_p_fdcan, SECF_NONE),
1588
+
STM32_GATE_CFG(CK_BUS_SPI1, ck_icn_p_spi1, SECF_NONE),
1589
+
STM32_GATE_CFG(CK_BUS_SPI4, ck_icn_p_spi4, SECF_NONE),
1590
+
STM32_GATE_CFG(CK_BUS_SPI5, ck_icn_p_spi5, SECF_NONE),
1591
+
STM32_GATE_CFG(CK_BUS_SPI6, ck_icn_p_spi6, SECF_NONE),
1592
+
STM32_GATE_CFG(CK_BUS_SPI7, ck_icn_p_spi7, SECF_NONE),
1593
+
STM32_GATE_CFG(CK_BUS_IWDG2, ck_icn_p_iwdg2, SECF_NONE),
1594
+
STM32_GATE_CFG(CK_BUS_IWDG3, ck_icn_p_iwdg3, SECF_NONE),
1595
+
STM32_GATE_CFG(CK_BUS_IWDG4, ck_icn_p_iwdg4, SECF_NONE),
1596
+
STM32_GATE_CFG(CK_BUS_WWDG1, ck_icn_p_wwdg1, SECF_NONE),
1597
+
STM32_GATE_CFG(CK_BUS_VREF, ck_icn_p_vref, SECF_NONE),
1598
+
STM32_GATE_CFG(CK_BUS_HDP, ck_icn_p_hdp, SECF_NONE),
1599
+
STM32_GATE_CFG(CK_BUS_IS2M, ck_icn_p_is2m, SECF_NONE),
1600
+
STM32_GATE_CFG(CK_BUS_DSI, ck_icn_p_dsi, SECF_NONE),
1601
+
STM32_GATE_CFG(CK_BUS_LTDC, ck_icn_p_ltdc, SECF_NONE),
1602
+
STM32_GATE_CFG(CK_BUS_CSI, ck_icn_p_csi, SECF_NONE),
1603
+
STM32_GATE_CFG(CK_BUS_DCMIPP, ck_icn_p_dcmipp, SECF_NONE),
1604
+
STM32_GATE_CFG(CK_BUS_LVDS, ck_icn_p_lvds, SECF_NONE),
1605
+
STM32_GATE_CFG(CK_BUS_USBTC, ck_icn_p_usbtc, SECF_NONE),
1606
+
STM32_GATE_CFG(CK_BUS_USB3PCIEPHY, ck_icn_p_usb3pciephy, SECF_NONE),
1607
+
STM32_GATE_CFG(CK_BUS_VDEC, ck_icn_p_vdec, SECF_NONE),
1608
+
STM32_GATE_CFG(CK_BUS_VENC, ck_icn_p_venc, SECF_NONE),
1609
+
STM32_GATE_CFG(CK_KER_TIM2, ck_ker_tim2, SECF_NONE),
1610
+
STM32_GATE_CFG(CK_KER_TIM3, ck_ker_tim3, SECF_NONE),
1611
+
STM32_GATE_CFG(CK_KER_TIM4, ck_ker_tim4, SECF_NONE),
1612
+
STM32_GATE_CFG(CK_KER_TIM5, ck_ker_tim5, SECF_NONE),
1613
+
STM32_GATE_CFG(CK_KER_TIM6, ck_ker_tim6, SECF_NONE),
1614
+
STM32_GATE_CFG(CK_KER_TIM7, ck_ker_tim7, SECF_NONE),
1615
+
STM32_GATE_CFG(CK_KER_TIM10, ck_ker_tim10, SECF_NONE),
1616
+
STM32_GATE_CFG(CK_KER_TIM11, ck_ker_tim11, SECF_NONE),
1617
+
STM32_GATE_CFG(CK_KER_TIM12, ck_ker_tim12, SECF_NONE),
1618
+
STM32_GATE_CFG(CK_KER_TIM13, ck_ker_tim13, SECF_NONE),
1619
+
STM32_GATE_CFG(CK_KER_TIM14, ck_ker_tim14, SECF_NONE),
1620
+
STM32_GATE_CFG(CK_KER_TIM1, ck_ker_tim1, SECF_NONE),
1621
+
STM32_GATE_CFG(CK_KER_TIM8, ck_ker_tim8, SECF_NONE),
1622
+
STM32_GATE_CFG(CK_KER_TIM15, ck_ker_tim15, SECF_NONE),
1623
+
STM32_GATE_CFG(CK_KER_TIM16, ck_ker_tim16, SECF_NONE),
1624
+
STM32_GATE_CFG(CK_KER_TIM17, ck_ker_tim17, SECF_NONE),
1625
+
STM32_GATE_CFG(CK_KER_TIM20, ck_ker_tim20, SECF_NONE),
1626
+
STM32_GATE_CFG(CK_KER_LPTIM1, ck_ker_lptim1, SECF_NONE),
1627
+
STM32_GATE_CFG(CK_KER_LPTIM2, ck_ker_lptim2, SECF_NONE),
1628
+
STM32_GATE_CFG(CK_KER_USART2, ck_ker_usart2, SECF_NONE),
1629
+
STM32_GATE_CFG(CK_KER_UART4, ck_ker_uart4, SECF_NONE),
1630
+
STM32_GATE_CFG(CK_KER_USART3, ck_ker_usart3, SECF_NONE),
1631
+
STM32_GATE_CFG(CK_KER_UART5, ck_ker_uart5, SECF_NONE),
1632
+
STM32_GATE_CFG(CK_KER_SPI2, ck_ker_spi2, SECF_NONE),
1633
+
STM32_GATE_CFG(CK_KER_SPI3, ck_ker_spi3, SECF_NONE),
1634
+
STM32_GATE_CFG(CK_KER_SPDIFRX, ck_ker_spdifrx, SECF_NONE),
1635
+
STM32_GATE_CFG(CK_KER_I2C1, ck_ker_i2c1, SECF_NONE),
1636
+
STM32_GATE_CFG(CK_KER_I2C2, ck_ker_i2c2, SECF_NONE),
1637
+
STM32_GATE_CFG(CK_KER_I3C1, ck_ker_i3c1, SECF_NONE),
1638
+
STM32_GATE_CFG(CK_KER_I3C2, ck_ker_i3c2, SECF_NONE),
1639
+
STM32_GATE_CFG(CK_KER_I2C3, ck_ker_i2c3, SECF_NONE),
1640
+
STM32_GATE_CFG(CK_KER_I2C5, ck_ker_i2c5, SECF_NONE),
1641
+
STM32_GATE_CFG(CK_KER_I3C3, ck_ker_i3c3, SECF_NONE),
1642
+
STM32_GATE_CFG(CK_KER_I2C4, ck_ker_i2c4, SECF_NONE),
1643
+
STM32_GATE_CFG(CK_KER_I2C6, ck_ker_i2c6, SECF_NONE),
1644
+
STM32_GATE_CFG(CK_KER_I2C7, ck_ker_i2c7, SECF_NONE),
1645
+
STM32_GATE_CFG(CK_KER_SPI1, ck_ker_spi1, SECF_NONE),
1646
+
STM32_GATE_CFG(CK_KER_SPI4, ck_ker_spi4, SECF_NONE),
1647
+
STM32_GATE_CFG(CK_KER_SPI5, ck_ker_spi5, SECF_NONE),
1648
+
STM32_GATE_CFG(CK_KER_SPI6, ck_ker_spi6, SECF_NONE),
1649
+
STM32_GATE_CFG(CK_KER_SPI7, ck_ker_spi7, SECF_NONE),
1650
+
STM32_GATE_CFG(CK_KER_USART1, ck_ker_usart1, SECF_NONE),
1651
+
STM32_GATE_CFG(CK_KER_USART6, ck_ker_usart6, SECF_NONE),
1652
+
STM32_GATE_CFG(CK_KER_UART7, ck_ker_uart7, SECF_NONE),
1653
+
STM32_GATE_CFG(CK_KER_UART8, ck_ker_uart8, SECF_NONE),
1654
+
STM32_GATE_CFG(CK_KER_UART9, ck_ker_uart9, SECF_NONE),
1655
+
STM32_GATE_CFG(CK_KER_MDF1, ck_ker_mdf1, SECF_NONE),
1656
+
STM32_GATE_CFG(CK_KER_SAI1, ck_ker_sai1, SECF_NONE),
1657
+
STM32_GATE_CFG(CK_KER_SAI2, ck_ker_sai2, SECF_NONE),
1658
+
STM32_GATE_CFG(CK_KER_SAI3, ck_ker_sai3, SECF_NONE),
1659
+
STM32_GATE_CFG(CK_KER_SAI4, ck_ker_sai4, SECF_NONE),
1660
+
STM32_GATE_CFG(CK_KER_FDCAN, ck_ker_fdcan, SECF_NONE),
1661
+
STM32_GATE_CFG(CK_KER_CSI, ck_ker_csi, SECF_NONE),
1662
+
STM32_GATE_CFG(CK_KER_CSITXESC, ck_ker_csitxesc, SECF_NONE),
1663
+
STM32_GATE_CFG(CK_KER_CSIPHY, ck_ker_csiphy, SECF_NONE),
1664
+
STM32_GATE_CFG(CK_KER_USBTC, ck_ker_usbtc, SECF_NONE),
1665
+
STM32_GATE_CFG(CK_KER_I3C4, ck_ker_i3c4, SECF_NONE),
1666
+
STM32_GATE_CFG(CK_KER_SPI8, ck_ker_spi8, SECF_NONE),
1667
+
STM32_GATE_CFG(CK_KER_I2C8, ck_ker_i2c8, SECF_NONE),
1668
+
STM32_GATE_CFG(CK_KER_LPUART1, ck_ker_lpuart1, SECF_NONE),
1669
+
STM32_GATE_CFG(CK_KER_LPTIM3, ck_ker_lptim3, SECF_NONE),
1670
+
STM32_GATE_CFG(CK_KER_LPTIM4, ck_ker_lptim4, SECF_NONE),
1671
+
STM32_GATE_CFG(CK_KER_LPTIM5, ck_ker_lptim5, SECF_NONE),
1672
+
STM32_GATE_CFG(CK_KER_ADF1, ck_ker_adf1, SECF_NONE),
1673
+
STM32_GATE_CFG(CK_KER_SDMMC1, ck_ker_sdmmc1, SECF_NONE),
1674
+
STM32_GATE_CFG(CK_KER_SDMMC2, ck_ker_sdmmc2, SECF_NONE),
1675
+
STM32_GATE_CFG(CK_KER_SDMMC3, ck_ker_sdmmc3, SECF_NONE),
1676
+
STM32_GATE_CFG(CK_KER_ETH1, ck_ker_eth1, SECF_NONE),
1677
+
STM32_GATE_CFG(CK_ETH1_STP, ck_ker_eth1stp, SECF_NONE),
1678
+
STM32_GATE_CFG(CK_KER_ETHSW, ck_ker_ethsw, SECF_NONE),
1679
+
STM32_GATE_CFG(CK_KER_ETH2, ck_ker_eth2, SECF_NONE),
1680
+
STM32_GATE_CFG(CK_ETH2_STP, ck_ker_eth2stp, SECF_NONE),
1681
+
STM32_GATE_CFG(CK_KER_ETH1PTP, ck_ker_eth1ptp, SECF_NONE),
1682
+
STM32_GATE_CFG(CK_KER_ETH2PTP, ck_ker_eth2ptp, SECF_NONE),
1683
+
STM32_GATE_CFG(CK_BUS_GPU, ck_icn_m_gpu, SECF_NONE),
1684
+
STM32_GATE_CFG(CK_KER_GPU, ck_ker_gpu, SECF_NONE),
1685
+
STM32_GATE_CFG(CK_KER_ETHSWREF, ck_ker_ethswref, SECF_NONE),
1686
+
STM32_GATE_CFG(CK_BUS_ETHSWACMCFG, ck_icn_p_ethsw_acm_cfg, SECF_NONE),
1687
+
STM32_GATE_CFG(CK_BUS_ETHSWACMMSG, ck_icn_p_ethsw_acm_msg, SECF_NONE),
1688
+
STM32_GATE_CFG(CK_ETH1_MAC, ck_ker_eth1mac, SECF_NONE),
1689
+
STM32_GATE_CFG(CK_ETH1_TX, ck_ker_eth1tx, SECF_NONE),
1690
+
STM32_GATE_CFG(CK_ETH1_RX, ck_ker_eth1rx, SECF_NONE),
1691
+
STM32_GATE_CFG(CK_ETH2_MAC, ck_ker_eth2mac, SECF_NONE),
1692
+
STM32_GATE_CFG(CK_ETH2_TX, ck_ker_eth2tx, SECF_NONE),
1693
+
STM32_GATE_CFG(CK_ETH2_RX, ck_ker_eth2rx, SECF_NONE),
1694
+
STM32_COMPOSITE_CFG(CK_MCO1, ck_mco1, SECF_NONE),
1695
+
STM32_COMPOSITE_CFG(CK_MCO2, ck_mco2, SECF_NONE),
1696
+
STM32_COMPOSITE_CFG(CK_KER_ADC12, ck_ker_adc12, SECF_NONE),
1697
+
STM32_COMPOSITE_CFG(CK_KER_ADC3, ck_ker_adc3, SECF_NONE),
1698
+
STM32_COMPOSITE_CFG(CK_KER_USB2PHY1, ck_ker_usb2phy1, SECF_NONE),
1699
+
STM32_GATE_CFG(CK_KER_USB2PHY2, ck_ker_usb2phy2, SECF_NONE),
1700
+
STM32_COMPOSITE_CFG(CK_KER_USB2PHY2EN, ck_ker_usb2phy2_en, SECF_NONE),
1701
+
STM32_COMPOSITE_CFG(CK_KER_USB3PCIEPHY, ck_ker_usb3pciephy, SECF_NONE),
1702
+
STM32_COMPOSITE_CFG(CK_KER_DSIBLANE, clk_lanebyte, SECF_NONE),
1703
+
STM32_COMPOSITE_CFG(CK_KER_DSIPHY, clk_phy_dsi, SECF_NONE),
1704
+
STM32_COMPOSITE_CFG(CK_KER_LVDSPHY, ck_ker_lvdsphy, SECF_NONE),
1705
+
STM32_COMPOSITE_CFG(CK_KER_DTS, ck_ker_dts, SECF_NONE),
1706
+
STM32_GATE_CFG(CK_KER_LTDC, ck_ker_ltdc, SECF_NONE),
1707
+
};
1708
+
1709
+
#define RESET_MP25(id, _offset, _bit_idx, _set_clr) \
1710
+
[id] = &(struct stm32_reset_cfg){ \
1711
+
.offset = (_offset), \
1712
+
.bit_idx = (_bit_idx), \
1713
+
.set_clr = (_set_clr), \
1714
+
}
1715
+
1716
+
static const struct stm32_reset_cfg *stm32mp25_reset_cfg[STM32MP25_LAST_RESET] = {
1717
+
RESET_MP25(TIM1_R, RCC_TIM1CFGR, 0, 0),
1718
+
RESET_MP25(TIM2_R, RCC_TIM2CFGR, 0, 0),
1719
+
RESET_MP25(TIM3_R, RCC_TIM3CFGR, 0, 0),
1720
+
RESET_MP25(TIM4_R, RCC_TIM4CFGR, 0, 0),
1721
+
RESET_MP25(TIM5_R, RCC_TIM5CFGR, 0, 0),
1722
+
RESET_MP25(TIM6_R, RCC_TIM6CFGR, 0, 0),
1723
+
RESET_MP25(TIM7_R, RCC_TIM7CFGR, 0, 0),
1724
+
RESET_MP25(TIM8_R, RCC_TIM8CFGR, 0, 0),
1725
+
RESET_MP25(TIM10_R, RCC_TIM10CFGR, 0, 0),
1726
+
RESET_MP25(TIM11_R, RCC_TIM11CFGR, 0, 0),
1727
+
RESET_MP25(TIM12_R, RCC_TIM12CFGR, 0, 0),
1728
+
RESET_MP25(TIM13_R, RCC_TIM13CFGR, 0, 0),
1729
+
RESET_MP25(TIM14_R, RCC_TIM14CFGR, 0, 0),
1730
+
RESET_MP25(TIM15_R, RCC_TIM15CFGR, 0, 0),
1731
+
RESET_MP25(TIM16_R, RCC_TIM16CFGR, 0, 0),
1732
+
RESET_MP25(TIM17_R, RCC_TIM17CFGR, 0, 0),
1733
+
RESET_MP25(TIM20_R, RCC_TIM20CFGR, 0, 0),
1734
+
RESET_MP25(LPTIM1_R, RCC_LPTIM1CFGR, 0, 0),
1735
+
RESET_MP25(LPTIM2_R, RCC_LPTIM2CFGR, 0, 0),
1736
+
RESET_MP25(LPTIM3_R, RCC_LPTIM3CFGR, 0, 0),
1737
+
RESET_MP25(LPTIM4_R, RCC_LPTIM4CFGR, 0, 0),
1738
+
RESET_MP25(LPTIM5_R, RCC_LPTIM5CFGR, 0, 0),
1739
+
RESET_MP25(SPI1_R, RCC_SPI1CFGR, 0, 0),
1740
+
RESET_MP25(SPI2_R, RCC_SPI2CFGR, 0, 0),
1741
+
RESET_MP25(SPI3_R, RCC_SPI3CFGR, 0, 0),
1742
+
RESET_MP25(SPI4_R, RCC_SPI4CFGR, 0, 0),
1743
+
RESET_MP25(SPI5_R, RCC_SPI5CFGR, 0, 0),
1744
+
RESET_MP25(SPI6_R, RCC_SPI6CFGR, 0, 0),
1745
+
RESET_MP25(SPI7_R, RCC_SPI7CFGR, 0, 0),
1746
+
RESET_MP25(SPI8_R, RCC_SPI8CFGR, 0, 0),
1747
+
RESET_MP25(SPDIFRX_R, RCC_SPDIFRXCFGR, 0, 0),
1748
+
RESET_MP25(USART1_R, RCC_USART1CFGR, 0, 0),
1749
+
RESET_MP25(USART2_R, RCC_USART2CFGR, 0, 0),
1750
+
RESET_MP25(USART3_R, RCC_USART3CFGR, 0, 0),
1751
+
RESET_MP25(UART4_R, RCC_UART4CFGR, 0, 0),
1752
+
RESET_MP25(UART5_R, RCC_UART5CFGR, 0, 0),
1753
+
RESET_MP25(USART6_R, RCC_USART6CFGR, 0, 0),
1754
+
RESET_MP25(UART7_R, RCC_UART7CFGR, 0, 0),
1755
+
RESET_MP25(UART8_R, RCC_UART8CFGR, 0, 0),
1756
+
RESET_MP25(UART9_R, RCC_UART9CFGR, 0, 0),
1757
+
RESET_MP25(LPUART1_R, RCC_LPUART1CFGR, 0, 0),
1758
+
RESET_MP25(IS2M_R, RCC_IS2MCFGR, 0, 0),
1759
+
RESET_MP25(I2C1_R, RCC_I2C1CFGR, 0, 0),
1760
+
RESET_MP25(I2C2_R, RCC_I2C2CFGR, 0, 0),
1761
+
RESET_MP25(I2C3_R, RCC_I2C3CFGR, 0, 0),
1762
+
RESET_MP25(I2C4_R, RCC_I2C4CFGR, 0, 0),
1763
+
RESET_MP25(I2C5_R, RCC_I2C5CFGR, 0, 0),
1764
+
RESET_MP25(I2C6_R, RCC_I2C6CFGR, 0, 0),
1765
+
RESET_MP25(I2C7_R, RCC_I2C7CFGR, 0, 0),
1766
+
RESET_MP25(I2C8_R, RCC_I2C8CFGR, 0, 0),
1767
+
RESET_MP25(SAI1_R, RCC_SAI1CFGR, 0, 0),
1768
+
RESET_MP25(SAI2_R, RCC_SAI2CFGR, 0, 0),
1769
+
RESET_MP25(SAI3_R, RCC_SAI3CFGR, 0, 0),
1770
+
RESET_MP25(SAI4_R, RCC_SAI4CFGR, 0, 0),
1771
+
RESET_MP25(MDF1_R, RCC_MDF1CFGR, 0, 0),
1772
+
RESET_MP25(MDF2_R, RCC_ADF1CFGR, 0, 0),
1773
+
RESET_MP25(FDCAN_R, RCC_FDCANCFGR, 0, 0),
1774
+
RESET_MP25(HDP_R, RCC_HDPCFGR, 0, 0),
1775
+
RESET_MP25(ADC12_R, RCC_ADC12CFGR, 0, 0),
1776
+
RESET_MP25(ADC3_R, RCC_ADC3CFGR, 0, 0),
1777
+
RESET_MP25(ETH1_R, RCC_ETH1CFGR, 0, 0),
1778
+
RESET_MP25(ETH2_R, RCC_ETH2CFGR, 0, 0),
1779
+
RESET_MP25(USBH_R, RCC_USBHCFGR, 0, 0),
1780
+
RESET_MP25(USB2PHY1_R, RCC_USB2PHY1CFGR, 0, 0),
1781
+
RESET_MP25(USB2PHY2_R, RCC_USB2PHY2CFGR, 0, 0),
1782
+
RESET_MP25(USB3DR_R, RCC_USB3DRCFGR, 0, 0),
1783
+
RESET_MP25(USB3PCIEPHY_R, RCC_USB3PCIEPHYCFGR, 0, 0),
1784
+
RESET_MP25(USBTC_R, RCC_USBTCCFGR, 0, 0),
1785
+
RESET_MP25(ETHSW_R, RCC_ETHSWCFGR, 0, 0),
1786
+
RESET_MP25(SDMMC1_R, RCC_SDMMC1CFGR, 0, 0),
1787
+
RESET_MP25(SDMMC1DLL_R, RCC_SDMMC1CFGR, 16, 0),
1788
+
RESET_MP25(SDMMC2_R, RCC_SDMMC2CFGR, 0, 0),
1789
+
RESET_MP25(SDMMC2DLL_R, RCC_SDMMC2CFGR, 16, 0),
1790
+
RESET_MP25(SDMMC3_R, RCC_SDMMC3CFGR, 0, 0),
1791
+
RESET_MP25(SDMMC3DLL_R, RCC_SDMMC3CFGR, 16, 0),
1792
+
RESET_MP25(GPU_R, RCC_GPUCFGR, 0, 0),
1793
+
RESET_MP25(LTDC_R, RCC_LTDCCFGR, 0, 0),
1794
+
RESET_MP25(DSI_R, RCC_DSICFGR, 0, 0),
1795
+
RESET_MP25(LVDS_R, RCC_LVDSCFGR, 0, 0),
1796
+
RESET_MP25(CSI_R, RCC_CSICFGR, 0, 0),
1797
+
RESET_MP25(DCMIPP_R, RCC_DCMIPPCFGR, 0, 0),
1798
+
RESET_MP25(CCI_R, RCC_CCICFGR, 0, 0),
1799
+
RESET_MP25(VDEC_R, RCC_VDECCFGR, 0, 0),
1800
+
RESET_MP25(VENC_R, RCC_VENCCFGR, 0, 0),
1801
+
RESET_MP25(WWDG1_R, RCC_WWDG1CFGR, 0, 0),
1802
+
RESET_MP25(WWDG2_R, RCC_WWDG2CFGR, 0, 0),
1803
+
RESET_MP25(VREF_R, RCC_VREFCFGR, 0, 0),
1804
+
RESET_MP25(DTS_R, RCC_DTSCFGR, 0, 0),
1805
+
RESET_MP25(CRC_R, RCC_CRCCFGR, 0, 0),
1806
+
RESET_MP25(SERC_R, RCC_SERCCFGR, 0, 0),
1807
+
RESET_MP25(OSPIIOM_R, RCC_OSPIIOMCFGR, 0, 0),
1808
+
RESET_MP25(I3C1_R, RCC_I3C1CFGR, 0, 0),
1809
+
RESET_MP25(I3C2_R, RCC_I3C2CFGR, 0, 0),
1810
+
RESET_MP25(I3C3_R, RCC_I3C3CFGR, 0, 0),
1811
+
RESET_MP25(I3C4_R, RCC_I3C4CFGR, 0, 0),
1812
+
RESET_MP25(IWDG2_KER_R, RCC_IWDGC1CFGSETR, 18, 1),
1813
+
RESET_MP25(IWDG4_KER_R, RCC_IWDGC2CFGSETR, 18, 1),
1814
+
RESET_MP25(RNG_R, RCC_RNGCFGR, 0, 0),
1815
+
RESET_MP25(PKA_R, RCC_PKACFGR, 0, 0),
1816
+
RESET_MP25(SAES_R, RCC_SAESCFGR, 0, 0),
1817
+
RESET_MP25(HASH_R, RCC_HASHCFGR, 0, 0),
1818
+
RESET_MP25(CRYP1_R, RCC_CRYP1CFGR, 0, 0),
1819
+
RESET_MP25(CRYP2_R, RCC_CRYP2CFGR, 0, 0),
1820
+
RESET_MP25(PCIE_R, RCC_PCIECFGR, 0, 0),
1821
+
};
1822
+
1823
+
static u16 stm32mp25_cpt_gate[GATE_NB];
1824
+
1825
+
static struct clk_stm32_clock_data stm32mp25_clock_data = {
1826
+
.gate_cpt = stm32mp25_cpt_gate,
1827
+
.gates = stm32mp25_gates,
1828
+
.muxes = stm32mp25_muxes,
1829
+
};
1830
+
1831
+
static struct clk_stm32_reset_data stm32mp25_reset_data = {
1832
+
.reset_lines = stm32mp25_reset_cfg,
1833
+
.nr_lines = ARRAY_SIZE(stm32mp25_reset_cfg),
1834
+
};
1835
+
1836
+
static const struct stm32_rcc_match_data stm32mp25_data = {
1837
+
.tab_clocks = stm32mp25_clock_cfg,
1838
+
.num_clocks = ARRAY_SIZE(stm32mp25_clock_cfg),
1839
+
.maxbinding = STM32MP25_LAST_CLK,
1840
+
.clock_data = &stm32mp25_clock_data,
1841
+
.reset_data = &stm32mp25_reset_data,
1842
+
};
1843
+
1844
+
static const struct of_device_id stm32mp25_match_data[] = {
1845
+
{ .compatible = "st,stm32mp25-rcc", .data = &stm32mp25_data, },
1846
+
{ }
1847
+
};
1848
+
MODULE_DEVICE_TABLE(of, stm32mp25_match_data);
1849
+
1850
+
static int stm32mp25_rcc_clocks_probe(struct platform_device *pdev)
1851
+
{
1852
+
struct device *dev = &pdev->dev;
1853
+
void __iomem *base;
1854
+
1855
+
base = devm_platform_ioremap_resource(pdev, 0);
1856
+
if (IS_ERR(base))
1857
+
return PTR_ERR(base);
1858
+
1859
+
return stm32_rcc_init(dev, stm32mp25_match_data, base);
1860
+
}
1861
+
1862
+
static struct platform_driver stm32mp25_rcc_clocks_driver = {
1863
+
.driver = {
1864
+
.name = "stm32mp25_rcc",
1865
+
.of_match_table = stm32mp25_match_data,
1866
+
},
1867
+
.probe = stm32mp25_rcc_clocks_probe,
1868
+
};
1869
+
1870
+
static int __init stm32mp25_clocks_init(void)
1871
+
{
1872
+
return platform_driver_register(&stm32mp25_rcc_clocks_driver);
1873
+
}
1874
+
1875
+
core_initcall(stm32mp25_clocks_init);
+44
-15
drivers/clk/stm32/reset-stm32.c
+44
-15
drivers/clk/stm32/reset-stm32.c
···
19
19
struct reset_controller_dev rcdev;
20
20
void __iomem *membase;
21
21
u32 clear_offset;
22
+
const struct stm32_reset_cfg **reset_lines;
22
23
};
23
24
24
25
static inline struct stm32_reset_data *
···
28
27
return container_of(rcdev, struct stm32_reset_data, rcdev);
29
28
}
30
29
30
+
static const struct stm32_reset_cfg *stm32_get_reset_line(struct reset_controller_dev *rcdev,
31
+
unsigned long id,
32
+
struct stm32_reset_cfg *line)
33
+
{
34
+
struct stm32_reset_data *data = to_stm32_reset_data(rcdev);
35
+
36
+
if (!data->reset_lines) {
37
+
int reg_width = sizeof(u32);
38
+
int bank = id / (reg_width * BITS_PER_BYTE);
39
+
int offset = id % (reg_width * BITS_PER_BYTE);
40
+
41
+
line->offset = bank * reg_width;
42
+
line->bit_idx = offset;
43
+
line->set_clr = (data->clear_offset ? true : false);
44
+
45
+
return line;
46
+
}
47
+
48
+
return data->reset_lines[id];
49
+
}
50
+
31
51
static int stm32_reset_update(struct reset_controller_dev *rcdev,
32
52
unsigned long id, bool assert)
33
53
{
34
54
struct stm32_reset_data *data = to_stm32_reset_data(rcdev);
35
-
int reg_width = sizeof(u32);
36
-
int bank = id / (reg_width * BITS_PER_BYTE);
37
-
int offset = id % (reg_width * BITS_PER_BYTE);
55
+
struct stm32_reset_cfg line_reset;
56
+
const struct stm32_reset_cfg *ptr_line;
38
57
39
-
if (data->clear_offset) {
58
+
ptr_line = stm32_get_reset_line(rcdev, id, &line_reset);
59
+
if (!ptr_line)
60
+
return -EPERM;
61
+
62
+
if (ptr_line->set_clr) {
40
63
void __iomem *addr;
41
64
42
-
addr = data->membase + (bank * reg_width);
65
+
addr = data->membase + ptr_line->offset;
43
66
if (!assert)
44
67
addr += data->clear_offset;
45
68
46
-
writel(BIT(offset), addr);
69
+
writel(BIT(ptr_line->bit_idx), addr);
47
70
48
71
} else {
49
72
unsigned long flags;
···
75
50
76
51
spin_lock_irqsave(&data->lock, flags);
77
52
78
-
reg = readl(data->membase + (bank * reg_width));
53
+
reg = readl(data->membase + ptr_line->offset);
79
54
80
55
if (assert)
81
-
reg |= BIT(offset);
56
+
reg |= BIT(ptr_line->bit_idx);
82
57
else
83
-
reg &= ~BIT(offset);
58
+
reg &= ~BIT(ptr_line->bit_idx);
84
59
85
-
writel(reg, data->membase + (bank * reg_width));
60
+
writel(reg, data->membase + ptr_line->offset);
86
61
87
62
spin_unlock_irqrestore(&data->lock, flags);
88
63
}
···
106
81
unsigned long id)
107
82
{
108
83
struct stm32_reset_data *data = to_stm32_reset_data(rcdev);
109
-
int reg_width = sizeof(u32);
110
-
int bank = id / (reg_width * BITS_PER_BYTE);
111
-
int offset = id % (reg_width * BITS_PER_BYTE);
84
+
struct stm32_reset_cfg line_reset;
85
+
const struct stm32_reset_cfg *ptr_line;
112
86
u32 reg;
113
87
114
-
reg = readl(data->membase + (bank * reg_width));
88
+
ptr_line = stm32_get_reset_line(rcdev, id, &line_reset);
89
+
if (!ptr_line)
90
+
return -EPERM;
115
91
116
-
return !!(reg & BIT(offset));
92
+
reg = readl(data->membase + ptr_line->offset);
93
+
94
+
return !!(reg & BIT(ptr_line->bit_idx));
117
95
}
118
96
119
97
static const struct reset_control_ops stm32_reset_ops = {
···
141
113
reset_data->rcdev.ops = &stm32_reset_ops;
142
114
reset_data->rcdev.of_node = dev_of_node(dev);
143
115
reset_data->rcdev.nr_resets = data->nr_lines;
116
+
reset_data->reset_lines = data->reset_lines;
144
117
reset_data->clear_offset = data->clear_offset;
145
118
146
119
return reset_controller_register(&reset_data->rcdev);
+7
drivers/clk/stm32/reset-stm32.h
+7
drivers/clk/stm32/reset-stm32.h
···
4
4
* Author: Gabriel Fernandez <gabriel.fernandez@foss.st.com> for STMicroelectronics.
5
5
*/
6
6
7
+
struct stm32_reset_cfg {
8
+
u16 offset;
9
+
u8 bit_idx;
10
+
bool set_clr;
11
+
};
12
+
7
13
struct clk_stm32_reset_data {
8
14
const struct reset_control_ops *ops;
15
+
const struct stm32_reset_cfg **reset_lines;
9
16
unsigned int nr_lines;
10
17
u32 clear_offset;
11
18
};
+712
drivers/clk/stm32/stm32mp25_rcc.h
+712
drivers/clk/stm32/stm32mp25_rcc.h
···
1
+
/* SPDX-License-Identifier: GPL-2.0-only */
2
+
/*
3
+
* Copyright (C) STMicroelectronics 2023 - All Rights Reserved
4
+
* Author: Gabriel Fernandez <gabriel.fernandez@foss.st.com> for STMicroelectronics.
5
+
*/
6
+
7
+
#ifndef STM32MP25_RCC_H
8
+
#define STM32MP25_RCC_H
9
+
10
+
#define RCC_SECCFGR0 0x0
11
+
#define RCC_SECCFGR1 0x4
12
+
#define RCC_SECCFGR2 0x8
13
+
#define RCC_SECCFGR3 0xC
14
+
#define RCC_PRIVCFGR0 0x10
15
+
#define RCC_PRIVCFGR1 0x14
16
+
#define RCC_PRIVCFGR2 0x18
17
+
#define RCC_PRIVCFGR3 0x1C
18
+
#define RCC_RCFGLOCKR0 0x20
19
+
#define RCC_RCFGLOCKR1 0x24
20
+
#define RCC_RCFGLOCKR2 0x28
21
+
#define RCC_RCFGLOCKR3 0x2C
22
+
#define RCC_R0CIDCFGR 0x30
23
+
#define RCC_R0SEMCR 0x34
24
+
#define RCC_R1CIDCFGR 0x38
25
+
#define RCC_R1SEMCR 0x3C
26
+
#define RCC_R2CIDCFGR 0x40
27
+
#define RCC_R2SEMCR 0x44
28
+
#define RCC_R3CIDCFGR 0x48
29
+
#define RCC_R3SEMCR 0x4C
30
+
#define RCC_R4CIDCFGR 0x50
31
+
#define RCC_R4SEMCR 0x54
32
+
#define RCC_R5CIDCFGR 0x58
33
+
#define RCC_R5SEMCR 0x5C
34
+
#define RCC_R6CIDCFGR 0x60
35
+
#define RCC_R6SEMCR 0x64
36
+
#define RCC_R7CIDCFGR 0x68
37
+
#define RCC_R7SEMCR 0x6C
38
+
#define RCC_R8CIDCFGR 0x70
39
+
#define RCC_R8SEMCR 0x74
40
+
#define RCC_R9CIDCFGR 0x78
41
+
#define RCC_R9SEMCR 0x7C
42
+
#define RCC_R10CIDCFGR 0x80
43
+
#define RCC_R10SEMCR 0x84
44
+
#define RCC_R11CIDCFGR 0x88
45
+
#define RCC_R11SEMCR 0x8C
46
+
#define RCC_R12CIDCFGR 0x90
47
+
#define RCC_R12SEMCR 0x94
48
+
#define RCC_R13CIDCFGR 0x98
49
+
#define RCC_R13SEMCR 0x9C
50
+
#define RCC_R14CIDCFGR 0xA0
51
+
#define RCC_R14SEMCR 0xA4
52
+
#define RCC_R15CIDCFGR 0xA8
53
+
#define RCC_R15SEMCR 0xAC
54
+
#define RCC_R16CIDCFGR 0xB0
55
+
#define RCC_R16SEMCR 0xB4
56
+
#define RCC_R17CIDCFGR 0xB8
57
+
#define RCC_R17SEMCR 0xBC
58
+
#define RCC_R18CIDCFGR 0xC0
59
+
#define RCC_R18SEMCR 0xC4
60
+
#define RCC_R19CIDCFGR 0xC8
61
+
#define RCC_R19SEMCR 0xCC
62
+
#define RCC_R20CIDCFGR 0xD0
63
+
#define RCC_R20SEMCR 0xD4
64
+
#define RCC_R21CIDCFGR 0xD8
65
+
#define RCC_R21SEMCR 0xDC
66
+
#define RCC_R22CIDCFGR 0xE0
67
+
#define RCC_R22SEMCR 0xE4
68
+
#define RCC_R23CIDCFGR 0xE8
69
+
#define RCC_R23SEMCR 0xEC
70
+
#define RCC_R24CIDCFGR 0xF0
71
+
#define RCC_R24SEMCR 0xF4
72
+
#define RCC_R25CIDCFGR 0xF8
73
+
#define RCC_R25SEMCR 0xFC
74
+
#define RCC_R26CIDCFGR 0x100
75
+
#define RCC_R26SEMCR 0x104
76
+
#define RCC_R27CIDCFGR 0x108
77
+
#define RCC_R27SEMCR 0x10C
78
+
#define RCC_R28CIDCFGR 0x110
79
+
#define RCC_R28SEMCR 0x114
80
+
#define RCC_R29CIDCFGR 0x118
81
+
#define RCC_R29SEMCR 0x11C
82
+
#define RCC_R30CIDCFGR 0x120
83
+
#define RCC_R30SEMCR 0x124
84
+
#define RCC_R31CIDCFGR 0x128
85
+
#define RCC_R31SEMCR 0x12C
86
+
#define RCC_R32CIDCFGR 0x130
87
+
#define RCC_R32SEMCR 0x134
88
+
#define RCC_R33CIDCFGR 0x138
89
+
#define RCC_R33SEMCR 0x13C
90
+
#define RCC_R34CIDCFGR 0x140
91
+
#define RCC_R34SEMCR 0x144
92
+
#define RCC_R35CIDCFGR 0x148
93
+
#define RCC_R35SEMCR 0x14C
94
+
#define RCC_R36CIDCFGR 0x150
95
+
#define RCC_R36SEMCR 0x154
96
+
#define RCC_R37CIDCFGR 0x158
97
+
#define RCC_R37SEMCR 0x15C
98
+
#define RCC_R38CIDCFGR 0x160
99
+
#define RCC_R38SEMCR 0x164
100
+
#define RCC_R39CIDCFGR 0x168
101
+
#define RCC_R39SEMCR 0x16C
102
+
#define RCC_R40CIDCFGR 0x170
103
+
#define RCC_R40SEMCR 0x174
104
+
#define RCC_R41CIDCFGR 0x178
105
+
#define RCC_R41SEMCR 0x17C
106
+
#define RCC_R42CIDCFGR 0x180
107
+
#define RCC_R42SEMCR 0x184
108
+
#define RCC_R43CIDCFGR 0x188
109
+
#define RCC_R43SEMCR 0x18C
110
+
#define RCC_R44CIDCFGR 0x190
111
+
#define RCC_R44SEMCR 0x194
112
+
#define RCC_R45CIDCFGR 0x198
113
+
#define RCC_R45SEMCR 0x19C
114
+
#define RCC_R46CIDCFGR 0x1A0
115
+
#define RCC_R46SEMCR 0x1A4
116
+
#define RCC_R47CIDCFGR 0x1A8
117
+
#define RCC_R47SEMCR 0x1AC
118
+
#define RCC_R48CIDCFGR 0x1B0
119
+
#define RCC_R48SEMCR 0x1B4
120
+
#define RCC_R49CIDCFGR 0x1B8
121
+
#define RCC_R49SEMCR 0x1BC
122
+
#define RCC_R50CIDCFGR 0x1C0
123
+
#define RCC_R50SEMCR 0x1C4
124
+
#define RCC_R51CIDCFGR 0x1C8
125
+
#define RCC_R51SEMCR 0x1CC
126
+
#define RCC_R52CIDCFGR 0x1D0
127
+
#define RCC_R52SEMCR 0x1D4
128
+
#define RCC_R53CIDCFGR 0x1D8
129
+
#define RCC_R53SEMCR 0x1DC
130
+
#define RCC_R54CIDCFGR 0x1E0
131
+
#define RCC_R54SEMCR 0x1E4
132
+
#define RCC_R55CIDCFGR 0x1E8
133
+
#define RCC_R55SEMCR 0x1EC
134
+
#define RCC_R56CIDCFGR 0x1F0
135
+
#define RCC_R56SEMCR 0x1F4
136
+
#define RCC_R57CIDCFGR 0x1F8
137
+
#define RCC_R57SEMCR 0x1FC
138
+
#define RCC_R58CIDCFGR 0x200
139
+
#define RCC_R58SEMCR 0x204
140
+
#define RCC_R59CIDCFGR 0x208
141
+
#define RCC_R59SEMCR 0x20C
142
+
#define RCC_R60CIDCFGR 0x210
143
+
#define RCC_R60SEMCR 0x214
144
+
#define RCC_R61CIDCFGR 0x218
145
+
#define RCC_R61SEMCR 0x21C
146
+
#define RCC_R62CIDCFGR 0x220
147
+
#define RCC_R62SEMCR 0x224
148
+
#define RCC_R63CIDCFGR 0x228
149
+
#define RCC_R63SEMCR 0x22C
150
+
#define RCC_R64CIDCFGR 0x230
151
+
#define RCC_R64SEMCR 0x234
152
+
#define RCC_R65CIDCFGR 0x238
153
+
#define RCC_R65SEMCR 0x23C
154
+
#define RCC_R66CIDCFGR 0x240
155
+
#define RCC_R66SEMCR 0x244
156
+
#define RCC_R67CIDCFGR 0x248
157
+
#define RCC_R67SEMCR 0x24C
158
+
#define RCC_R68CIDCFGR 0x250
159
+
#define RCC_R68SEMCR 0x254
160
+
#define RCC_R69CIDCFGR 0x258
161
+
#define RCC_R69SEMCR 0x25C
162
+
#define RCC_R70CIDCFGR 0x260
163
+
#define RCC_R70SEMCR 0x264
164
+
#define RCC_R71CIDCFGR 0x268
165
+
#define RCC_R71SEMCR 0x26C
166
+
#define RCC_R72CIDCFGR 0x270
167
+
#define RCC_R72SEMCR 0x274
168
+
#define RCC_R73CIDCFGR 0x278
169
+
#define RCC_R73SEMCR 0x27C
170
+
#define RCC_R74CIDCFGR 0x280
171
+
#define RCC_R74SEMCR 0x284
172
+
#define RCC_R75CIDCFGR 0x288
173
+
#define RCC_R75SEMCR 0x28C
174
+
#define RCC_R76CIDCFGR 0x290
175
+
#define RCC_R76SEMCR 0x294
176
+
#define RCC_R77CIDCFGR 0x298
177
+
#define RCC_R77SEMCR 0x29C
178
+
#define RCC_R78CIDCFGR 0x2A0
179
+
#define RCC_R78SEMCR 0x2A4
180
+
#define RCC_R79CIDCFGR 0x2A8
181
+
#define RCC_R79SEMCR 0x2AC
182
+
#define RCC_R80CIDCFGR 0x2B0
183
+
#define RCC_R80SEMCR 0x2B4
184
+
#define RCC_R81CIDCFGR 0x2B8
185
+
#define RCC_R81SEMCR 0x2BC
186
+
#define RCC_R82CIDCFGR 0x2C0
187
+
#define RCC_R82SEMCR 0x2C4
188
+
#define RCC_R83CIDCFGR 0x2C8
189
+
#define RCC_R83SEMCR 0x2CC
190
+
#define RCC_R84CIDCFGR 0x2D0
191
+
#define RCC_R84SEMCR 0x2D4
192
+
#define RCC_R85CIDCFGR 0x2D8
193
+
#define RCC_R85SEMCR 0x2DC
194
+
#define RCC_R86CIDCFGR 0x2E0
195
+
#define RCC_R86SEMCR 0x2E4
196
+
#define RCC_R87CIDCFGR 0x2E8
197
+
#define RCC_R87SEMCR 0x2EC
198
+
#define RCC_R88CIDCFGR 0x2F0
199
+
#define RCC_R88SEMCR 0x2F4
200
+
#define RCC_R89CIDCFGR 0x2F8
201
+
#define RCC_R89SEMCR 0x2FC
202
+
#define RCC_R90CIDCFGR 0x300
203
+
#define RCC_R90SEMCR 0x304
204
+
#define RCC_R91CIDCFGR 0x308
205
+
#define RCC_R91SEMCR 0x30C
206
+
#define RCC_R92CIDCFGR 0x310
207
+
#define RCC_R92SEMCR 0x314
208
+
#define RCC_R93CIDCFGR 0x318
209
+
#define RCC_R93SEMCR 0x31C
210
+
#define RCC_R94CIDCFGR 0x320
211
+
#define RCC_R94SEMCR 0x324
212
+
#define RCC_R95CIDCFGR 0x328
213
+
#define RCC_R95SEMCR 0x32C
214
+
#define RCC_R96CIDCFGR 0x330
215
+
#define RCC_R96SEMCR 0x334
216
+
#define RCC_R97CIDCFGR 0x338
217
+
#define RCC_R97SEMCR 0x33C
218
+
#define RCC_R98CIDCFGR 0x340
219
+
#define RCC_R98SEMCR 0x344
220
+
#define RCC_R99CIDCFGR 0x348
221
+
#define RCC_R99SEMCR 0x34C
222
+
#define RCC_R100CIDCFGR 0x350
223
+
#define RCC_R100SEMCR 0x354
224
+
#define RCC_R101CIDCFGR 0x358
225
+
#define RCC_R101SEMCR 0x35C
226
+
#define RCC_R102CIDCFGR 0x360
227
+
#define RCC_R102SEMCR 0x364
228
+
#define RCC_R103CIDCFGR 0x368
229
+
#define RCC_R103SEMCR 0x36C
230
+
#define RCC_R104CIDCFGR 0x370
231
+
#define RCC_R104SEMCR 0x374
232
+
#define RCC_R105CIDCFGR 0x378
233
+
#define RCC_R105SEMCR 0x37C
234
+
#define RCC_R106CIDCFGR 0x380
235
+
#define RCC_R106SEMCR 0x384
236
+
#define RCC_R107CIDCFGR 0x388
237
+
#define RCC_R107SEMCR 0x38C
238
+
#define RCC_R108CIDCFGR 0x390
239
+
#define RCC_R108SEMCR 0x394
240
+
#define RCC_R109CIDCFGR 0x398
241
+
#define RCC_R109SEMCR 0x39C
242
+
#define RCC_R110CIDCFGR 0x3A0
243
+
#define RCC_R110SEMCR 0x3A4
244
+
#define RCC_R111CIDCFGR 0x3A8
245
+
#define RCC_R111SEMCR 0x3AC
246
+
#define RCC_R112CIDCFGR 0x3B0
247
+
#define RCC_R112SEMCR 0x3B4
248
+
#define RCC_R113CIDCFGR 0x3B8
249
+
#define RCC_R113SEMCR 0x3BC
250
+
#define RCC_GRSTCSETR 0x400
251
+
#define RCC_C1RSTCSETR 0x404
252
+
#define RCC_C1P1RSTCSETR 0x408
253
+
#define RCC_C2RSTCSETR 0x40C
254
+
#define RCC_HWRSTSCLRR 0x410
255
+
#define RCC_C1HWRSTSCLRR 0x414
256
+
#define RCC_C2HWRSTSCLRR 0x418
257
+
#define RCC_C1BOOTRSTSSETR 0x41C
258
+
#define RCC_C1BOOTRSTSCLRR 0x420
259
+
#define RCC_C2BOOTRSTSSETR 0x424
260
+
#define RCC_C2BOOTRSTSCLRR 0x428
261
+
#define RCC_C1SREQSETR 0x42C
262
+
#define RCC_C1SREQCLRR 0x430
263
+
#define RCC_CPUBOOTCR 0x434
264
+
#define RCC_STBYBOOTCR 0x438
265
+
#define RCC_LEGBOOTCR 0x43C
266
+
#define RCC_BDCR 0x440
267
+
#define RCC_D3DCR 0x444
268
+
#define RCC_D3DSR 0x448
269
+
#define RCC_RDCR 0x44C
270
+
#define RCC_C1MSRDCR 0x450
271
+
#define RCC_PWRLPDLYCR 0x454
272
+
#define RCC_C1CIESETR 0x458
273
+
#define RCC_C1CIFCLRR 0x45C
274
+
#define RCC_C2CIESETR 0x460
275
+
#define RCC_C2CIFCLRR 0x464
276
+
#define RCC_IWDGC1FZSETR 0x468
277
+
#define RCC_IWDGC1FZCLRR 0x46C
278
+
#define RCC_IWDGC1CFGSETR 0x470
279
+
#define RCC_IWDGC1CFGCLRR 0x474
280
+
#define RCC_IWDGC2FZSETR 0x478
281
+
#define RCC_IWDGC2FZCLRR 0x47C
282
+
#define RCC_IWDGC2CFGSETR 0x480
283
+
#define RCC_IWDGC2CFGCLRR 0x484
284
+
#define RCC_IWDGC3CFGSETR 0x488
285
+
#define RCC_IWDGC3CFGCLRR 0x48C
286
+
#define RCC_C3CFGR 0x490
287
+
#define RCC_MCO1CFGR 0x494
288
+
#define RCC_MCO2CFGR 0x498
289
+
#define RCC_OCENSETR 0x49C
290
+
#define RCC_OCENCLRR 0x4A0
291
+
#define RCC_OCRDYR 0x4A4
292
+
#define RCC_HSICFGR 0x4A8
293
+
#define RCC_MSICFGR 0x4AC
294
+
#define RCC_RTCDIVR 0x4B0
295
+
#define RCC_APB1DIVR 0x4B4
296
+
#define RCC_APB2DIVR 0x4B8
297
+
#define RCC_APB3DIVR 0x4BC
298
+
#define RCC_APB4DIVR 0x4C0
299
+
#define RCC_APBDBGDIVR 0x4C4
300
+
#define RCC_TIMG1PRER 0x4C8
301
+
#define RCC_TIMG2PRER 0x4CC
302
+
#define RCC_LSMCUDIVR 0x4D0
303
+
#define RCC_DDRCPCFGR 0x4D4
304
+
#define RCC_DDRCAPBCFGR 0x4D8
305
+
#define RCC_DDRPHYCAPBCFGR 0x4DC
306
+
#define RCC_DDRPHYCCFGR 0x4E0
307
+
#define RCC_DDRCFGR 0x4E4
308
+
#define RCC_DDRITFCFGR 0x4E8
309
+
#define RCC_SYSRAMCFGR 0x4F0
310
+
#define RCC_VDERAMCFGR 0x4F4
311
+
#define RCC_SRAM1CFGR 0x4F8
312
+
#define RCC_SRAM2CFGR 0x4FC
313
+
#define RCC_RETRAMCFGR 0x500
314
+
#define RCC_BKPSRAMCFGR 0x504
315
+
#define RCC_LPSRAM1CFGR 0x508
316
+
#define RCC_LPSRAM2CFGR 0x50C
317
+
#define RCC_LPSRAM3CFGR 0x510
318
+
#define RCC_OSPI1CFGR 0x514
319
+
#define RCC_OSPI2CFGR 0x518
320
+
#define RCC_FMCCFGR 0x51C
321
+
#define RCC_DBGCFGR 0x520
322
+
#define RCC_STM500CFGR 0x524
323
+
#define RCC_ETRCFGR 0x528
324
+
#define RCC_GPIOACFGR 0x52C
325
+
#define RCC_GPIOBCFGR 0x530
326
+
#define RCC_GPIOCCFGR 0x534
327
+
#define RCC_GPIODCFGR 0x538
328
+
#define RCC_GPIOECFGR 0x53C
329
+
#define RCC_GPIOFCFGR 0x540
330
+
#define RCC_GPIOGCFGR 0x544
331
+
#define RCC_GPIOHCFGR 0x548
332
+
#define RCC_GPIOICFGR 0x54C
333
+
#define RCC_GPIOJCFGR 0x550
334
+
#define RCC_GPIOKCFGR 0x554
335
+
#define RCC_GPIOZCFGR 0x558
336
+
#define RCC_HPDMA1CFGR 0x55C
337
+
#define RCC_HPDMA2CFGR 0x560
338
+
#define RCC_HPDMA3CFGR 0x564
339
+
#define RCC_LPDMACFGR 0x568
340
+
#define RCC_HSEMCFGR 0x56C
341
+
#define RCC_IPCC1CFGR 0x570
342
+
#define RCC_IPCC2CFGR 0x574
343
+
#define RCC_RTCCFGR 0x578
344
+
#define RCC_SYSCPU1CFGR 0x580
345
+
#define RCC_BSECCFGR 0x584
346
+
#define RCC_IS2MCFGR 0x58C
347
+
#define RCC_PLL2CFGR1 0x590
348
+
#define RCC_PLL2CFGR2 0x594
349
+
#define RCC_PLL2CFGR3 0x598
350
+
#define RCC_PLL2CFGR4 0x59C
351
+
#define RCC_PLL2CFGR5 0x5A0
352
+
#define RCC_PLL2CFGR6 0x5A8
353
+
#define RCC_PLL2CFGR7 0x5AC
354
+
#define RCC_PLL3CFGR1 0x5B8
355
+
#define RCC_PLL3CFGR2 0x5BC
356
+
#define RCC_PLL3CFGR3 0x5C0
357
+
#define RCC_PLL3CFGR4 0x5C4
358
+
#define RCC_PLL3CFGR5 0x5C8
359
+
#define RCC_PLL3CFGR6 0x5D0
360
+
#define RCC_PLL3CFGR7 0x5D4
361
+
#define RCC_HSIFMONCR 0x5E0
362
+
#define RCC_HSIFVALR 0x5E4
363
+
#define RCC_TIM1CFGR 0x700
364
+
#define RCC_TIM2CFGR 0x704
365
+
#define RCC_TIM3CFGR 0x708
366
+
#define RCC_TIM4CFGR 0x70C
367
+
#define RCC_TIM5CFGR 0x710
368
+
#define RCC_TIM6CFGR 0x714
369
+
#define RCC_TIM7CFGR 0x718
370
+
#define RCC_TIM8CFGR 0x71C
371
+
#define RCC_TIM10CFGR 0x720
372
+
#define RCC_TIM11CFGR 0x724
373
+
#define RCC_TIM12CFGR 0x728
374
+
#define RCC_TIM13CFGR 0x72C
375
+
#define RCC_TIM14CFGR 0x730
376
+
#define RCC_TIM15CFGR 0x734
377
+
#define RCC_TIM16CFGR 0x738
378
+
#define RCC_TIM17CFGR 0x73C
379
+
#define RCC_TIM20CFGR 0x740
380
+
#define RCC_LPTIM1CFGR 0x744
381
+
#define RCC_LPTIM2CFGR 0x748
382
+
#define RCC_LPTIM3CFGR 0x74C
383
+
#define RCC_LPTIM4CFGR 0x750
384
+
#define RCC_LPTIM5CFGR 0x754
385
+
#define RCC_SPI1CFGR 0x758
386
+
#define RCC_SPI2CFGR 0x75C
387
+
#define RCC_SPI3CFGR 0x760
388
+
#define RCC_SPI4CFGR 0x764
389
+
#define RCC_SPI5CFGR 0x768
390
+
#define RCC_SPI6CFGR 0x76C
391
+
#define RCC_SPI7CFGR 0x770
392
+
#define RCC_SPI8CFGR 0x774
393
+
#define RCC_SPDIFRXCFGR 0x778
394
+
#define RCC_USART1CFGR 0x77C
395
+
#define RCC_USART2CFGR 0x780
396
+
#define RCC_USART3CFGR 0x784
397
+
#define RCC_UART4CFGR 0x788
398
+
#define RCC_UART5CFGR 0x78C
399
+
#define RCC_USART6CFGR 0x790
400
+
#define RCC_UART7CFGR 0x794
401
+
#define RCC_UART8CFGR 0x798
402
+
#define RCC_UART9CFGR 0x79C
403
+
#define RCC_LPUART1CFGR 0x7A0
404
+
#define RCC_I2C1CFGR 0x7A4
405
+
#define RCC_I2C2CFGR 0x7A8
406
+
#define RCC_I2C3CFGR 0x7AC
407
+
#define RCC_I2C4CFGR 0x7B0
408
+
#define RCC_I2C5CFGR 0x7B4
409
+
#define RCC_I2C6CFGR 0x7B8
410
+
#define RCC_I2C7CFGR 0x7BC
411
+
#define RCC_I2C8CFGR 0x7C0
412
+
#define RCC_SAI1CFGR 0x7C4
413
+
#define RCC_SAI2CFGR 0x7C8
414
+
#define RCC_SAI3CFGR 0x7CC
415
+
#define RCC_SAI4CFGR 0x7D0
416
+
#define RCC_MDF1CFGR 0x7D8
417
+
#define RCC_ADF1CFGR 0x7DC
418
+
#define RCC_FDCANCFGR 0x7E0
419
+
#define RCC_HDPCFGR 0x7E4
420
+
#define RCC_ADC12CFGR 0x7E8
421
+
#define RCC_ADC3CFGR 0x7EC
422
+
#define RCC_ETH1CFGR 0x7F0
423
+
#define RCC_ETH2CFGR 0x7F4
424
+
#define RCC_USBHCFGR 0x7FC
425
+
#define RCC_USB2PHY1CFGR 0x800
426
+
#define RCC_USB2PHY2CFGR 0x804
427
+
#define RCC_USB3DRCFGR 0x808
428
+
#define RCC_USB3PCIEPHYCFGR 0x80C
429
+
#define RCC_PCIECFGR 0x810
430
+
#define RCC_USBTCCFGR 0x814
431
+
#define RCC_ETHSWCFGR 0x818
432
+
#define RCC_ETHSWACMCFGR 0x81C
433
+
#define RCC_ETHSWACMMSGCFGR 0x820
434
+
#define RCC_STGENCFGR 0x824
435
+
#define RCC_SDMMC1CFGR 0x830
436
+
#define RCC_SDMMC2CFGR 0x834
437
+
#define RCC_SDMMC3CFGR 0x838
438
+
#define RCC_GPUCFGR 0x83C
439
+
#define RCC_LTDCCFGR 0x840
440
+
#define RCC_DSICFGR 0x844
441
+
#define RCC_LVDSCFGR 0x850
442
+
#define RCC_CSICFGR 0x858
443
+
#define RCC_DCMIPPCFGR 0x85C
444
+
#define RCC_CCICFGR 0x860
445
+
#define RCC_VDECCFGR 0x864
446
+
#define RCC_VENCCFGR 0x868
447
+
#define RCC_RNGCFGR 0x870
448
+
#define RCC_PKACFGR 0x874
449
+
#define RCC_SAESCFGR 0x878
450
+
#define RCC_HASHCFGR 0x87C
451
+
#define RCC_CRYP1CFGR 0x880
452
+
#define RCC_CRYP2CFGR 0x884
453
+
#define RCC_IWDG1CFGR 0x888
454
+
#define RCC_IWDG2CFGR 0x88C
455
+
#define RCC_IWDG3CFGR 0x890
456
+
#define RCC_IWDG4CFGR 0x894
457
+
#define RCC_IWDG5CFGR 0x898
458
+
#define RCC_WWDG1CFGR 0x89C
459
+
#define RCC_WWDG2CFGR 0x8A0
460
+
#define RCC_VREFCFGR 0x8A8
461
+
#define RCC_DTSCFGR 0x8AC
462
+
#define RCC_CRCCFGR 0x8B4
463
+
#define RCC_SERCCFGR 0x8B8
464
+
#define RCC_OSPIIOMCFGR 0x8BC
465
+
#define RCC_GICV2MCFGR 0x8C0
466
+
#define RCC_I3C1CFGR 0x8C8
467
+
#define RCC_I3C2CFGR 0x8CC
468
+
#define RCC_I3C3CFGR 0x8D0
469
+
#define RCC_I3C4CFGR 0x8D4
470
+
#define RCC_MUXSELCFGR 0x1000
471
+
#define RCC_XBAR0CFGR 0x1018
472
+
#define RCC_XBAR1CFGR 0x101C
473
+
#define RCC_XBAR2CFGR 0x1020
474
+
#define RCC_XBAR3CFGR 0x1024
475
+
#define RCC_XBAR4CFGR 0x1028
476
+
#define RCC_XBAR5CFGR 0x102C
477
+
#define RCC_XBAR6CFGR 0x1030
478
+
#define RCC_XBAR7CFGR 0x1034
479
+
#define RCC_XBAR8CFGR 0x1038
480
+
#define RCC_XBAR9CFGR 0x103C
481
+
#define RCC_XBAR10CFGR 0x1040
482
+
#define RCC_XBAR11CFGR 0x1044
483
+
#define RCC_XBAR12CFGR 0x1048
484
+
#define RCC_XBAR13CFGR 0x104C
485
+
#define RCC_XBAR14CFGR 0x1050
486
+
#define RCC_XBAR15CFGR 0x1054
487
+
#define RCC_XBAR16CFGR 0x1058
488
+
#define RCC_XBAR17CFGR 0x105C
489
+
#define RCC_XBAR18CFGR 0x1060
490
+
#define RCC_XBAR19CFGR 0x1064
491
+
#define RCC_XBAR20CFGR 0x1068
492
+
#define RCC_XBAR21CFGR 0x106C
493
+
#define RCC_XBAR22CFGR 0x1070
494
+
#define RCC_XBAR23CFGR 0x1074
495
+
#define RCC_XBAR24CFGR 0x1078
496
+
#define RCC_XBAR25CFGR 0x107C
497
+
#define RCC_XBAR26CFGR 0x1080
498
+
#define RCC_XBAR27CFGR 0x1084
499
+
#define RCC_XBAR28CFGR 0x1088
500
+
#define RCC_XBAR29CFGR 0x108C
501
+
#define RCC_XBAR30CFGR 0x1090
502
+
#define RCC_XBAR31CFGR 0x1094
503
+
#define RCC_XBAR32CFGR 0x1098
504
+
#define RCC_XBAR33CFGR 0x109C
505
+
#define RCC_XBAR34CFGR 0x10A0
506
+
#define RCC_XBAR35CFGR 0x10A4
507
+
#define RCC_XBAR36CFGR 0x10A8
508
+
#define RCC_XBAR37CFGR 0x10AC
509
+
#define RCC_XBAR38CFGR 0x10B0
510
+
#define RCC_XBAR39CFGR 0x10B4
511
+
#define RCC_XBAR40CFGR 0x10B8
512
+
#define RCC_XBAR41CFGR 0x10BC
513
+
#define RCC_XBAR42CFGR 0x10C0
514
+
#define RCC_XBAR43CFGR 0x10C4
515
+
#define RCC_XBAR44CFGR 0x10C8
516
+
#define RCC_XBAR45CFGR 0x10CC
517
+
#define RCC_XBAR46CFGR 0x10D0
518
+
#define RCC_XBAR47CFGR 0x10D4
519
+
#define RCC_XBAR48CFGR 0x10D8
520
+
#define RCC_XBAR49CFGR 0x10DC
521
+
#define RCC_XBAR50CFGR 0x10E0
522
+
#define RCC_XBAR51CFGR 0x10E4
523
+
#define RCC_XBAR52CFGR 0x10E8
524
+
#define RCC_XBAR53CFGR 0x10EC
525
+
#define RCC_XBAR54CFGR 0x10F0
526
+
#define RCC_XBAR55CFGR 0x10F4
527
+
#define RCC_XBAR56CFGR 0x10F8
528
+
#define RCC_XBAR57CFGR 0x10FC
529
+
#define RCC_XBAR58CFGR 0x1100
530
+
#define RCC_XBAR59CFGR 0x1104
531
+
#define RCC_XBAR60CFGR 0x1108
532
+
#define RCC_XBAR61CFGR 0x110C
533
+
#define RCC_XBAR62CFGR 0x1110
534
+
#define RCC_XBAR63CFGR 0x1114
535
+
#define RCC_PREDIV0CFGR 0x1118
536
+
#define RCC_PREDIV1CFGR 0x111C
537
+
#define RCC_PREDIV2CFGR 0x1120
538
+
#define RCC_PREDIV3CFGR 0x1124
539
+
#define RCC_PREDIV4CFGR 0x1128
540
+
#define RCC_PREDIV5CFGR 0x112C
541
+
#define RCC_PREDIV6CFGR 0x1130
542
+
#define RCC_PREDIV7CFGR 0x1134
543
+
#define RCC_PREDIV8CFGR 0x1138
544
+
#define RCC_PREDIV9CFGR 0x113C
545
+
#define RCC_PREDIV10CFGR 0x1140
546
+
#define RCC_PREDIV11CFGR 0x1144
547
+
#define RCC_PREDIV12CFGR 0x1148
548
+
#define RCC_PREDIV13CFGR 0x114C
549
+
#define RCC_PREDIV14CFGR 0x1150
550
+
#define RCC_PREDIV15CFGR 0x1154
551
+
#define RCC_PREDIV16CFGR 0x1158
552
+
#define RCC_PREDIV17CFGR 0x115C
553
+
#define RCC_PREDIV18CFGR 0x1160
554
+
#define RCC_PREDIV19CFGR 0x1164
555
+
#define RCC_PREDIV20CFGR 0x1168
556
+
#define RCC_PREDIV21CFGR 0x116C
557
+
#define RCC_PREDIV22CFGR 0x1170
558
+
#define RCC_PREDIV23CFGR 0x1174
559
+
#define RCC_PREDIV24CFGR 0x1178
560
+
#define RCC_PREDIV25CFGR 0x117C
561
+
#define RCC_PREDIV26CFGR 0x1180
562
+
#define RCC_PREDIV27CFGR 0x1184
563
+
#define RCC_PREDIV28CFGR 0x1188
564
+
#define RCC_PREDIV29CFGR 0x118C
565
+
#define RCC_PREDIV30CFGR 0x1190
566
+
#define RCC_PREDIV31CFGR 0x1194
567
+
#define RCC_PREDIV32CFGR 0x1198
568
+
#define RCC_PREDIV33CFGR 0x119C
569
+
#define RCC_PREDIV34CFGR 0x11A0
570
+
#define RCC_PREDIV35CFGR 0x11A4
571
+
#define RCC_PREDIV36CFGR 0x11A8
572
+
#define RCC_PREDIV37CFGR 0x11AC
573
+
#define RCC_PREDIV38CFGR 0x11B0
574
+
#define RCC_PREDIV39CFGR 0x11B4
575
+
#define RCC_PREDIV40CFGR 0x11B8
576
+
#define RCC_PREDIV41CFGR 0x11BC
577
+
#define RCC_PREDIV42CFGR 0x11C0
578
+
#define RCC_PREDIV43CFGR 0x11C4
579
+
#define RCC_PREDIV44CFGR 0x11C8
580
+
#define RCC_PREDIV45CFGR 0x11CC
581
+
#define RCC_PREDIV46CFGR 0x11D0
582
+
#define RCC_PREDIV47CFGR 0x11D4
583
+
#define RCC_PREDIV48CFGR 0x11D8
584
+
#define RCC_PREDIV49CFGR 0x11DC
585
+
#define RCC_PREDIV50CFGR 0x11E0
586
+
#define RCC_PREDIV51CFGR 0x11E4
587
+
#define RCC_PREDIV52CFGR 0x11E8
588
+
#define RCC_PREDIV53CFGR 0x11EC
589
+
#define RCC_PREDIV54CFGR 0x11F0
590
+
#define RCC_PREDIV55CFGR 0x11F4
591
+
#define RCC_PREDIV56CFGR 0x11F8
592
+
#define RCC_PREDIV57CFGR 0x11FC
593
+
#define RCC_PREDIV58CFGR 0x1200
594
+
#define RCC_PREDIV59CFGR 0x1204
595
+
#define RCC_PREDIV60CFGR 0x1208
596
+
#define RCC_PREDIV61CFGR 0x120C
597
+
#define RCC_PREDIV62CFGR 0x1210
598
+
#define RCC_PREDIV63CFGR 0x1214
599
+
#define RCC_PREDIVSR1 0x1218
600
+
#define RCC_PREDIVSR2 0x121C
601
+
#define RCC_FINDIV0CFGR 0x1224
602
+
#define RCC_FINDIV1CFGR 0x1228
603
+
#define RCC_FINDIV2CFGR 0x122C
604
+
#define RCC_FINDIV3CFGR 0x1230
605
+
#define RCC_FINDIV4CFGR 0x1234
606
+
#define RCC_FINDIV5CFGR 0x1238
607
+
#define RCC_FINDIV6CFGR 0x123C
608
+
#define RCC_FINDIV7CFGR 0x1240
609
+
#define RCC_FINDIV8CFGR 0x1244
610
+
#define RCC_FINDIV9CFGR 0x1248
611
+
#define RCC_FINDIV10CFGR 0x124C
612
+
#define RCC_FINDIV11CFGR 0x1250
613
+
#define RCC_FINDIV12CFGR 0x1254
614
+
#define RCC_FINDIV13CFGR 0x1258
615
+
#define RCC_FINDIV14CFGR 0x125C
616
+
#define RCC_FINDIV15CFGR 0x1260
617
+
#define RCC_FINDIV16CFGR 0x1264
618
+
#define RCC_FINDIV17CFGR 0x1268
619
+
#define RCC_FINDIV18CFGR 0x126C
620
+
#define RCC_FINDIV19CFGR 0x1270
621
+
#define RCC_FINDIV20CFGR 0x1274
622
+
#define RCC_FINDIV21CFGR 0x1278
623
+
#define RCC_FINDIV22CFGR 0x127C
624
+
#define RCC_FINDIV23CFGR 0x1280
625
+
#define RCC_FINDIV24CFGR 0x1284
626
+
#define RCC_FINDIV25CFGR 0x1288
627
+
#define RCC_FINDIV26CFGR 0x128C
628
+
#define RCC_FINDIV27CFGR 0x1290
629
+
#define RCC_FINDIV28CFGR 0x1294
630
+
#define RCC_FINDIV29CFGR 0x1298
631
+
#define RCC_FINDIV30CFGR 0x129C
632
+
#define RCC_FINDIV31CFGR 0x12A0
633
+
#define RCC_FINDIV32CFGR 0x12A4
634
+
#define RCC_FINDIV33CFGR 0x12A8
635
+
#define RCC_FINDIV34CFGR 0x12AC
636
+
#define RCC_FINDIV35CFGR 0x12B0
637
+
#define RCC_FINDIV36CFGR 0x12B4
638
+
#define RCC_FINDIV37CFGR 0x12B8
639
+
#define RCC_FINDIV38CFGR 0x12BC
640
+
#define RCC_FINDIV39CFGR 0x12C0
641
+
#define RCC_FINDIV40CFGR 0x12C4
642
+
#define RCC_FINDIV41CFGR 0x12C8
643
+
#define RCC_FINDIV42CFGR 0x12CC
644
+
#define RCC_FINDIV43CFGR 0x12D0
645
+
#define RCC_FINDIV44CFGR 0x12D4
646
+
#define RCC_FINDIV45CFGR 0x12D8
647
+
#define RCC_FINDIV46CFGR 0x12DC
648
+
#define RCC_FINDIV47CFGR 0x12E0
649
+
#define RCC_FINDIV48CFGR 0x12E4
650
+
#define RCC_FINDIV49CFGR 0x12E8
651
+
#define RCC_FINDIV50CFGR 0x12EC
652
+
#define RCC_FINDIV51CFGR 0x12F0
653
+
#define RCC_FINDIV52CFGR 0x12F4
654
+
#define RCC_FINDIV53CFGR 0x12F8
655
+
#define RCC_FINDIV54CFGR 0x12FC
656
+
#define RCC_FINDIV55CFGR 0x1300
657
+
#define RCC_FINDIV56CFGR 0x1304
658
+
#define RCC_FINDIV57CFGR 0x1308
659
+
#define RCC_FINDIV58CFGR 0x130C
660
+
#define RCC_FINDIV59CFGR 0x1310
661
+
#define RCC_FINDIV60CFGR 0x1314
662
+
#define RCC_FINDIV61CFGR 0x1318
663
+
#define RCC_FINDIV62CFGR 0x131C
664
+
#define RCC_FINDIV63CFGR 0x1320
665
+
#define RCC_FINDIVSR1 0x1324
666
+
#define RCC_FINDIVSR2 0x1328
667
+
#define RCC_FCALCOBS0CFGR 0x1340
668
+
#define RCC_FCALCOBS1CFGR 0x1344
669
+
#define RCC_FCALCREFCFGR 0x1348
670
+
#define RCC_FCALCCR1 0x134C
671
+
#define RCC_FCALCCR2 0x1354
672
+
#define RCC_FCALCSR 0x1358
673
+
#define RCC_PLL4CFGR1 0x1360
674
+
#define RCC_PLL4CFGR2 0x1364
675
+
#define RCC_PLL4CFGR3 0x1368
676
+
#define RCC_PLL4CFGR4 0x136C
677
+
#define RCC_PLL4CFGR5 0x1370
678
+
#define RCC_PLL4CFGR6 0x1378
679
+
#define RCC_PLL4CFGR7 0x137C
680
+
#define RCC_PLL5CFGR1 0x1388
681
+
#define RCC_PLL5CFGR2 0x138C
682
+
#define RCC_PLL5CFGR3 0x1390
683
+
#define RCC_PLL5CFGR4 0x1394
684
+
#define RCC_PLL5CFGR5 0x1398
685
+
#define RCC_PLL5CFGR6 0x13A0
686
+
#define RCC_PLL5CFGR7 0x13A4
687
+
#define RCC_PLL6CFGR1 0x13B0
688
+
#define RCC_PLL6CFGR2 0x13B4
689
+
#define RCC_PLL6CFGR3 0x13B8
690
+
#define RCC_PLL6CFGR4 0x13BC
691
+
#define RCC_PLL6CFGR5 0x13C0
692
+
#define RCC_PLL6CFGR6 0x13C8
693
+
#define RCC_PLL6CFGR7 0x13CC
694
+
#define RCC_PLL7CFGR1 0x13D8
695
+
#define RCC_PLL7CFGR2 0x13DC
696
+
#define RCC_PLL7CFGR3 0x13E0
697
+
#define RCC_PLL7CFGR4 0x13E4
698
+
#define RCC_PLL7CFGR5 0x13E8
699
+
#define RCC_PLL7CFGR6 0x13F0
700
+
#define RCC_PLL7CFGR7 0x13F4
701
+
#define RCC_PLL8CFGR1 0x1400
702
+
#define RCC_PLL8CFGR2 0x1404
703
+
#define RCC_PLL8CFGR3 0x1408
704
+
#define RCC_PLL8CFGR4 0x140C
705
+
#define RCC_PLL8CFGR5 0x1410
706
+
#define RCC_PLL8CFGR6 0x1418
707
+
#define RCC_PLL8CFGR7 0x141C
708
+
#define RCC_VERR 0xFFF4
709
+
#define RCC_IDR 0xFFF8
710
+
#define RCC_SIDR 0xFFFC
711
+
712
+
#endif /* STM32MP25_RCC_H */
+1
drivers/clk/sunxi-ng/ccu-sun20i-d1-r.c
+1
drivers/clk/sunxi-ng/ccu-sun20i-d1-r.c
+1
drivers/clk/sunxi-ng/ccu-sun20i-d1.c
+1
drivers/clk/sunxi-ng/ccu-sun20i-d1.c
+1
drivers/clk/sunxi-ng/ccu-sun4i-a10.c
+1
drivers/clk/sunxi-ng/ccu-sun4i-a10.c
+1
drivers/clk/sunxi-ng/ccu-sun50i-a100-r.c
+1
drivers/clk/sunxi-ng/ccu-sun50i-a100-r.c
+1
drivers/clk/sunxi-ng/ccu-sun50i-a100.c
+1
drivers/clk/sunxi-ng/ccu-sun50i-a100.c
+8
-5
drivers/clk/sunxi-ng/ccu-sun50i-a64.c
+8
-5
drivers/clk/sunxi-ng/ccu-sun50i-a64.c
···
171
171
* user manual, and by experiments the PLL doesn't work without
172
172
* these bits toggled.
173
173
*/
174
-
.enable = BIT(31) | BIT(23) | BIT(22),
175
-
.lock = BIT(28),
176
-
.n = _SUNXI_CCU_MULT(8, 4),
177
-
.k = _SUNXI_CCU_MULT_MIN(4, 2, 2),
178
-
.m = _SUNXI_CCU_DIV(0, 4),
174
+
.enable = BIT(31) | BIT(23) | BIT(22),
175
+
.lock = BIT(28),
176
+
.n = _SUNXI_CCU_MULT(8, 4),
177
+
.k = _SUNXI_CCU_MULT_MIN(4, 2, 2),
178
+
.m = _SUNXI_CCU_DIV(0, 4),
179
+
.max_m_n_ratio = 3,
180
+
.min_parent_m_ratio = 24000000,
179
181
.common = {
180
182
.reg = 0x040,
181
183
.hw.init = CLK_HW_INIT("pll-mipi", "pll-video0",
···
982
980
{ .compatible = "allwinner,sun50i-a64-ccu" },
983
981
{ }
984
982
};
983
+
MODULE_DEVICE_TABLE(of, sun50i_a64_ccu_ids);
985
984
986
985
static struct platform_driver sun50i_a64_ccu_driver = {
987
986
.probe = sun50i_a64_ccu_probe,
+1
drivers/clk/sunxi-ng/ccu-sun50i-h6-r.c
+1
drivers/clk/sunxi-ng/ccu-sun50i-h6-r.c
+1
drivers/clk/sunxi-ng/ccu-sun50i-h6.c
+1
drivers/clk/sunxi-ng/ccu-sun50i-h6.c
+1
drivers/clk/sunxi-ng/ccu-sun50i-h616.c
+1
drivers/clk/sunxi-ng/ccu-sun50i-h616.c
+1
drivers/clk/sunxi-ng/ccu-sun6i-a31.c
+1
drivers/clk/sunxi-ng/ccu-sun6i-a31.c
+1
drivers/clk/sunxi-ng/ccu-sun6i-rtc.c
+1
drivers/clk/sunxi-ng/ccu-sun6i-rtc.c
+1
drivers/clk/sunxi-ng/ccu-sun8i-a23.c
+1
drivers/clk/sunxi-ng/ccu-sun8i-a23.c
+1
drivers/clk/sunxi-ng/ccu-sun8i-a33.c
+1
drivers/clk/sunxi-ng/ccu-sun8i-a33.c
+1
drivers/clk/sunxi-ng/ccu-sun8i-a83t.c
+1
drivers/clk/sunxi-ng/ccu-sun8i-a83t.c
+1
drivers/clk/sunxi-ng/ccu-sun8i-de2.c
+1
drivers/clk/sunxi-ng/ccu-sun8i-de2.c
+1
drivers/clk/sunxi-ng/ccu-sun8i-h3.c
+1
drivers/clk/sunxi-ng/ccu-sun8i-h3.c
+1
drivers/clk/sunxi-ng/ccu-sun8i-r.c
+1
drivers/clk/sunxi-ng/ccu-sun8i-r.c
+1
drivers/clk/sunxi-ng/ccu-sun8i-r40.c
+1
drivers/clk/sunxi-ng/ccu-sun8i-r40.c
+1
drivers/clk/sunxi-ng/ccu-sun8i-v3s.c
+1
drivers/clk/sunxi-ng/ccu-sun8i-v3s.c
+1
drivers/clk/sunxi-ng/ccu-sun9i-a80-de.c
+1
drivers/clk/sunxi-ng/ccu-sun9i-a80-de.c
+1
drivers/clk/sunxi-ng/ccu-sun9i-a80-usb.c
+1
drivers/clk/sunxi-ng/ccu-sun9i-a80-usb.c
+1
drivers/clk/sunxi-ng/ccu-sun9i-a80.c
+1
drivers/clk/sunxi-ng/ccu-sun9i-a80.c
+1
drivers/clk/sunxi-ng/ccu-suniv-f1c100s.c
+1
drivers/clk/sunxi-ng/ccu-suniv-f1c100s.c
+21
drivers/clk/sunxi-ng/ccu_nkm.c
+21
drivers/clk/sunxi-ng/ccu_nkm.c
···
16
16
unsigned long m, min_m, max_m;
17
17
};
18
18
19
+
static bool ccu_nkm_is_valid_rate(struct ccu_common *common, unsigned long parent,
20
+
unsigned long n, unsigned long m)
21
+
{
22
+
struct ccu_nkm *nkm = container_of(common, struct ccu_nkm, common);
23
+
24
+
if (nkm->max_m_n_ratio && (m > nkm->max_m_n_ratio * n))
25
+
return false;
26
+
27
+
if (nkm->min_parent_m_ratio && (parent < nkm->min_parent_m_ratio * m))
28
+
return false;
29
+
30
+
return true;
31
+
}
32
+
19
33
static unsigned long ccu_nkm_find_best_with_parent_adj(struct ccu_common *common,
20
34
struct clk_hw *parent_hw,
21
35
unsigned long *parent, unsigned long rate,
···
45
31
unsigned long tmp_rate, tmp_parent;
46
32
47
33
tmp_parent = clk_hw_round_rate(parent_hw, rate * _m / (_n * _k));
34
+
35
+
if (!ccu_nkm_is_valid_rate(common, tmp_parent, _n, _m))
36
+
continue;
37
+
48
38
tmp_rate = tmp_parent * _n * _k / _m;
49
39
50
40
if (ccu_is_better_rate(common, rate, tmp_rate, best_rate) ||
···
82
64
for (_k = nkm->min_k; _k <= nkm->max_k; _k++) {
83
65
for (_n = nkm->min_n; _n <= nkm->max_n; _n++) {
84
66
for (_m = nkm->min_m; _m <= nkm->max_m; _m++) {
67
+
if (!ccu_nkm_is_valid_rate(common, parent, _n, _m))
68
+
continue;
69
+
85
70
unsigned long tmp_rate;
86
71
87
72
tmp_rate = parent * _n * _k / _m;
+2
drivers/clk/sunxi-ng/ccu_nkm.h
+2
drivers/clk/sunxi-ng/ccu_nkm.h
+4
-6
drivers/clk/ti/dpll.c
+4
-6
drivers/clk/ti/dpll.c
···
34
34
.save_context = &omap3_core_dpll_save_context,
35
35
.restore_context = &omap3_core_dpll_restore_context,
36
36
};
37
-
#else
38
-
static const struct clk_ops dpll_m4xen_ck_ops = {};
39
37
#endif
40
38
41
39
#if defined(CONFIG_ARCH_OMAP3) || defined(CONFIG_ARCH_OMAP4) || \
···
93
95
.recalc_rate = &omap3_dpll_recalc,
94
96
.round_rate = &omap2_dpll_round_rate,
95
97
};
96
-
#else
97
-
static const struct clk_ops omap3_dpll_core_ck_ops = {};
98
-
#endif
99
98
100
-
#ifdef CONFIG_ARCH_OMAP3
101
99
static const struct clk_ops omap3_dpll_ck_ops = {
102
100
.enable = &omap3_noncore_dpll_enable,
103
101
.disable = &omap3_noncore_dpll_disable,
···
131
137
};
132
138
#endif
133
139
140
+
#if defined(CONFIG_ARCH_OMAP4) || defined(CONFIG_SOC_OMAP5) || \
141
+
defined(CONFIG_SOC_DRA7XX) || defined(CONFIG_SOC_AM33XX) || \
142
+
defined(CONFIG_SOC_AM43XX)
134
143
static const struct clk_ops dpll_x2_ck_ops = {
135
144
.recalc_rate = &omap3_clkoutx2_recalc,
136
145
};
146
+
#endif
137
147
138
148
/**
139
149
* _register_dpll - low level registration of a DPLL clock
+86
-9
drivers/reset/reset-mpfs.c
+86
-9
drivers/reset/reset-mpfs.c
···
8
8
*/
9
9
#include <linux/auxiliary_bus.h>
10
10
#include <linux/delay.h>
11
+
#include <linux/io.h>
11
12
#include <linux/module.h>
12
13
#include <linux/of.h>
13
14
#include <linux/platform_device.h>
15
+
#include <linux/slab.h>
14
16
#include <linux/reset-controller.h>
15
17
#include <dt-bindings/clock/microchip,mpfs-clock.h>
16
18
#include <soc/microchip/mpfs.h>
···
30
28
/* block concurrent access to the soft reset register */
31
29
static DEFINE_SPINLOCK(mpfs_reset_lock);
32
30
31
+
struct mpfs_reset {
32
+
void __iomem *base;
33
+
struct reset_controller_dev rcdev;
34
+
};
35
+
36
+
static inline struct mpfs_reset *to_mpfs_reset(struct reset_controller_dev *rcdev)
37
+
{
38
+
return container_of(rcdev, struct mpfs_reset, rcdev);
39
+
}
40
+
33
41
/*
34
42
* Peripheral clock resets
35
43
*/
36
-
37
44
static int mpfs_assert(struct reset_controller_dev *rcdev, unsigned long id)
38
45
{
46
+
struct mpfs_reset *rst = to_mpfs_reset(rcdev);
39
47
unsigned long flags;
40
48
u32 reg;
41
49
42
50
spin_lock_irqsave(&mpfs_reset_lock, flags);
43
51
44
-
reg = mpfs_reset_read(rcdev->dev);
52
+
reg = readl(rst->base);
45
53
reg |= BIT(id);
46
-
mpfs_reset_write(rcdev->dev, reg);
54
+
writel(reg, rst->base);
47
55
48
56
spin_unlock_irqrestore(&mpfs_reset_lock, flags);
49
57
···
62
50
63
51
static int mpfs_deassert(struct reset_controller_dev *rcdev, unsigned long id)
64
52
{
53
+
struct mpfs_reset *rst = to_mpfs_reset(rcdev);
65
54
unsigned long flags;
66
55
u32 reg;
67
56
68
57
spin_lock_irqsave(&mpfs_reset_lock, flags);
69
58
70
-
reg = mpfs_reset_read(rcdev->dev);
59
+
reg = readl(rst->base);
71
60
reg &= ~BIT(id);
72
-
mpfs_reset_write(rcdev->dev, reg);
61
+
writel(reg, rst->base);
73
62
74
63
spin_unlock_irqrestore(&mpfs_reset_lock, flags);
75
64
···
79
66
80
67
static int mpfs_status(struct reset_controller_dev *rcdev, unsigned long id)
81
68
{
82
-
u32 reg = mpfs_reset_read(rcdev->dev);
69
+
struct mpfs_reset *rst = to_mpfs_reset(rcdev);
70
+
u32 reg = readl(rst->base);
83
71
84
72
/*
85
73
* It is safe to return here as MPFS_NUM_RESETS makes sure the sign bit
···
135
121
{
136
122
struct device *dev = &adev->dev;
137
123
struct reset_controller_dev *rcdev;
124
+
struct mpfs_reset *rst;
138
125
139
-
rcdev = devm_kzalloc(dev, sizeof(*rcdev), GFP_KERNEL);
140
-
if (!rcdev)
126
+
rst = devm_kzalloc(dev, sizeof(*rst), GFP_KERNEL);
127
+
if (!rst)
141
128
return -ENOMEM;
142
129
130
+
rst->base = (void __iomem *)adev->dev.platform_data;
131
+
132
+
rcdev = &rst->rcdev;
143
133
rcdev->dev = dev;
144
134
rcdev->dev->parent = dev->parent;
145
135
rcdev->ops = &mpfs_reset_ops;
···
155
137
return devm_reset_controller_register(dev, rcdev);
156
138
}
157
139
140
+
static void mpfs_reset_unregister_adev(void *_adev)
141
+
{
142
+
struct auxiliary_device *adev = _adev;
143
+
144
+
auxiliary_device_delete(adev);
145
+
auxiliary_device_uninit(adev);
146
+
}
147
+
148
+
static void mpfs_reset_adev_release(struct device *dev)
149
+
{
150
+
struct auxiliary_device *adev = to_auxiliary_dev(dev);
151
+
152
+
kfree(adev);
153
+
}
154
+
155
+
static struct auxiliary_device *mpfs_reset_adev_alloc(struct device *clk_dev)
156
+
{
157
+
struct auxiliary_device *adev;
158
+
int ret;
159
+
160
+
adev = kzalloc(sizeof(*adev), GFP_KERNEL);
161
+
if (!adev)
162
+
return ERR_PTR(-ENOMEM);
163
+
164
+
adev->name = "reset-mpfs";
165
+
adev->dev.parent = clk_dev;
166
+
adev->dev.release = mpfs_reset_adev_release;
167
+
adev->id = 666u;
168
+
169
+
ret = auxiliary_device_init(adev);
170
+
if (ret) {
171
+
kfree(adev);
172
+
return ERR_PTR(ret);
173
+
}
174
+
175
+
return adev;
176
+
}
177
+
178
+
int mpfs_reset_controller_register(struct device *clk_dev, void __iomem *base)
179
+
{
180
+
struct auxiliary_device *adev;
181
+
int ret;
182
+
183
+
adev = mpfs_reset_adev_alloc(clk_dev);
184
+
if (IS_ERR(adev))
185
+
return PTR_ERR(adev);
186
+
187
+
ret = auxiliary_device_add(adev);
188
+
if (ret) {
189
+
auxiliary_device_uninit(adev);
190
+
return ret;
191
+
}
192
+
193
+
adev->dev.platform_data = (__force void *)base;
194
+
195
+
return devm_add_action_or_reset(clk_dev, mpfs_reset_unregister_adev, adev);
196
+
}
197
+
EXPORT_SYMBOL_NS_GPL(mpfs_reset_controller_register, MCHP_CLK_MPFS);
198
+
158
199
static const struct auxiliary_device_id mpfs_reset_ids[] = {
159
200
{
160
-
.name = "clk_mpfs.reset-mpfs",
201
+
.name = "reset_mpfs.reset-mpfs",
161
202
},
162
203
{ }
163
204
};
+35
-19
include/dt-bindings/clock/loongson,ls2k-clk.h
+35
-19
include/dt-bindings/clock/loongson,ls2k-clk.h
···
7
7
#ifndef __DT_BINDINGS_CLOCK_LOONGSON2_H
8
8
#define __DT_BINDINGS_CLOCK_LOONGSON2_H
9
9
10
-
#define LOONGSON2_REF_100M 0
11
-
#define LOONGSON2_NODE_PLL 1
12
-
#define LOONGSON2_DDR_PLL 2
13
-
#define LOONGSON2_DC_PLL 3
14
-
#define LOONGSON2_PIX0_PLL 4
15
-
#define LOONGSON2_PIX1_PLL 5
16
-
#define LOONGSON2_NODE_CLK 6
17
-
#define LOONGSON2_HDA_CLK 7
18
-
#define LOONGSON2_GPU_CLK 8
19
-
#define LOONGSON2_DDR_CLK 9
20
-
#define LOONGSON2_GMAC_CLK 10
21
-
#define LOONGSON2_DC_CLK 11
22
-
#define LOONGSON2_APB_CLK 12
23
-
#define LOONGSON2_USB_CLK 13
24
-
#define LOONGSON2_SATA_CLK 14
25
-
#define LOONGSON2_PIX0_CLK 15
26
-
#define LOONGSON2_PIX1_CLK 16
27
-
#define LOONGSON2_BOOT_CLK 17
28
-
#define LOONGSON2_CLK_END 18
10
+
#define LOONGSON2_REF_100M 0
11
+
#define LOONGSON2_NODE_PLL 1
12
+
#define LOONGSON2_DDR_PLL 2
13
+
#define LOONGSON2_DC_PLL 3
14
+
#define LOONGSON2_PIX0_PLL 4
15
+
#define LOONGSON2_PIX1_PLL 5
16
+
#define LOONGSON2_NODE_CLK 6
17
+
#define LOONGSON2_HDA_CLK 7
18
+
#define LOONGSON2_GPU_CLK 8
19
+
#define LOONGSON2_DDR_CLK 9
20
+
#define LOONGSON2_GMAC_CLK 10
21
+
#define LOONGSON2_DC_CLK 11
22
+
#define LOONGSON2_APB_CLK 12
23
+
#define LOONGSON2_USB_CLK 13
24
+
#define LOONGSON2_SATA_CLK 14
25
+
#define LOONGSON2_PIX0_CLK 15
26
+
#define LOONGSON2_PIX1_CLK 16
27
+
#define LOONGSON2_BOOT_CLK 17
28
+
#define LOONGSON2_OUT0_GATE 18
29
+
#define LOONGSON2_GMAC_GATE 19
30
+
#define LOONGSON2_RIO_GATE 20
31
+
#define LOONGSON2_DC_GATE 21
32
+
#define LOONGSON2_GPU_GATE 22
33
+
#define LOONGSON2_DDR_GATE 23
34
+
#define LOONGSON2_HDA_GATE 24
35
+
#define LOONGSON2_NODE_GATE 25
36
+
#define LOONGSON2_EMMC_GATE 26
37
+
#define LOONGSON2_PIX0_GATE 27
38
+
#define LOONGSON2_PIX1_GATE 28
39
+
#define LOONGSON2_OUT0_CLK 29
40
+
#define LOONGSON2_RIO_CLK 30
41
+
#define LOONGSON2_EMMC_CLK 31
42
+
#define LOONGSON2_DES_CLK 32
43
+
#define LOONGSON2_I2S_CLK 33
44
+
#define LOONGSON2_MISC_CLK 34
29
45
30
46
#endif
+28
include/dt-bindings/clock/nxp,imx95-clock.h
+28
include/dt-bindings/clock/nxp,imx95-clock.h
···
1
+
/* SPDX-License-Identifier: GPL-2.0-only OR MIT */
2
+
/*
3
+
* Copyright 2024 NXP
4
+
*/
5
+
6
+
#ifndef __DT_BINDINGS_CLOCK_IMX95_H
7
+
#define __DT_BINDINGS_CLOCK_IMX95_H
8
+
9
+
#define IMX95_CLK_VPUBLK_WAVE 0
10
+
#define IMX95_CLK_VPUBLK_JPEG_ENC 1
11
+
#define IMX95_CLK_VPUBLK_JPEG_DEC 2
12
+
13
+
#define IMX95_CLK_CAMBLK_CSI2_FOR0 0
14
+
#define IMX95_CLK_CAMBLK_CSI2_FOR1 1
15
+
#define IMX95_CLK_CAMBLK_ISP_AXI 2
16
+
#define IMX95_CLK_CAMBLK_ISP_PIXEL 3
17
+
#define IMX95_CLK_CAMBLK_ISP 4
18
+
19
+
#define IMX95_CLK_DISPMIX_LVDS_PHY_DIV 0
20
+
#define IMX95_CLK_DISPMIX_LVDS_CH0_GATE 1
21
+
#define IMX95_CLK_DISPMIX_LVDS_CH1_GATE 2
22
+
#define IMX95_CLK_DISPMIX_PIX_DI0_GATE 3
23
+
#define IMX95_CLK_DISPMIX_PIX_DI1_GATE 4
24
+
25
+
#define IMX95_CLK_DISPMIX_ENG0_SEL 0
26
+
#define IMX95_CLK_DISPMIX_ENG1_SEL 1
27
+
28
+
#endif /* __DT_BINDINGS_CLOCK_IMX95_H */
+55
-3
include/dt-bindings/clock/r9a07g043-cpg.h
+55
-3
include/dt-bindings/clock/r9a07g043-cpg.h
···
16
16
#define R9A07G043_CLK_SD0 5
17
17
#define R9A07G043_CLK_SD1 6
18
18
#define R9A07G043_CLK_M0 7
19
-
#define R9A07G043_CLK_M2 8
20
-
#define R9A07G043_CLK_M3 9
19
+
#define R9A07G043_CLK_M2 8 /* RZ/G2UL Only */
20
+
#define R9A07G043_CLK_M3 9 /* RZ/G2UL Only */
21
21
#define R9A07G043_CLK_HP 10
22
22
#define R9A07G043_CLK_TSU 11
23
23
#define R9A07G043_CLK_ZT 12
24
24
#define R9A07G043_CLK_P0 13
25
25
#define R9A07G043_CLK_P1 14
26
26
#define R9A07G043_CLK_P2 15
27
-
#define R9A07G043_CLK_AT 16
27
+
#define R9A07G043_CLK_AT 16 /* RZ/G2UL Only */
28
28
#define R9A07G043_OSCCLK 17
29
29
#define R9A07G043_CLK_P0_DIV2 18
30
30
···
200
200
#define R9A07G043_AX45MP_CORE0_RESETN 78 /* RZ/Five Only */
201
201
#define R9A07G043_IAX45_RESETN 79 /* RZ/Five Only */
202
202
203
+
/* Power domain IDs. */
204
+
#define R9A07G043_PD_ALWAYS_ON 0
205
+
#define R9A07G043_PD_GIC 1 /* RZ/G2UL Only */
206
+
#define R9A07G043_PD_IA55 2 /* RZ/G2UL Only */
207
+
#define R9A07G043_PD_MHU 3 /* RZ/G2UL Only */
208
+
#define R9A07G043_PD_CORESIGHT 4 /* RZ/G2UL Only */
209
+
#define R9A07G043_PD_SYC 5 /* RZ/G2UL Only */
210
+
#define R9A07G043_PD_DMAC 6
211
+
#define R9A07G043_PD_GTM0 7
212
+
#define R9A07G043_PD_GTM1 8
213
+
#define R9A07G043_PD_GTM2 9
214
+
#define R9A07G043_PD_MTU 10
215
+
#define R9A07G043_PD_POE3 11
216
+
#define R9A07G043_PD_WDT0 12
217
+
#define R9A07G043_PD_SPI 13
218
+
#define R9A07G043_PD_SDHI0 14
219
+
#define R9A07G043_PD_SDHI1 15
220
+
#define R9A07G043_PD_ISU 16 /* RZ/G2UL Only */
221
+
#define R9A07G043_PD_CRU 17 /* RZ/G2UL Only */
222
+
#define R9A07G043_PD_LCDC 18 /* RZ/G2UL Only */
223
+
#define R9A07G043_PD_SSI0 19
224
+
#define R9A07G043_PD_SSI1 20
225
+
#define R9A07G043_PD_SSI2 21
226
+
#define R9A07G043_PD_SSI3 22
227
+
#define R9A07G043_PD_SRC 23
228
+
#define R9A07G043_PD_USB0 24
229
+
#define R9A07G043_PD_USB1 25
230
+
#define R9A07G043_PD_USB_PHY 26
231
+
#define R9A07G043_PD_ETHER0 27
232
+
#define R9A07G043_PD_ETHER1 28
233
+
#define R9A07G043_PD_I2C0 29
234
+
#define R9A07G043_PD_I2C1 30
235
+
#define R9A07G043_PD_I2C2 31
236
+
#define R9A07G043_PD_I2C3 32
237
+
#define R9A07G043_PD_SCIF0 33
238
+
#define R9A07G043_PD_SCIF1 34
239
+
#define R9A07G043_PD_SCIF2 35
240
+
#define R9A07G043_PD_SCIF3 36
241
+
#define R9A07G043_PD_SCIF4 37
242
+
#define R9A07G043_PD_SCI0 38
243
+
#define R9A07G043_PD_SCI1 39
244
+
#define R9A07G043_PD_IRDA 40
245
+
#define R9A07G043_PD_RSPI0 41
246
+
#define R9A07G043_PD_RSPI1 42
247
+
#define R9A07G043_PD_RSPI2 43
248
+
#define R9A07G043_PD_CANFD 44
249
+
#define R9A07G043_PD_ADC 45
250
+
#define R9A07G043_PD_TSU 46
251
+
#define R9A07G043_PD_PLIC 47 /* RZ/Five Only */
252
+
#define R9A07G043_PD_IAX45 48 /* RZ/Five Only */
253
+
#define R9A07G043_PD_NCEPLDM 49 /* RZ/Five Only */
254
+
#define R9A07G043_PD_NCEPLMT 50 /* RZ/Five Only */
203
255
204
256
#endif /* __DT_BINDINGS_CLOCK_R9A07G043_CPG_H__ */
+58
include/dt-bindings/clock/r9a07g044-cpg.h
+58
include/dt-bindings/clock/r9a07g044-cpg.h
···
217
217
#define R9A07G044_ADC_ADRST_N 82
218
218
#define R9A07G044_TSU_PRESETN 83
219
219
220
+
/* Power domain IDs. */
221
+
#define R9A07G044_PD_ALWAYS_ON 0
222
+
#define R9A07G044_PD_GIC 1
223
+
#define R9A07G044_PD_IA55 2
224
+
#define R9A07G044_PD_MHU 3
225
+
#define R9A07G044_PD_CORESIGHT 4
226
+
#define R9A07G044_PD_SYC 5
227
+
#define R9A07G044_PD_DMAC 6
228
+
#define R9A07G044_PD_GTM0 7
229
+
#define R9A07G044_PD_GTM1 8
230
+
#define R9A07G044_PD_GTM2 9
231
+
#define R9A07G044_PD_MTU 10
232
+
#define R9A07G044_PD_POE3 11
233
+
#define R9A07G044_PD_GPT 12
234
+
#define R9A07G044_PD_POEGA 13
235
+
#define R9A07G044_PD_POEGB 14
236
+
#define R9A07G044_PD_POEGC 15
237
+
#define R9A07G044_PD_POEGD 16
238
+
#define R9A07G044_PD_WDT0 17
239
+
#define R9A07G044_PD_WDT1 18
240
+
#define R9A07G044_PD_SPI 19
241
+
#define R9A07G044_PD_SDHI0 20
242
+
#define R9A07G044_PD_SDHI1 21
243
+
#define R9A07G044_PD_3DGE 22
244
+
#define R9A07G044_PD_ISU 23
245
+
#define R9A07G044_PD_VCPL4 24
246
+
#define R9A07G044_PD_CRU 25
247
+
#define R9A07G044_PD_MIPI_DSI 26
248
+
#define R9A07G044_PD_LCDC 27
249
+
#define R9A07G044_PD_SSI0 28
250
+
#define R9A07G044_PD_SSI1 29
251
+
#define R9A07G044_PD_SSI2 30
252
+
#define R9A07G044_PD_SSI3 31
253
+
#define R9A07G044_PD_SRC 32
254
+
#define R9A07G044_PD_USB0 33
255
+
#define R9A07G044_PD_USB1 34
256
+
#define R9A07G044_PD_USB_PHY 35
257
+
#define R9A07G044_PD_ETHER0 36
258
+
#define R9A07G044_PD_ETHER1 37
259
+
#define R9A07G044_PD_I2C0 38
260
+
#define R9A07G044_PD_I2C1 39
261
+
#define R9A07G044_PD_I2C2 40
262
+
#define R9A07G044_PD_I2C3 41
263
+
#define R9A07G044_PD_SCIF0 42
264
+
#define R9A07G044_PD_SCIF1 43
265
+
#define R9A07G044_PD_SCIF2 44
266
+
#define R9A07G044_PD_SCIF3 45
267
+
#define R9A07G044_PD_SCIF4 46
268
+
#define R9A07G044_PD_SCI0 47
269
+
#define R9A07G044_PD_SCI1 48
270
+
#define R9A07G044_PD_IRDA 49
271
+
#define R9A07G044_PD_RSPI0 50
272
+
#define R9A07G044_PD_RSPI1 51
273
+
#define R9A07G044_PD_RSPI2 52
274
+
#define R9A07G044_PD_CANFD 53
275
+
#define R9A07G044_PD_ADC 54
276
+
#define R9A07G044_PD_TSU 55
277
+
220
278
#endif /* __DT_BINDINGS_CLOCK_R9A07G044_CPG_H__ */
+58
include/dt-bindings/clock/r9a07g054-cpg.h
+58
include/dt-bindings/clock/r9a07g054-cpg.h
···
226
226
#define R9A07G054_TSU_PRESETN 83
227
227
#define R9A07G054_STPAI_ARESETN 84
228
228
229
+
/* Power domain IDs. */
230
+
#define R9A07G054_PD_ALWAYS_ON 0
231
+
#define R9A07G054_PD_GIC 1
232
+
#define R9A07G054_PD_IA55 2
233
+
#define R9A07G054_PD_MHU 3
234
+
#define R9A07G054_PD_CORESIGHT 4
235
+
#define R9A07G054_PD_SYC 5
236
+
#define R9A07G054_PD_DMAC 6
237
+
#define R9A07G054_PD_GTM0 7
238
+
#define R9A07G054_PD_GTM1 8
239
+
#define R9A07G054_PD_GTM2 9
240
+
#define R9A07G054_PD_MTU 10
241
+
#define R9A07G054_PD_POE3 11
242
+
#define R9A07G054_PD_GPT 12
243
+
#define R9A07G054_PD_POEGA 13
244
+
#define R9A07G054_PD_POEGB 14
245
+
#define R9A07G054_PD_POEGC 15
246
+
#define R9A07G054_PD_POEGD 16
247
+
#define R9A07G054_PD_WDT0 17
248
+
#define R9A07G054_PD_WDT1 18
249
+
#define R9A07G054_PD_SPI 19
250
+
#define R9A07G054_PD_SDHI0 20
251
+
#define R9A07G054_PD_SDHI1 21
252
+
#define R9A07G054_PD_3DGE 22
253
+
#define R9A07G054_PD_ISU 23
254
+
#define R9A07G054_PD_VCPL4 24
255
+
#define R9A07G054_PD_CRU 25
256
+
#define R9A07G054_PD_MIPI_DSI 26
257
+
#define R9A07G054_PD_LCDC 27
258
+
#define R9A07G054_PD_SSI0 28
259
+
#define R9A07G054_PD_SSI1 29
260
+
#define R9A07G054_PD_SSI2 30
261
+
#define R9A07G054_PD_SSI3 31
262
+
#define R9A07G054_PD_SRC 32
263
+
#define R9A07G054_PD_USB0 33
264
+
#define R9A07G054_PD_USB1 34
265
+
#define R9A07G054_PD_USB_PHY 35
266
+
#define R9A07G054_PD_ETHER0 36
267
+
#define R9A07G054_PD_ETHER1 37
268
+
#define R9A07G054_PD_I2C0 38
269
+
#define R9A07G054_PD_I2C1 39
270
+
#define R9A07G054_PD_I2C2 40
271
+
#define R9A07G054_PD_I2C3 41
272
+
#define R9A07G054_PD_SCIF0 42
273
+
#define R9A07G054_PD_SCIF1 43
274
+
#define R9A07G054_PD_SCIF2 44
275
+
#define R9A07G054_PD_SCIF3 45
276
+
#define R9A07G054_PD_SCIF4 46
277
+
#define R9A07G054_PD_SCI0 47
278
+
#define R9A07G054_PD_SCI1 48
279
+
#define R9A07G054_PD_IRDA 49
280
+
#define R9A07G054_PD_RSPI0 50
281
+
#define R9A07G054_PD_RSPI1 51
282
+
#define R9A07G054_PD_RSPI2 52
283
+
#define R9A07G054_PD_CANFD 53
284
+
#define R9A07G054_PD_ADC 54
285
+
#define R9A07G054_PD_TSU 55
286
+
229
287
#endif /* __DT_BINDINGS_CLOCK_R9A07G054_CPG_H__ */
+70
include/dt-bindings/clock/r9a08g045-cpg.h
+70
include/dt-bindings/clock/r9a08g045-cpg.h
···
239
239
#define R9A08G045_I3C_PRESETN 92
240
240
#define R9A08G045_VBAT_BRESETN 93
241
241
242
+
/* Power domain IDs. */
243
+
#define R9A08G045_PD_ALWAYS_ON 0
244
+
#define R9A08G045_PD_GIC 1
245
+
#define R9A08G045_PD_IA55 2
246
+
#define R9A08G045_PD_MHU 3
247
+
#define R9A08G045_PD_CORESIGHT 4
248
+
#define R9A08G045_PD_SYC 5
249
+
#define R9A08G045_PD_DMAC 6
250
+
#define R9A08G045_PD_GTM0 7
251
+
#define R9A08G045_PD_GTM1 8
252
+
#define R9A08G045_PD_GTM2 9
253
+
#define R9A08G045_PD_GTM3 10
254
+
#define R9A08G045_PD_GTM4 11
255
+
#define R9A08G045_PD_GTM5 12
256
+
#define R9A08G045_PD_GTM6 13
257
+
#define R9A08G045_PD_GTM7 14
258
+
#define R9A08G045_PD_MTU 15
259
+
#define R9A08G045_PD_POE3 16
260
+
#define R9A08G045_PD_GPT 17
261
+
#define R9A08G045_PD_POEGA 18
262
+
#define R9A08G045_PD_POEGB 19
263
+
#define R9A08G045_PD_POEGC 20
264
+
#define R9A08G045_PD_POEGD 21
265
+
#define R9A08G045_PD_WDT0 22
266
+
#define R9A08G045_PD_XSPI 23
267
+
#define R9A08G045_PD_SDHI0 24
268
+
#define R9A08G045_PD_SDHI1 25
269
+
#define R9A08G045_PD_SDHI2 26
270
+
#define R9A08G045_PD_SSI0 27
271
+
#define R9A08G045_PD_SSI1 28
272
+
#define R9A08G045_PD_SSI2 29
273
+
#define R9A08G045_PD_SSI3 30
274
+
#define R9A08G045_PD_SRC 31
275
+
#define R9A08G045_PD_USB0 32
276
+
#define R9A08G045_PD_USB1 33
277
+
#define R9A08G045_PD_USB_PHY 34
278
+
#define R9A08G045_PD_ETHER0 35
279
+
#define R9A08G045_PD_ETHER1 36
280
+
#define R9A08G045_PD_I2C0 37
281
+
#define R9A08G045_PD_I2C1 38
282
+
#define R9A08G045_PD_I2C2 39
283
+
#define R9A08G045_PD_I2C3 40
284
+
#define R9A08G045_PD_SCIF0 41
285
+
#define R9A08G045_PD_SCIF1 42
286
+
#define R9A08G045_PD_SCIF2 43
287
+
#define R9A08G045_PD_SCIF3 44
288
+
#define R9A08G045_PD_SCIF4 45
289
+
#define R9A08G045_PD_SCIF5 46
290
+
#define R9A08G045_PD_SCI0 47
291
+
#define R9A08G045_PD_SCI1 48
292
+
#define R9A08G045_PD_IRDA 49
293
+
#define R9A08G045_PD_RSPI0 50
294
+
#define R9A08G045_PD_RSPI1 51
295
+
#define R9A08G045_PD_RSPI2 52
296
+
#define R9A08G045_PD_RSPI3 53
297
+
#define R9A08G045_PD_RSPI4 54
298
+
#define R9A08G045_PD_CANFD 55
299
+
#define R9A08G045_PD_ADC 56
300
+
#define R9A08G045_PD_TSU 57
301
+
#define R9A08G045_PD_OCTA 58
302
+
#define R9A08G045_PD_PDM 59
303
+
#define R9A08G045_PD_PCI 60
304
+
#define R9A08G045_PD_SPDIF 61
305
+
#define R9A08G045_PD_I3C 62
306
+
#define R9A08G045_PD_VBAT 63
307
+
308
+
#define R9A08G045_PD_DDR 64
309
+
#define R9A08G045_PD_TZCDDR 65
310
+
#define R9A08G045_PD_OTFDE_DDR 66
311
+
242
312
#endif /* __DT_BINDINGS_CLOCK_R9A08G045_CPG_H__ */
+1
include/dt-bindings/clock/rk3568-cru.h
+1
include/dt-bindings/clock/rk3568-cru.h
+2
include/dt-bindings/reset/rockchip,rk3588-cru.h
+2
include/dt-bindings/reset/rockchip,rk3588-cru.h
+1
-1
include/dt-bindings/reset/st,stm32mp25-rcc.h
+1
-1
include/dt-bindings/reset/st,stm32mp25-rcc.h
+5
-5
include/soc/microchip/mpfs.h
+5
-5
include/soc/microchip/mpfs.h
···
43
43
#endif /* if IS_ENABLED(CONFIG_POLARFIRE_SOC_SYS_CTRL) */
44
44
45
45
#if IS_ENABLED(CONFIG_MCHP_CLK_MPFS)
46
-
47
-
u32 mpfs_reset_read(struct device *dev);
48
-
49
-
void mpfs_reset_write(struct device *dev, u32 val);
50
-
46
+
#if IS_ENABLED(CONFIG_RESET_POLARFIRE_SOC)
47
+
int mpfs_reset_controller_register(struct device *clk_dev, void __iomem *base);
48
+
#else
49
+
static inline int mpfs_reset_controller_register(struct device *clk_dev, void __iomem *base) { return 0; }
50
+
#endif /* if IS_ENABLED(CONFIG_RESET_POLARFIRE_SOC) */
51
51
#endif /* if IS_ENABLED(CONFIG_MCHP_CLK_MPFS) */
52
52
53
53
#endif /* __SOC_MPFS_H__ */