Merge tag 'x86-apic-2024-09-17' of git://git.kernel.org/pub/scm/linux/kernel/git/tip/tip

+18 -28

arch/x86/include/asm/apic.h

··· 18 18 19 19 #define ARCH_APICTIMER_STOPS_ON_C3 1 20 20 21 + /* Macros for apic_extnmi which controls external NMI masking */ 22 + #define APIC_EXTNMI_BSP 0 /* Default */ 23 + #define APIC_EXTNMI_ALL 1 24 + #define APIC_EXTNMI_NONE 2 25 + 21 26 /* 22 27 * Debugging macros 23 28 */ ··· 30 25 #define APIC_VERBOSE 1 31 26 #define APIC_DEBUG 2 32 27 33 - /* Macros for apic_extnmi which controls external NMI masking */ 34 - #define APIC_EXTNMI_BSP 0 /* Default */ 35 - #define APIC_EXTNMI_ALL 1 36 - #define APIC_EXTNMI_NONE 2 37 - 38 28 /* 39 - * Define the default level of output to be very little 40 - * This can be turned up by using apic=verbose for more 41 - * information and apic=debug for _lots_ of information. 42 - * apic_verbosity is defined in apic.c 29 + * Define the default level of output to be very little This can be turned 30 + * up by using apic=verbose for more information and apic=debug for _lots_ 31 + * of information. apic_verbosity is defined in apic.c 43 32 */ 44 - #define apic_printk(v, s, a...) do { \ 45 - if ((v) <= apic_verbosity) \ 46 - printk(s, ##a); \ 47 - } while (0) 33 + #define apic_printk(v, s, a...) \ 34 + do { \ 35 + if ((v) <= apic_verbosity) \ 36 + printk(s, ##a); \ 37 + } while (0) 48 38 39 + #define apic_pr_verbose(s, a...) apic_printk(APIC_VERBOSE, KERN_INFO s, ##a) 40 + #define apic_pr_debug(s, a...) apic_printk(APIC_DEBUG, KERN_DEBUG s, ##a) 41 + #define apic_pr_debug_cont(s, a...) apic_printk(APIC_DEBUG, KERN_CONT s, ##a) 42 + /* Unconditional debug prints for code which is guarded by apic_verbosity already */ 43 + #define apic_dbg(s, a...) printk(KERN_DEBUG s, ##a) 49 44 50 45 #if defined(CONFIG_X86_LOCAL_APIC) && defined(CONFIG_X86_32) 51 46 extern void x86_32_probe_apic(void); ··· 126 121 } 127 122 128 123 extern void enable_IR_x2apic(void); 129 - 130 - extern int get_physical_broadcast(void); 131 124 132 125 extern int lapic_get_maxlvt(void); 133 126 extern void clear_local_APIC(void); ··· 348 345 * APIC drivers are probed based on how they are listed in the .apicdrivers 349 346 * section. So the order is important and enforced by the ordering 350 347 * of different apic driver files in the Makefile. 351 - * 352 - * For the files having two apic drivers, we use apic_drivers() 353 - * to enforce the order with in them. 354 348 */ 355 349 #define apic_driver(sym) \ 356 350 static const struct apic *__apicdrivers_##sym __used \ 357 351 __aligned(sizeof(struct apic *)) \ 358 352 __section(".apicdrivers") = { &sym } 359 - 360 - #define apic_drivers(sym1, sym2) \ 361 - static struct apic *__apicdrivers_##sym1##sym2[2] __used \ 362 - __aligned(sizeof(struct apic *)) \ 363 - __section(".apicdrivers") = { &sym1, &sym2 } 364 353 365 354 extern struct apic *__apicdrivers[], *__apicdrivers_end[]; 366 355 ··· 479 484 static inline void apic_icr_write(u32 low, u32 high) { } 480 485 static inline void apic_wait_icr_idle(void) { } 481 486 static inline u32 safe_apic_wait_icr_idle(void) { return 0; } 482 - static inline void apic_set_eoi_cb(void (*eoi)(void)) {} 483 487 static inline void apic_native_eoi(void) { WARN_ON_ONCE(1); } 484 488 static inline void apic_setup_apic_calls(void) { } 485 489 ··· 506 512 #define TRAMPOLINE_PHYS_LOW 0x467 507 513 #define TRAMPOLINE_PHYS_HIGH 0x469 508 514 509 - extern void generic_bigsmp_probe(void); 510 - 511 515 #ifdef CONFIG_X86_LOCAL_APIC 512 516 513 517 #include <asm/smp.h> ··· 527 535 static inline int default_acpi_madt_oem_check(char *a, char *b) { return 0; } 528 536 static inline void x86_64_probe_apic(void) { } 529 537 #endif 530 - 531 - extern int default_apic_id_valid(u32 apicid); 532 538 533 539 extern u32 apic_default_calc_apicid(unsigned int cpu); 534 540 extern u32 apic_flat_calc_apicid(unsigned int cpu);

+2 -2

arch/x86/include/asm/irq_vectors.h

··· 18 18 * Vectors 0 ... 31 : system traps and exceptions - hardcoded events 19 19 * Vectors 32 ... 127 : device interrupts 20 20 * Vector 128 : legacy int80 syscall interface 21 - * Vectors 129 ... LOCAL_TIMER_VECTOR-1 22 - * Vectors LOCAL_TIMER_VECTOR ... 255 : special interrupts 21 + * Vectors 129 ... FIRST_SYSTEM_VECTOR-1 : device interrupts 22 + * Vectors FIRST_SYSTEM_VECTOR ... 255 : special interrupts 23 23 * 24 24 * 64-bit x86 has per CPU IDT tables, 32-bit has one shared IDT table. 25 25 *

+35 -46

arch/x86/kernel/apic/apic.c

··· 677 677 return -1; 678 678 #endif 679 679 680 - apic_printk(APIC_VERBOSE, "... PM-Timer delta = %u\n", deltapm); 680 + apic_pr_verbose("... PM-Timer delta = %u\n", deltapm); 681 681 682 682 /* Check, if the PM timer is available */ 683 683 if (!deltapm) ··· 687 687 688 688 if (deltapm > (pm_100ms - pm_thresh) && 689 689 deltapm < (pm_100ms + pm_thresh)) { 690 - apic_printk(APIC_VERBOSE, "... PM-Timer result ok\n"); 690 + apic_pr_verbose("... PM-Timer result ok\n"); 691 691 return 0; 692 692 } 693 693 694 694 res = (((u64)deltapm) * mult) >> 22; 695 695 do_div(res, 1000000); 696 - pr_warn("APIC calibration not consistent " 697 - "with PM-Timer: %ldms instead of 100ms\n", (long)res); 696 + pr_warn("APIC calibration not consistent with PM-Timer: %ldms instead of 100ms\n", 697 + (long)res); 698 698 699 699 /* Correct the lapic counter value */ 700 700 res = (((u64)(*delta)) * pm_100ms); ··· 707 707 if (boot_cpu_has(X86_FEATURE_TSC)) { 708 708 res = (((u64)(*deltatsc)) * pm_100ms); 709 709 do_div(res, deltapm); 710 - apic_printk(APIC_VERBOSE, "TSC delta adjusted to " 711 - "PM-Timer: %lu (%ld)\n", 712 - (unsigned long)res, *deltatsc); 710 + apic_pr_verbose("TSC delta adjusted to PM-Timer: %lu (%ld)\n", 711 + (unsigned long)res, *deltatsc); 713 712 *deltatsc = (long)res; 714 713 } 715 714 ··· 791 792 * in the clockevent structure and return. 792 793 */ 793 794 if (!lapic_init_clockevent()) { 794 - apic_printk(APIC_VERBOSE, "lapic timer already calibrated %d\n", 795 - lapic_timer_period); 795 + apic_pr_verbose("lapic timer already calibrated %d\n", lapic_timer_period); 796 796 /* 797 797 * Direct calibration methods must have an always running 798 798 * local APIC timer, no need for broadcast timer. ··· 800 802 return 0; 801 803 } 802 804 803 - apic_printk(APIC_VERBOSE, "Using local APIC timer interrupts.\n" 804 - "calibrating APIC timer ...\n"); 805 + apic_pr_verbose("Using local APIC timer interrupts. Calibrating APIC timer ...\n"); 805 806 806 807 /* 807 808 * There are platforms w/o global clockevent devices. Instead of ··· 863 866 864 867 /* Build delta t1-t2 as apic timer counts down */ 865 868 delta = lapic_cal_t1 - lapic_cal_t2; 866 - apic_printk(APIC_VERBOSE, "... lapic delta = %ld\n", delta); 869 + apic_pr_verbose("... lapic delta = %ld\n", delta); 867 870 868 871 deltatsc = (long)(lapic_cal_tsc2 - lapic_cal_tsc1); 869 872 ··· 874 877 lapic_timer_period = (delta * APIC_DIVISOR) / LAPIC_CAL_LOOPS; 875 878 lapic_init_clockevent(); 876 879 877 - apic_printk(APIC_VERBOSE, "..... delta %ld\n", delta); 878 - apic_printk(APIC_VERBOSE, "..... mult: %u\n", lapic_clockevent.mult); 879 - apic_printk(APIC_VERBOSE, "..... calibration result: %u\n", 880 - lapic_timer_period); 880 + apic_pr_verbose("..... delta %ld\n", delta); 881 + apic_pr_verbose("..... mult: %u\n", lapic_clockevent.mult); 882 + apic_pr_verbose("..... calibration result: %u\n", lapic_timer_period); 881 883 882 884 if (boot_cpu_has(X86_FEATURE_TSC)) { 883 - apic_printk(APIC_VERBOSE, "..... CPU clock speed is " 884 - "%ld.%04ld MHz.\n", 885 - (deltatsc / LAPIC_CAL_LOOPS) / (1000000 / HZ), 886 - (deltatsc / LAPIC_CAL_LOOPS) % (1000000 / HZ)); 885 + apic_pr_verbose("..... CPU clock speed is %ld.%04ld MHz.\n", 886 + (deltatsc / LAPIC_CAL_LOOPS) / (1000000 / HZ), 887 + (deltatsc / LAPIC_CAL_LOOPS) % (1000000 / HZ)); 887 888 } 888 889 889 - apic_printk(APIC_VERBOSE, "..... host bus clock speed is " 890 - "%u.%04u MHz.\n", 891 - lapic_timer_period / (1000000 / HZ), 892 - lapic_timer_period % (1000000 / HZ)); 890 + apic_pr_verbose("..... host bus clock speed is %u.%04u MHz.\n", 891 + lapic_timer_period / (1000000 / HZ), 892 + lapic_timer_period % (1000000 / HZ)); 893 893 894 894 /* 895 895 * Do a sanity check on the APIC calibration result ··· 905 911 * available. 906 912 */ 907 913 if (!pm_referenced && global_clock_event) { 908 - apic_printk(APIC_VERBOSE, "... verify APIC timer\n"); 914 + apic_pr_verbose("... verify APIC timer\n"); 909 915 910 916 /* 911 917 * Setup the apic timer manually ··· 926 932 927 933 /* Jiffies delta */ 928 934 deltaj = lapic_cal_j2 - lapic_cal_j1; 929 - apic_printk(APIC_VERBOSE, "... jiffies delta = %lu\n", deltaj); 935 + apic_pr_verbose("... jiffies delta = %lu\n", deltaj); 930 936 931 937 /* Check, if the jiffies result is consistent */ 932 938 if (deltaj >= LAPIC_CAL_LOOPS-2 && deltaj <= LAPIC_CAL_LOOPS+2) 933 - apic_printk(APIC_VERBOSE, "... jiffies result ok\n"); 939 + apic_pr_verbose("... jiffies result ok\n"); 934 940 else 935 941 levt->features |= CLOCK_EVT_FEAT_DUMMY; 936 942 } ··· 1215 1221 */ 1216 1222 apic_wait_icr_idle(); 1217 1223 1218 - apic_printk(APIC_DEBUG, "Synchronizing Arb IDs.\n"); 1219 - apic_write(APIC_ICR, APIC_DEST_ALLINC | 1220 - APIC_INT_LEVELTRIG | APIC_DM_INIT); 1224 + apic_pr_debug("Synchronizing Arb IDs.\n"); 1225 + apic_write(APIC_ICR, APIC_DEST_ALLINC | APIC_INT_LEVELTRIG | APIC_DM_INIT); 1221 1226 } 1222 1227 1223 1228 enum apic_intr_mode_id apic_intr_mode __ro_after_init; ··· 1402 1409 if (maxlvt > 3) 1403 1410 apic_write(APIC_ESR, 0); 1404 1411 value = apic_read(APIC_ESR); 1405 - if (value != oldvalue) 1406 - apic_printk(APIC_VERBOSE, "ESR value before enabling " 1407 - "vector: 0x%08x after: 0x%08x\n", 1408 - oldvalue, value); 1412 + if (value != oldvalue) { 1413 + apic_pr_verbose("ESR value before enabling vector: 0x%08x after: 0x%08x\n", 1414 + oldvalue, value); 1415 + } 1409 1416 } 1410 1417 1411 1418 #define APIC_IR_REGS APIC_ISR_NR ··· 1592 1599 value = apic_read(APIC_LVT0) & APIC_LVT_MASKED; 1593 1600 if (!cpu && (pic_mode || !value || ioapic_is_disabled)) { 1594 1601 value = APIC_DM_EXTINT; 1595 - apic_printk(APIC_VERBOSE, "enabled ExtINT on CPU#%d\n", cpu); 1602 + apic_pr_verbose("Enabled ExtINT on CPU#%d\n", cpu); 1596 1603 } else { 1597 1604 value = APIC_DM_EXTINT | APIC_LVT_MASKED; 1598 - apic_printk(APIC_VERBOSE, "masked ExtINT on CPU#%d\n", cpu); 1605 + apic_pr_verbose("Masked ExtINT on CPU#%d\n", cpu); 1599 1606 } 1600 1607 apic_write(APIC_LVT0, value); 1601 1608 ··· 2060 2067 { 2061 2068 set_fixmap_nocache(FIX_APIC_BASE, mp_lapic_addr); 2062 2069 apic_mmio_base = APIC_BASE; 2063 - apic_printk(APIC_VERBOSE, "mapped APIC to %16lx (%16lx)\n", 2064 - apic_mmio_base, mp_lapic_addr); 2070 + apic_pr_verbose("Mapped APIC to %16lx (%16lx)\n", apic_mmio_base, mp_lapic_addr); 2065 2071 if (read_apic) 2066 2072 apic_read_boot_cpu_id(false); 2067 2073 } ··· 2163 2171 apic_eoi(); 2164 2172 atomic_inc(&irq_err_count); 2165 2173 2166 - apic_printk(APIC_DEBUG, KERN_DEBUG "APIC error on CPU%d: %02x", 2167 - smp_processor_id(), v); 2174 + apic_pr_debug("APIC error on CPU%d: %02x", smp_processor_id(), v); 2168 2175 2169 2176 v &= 0xff; 2170 2177 while (v) { 2171 2178 if (v & 0x1) 2172 - apic_printk(APIC_DEBUG, KERN_CONT " : %s", error_interrupt_reason[i]); 2179 + apic_pr_debug_cont(" : %s", error_interrupt_reason[i]); 2173 2180 i++; 2174 2181 v >>= 1; 2175 2182 } 2176 2183 2177 - apic_printk(APIC_DEBUG, KERN_CONT "\n"); 2184 + apic_pr_debug_cont("\n"); 2178 2185 2179 2186 trace_error_apic_exit(ERROR_APIC_VECTOR); 2180 2187 } ··· 2193 2202 * PIC mode, enable APIC mode in the IMCR, i.e. connect BSP's 2194 2203 * local APIC to INT and NMI lines. 2195 2204 */ 2196 - apic_printk(APIC_VERBOSE, "leaving PIC mode, " 2197 - "enabling APIC mode.\n"); 2205 + apic_pr_verbose("Leaving PIC mode, enabling APIC mode.\n"); 2198 2206 imcr_pic_to_apic(); 2199 2207 } 2200 2208 #endif ··· 2218 2228 * IPIs, won't work beyond this point! The only exception are 2219 2229 * INIT IPIs. 2220 2230 */ 2221 - apic_printk(APIC_VERBOSE, "disabling APIC mode, " 2222 - "entering PIC mode.\n"); 2231 + apic_pr_verbose("Disabling APIC mode, entering PIC mode.\n"); 2223 2232 imcr_apic_to_pic(); 2224 2233 return; 2225 2234 }

+7 -112

arch/x86/kernel/apic/apic_flat_64.c

··· 8 8 * Martin Bligh, Andi Kleen, James Bottomley, John Stultz, and 9 9 * James Cleverdon. 10 10 */ 11 - #include <linux/cpumask.h> 12 11 #include <linux/export.h> 13 - #include <linux/acpi.h> 14 12 15 - #include <asm/jailhouse_para.h> 16 13 #include <asm/apic.h> 17 14 18 15 #include "local.h" 19 16 20 - static struct apic apic_physflat; 21 - static struct apic apic_flat; 22 - 23 - struct apic *apic __ro_after_init = &apic_flat; 24 - EXPORT_SYMBOL_GPL(apic); 25 - 26 - static int flat_acpi_madt_oem_check(char *oem_id, char *oem_table_id) 27 - { 28 - return 1; 29 - } 30 - 31 - static void _flat_send_IPI_mask(unsigned long mask, int vector) 32 - { 33 - unsigned long flags; 34 - 35 - local_irq_save(flags); 36 - __default_send_IPI_dest_field(mask, vector, APIC_DEST_LOGICAL); 37 - local_irq_restore(flags); 38 - } 39 - 40 - static void flat_send_IPI_mask(const struct cpumask *cpumask, int vector) 41 - { 42 - unsigned long mask = cpumask_bits(cpumask)[0]; 43 - 44 - _flat_send_IPI_mask(mask, vector); 45 - } 46 - 47 - static void 48 - flat_send_IPI_mask_allbutself(const struct cpumask *cpumask, int vector) 49 - { 50 - unsigned long mask = cpumask_bits(cpumask)[0]; 51 - int cpu = smp_processor_id(); 52 - 53 - if (cpu < BITS_PER_LONG) 54 - __clear_bit(cpu, &mask); 55 - 56 - _flat_send_IPI_mask(mask, vector); 57 - } 58 - 59 - static u32 flat_get_apic_id(u32 x) 17 + static u32 physflat_get_apic_id(u32 x) 60 18 { 61 19 return (x >> 24) & 0xFF; 62 20 } 63 21 64 - static int flat_probe(void) 22 + static int physflat_probe(void) 65 23 { 66 24 return 1; 67 25 } 68 26 69 - static struct apic apic_flat __ro_after_init = { 70 - .name = "flat", 71 - .probe = flat_probe, 72 - .acpi_madt_oem_check = flat_acpi_madt_oem_check, 73 - 74 - .dest_mode_logical = true, 75 - 76 - .disable_esr = 0, 77 - 78 - .init_apic_ldr = default_init_apic_ldr, 79 - .cpu_present_to_apicid = default_cpu_present_to_apicid, 80 - 81 - .max_apic_id = 0xFE, 82 - .get_apic_id = flat_get_apic_id, 83 - 84 - .calc_dest_apicid = apic_flat_calc_apicid, 85 - 86 - .send_IPI = default_send_IPI_single, 87 - .send_IPI_mask = flat_send_IPI_mask, 88 - .send_IPI_mask_allbutself = flat_send_IPI_mask_allbutself, 89 - .send_IPI_allbutself = default_send_IPI_allbutself, 90 - .send_IPI_all = default_send_IPI_all, 91 - .send_IPI_self = default_send_IPI_self, 92 - .nmi_to_offline_cpu = true, 93 - 94 - .read = native_apic_mem_read, 95 - .write = native_apic_mem_write, 96 - .eoi = native_apic_mem_eoi, 97 - .icr_read = native_apic_icr_read, 98 - .icr_write = native_apic_icr_write, 99 - .wait_icr_idle = apic_mem_wait_icr_idle, 100 - .safe_wait_icr_idle = apic_mem_wait_icr_idle_timeout, 101 - }; 102 - 103 - /* 104 - * Physflat mode is used when there are more than 8 CPUs on a system. 105 - * We cannot use logical delivery in this case because the mask 106 - * overflows, so use physical mode. 107 - */ 108 27 static int physflat_acpi_madt_oem_check(char *oem_id, char *oem_table_id) 109 28 { 110 - #ifdef CONFIG_ACPI 111 - /* 112 - * Quirk: some x86_64 machines can only use physical APIC mode 113 - * regardless of how many processors are present (x86_64 ES7000 114 - * is an example). 115 - */ 116 - if (acpi_gbl_FADT.header.revision >= FADT2_REVISION_ID && 117 - (acpi_gbl_FADT.flags & ACPI_FADT_APIC_PHYSICAL)) { 118 - printk(KERN_DEBUG "system APIC only can use physical flat"); 119 - return 1; 120 - } 121 - 122 - if (!strncmp(oem_id, "IBM", 3) && !strncmp(oem_table_id, "EXA", 3)) { 123 - printk(KERN_DEBUG "IBM Summit detected, will use apic physical"); 124 - return 1; 125 - } 126 - #endif 127 - 128 - return 0; 129 - } 130 - 131 - static int physflat_probe(void) 132 - { 133 - return apic == &apic_physflat || num_possible_cpus() > 8 || jailhouse_paravirt(); 29 + return 1; 134 30 } 135 31 136 32 static struct apic apic_physflat __ro_after_init = { ··· 42 146 .cpu_present_to_apicid = default_cpu_present_to_apicid, 43 147 44 148 .max_apic_id = 0xFE, 45 - .get_apic_id = flat_get_apic_id, 149 + .get_apic_id = physflat_get_apic_id, 46 150 47 151 .calc_dest_apicid = apic_default_calc_apicid, 48 152 ··· 62 166 .wait_icr_idle = apic_mem_wait_icr_idle, 63 167 .safe_wait_icr_idle = apic_mem_wait_icr_idle_timeout, 64 168 }; 169 + apic_driver(apic_physflat); 65 170 66 - /* 67 - * We need to check for physflat first, so this order is important. 68 - */ 69 - apic_drivers(apic_physflat, apic_flat); 171 + struct apic *apic __ro_after_init = &apic_physflat; 172 + EXPORT_SYMBOL_GPL(apic);

+303 -444

arch/x86/kernel/apic/io_apic.c

··· 86 86 static int ioapic_initialized; 87 87 88 88 struct irq_pin_list { 89 - struct list_head list; 90 - int apic, pin; 89 + struct list_head list; 90 + int apic, pin; 91 91 }; 92 92 93 93 struct mp_chip_data { ··· 96 96 bool is_level; 97 97 bool active_low; 98 98 bool isa_irq; 99 - u32 count; 99 + u32 count; 100 100 }; 101 101 102 102 struct mp_ioapic_gsi { ··· 105 105 }; 106 106 107 107 static struct ioapic { 108 - /* 109 - * # of IRQ routing registers 110 - */ 111 - int nr_registers; 112 - /* 113 - * Saved state during suspend/resume, or while enabling intr-remap. 114 - */ 115 - struct IO_APIC_route_entry *saved_registers; 108 + /* # of IRQ routing registers */ 109 + int nr_registers; 110 + /* Saved state during suspend/resume, or while enabling intr-remap. */ 111 + struct IO_APIC_route_entry *saved_registers; 116 112 /* I/O APIC config */ 117 - struct mpc_ioapic mp_config; 113 + struct mpc_ioapic mp_config; 118 114 /* IO APIC gsi routing info */ 119 - struct mp_ioapic_gsi gsi_config; 120 - struct ioapic_domain_cfg irqdomain_cfg; 121 - struct irq_domain *irqdomain; 122 - struct resource *iomem_res; 115 + struct mp_ioapic_gsi gsi_config; 116 + struct ioapic_domain_cfg irqdomain_cfg; 117 + struct irq_domain *irqdomain; 118 + struct resource *iomem_res; 123 119 } ioapics[MAX_IO_APICS]; 124 120 125 121 #define mpc_ioapic_ver(ioapic_idx) ioapics[ioapic_idx].mp_config.apicver ··· 201 205 { 202 206 int i; 203 207 204 - apic_printk(APIC_VERBOSE, "Int: type %d, pol %d, trig %d, bus %02x," 205 - " IRQ %02x, APIC ID %x, APIC INT %02x\n", 206 - m->irqtype, m->irqflag & 3, (m->irqflag >> 2) & 3, m->srcbus, 207 - m->srcbusirq, m->dstapic, m->dstirq); 208 + apic_pr_verbose("Int: type %d, pol %d, trig %d, bus %02x, IRQ %02x, APIC ID %x, APIC INT %02x\n", 209 + m->irqtype, m->irqflag & 3, (m->irqflag >> 2) & 3, m->srcbus, 210 + m->srcbusirq, m->dstapic, m->dstirq); 208 211 209 212 for (i = 0; i < mp_irq_entries; i++) { 210 213 if (!memcmp(&mp_irqs[i], m, sizeof(*m))) ··· 264 269 static inline void io_apic_eoi(unsigned int apic, unsigned int vector) 265 270 { 266 271 struct io_apic __iomem *io_apic = io_apic_base(apic); 272 + 267 273 writel(vector, &io_apic->eoi); 268 274 } 269 275 270 276 unsigned int native_io_apic_read(unsigned int apic, unsigned int reg) 271 277 { 272 278 struct io_apic __iomem *io_apic = io_apic_base(apic); 279 + 273 280 writel(reg, &io_apic->index); 274 281 return readl(&io_apic->data); 275 282 } ··· 297 300 298 301 static struct IO_APIC_route_entry ioapic_read_entry(int apic, int pin) 299 302 { 300 - struct IO_APIC_route_entry entry; 301 - unsigned long flags; 302 - 303 - raw_spin_lock_irqsave(&ioapic_lock, flags); 304 - entry = __ioapic_read_entry(apic, pin); 305 - raw_spin_unlock_irqrestore(&ioapic_lock, flags); 306 - 307 - return entry; 303 + guard(raw_spinlock_irqsave)(&ioapic_lock); 304 + return __ioapic_read_entry(apic, pin); 308 305 } 309 306 310 307 /* ··· 315 324 316 325 static void ioapic_write_entry(int apic, int pin, struct IO_APIC_route_entry e) 317 326 { 318 - unsigned long flags; 319 - 320 - raw_spin_lock_irqsave(&ioapic_lock, flags); 327 + guard(raw_spinlock_irqsave)(&ioapic_lock); 321 328 __ioapic_write_entry(apic, pin, e); 322 - raw_spin_unlock_irqrestore(&ioapic_lock, flags); 323 329 } 324 330 325 331 /* ··· 327 339 static void ioapic_mask_entry(int apic, int pin) 328 340 { 329 341 struct IO_APIC_route_entry e = { .masked = true }; 330 - unsigned long flags; 331 342 332 - raw_spin_lock_irqsave(&ioapic_lock, flags); 343 + guard(raw_spinlock_irqsave)(&ioapic_lock); 333 344 io_apic_write(apic, 0x10 + 2*pin, e.w1); 334 345 io_apic_write(apic, 0x11 + 2*pin, e.w2); 335 - raw_spin_unlock_irqrestore(&ioapic_lock, flags); 336 346 } 337 347 338 348 /* ··· 338 352 * shared ISA-space IRQs, so we have to support them. We are super 339 353 * fast in the common case, and fast for shared ISA-space IRQs. 340 354 */ 341 - static int __add_pin_to_irq_node(struct mp_chip_data *data, 342 - int node, int apic, int pin) 355 + static bool add_pin_to_irq_node(struct mp_chip_data *data, int node, int apic, int pin) 343 356 { 344 357 struct irq_pin_list *entry; 345 358 346 - /* don't allow duplicates */ 347 - for_each_irq_pin(entry, data->irq_2_pin) 359 + /* Don't allow duplicates */ 360 + for_each_irq_pin(entry, data->irq_2_pin) { 348 361 if (entry->apic == apic && entry->pin == pin) 349 - return 0; 362 + return true; 363 + } 350 364 351 365 entry = kzalloc_node(sizeof(struct irq_pin_list), GFP_ATOMIC, node); 352 366 if (!entry) { 353 - pr_err("can not alloc irq_pin_list (%d,%d,%d)\n", 354 - node, apic, pin); 355 - return -ENOMEM; 367 + pr_err("Cannot allocate irq_pin_list (%d,%d,%d)\n", node, apic, pin); 368 + return false; 356 369 } 370 + 357 371 entry->apic = apic; 358 372 entry->pin = pin; 359 373 list_add_tail(&entry->list, &data->irq_2_pin); 360 - 361 - return 0; 374 + return true; 362 375 } 363 376 364 377 static void __remove_pin_from_irq(struct mp_chip_data *data, int apic, int pin) 365 378 { 366 379 struct irq_pin_list *tmp, *entry; 367 380 368 - list_for_each_entry_safe(entry, tmp, &data->irq_2_pin, list) 381 + list_for_each_entry_safe(entry, tmp, &data->irq_2_pin, list) { 369 382 if (entry->apic == apic && entry->pin == pin) { 370 383 list_del(&entry->list); 371 384 kfree(entry); 372 385 return; 373 386 } 374 - } 375 - 376 - static void add_pin_to_irq_node(struct mp_chip_data *data, 377 - int node, int apic, int pin) 378 - { 379 - if (__add_pin_to_irq_node(data, node, apic, pin)) 380 - panic("IO-APIC: failed to add irq-pin. Can not proceed\n"); 381 - } 382 - 383 - /* 384 - * Reroute an IRQ to a different pin. 385 - */ 386 - static void __init replace_pin_at_irq_node(struct mp_chip_data *data, int node, 387 - int oldapic, int oldpin, 388 - int newapic, int newpin) 389 - { 390 - struct irq_pin_list *entry; 391 - 392 - for_each_irq_pin(entry, data->irq_2_pin) { 393 - if (entry->apic == oldapic && entry->pin == oldpin) { 394 - entry->apic = newapic; 395 - entry->pin = newpin; 396 - /* every one is different, right? */ 397 - return; 398 - } 399 387 } 400 - 401 - /* old apic/pin didn't exist, so just add new ones */ 402 - add_pin_to_irq_node(data, node, newapic, newpin); 403 388 } 404 389 405 390 static void io_apic_modify_irq(struct mp_chip_data *data, bool masked, ··· 387 430 } 388 431 } 389 432 433 + /* 434 + * Synchronize the IO-APIC and the CPU by doing a dummy read from the 435 + * IO-APIC 436 + */ 390 437 static void io_apic_sync(struct irq_pin_list *entry) 391 438 { 392 - /* 393 - * Synchronize the IO-APIC and the CPU by doing 394 - * a dummy read from the IO-APIC 395 - */ 396 439 struct io_apic __iomem *io_apic; 397 440 398 441 io_apic = io_apic_base(entry->apic); ··· 402 445 static void mask_ioapic_irq(struct irq_data *irq_data) 403 446 { 404 447 struct mp_chip_data *data = irq_data->chip_data; 405 - unsigned long flags; 406 448 407 - raw_spin_lock_irqsave(&ioapic_lock, flags); 449 + guard(raw_spinlock_irqsave)(&ioapic_lock); 408 450 io_apic_modify_irq(data, true, &io_apic_sync); 409 - raw_spin_unlock_irqrestore(&ioapic_lock, flags); 410 451 } 411 452 412 453 static void __unmask_ioapic(struct mp_chip_data *data) ··· 415 460 static void unmask_ioapic_irq(struct irq_data *irq_data) 416 461 { 417 462 struct mp_chip_data *data = irq_data->chip_data; 418 - unsigned long flags; 419 463 420 - raw_spin_lock_irqsave(&ioapic_lock, flags); 464 + guard(raw_spinlock_irqsave)(&ioapic_lock); 421 465 __unmask_ioapic(data); 422 - raw_spin_unlock_irqrestore(&ioapic_lock, flags); 423 466 } 424 467 425 468 /* ··· 445 492 446 493 entry = entry1 = __ioapic_read_entry(apic, pin); 447 494 448 - /* 449 - * Mask the entry and change the trigger mode to edge. 450 - */ 495 + /* Mask the entry and change the trigger mode to edge. */ 451 496 entry1.masked = true; 452 497 entry1.is_level = false; 453 498 454 499 __ioapic_write_entry(apic, pin, entry1); 455 500 456 - /* 457 - * Restore the previous level triggered entry. 458 - */ 501 + /* Restore the previous level triggered entry. */ 459 502 __ioapic_write_entry(apic, pin, entry); 460 503 } 461 504 } 462 505 463 506 static void eoi_ioapic_pin(int vector, struct mp_chip_data *data) 464 507 { 465 - unsigned long flags; 466 508 struct irq_pin_list *entry; 467 509 468 - raw_spin_lock_irqsave(&ioapic_lock, flags); 510 + guard(raw_spinlock_irqsave)(&ioapic_lock); 469 511 for_each_irq_pin(entry, data->irq_2_pin) 470 512 __eoi_ioapic_pin(entry->apic, entry->pin, vector); 471 - raw_spin_unlock_irqrestore(&ioapic_lock, flags); 472 513 } 473 514 474 515 static void clear_IO_APIC_pin(unsigned int apic, unsigned int pin) ··· 485 538 } 486 539 487 540 if (entry.irr) { 488 - unsigned long flags; 489 - 490 541 /* 491 542 * Make sure the trigger mode is set to level. Explicit EOI 492 543 * doesn't clear the remote-IRR if the trigger mode is not ··· 494 549 entry.is_level = true; 495 550 ioapic_write_entry(apic, pin, entry); 496 551 } 497 - raw_spin_lock_irqsave(&ioapic_lock, flags); 552 + guard(raw_spinlock_irqsave)(&ioapic_lock); 498 553 __eoi_ioapic_pin(apic, pin, entry.vector); 499 - raw_spin_unlock_irqrestore(&ioapic_lock, flags); 500 554 } 501 555 502 556 /* ··· 530 586 531 587 static int __init ioapic_pirq_setup(char *str) 532 588 { 533 - int i, max; 534 - int ints[MAX_PIRQS+1]; 589 + int i, max, ints[MAX_PIRQS+1]; 535 590 536 591 get_options(str, ARRAY_SIZE(ints), ints); 537 592 538 - apic_printk(APIC_VERBOSE, KERN_INFO 539 - "PIRQ redirection, working around broken MP-BIOS.\n"); 593 + apic_pr_verbose("PIRQ redirection, working around broken MP-BIOS.\n"); 594 + 540 595 max = MAX_PIRQS; 541 596 if (ints[0] < MAX_PIRQS) 542 597 max = ints[0]; 543 598 544 599 for (i = 0; i < max; i++) { 545 - apic_printk(APIC_VERBOSE, KERN_DEBUG 546 - "... PIRQ%d -> IRQ %d\n", i, ints[i+1]); 547 - /* 548 - * PIRQs are mapped upside down, usually. 549 - */ 600 + apic_pr_verbose("... PIRQ%d -> IRQ %d\n", i, ints[i + 1]); 601 + /* PIRQs are mapped upside down, usually */ 550 602 pirq_entries[MAX_PIRQS-i-1] = ints[i+1]; 551 603 } 552 604 return 1; 553 605 } 554 - 555 606 __setup("pirq=", ioapic_pirq_setup); 556 607 #endif /* CONFIG_X86_32 */ 557 608 ··· 565 626 } 566 627 567 628 for_each_pin(apic, pin) 568 - ioapics[apic].saved_registers[pin] = 569 - ioapic_read_entry(apic, pin); 629 + ioapics[apic].saved_registers[pin] = ioapic_read_entry(apic, pin); 570 630 } 571 631 572 632 return err; ··· 606 668 continue; 607 669 608 670 for_each_pin(apic, pin) 609 - ioapic_write_entry(apic, pin, 610 - ioapics[apic].saved_registers[pin]); 671 + ioapic_write_entry(apic, pin, ioapics[apic].saved_registers[pin]); 611 672 } 612 673 return 0; 613 674 } ··· 618 681 { 619 682 int i; 620 683 621 - for (i = 0; i < mp_irq_entries; i++) 684 + for (i = 0; i < mp_irq_entries; i++) { 622 685 if (mp_irqs[i].irqtype == type && 623 686 (mp_irqs[i].dstapic == mpc_ioapic_id(ioapic_idx) || 624 687 mp_irqs[i].dstapic == MP_APIC_ALL) && 625 688 mp_irqs[i].dstirq == pin) 626 689 return i; 690 + } 627 691 628 692 return -1; 629 693 } ··· 639 701 for (i = 0; i < mp_irq_entries; i++) { 640 702 int lbus = mp_irqs[i].srcbus; 641 703 642 - if (test_bit(lbus, mp_bus_not_pci) && 643 - (mp_irqs[i].irqtype == type) && 704 + if (test_bit(lbus, mp_bus_not_pci) && (mp_irqs[i].irqtype == type) && 644 705 (mp_irqs[i].srcbusirq == irq)) 645 - 646 706 return mp_irqs[i].dstirq; 647 707 } 648 708 return -1; ··· 653 717 for (i = 0; i < mp_irq_entries; i++) { 654 718 int lbus = mp_irqs[i].srcbus; 655 719 656 - if (test_bit(lbus, mp_bus_not_pci) && 657 - (mp_irqs[i].irqtype == type) && 720 + if (test_bit(lbus, mp_bus_not_pci) && (mp_irqs[i].irqtype == type) && 658 721 (mp_irqs[i].srcbusirq == irq)) 659 722 break; 660 723 } ··· 661 726 if (i < mp_irq_entries) { 662 727 int ioapic_idx; 663 728 664 - for_each_ioapic(ioapic_idx) 729 + for_each_ioapic(ioapic_idx) { 665 730 if (mpc_ioapic_id(ioapic_idx) == mp_irqs[i].dstapic) 666 731 return ioapic_idx; 732 + } 667 733 } 668 734 669 735 return -1; ··· 705 769 unsigned int port = PIC_ELCR1 + (irq >> 3); 706 770 return (inb(port) >> (irq & 7)) & 1; 707 771 } 708 - apic_printk(APIC_VERBOSE, KERN_INFO 709 - "Broken MPtable reports ISA irq %d\n", irq); 772 + apic_pr_verbose("Broken MPtable reports ISA irq %d\n", irq); 710 773 return false; 711 774 } 712 775 ··· 882 947 static int alloc_irq_from_domain(struct irq_domain *domain, int ioapic, u32 gsi, 883 948 struct irq_alloc_info *info) 884 949 { 950 + int type = ioapics[ioapic].irqdomain_cfg.type; 885 951 bool legacy = false; 886 952 int irq = -1; 887 - int type = ioapics[ioapic].irqdomain_cfg.type; 888 953 889 954 switch (type) { 890 955 case IOAPIC_DOMAIN_LEGACY: ··· 906 971 return -1; 907 972 } 908 973 909 - return __irq_domain_alloc_irqs(domain, irq, 1, 910 - ioapic_alloc_attr_node(info), 974 + return __irq_domain_alloc_irqs(domain, irq, 1, ioapic_alloc_attr_node(info), 911 975 info, legacy, NULL); 912 976 } 913 977 ··· 920 986 * PIRQs instead of reprogramming the interrupt routing logic. Thus there may be 921 987 * multiple pins sharing the same legacy IRQ number when ACPI is disabled. 922 988 */ 923 - static int alloc_isa_irq_from_domain(struct irq_domain *domain, 924 - int irq, int ioapic, int pin, 989 + static int alloc_isa_irq_from_domain(struct irq_domain *domain, int irq, int ioapic, int pin, 925 990 struct irq_alloc_info *info) 926 991 { 927 - struct mp_chip_data *data; 928 992 struct irq_data *irq_data = irq_get_irq_data(irq); 929 993 int node = ioapic_alloc_attr_node(info); 994 + struct mp_chip_data *data; 930 995 931 996 /* 932 997 * Legacy ISA IRQ has already been allocated, just add pin to ··· 935 1002 if (irq_data && irq_data->parent_data) { 936 1003 if (!mp_check_pin_attr(irq, info)) 937 1004 return -EBUSY; 938 - if (__add_pin_to_irq_node(irq_data->chip_data, node, ioapic, 939 - info->ioapic.pin)) 1005 + if (!add_pin_to_irq_node(irq_data->chip_data, node, ioapic, info->ioapic.pin)) 940 1006 return -ENOMEM; 941 1007 } else { 942 1008 info->flags |= X86_IRQ_ALLOC_LEGACY; 943 - irq = __irq_domain_alloc_irqs(domain, irq, 1, node, info, true, 944 - NULL); 1009 + irq = __irq_domain_alloc_irqs(domain, irq, 1, node, info, true, NULL); 945 1010 if (irq >= 0) { 946 1011 irq_data = irq_domain_get_irq_data(domain, irq); 947 1012 data = irq_data->chip_data; ··· 953 1022 static int mp_map_pin_to_irq(u32 gsi, int idx, int ioapic, int pin, 954 1023 unsigned int flags, struct irq_alloc_info *info) 955 1024 { 956 - int irq; 957 - bool legacy = false; 1025 + struct irq_domain *domain = mp_ioapic_irqdomain(ioapic); 958 1026 struct irq_alloc_info tmp; 959 1027 struct mp_chip_data *data; 960 - struct irq_domain *domain = mp_ioapic_irqdomain(ioapic); 1028 + bool legacy = false; 1029 + int irq; 961 1030 962 1031 if (!domain) 963 1032 return -ENOSYS; ··· 977 1046 return -EINVAL; 978 1047 } 979 1048 980 - mutex_lock(&ioapic_mutex); 1049 + guard(mutex)(&ioapic_mutex); 981 1050 if (!(flags & IOAPIC_MAP_ALLOC)) { 982 1051 if (!legacy) { 983 1052 irq = irq_find_mapping(domain, pin); ··· 998 1067 data->count++; 999 1068 } 1000 1069 } 1001 - mutex_unlock(&ioapic_mutex); 1002 - 1003 1070 return irq; 1004 1071 } 1005 1072 ··· 1005 1076 { 1006 1077 u32 gsi = mp_pin_to_gsi(ioapic, pin); 1007 1078 1008 - /* 1009 - * Debugging check, we are in big trouble if this message pops up! 1010 - */ 1079 + /* Debugging check, we are in big trouble if this message pops up! */ 1011 1080 if (mp_irqs[idx].dstirq != pin) 1012 1081 pr_err("broken BIOS or MPTABLE parser, ayiee!!\n"); 1013 1082 1014 1083 #ifdef CONFIG_X86_32 1015 - /* 1016 - * PCI IRQ command line redirection. Yes, limits are hardcoded. 1017 - */ 1084 + /* PCI IRQ command line redirection. Yes, limits are hardcoded. */ 1018 1085 if ((pin >= 16) && (pin <= 23)) { 1019 - if (pirq_entries[pin-16] != -1) { 1020 - if (!pirq_entries[pin-16]) { 1021 - apic_printk(APIC_VERBOSE, KERN_DEBUG 1022 - "disabling PIRQ%d\n", pin-16); 1086 + if (pirq_entries[pin - 16] != -1) { 1087 + if (!pirq_entries[pin - 16]) { 1088 + apic_pr_verbose("Disabling PIRQ%d\n", pin - 16); 1023 1089 } else { 1024 1090 int irq = pirq_entries[pin-16]; 1025 - apic_printk(APIC_VERBOSE, KERN_DEBUG 1026 - "using PIRQ%d -> IRQ %d\n", 1027 - pin-16, irq); 1091 + 1092 + apic_pr_verbose("Using PIRQ%d -> IRQ %d\n", pin - 16, irq); 1028 1093 return irq; 1029 1094 } 1030 1095 } ··· 1056 1133 if (!data || data->isa_irq) 1057 1134 return; 1058 1135 1059 - mutex_lock(&ioapic_mutex); 1136 + guard(mutex)(&ioapic_mutex); 1060 1137 if (--data->count == 0) 1061 1138 irq_domain_free_irqs(irq, 1); 1062 - mutex_unlock(&ioapic_mutex); 1063 1139 } 1064 1140 1065 1141 /* ··· 1069 1147 { 1070 1148 int irq, i, best_ioapic = -1, best_idx = -1; 1071 1149 1072 - apic_printk(APIC_DEBUG, 1073 - "querying PCI -> IRQ mapping bus:%d, slot:%d, pin:%d.\n", 1074 - bus, slot, pin); 1150 + apic_pr_debug("Querying PCI -> IRQ mapping bus:%d, slot:%d, pin:%d.\n", 1151 + bus, slot, pin); 1075 1152 if (test_bit(bus, mp_bus_not_pci)) { 1076 - apic_printk(APIC_VERBOSE, 1077 - "PCI BIOS passed nonexistent PCI bus %d!\n", bus); 1153 + apic_pr_verbose("PCI BIOS passed nonexistent PCI bus %d!\n", bus); 1078 1154 return -1; 1079 1155 } 1080 1156 ··· 1117 1197 return -1; 1118 1198 1119 1199 out: 1120 - return pin_2_irq(best_idx, best_ioapic, mp_irqs[best_idx].dstirq, 1121 - IOAPIC_MAP_ALLOC); 1200 + return pin_2_irq(best_idx, best_ioapic, mp_irqs[best_idx].dstirq, IOAPIC_MAP_ALLOC); 1122 1201 } 1123 1202 EXPORT_SYMBOL(IO_APIC_get_PCI_irq_vector); 1124 1203 ··· 1128 1209 unsigned int ioapic, pin; 1129 1210 int idx; 1130 1211 1131 - apic_printk(APIC_VERBOSE, KERN_DEBUG "init IO_APIC IRQs\n"); 1212 + apic_pr_verbose("Init IO_APIC IRQs\n"); 1132 1213 1133 1214 for_each_ioapic_pin(ioapic, pin) { 1134 1215 idx = find_irq_entry(ioapic, pin, mp_INT); 1135 - if (idx < 0) 1136 - apic_printk(APIC_VERBOSE, 1137 - KERN_DEBUG " apic %d pin %d not connected\n", 1138 - mpc_ioapic_id(ioapic), pin); 1139 - else 1140 - pin_2_irq(idx, ioapic, pin, 1141 - ioapic ? 0 : IOAPIC_MAP_ALLOC); 1216 + if (idx < 0) { 1217 + apic_pr_verbose("apic %d pin %d not connected\n", 1218 + mpc_ioapic_id(ioapic), pin); 1219 + } else { 1220 + pin_2_irq(idx, ioapic, pin, ioapic ? 0 : IOAPIC_MAP_ALLOC); 1221 + } 1142 1222 } 1143 1223 } 1144 1224 ··· 1152 1234 char buf[256]; 1153 1235 int i; 1154 1236 1155 - printk(KERN_DEBUG "IOAPIC %d:\n", apic); 1237 + apic_dbg("IOAPIC %d:\n", apic); 1156 1238 for (i = 0; i <= nr_entries; i++) { 1157 1239 entry = ioapic_read_entry(apic, i); 1158 - snprintf(buf, sizeof(buf), 1159 - " pin%02x, %s, %s, %s, V(%02X), IRR(%1d), S(%1d)", 1160 - i, 1161 - entry.masked ? "disabled" : "enabled ", 1240 + snprintf(buf, sizeof(buf), " pin%02x, %s, %s, %s, V(%02X), IRR(%1d), S(%1d)", 1241 + i, entry.masked ? "disabled" : "enabled ", 1162 1242 entry.is_level ? "level" : "edge ", 1163 1243 entry.active_low ? "low " : "high", 1164 1244 entry.vector, entry.irr, entry.delivery_status); 1165 1245 if (entry.ir_format) { 1166 - printk(KERN_DEBUG "%s, remapped, I(%04X), Z(%X)\n", 1167 - buf, 1168 - (entry.ir_index_15 << 15) | entry.ir_index_0_14, 1169 - entry.ir_zero); 1246 + apic_dbg("%s, remapped, I(%04X), Z(%X)\n", buf, 1247 + (entry.ir_index_15 << 15) | entry.ir_index_0_14, entry.ir_zero); 1170 1248 } else { 1171 - printk(KERN_DEBUG "%s, %s, D(%02X%02X), M(%1d)\n", buf, 1172 - entry.dest_mode_logical ? "logical " : "physical", 1173 - entry.virt_destid_8_14, entry.destid_0_7, 1174 - entry.delivery_mode); 1249 + apic_dbg("%s, %s, D(%02X%02X), M(%1d)\n", buf, 1250 + entry.dest_mode_logical ? "logical " : "physic al", 1251 + entry.virt_destid_8_14, entry.destid_0_7, entry.delivery_mode); 1175 1252 } 1176 1253 } 1177 1254 } ··· 1177 1264 union IO_APIC_reg_01 reg_01; 1178 1265 union IO_APIC_reg_02 reg_02; 1179 1266 union IO_APIC_reg_03 reg_03; 1180 - unsigned long flags; 1181 1267 1182 - raw_spin_lock_irqsave(&ioapic_lock, flags); 1183 - reg_00.raw = io_apic_read(ioapic_idx, 0); 1184 - reg_01.raw = io_apic_read(ioapic_idx, 1); 1185 - if (reg_01.bits.version >= 0x10) 1186 - reg_02.raw = io_apic_read(ioapic_idx, 2); 1187 - if (reg_01.bits.version >= 0x20) 1188 - reg_03.raw = io_apic_read(ioapic_idx, 3); 1189 - raw_spin_unlock_irqrestore(&ioapic_lock, flags); 1268 + scoped_guard (raw_spinlock_irqsave, &ioapic_lock) { 1269 + reg_00.raw = io_apic_read(ioapic_idx, 0); 1270 + reg_01.raw = io_apic_read(ioapic_idx, 1); 1271 + if (reg_01.bits.version >= 0x10) 1272 + reg_02.raw = io_apic_read(ioapic_idx, 2); 1273 + if (reg_01.bits.version >= 0x20) 1274 + reg_03.raw = io_apic_read(ioapic_idx, 3); 1275 + } 1190 1276 1191 - printk(KERN_DEBUG "IO APIC #%d......\n", mpc_ioapic_id(ioapic_idx)); 1192 - printk(KERN_DEBUG ".... register #00: %08X\n", reg_00.raw); 1193 - printk(KERN_DEBUG "....... : physical APIC id: %02X\n", reg_00.bits.ID); 1194 - printk(KERN_DEBUG "....... : Delivery Type: %X\n", reg_00.bits.delivery_type); 1195 - printk(KERN_DEBUG "....... : LTS : %X\n", reg_00.bits.LTS); 1196 - 1197 - printk(KERN_DEBUG ".... register #01: %08X\n", *(int *)&reg_01); 1198 - printk(KERN_DEBUG "....... : max redirection entries: %02X\n", 1199 - reg_01.bits.entries); 1200 - 1201 - printk(KERN_DEBUG "....... : PRQ implemented: %X\n", reg_01.bits.PRQ); 1202 - printk(KERN_DEBUG "....... : IO APIC version: %02X\n", 1203 - reg_01.bits.version); 1277 + apic_dbg("IO APIC #%d......\n", mpc_ioapic_id(ioapic_idx)); 1278 + apic_dbg(".... register #00: %08X\n", reg_00.raw); 1279 + apic_dbg("....... : physical APIC id: %02X\n", reg_00.bits.ID); 1280 + apic_dbg("....... : Delivery Type: %X\n", reg_00.bits.delivery_type); 1281 + apic_dbg("....... : LTS : %X\n", reg_00.bits.LTS); 1282 + apic_dbg(".... register #01: %08X\n", *(int *)&reg_01); 1283 + apic_dbg("....... : max redirection entries: %02X\n", reg_01.bits.entries); 1284 + apic_dbg("....... : PRQ implemented: %X\n", reg_01.bits.PRQ); 1285 + apic_dbg("....... : IO APIC version: %02X\n", reg_01.bits.version); 1204 1286 1205 1287 /* 1206 1288 * Some Intel chipsets with IO APIC VERSION of 0x1? don't have reg_02, ··· 1203 1295 * value, so ignore it if reg_02 == reg_01. 1204 1296 */ 1205 1297 if (reg_01.bits.version >= 0x10 && reg_02.raw != reg_01.raw) { 1206 - printk(KERN_DEBUG ".... register #02: %08X\n", reg_02.raw); 1207 - printk(KERN_DEBUG "....... : arbitration: %02X\n", reg_02.bits.arbitration); 1298 + apic_dbg(".... register #02: %08X\n", reg_02.raw); 1299 + apic_dbg("....... : arbitration: %02X\n", reg_02.bits.arbitration); 1208 1300 } 1209 1301 1210 1302 /* ··· 1214 1306 */ 1215 1307 if (reg_01.bits.version >= 0x20 && reg_03.raw != reg_02.raw && 1216 1308 reg_03.raw != reg_01.raw) { 1217 - printk(KERN_DEBUG ".... register #03: %08X\n", reg_03.raw); 1218 - printk(KERN_DEBUG "....... : Boot DT : %X\n", reg_03.bits.boot_DT); 1309 + apic_dbg(".... register #03: %08X\n", reg_03.raw); 1310 + apic_dbg("....... : Boot DT : %X\n", reg_03.bits.boot_DT); 1219 1311 } 1220 1312 1221 - printk(KERN_DEBUG ".... IRQ redirection table:\n"); 1313 + apic_dbg(".... IRQ redirection table:\n"); 1222 1314 io_apic_print_entries(ioapic_idx, reg_01.bits.entries); 1223 1315 } 1224 1316 ··· 1227 1319 int ioapic_idx; 1228 1320 unsigned int irq; 1229 1321 1230 - printk(KERN_DEBUG "number of MP IRQ sources: %d.\n", mp_irq_entries); 1231 - for_each_ioapic(ioapic_idx) 1232 - printk(KERN_DEBUG "number of IO-APIC #%d registers: %d.\n", 1233 - mpc_ioapic_id(ioapic_idx), 1234 - ioapics[ioapic_idx].nr_registers); 1322 + apic_dbg("number of MP IRQ sources: %d.\n", mp_irq_entries); 1323 + for_each_ioapic(ioapic_idx) { 1324 + apic_dbg("number of IO-APIC #%d registers: %d.\n", 1325 + mpc_ioapic_id(ioapic_idx), ioapics[ioapic_idx].nr_registers); 1326 + } 1235 1327 1236 1328 /* 1237 1329 * We are a bit conservative about what we expect. We have to ··· 1242 1334 for_each_ioapic(ioapic_idx) 1243 1335 print_IO_APIC(ioapic_idx); 1244 1336 1245 - printk(KERN_DEBUG "IRQ to pin mappings:\n"); 1337 + apic_dbg("IRQ to pin mappings:\n"); 1246 1338 for_each_active_irq(irq) { 1247 1339 struct irq_pin_list *entry; 1248 1340 struct irq_chip *chip; ··· 1257 1349 if (list_empty(&data->irq_2_pin)) 1258 1350 continue; 1259 1351 1260 - printk(KERN_DEBUG "IRQ%d ", irq); 1352 + apic_dbg("IRQ%d ", irq); 1261 1353 for_each_irq_pin(entry, data->irq_2_pin) 1262 1354 pr_cont("-> %d:%d", entry->apic, entry->pin); 1263 1355 pr_cont("\n"); ··· 1271 1363 1272 1364 void __init enable_IO_APIC(void) 1273 1365 { 1274 - int i8259_apic, i8259_pin; 1275 - int apic, pin; 1366 + int i8259_apic, i8259_pin, apic, pin; 1276 1367 1277 1368 if (ioapic_is_disabled) 1278 1369 nr_ioapics = 0; ··· 1283 1376 /* See if any of the pins is in ExtINT mode */ 1284 1377 struct IO_APIC_route_entry entry = ioapic_read_entry(apic, pin); 1285 1378 1286 - /* If the interrupt line is enabled and in ExtInt mode 1287 - * I have found the pin where the i8259 is connected. 1379 + /* 1380 + * If the interrupt line is enabled and in ExtInt mode I 1381 + * have found the pin where the i8259 is connected. 1288 1382 */ 1289 - if (!entry.masked && 1290 - entry.delivery_mode == APIC_DELIVERY_MODE_EXTINT) { 1383 + if (!entry.masked && entry.delivery_mode == APIC_DELIVERY_MODE_EXTINT) { 1291 1384 ioapic_i8259.apic = apic; 1292 1385 ioapic_i8259.pin = pin; 1293 - goto found_i8259; 1386 + break; 1294 1387 } 1295 1388 } 1296 - found_i8259: 1297 - /* Look to see what if the MP table has reported the ExtINT */ 1298 - /* If we could not find the appropriate pin by looking at the ioapic 1389 + 1390 + /* 1391 + * Look to see what if the MP table has reported the ExtINT 1392 + * 1393 + * If we could not find the appropriate pin by looking at the ioapic 1299 1394 * the i8259 probably is not connected the ioapic but give the 1300 1395 * mptable a chance anyway. 1301 1396 */ ··· 1305 1396 i8259_apic = find_isa_irq_apic(0, mp_ExtINT); 1306 1397 /* Trust the MP table if nothing is setup in the hardware */ 1307 1398 if ((ioapic_i8259.pin == -1) && (i8259_pin >= 0)) { 1308 - printk(KERN_WARNING "ExtINT not setup in hardware but reported by MP table\n"); 1399 + pr_warn("ExtINT not setup in hardware but reported by MP table\n"); 1309 1400 ioapic_i8259.pin = i8259_pin; 1310 1401 ioapic_i8259.apic = i8259_apic; 1311 1402 } 1312 1403 /* Complain if the MP table and the hardware disagree */ 1313 1404 if (((ioapic_i8259.apic != i8259_apic) || (ioapic_i8259.pin != i8259_pin)) && 1314 - (i8259_pin >= 0) && (ioapic_i8259.pin >= 0)) 1315 - { 1316 - printk(KERN_WARNING "ExtINT in hardware and MP table differ\n"); 1317 - } 1405 + (i8259_pin >= 0) && (ioapic_i8259.pin >= 0)) 1406 + pr_warn("ExtINT in hardware and MP table differ\n"); 1318 1407 1319 - /* 1320 - * Do not trust the IO-APIC being empty at bootup 1321 - */ 1408 + /* Do not trust the IO-APIC being empty at bootup */ 1322 1409 clear_IO_APIC(); 1323 1410 } 1324 1411 1325 1412 void native_restore_boot_irq_mode(void) 1326 1413 { 1327 1414 /* 1328 - * If the i8259 is routed through an IOAPIC 1329 - * Put that IOAPIC in virtual wire mode 1330 - * so legacy interrupts can be delivered. 1415 + * If the i8259 is routed through an IOAPIC Put that IOAPIC in 1416 + * virtual wire mode so legacy interrupts can be delivered. 1331 1417 */ 1332 1418 if (ioapic_i8259.pin != -1) { 1333 1419 struct IO_APIC_route_entry entry; ··· 1337 1433 entry.destid_0_7 = apic_id & 0xFF; 1338 1434 entry.virt_destid_8_14 = apic_id >> 8; 1339 1435 1340 - /* 1341 - * Add it to the IO-APIC irq-routing table: 1342 - */ 1436 + /* Add it to the IO-APIC irq-routing table */ 1343 1437 ioapic_write_entry(ioapic_i8259.apic, ioapic_i8259.pin, entry); 1344 1438 } 1345 1439 ··· 1366 1464 const u32 broadcast_id = 0xF; 1367 1465 union IO_APIC_reg_00 reg_00; 1368 1466 unsigned char old_id; 1369 - unsigned long flags; 1370 1467 int ioapic_idx, i; 1371 1468 1372 1469 /* ··· 1379 1478 */ 1380 1479 for_each_ioapic(ioapic_idx) { 1381 1480 /* Read the register 0 value */ 1382 - raw_spin_lock_irqsave(&ioapic_lock, flags); 1383 - reg_00.raw = io_apic_read(ioapic_idx, 0); 1384 - raw_spin_unlock_irqrestore(&ioapic_lock, flags); 1481 + scoped_guard (raw_spinlock_irqsave, &ioapic_lock) 1482 + reg_00.raw = io_apic_read(ioapic_idx, 0); 1385 1483 1386 1484 old_id = mpc_ioapic_id(ioapic_idx); 1387 1485 ··· 1408 1508 set_bit(i, phys_id_present_map); 1409 1509 ioapics[ioapic_idx].mp_config.apicid = i; 1410 1510 } else { 1411 - apic_printk(APIC_VERBOSE, "Setting %d in the phys_id_present_map\n", 1412 - mpc_ioapic_id(ioapic_idx)); 1511 + apic_pr_verbose("Setting %d in the phys_id_present_map\n", 1512 + mpc_ioapic_id(ioapic_idx)); 1413 1513 set_bit(mpc_ioapic_id(ioapic_idx), phys_id_present_map); 1414 1514 } 1415 1515 1416 1516 /* 1417 - * We need to adjust the IRQ routing table 1418 - * if the ID changed. 1517 + * We need to adjust the IRQ routing table if the ID 1518 + * changed. 1419 1519 */ 1420 - if (old_id != mpc_ioapic_id(ioapic_idx)) 1421 - for (i = 0; i < mp_irq_entries; i++) 1520 + if (old_id != mpc_ioapic_id(ioapic_idx)) { 1521 + for (i = 0; i < mp_irq_entries; i++) { 1422 1522 if (mp_irqs[i].dstapic == old_id) 1423 - mp_irqs[i].dstapic 1424 - = mpc_ioapic_id(ioapic_idx); 1523 + mp_irqs[i].dstapic = mpc_ioapic_id(ioapic_idx); 1524 + } 1525 + } 1425 1526 1426 1527 /* 1427 - * Update the ID register according to the right value 1428 - * from the MPC table if they are different. 1528 + * Update the ID register according to the right value from 1529 + * the MPC table if they are different. 1429 1530 */ 1430 1531 if (mpc_ioapic_id(ioapic_idx) == reg_00.bits.ID) 1431 1532 continue; 1432 1533 1433 - apic_printk(APIC_VERBOSE, KERN_INFO 1434 - "...changing IO-APIC physical APIC ID to %d ...", 1435 - mpc_ioapic_id(ioapic_idx)); 1534 + apic_pr_verbose("...changing IO-APIC physical APIC ID to %d ...", 1535 + mpc_ioapic_id(ioapic_idx)); 1436 1536 1437 1537 reg_00.bits.ID = mpc_ioapic_id(ioapic_idx); 1438 - raw_spin_lock_irqsave(&ioapic_lock, flags); 1439 - io_apic_write(ioapic_idx, 0, reg_00.raw); 1440 - raw_spin_unlock_irqrestore(&ioapic_lock, flags); 1441 - 1442 - /* 1443 - * Sanity check 1444 - */ 1445 - raw_spin_lock_irqsave(&ioapic_lock, flags); 1446 - reg_00.raw = io_apic_read(ioapic_idx, 0); 1447 - raw_spin_unlock_irqrestore(&ioapic_lock, flags); 1538 + scoped_guard (raw_spinlock_irqsave, &ioapic_lock) { 1539 + io_apic_write(ioapic_idx, 0, reg_00.raw); 1540 + reg_00.raw = io_apic_read(ioapic_idx, 0); 1541 + } 1542 + /* Sanity check */ 1448 1543 if (reg_00.bits.ID != mpc_ioapic_id(ioapic_idx)) 1449 1544 pr_cont("could not set ID!\n"); 1450 1545 else 1451 - apic_printk(APIC_VERBOSE, " ok.\n"); 1546 + apic_pr_verbose(" ok.\n"); 1452 1547 } 1453 1548 } 1454 1549 ··· 1488 1593 do { 1489 1594 rep_nop(); 1490 1595 now = rdtsc(); 1491 - } while ((now - start) < 40000000000ULL / HZ && 1492 - time_before_eq(jiffies, end)); 1596 + } while ((now - start) < 40000000000ULL / HZ && time_before_eq(jiffies, end)); 1493 1597 } 1494 1598 1495 1599 static void __init delay_without_tsc(void) ··· 1549 1655 * so we 'resend' these IRQs via IPIs, to the same CPU. It's much 1550 1656 * better to do it this way as thus we do not have to be aware of 1551 1657 * 'pending' interrupts in the IRQ path, except at this point. 1552 - */ 1553 - /* 1554 - * Edge triggered needs to resend any interrupt 1555 - * that was delayed but this is now handled in the device 1556 - * independent code. 1557 - */ 1558 - 1559 - /* 1560 - * Starting up a edge-triggered IO-APIC interrupt is 1561 - * nasty - we need to make sure that we get the edge. 1562 - * If it is already asserted for some reason, we need 1563 - * return 1 to indicate that is was pending. 1564 1658 * 1565 - * This is not complete - we should be able to fake 1566 - * an edge even if it isn't on the 8259A... 1659 + * 1660 + * Edge triggered needs to resend any interrupt that was delayed but this 1661 + * is now handled in the device independent code. 1662 + * 1663 + * Starting up a edge-triggered IO-APIC interrupt is nasty - we need to 1664 + * make sure that we get the edge. If it is already asserted for some 1665 + * reason, we need return 1 to indicate that is was pending. 1666 + * 1667 + * This is not complete - we should be able to fake an edge even if it 1668 + * isn't on the 8259A... 1567 1669 */ 1568 1670 static unsigned int startup_ioapic_irq(struct irq_data *data) 1569 1671 { 1570 1672 int was_pending = 0, irq = data->irq; 1571 - unsigned long flags; 1572 1673 1573 - raw_spin_lock_irqsave(&ioapic_lock, flags); 1674 + guard(raw_spinlock_irqsave)(&ioapic_lock); 1574 1675 if (irq < nr_legacy_irqs()) { 1575 1676 legacy_pic->mask(irq); 1576 1677 if (legacy_pic->irq_pending(irq)) 1577 1678 was_pending = 1; 1578 1679 } 1579 1680 __unmask_ioapic(data->chip_data); 1580 - raw_spin_unlock_irqrestore(&ioapic_lock, flags); 1581 - 1582 1681 return was_pending; 1583 1682 } 1584 1683 ··· 1581 1694 static bool io_apic_level_ack_pending(struct mp_chip_data *data) 1582 1695 { 1583 1696 struct irq_pin_list *entry; 1584 - unsigned long flags; 1585 1697 1586 - raw_spin_lock_irqsave(&ioapic_lock, flags); 1698 + guard(raw_spinlock_irqsave)(&ioapic_lock); 1587 1699 for_each_irq_pin(entry, data->irq_2_pin) { 1588 1700 struct IO_APIC_route_entry e; 1589 1701 int pin; ··· 1590 1704 pin = entry->pin; 1591 1705 e.w1 = io_apic_read(entry->apic, 0x10 + pin*2); 1592 1706 /* Is the remote IRR bit set? */ 1593 - if (e.irr) { 1594 - raw_spin_unlock_irqrestore(&ioapic_lock, flags); 1707 + if (e.irr) 1595 1708 return true; 1596 - } 1597 1709 } 1598 - raw_spin_unlock_irqrestore(&ioapic_lock, flags); 1599 - 1600 1710 return false; 1601 1711 } 1602 1712 ··· 1610 1728 static inline void ioapic_finish_move(struct irq_data *data, bool moveit) 1611 1729 { 1612 1730 if (unlikely(moveit)) { 1613 - /* Only migrate the irq if the ack has been received. 1731 + /* 1732 + * Only migrate the irq if the ack has been received. 1614 1733 * 1615 1734 * On rare occasions the broadcast level triggered ack gets 1616 1735 * delayed going to ioapics, and if we reprogram the ··· 1794 1911 __ioapic_write_entry(entry->apic, entry->pin, mpd->entry); 1795 1912 } 1796 1913 1797 - static int ioapic_set_affinity(struct irq_data *irq_data, 1798 - const struct cpumask *mask, bool force) 1914 + static int ioapic_set_affinity(struct irq_data *irq_data, const struct cpumask *mask, bool force) 1799 1915 { 1800 1916 struct irq_data *parent = irq_data->parent_data; 1801 - unsigned long flags; 1802 1917 int ret; 1803 1918 1804 1919 ret = parent->chip->irq_set_affinity(parent, mask, force); 1805 - raw_spin_lock_irqsave(&ioapic_lock, flags); 1920 + 1921 + guard(raw_spinlock_irqsave)(&ioapic_lock); 1806 1922 if (ret >= 0 && ret != IRQ_SET_MASK_OK_DONE) 1807 1923 ioapic_configure_entry(irq_data); 1808 - raw_spin_unlock_irqrestore(&ioapic_lock, flags); 1809 1924 1810 1925 return ret; 1811 1926 } ··· 1822 1941 * 1823 1942 * Verify that the corresponding Remote-IRR bits are clear. 1824 1943 */ 1825 - static int ioapic_irq_get_chip_state(struct irq_data *irqd, 1826 - enum irqchip_irq_state which, 1827 - bool *state) 1944 + static int ioapic_irq_get_chip_state(struct irq_data *irqd, enum irqchip_irq_state which, 1945 + bool *state) 1828 1946 { 1829 1947 struct mp_chip_data *mcd = irqd->chip_data; 1830 1948 struct IO_APIC_route_entry rentry; ··· 1833 1953 return -EINVAL; 1834 1954 1835 1955 *state = false; 1836 - raw_spin_lock(&ioapic_lock); 1956 + 1957 + guard(raw_spinlock)(&ioapic_lock); 1837 1958 for_each_irq_pin(p, mcd->irq_2_pin) { 1838 1959 rentry = __ioapic_read_entry(p->apic, p->pin); 1839 1960 /* ··· 1848 1967 break; 1849 1968 } 1850 1969 } 1851 - raw_spin_unlock(&ioapic_lock); 1852 1970 return 0; 1853 1971 } 1854 1972 ··· 1888 2008 cfg = irq_cfg(irq); 1889 2009 if (IO_APIC_IRQ(irq) && cfg && !cfg->vector) { 1890 2010 /* 1891 - * Hmm.. We don't have an entry for this, 1892 - * so default to an old-fashioned 8259 1893 - * interrupt if we can.. 2011 + * Hmm.. We don't have an entry for this, so 2012 + * default to an old-fashioned 8259 interrupt if we 2013 + * can. Otherwise set the dummy interrupt chip. 1894 2014 */ 1895 2015 if (irq < nr_legacy_irqs()) 1896 2016 legacy_pic->make_irq(irq); 1897 2017 else 1898 - /* Strange. Oh, well.. */ 1899 2018 irq_set_chip(irq, &no_irq_chip); 1900 2019 } 1901 2020 } ··· 1903 2024 /* 1904 2025 * The local APIC irq-chip implementation: 1905 2026 */ 1906 - 1907 2027 static void mask_lapic_irq(struct irq_data *data) 1908 2028 { 1909 - unsigned long v; 2029 + unsigned long v = apic_read(APIC_LVT0); 1910 2030 1911 - v = apic_read(APIC_LVT0); 1912 2031 apic_write(APIC_LVT0, v | APIC_LVT_MASKED); 1913 2032 } 1914 2033 1915 2034 static void unmask_lapic_irq(struct irq_data *data) 1916 2035 { 1917 - unsigned long v; 2036 + unsigned long v = apic_read(APIC_LVT0); 1918 2037 1919 - v = apic_read(APIC_LVT0); 1920 2038 apic_write(APIC_LVT0, v & ~APIC_LVT_MASKED); 1921 2039 } 1922 2040 ··· 1932 2056 static void lapic_register_intr(int irq) 1933 2057 { 1934 2058 irq_clear_status_flags(irq, IRQ_LEVEL); 1935 - irq_set_chip_and_handler_name(irq, &lapic_chip, handle_edge_irq, 1936 - "edge"); 2059 + irq_set_chip_and_handler_name(irq, &lapic_chip, handle_edge_irq, "edge"); 1937 2060 } 1938 2061 1939 2062 /* ··· 1944 2069 */ 1945 2070 static inline void __init unlock_ExtINT_logic(void) 1946 2071 { 1947 - int apic, pin, i; 1948 - struct IO_APIC_route_entry entry0, entry1; 1949 2072 unsigned char save_control, save_freq_select; 2073 + struct IO_APIC_route_entry entry0, entry1; 2074 + int apic, pin, i; 1950 2075 u32 apic_id; 1951 2076 1952 2077 pin = find_isa_irq_pin(8, mp_INT); ··· 2006 2131 } 2007 2132 early_param("disable_timer_pin_1", disable_timer_pin_setup); 2008 2133 2009 - static int mp_alloc_timer_irq(int ioapic, int pin) 2134 + static int __init mp_alloc_timer_irq(int ioapic, int pin) 2010 2135 { 2011 - int irq = -1; 2012 2136 struct irq_domain *domain = mp_ioapic_irqdomain(ioapic); 2137 + int irq = -1; 2013 2138 2014 2139 if (domain) { 2015 2140 struct irq_alloc_info info; ··· 2017 2142 ioapic_set_alloc_attr(&info, NUMA_NO_NODE, 0, 0); 2018 2143 info.devid = mpc_ioapic_id(ioapic); 2019 2144 info.ioapic.pin = pin; 2020 - mutex_lock(&ioapic_mutex); 2145 + guard(mutex)(&ioapic_mutex); 2021 2146 irq = alloc_isa_irq_from_domain(domain, 0, ioapic, pin, &info); 2022 - mutex_unlock(&ioapic_mutex); 2023 2147 } 2024 2148 2025 2149 return irq; 2150 + } 2151 + 2152 + static void __init replace_pin_at_irq_node(struct mp_chip_data *data, int node, 2153 + int oldapic, int oldpin, 2154 + int newapic, int newpin) 2155 + { 2156 + struct irq_pin_list *entry; 2157 + 2158 + for_each_irq_pin(entry, data->irq_2_pin) { 2159 + if (entry->apic == oldapic && entry->pin == oldpin) { 2160 + entry->apic = newapic; 2161 + entry->pin = newpin; 2162 + return; 2163 + } 2164 + } 2165 + 2166 + /* Old apic/pin didn't exist, so just add a new one */ 2167 + add_pin_to_irq_node(data, node, newapic, newpin); 2026 2168 } 2027 2169 2028 2170 /* ··· 2047 2155 * a wide range of boards and BIOS bugs. Fortunately only the timer IRQ 2048 2156 * is so screwy. Thanks to Brian Perkins for testing/hacking this beast 2049 2157 * fanatically on his truly buggy board. 2050 - * 2051 - * FIXME: really need to revamp this for all platforms. 2052 2158 */ 2053 2159 static inline void __init check_timer(void) 2054 2160 { ··· 2084 2194 pin2 = ioapic_i8259.pin; 2085 2195 apic2 = ioapic_i8259.apic; 2086 2196 2087 - apic_printk(APIC_QUIET, KERN_INFO "..TIMER: vector=0x%02X " 2088 - "apic1=%d pin1=%d apic2=%d pin2=%d\n", 2089 - cfg->vector, apic1, pin1, apic2, pin2); 2197 + pr_info("..TIMER: vector=0x%02X apic1=%d pin1=%d apic2=%d pin2=%d\n", 2198 + cfg->vector, apic1, pin1, apic2, pin2); 2090 2199 2091 2200 /* 2092 2201 * Some BIOS writers are clueless and report the ExtINTA ··· 2129 2240 panic_if_irq_remap("timer doesn't work through Interrupt-remapped IO-APIC"); 2130 2241 clear_IO_APIC_pin(apic1, pin1); 2131 2242 if (!no_pin1) 2132 - apic_printk(APIC_QUIET, KERN_ERR "..MP-BIOS bug: " 2133 - "8254 timer not connected to IO-APIC\n"); 2243 + pr_err("..MP-BIOS bug: 8254 timer not connected to IO-APIC\n"); 2134 2244 2135 - apic_printk(APIC_QUIET, KERN_INFO "...trying to set up timer " 2136 - "(IRQ0) through the 8259A ...\n"); 2137 - apic_printk(APIC_QUIET, KERN_INFO 2138 - "..... (found apic %d pin %d) ...\n", apic2, pin2); 2245 + pr_info("...trying to set up timer (IRQ0) through the 8259A ...\n"); 2246 + pr_info("..... (found apic %d pin %d) ...\n", apic2, pin2); 2139 2247 /* 2140 2248 * legacy devices should be connected to IO APIC #0 2141 2249 */ ··· 2141 2255 irq_domain_activate_irq(irq_data, false); 2142 2256 legacy_pic->unmask(0); 2143 2257 if (timer_irq_works()) { 2144 - apic_printk(APIC_QUIET, KERN_INFO "....... works.\n"); 2258 + pr_info("....... works.\n"); 2145 2259 goto out; 2146 2260 } 2147 2261 /* ··· 2149 2263 */ 2150 2264 legacy_pic->mask(0); 2151 2265 clear_IO_APIC_pin(apic2, pin2); 2152 - apic_printk(APIC_QUIET, KERN_INFO "....... failed.\n"); 2266 + pr_info("....... failed.\n"); 2153 2267 } 2154 2268 2155 - apic_printk(APIC_QUIET, KERN_INFO 2156 - "...trying to set up timer as Virtual Wire IRQ...\n"); 2269 + pr_info("...trying to set up timer as Virtual Wire IRQ...\n"); 2157 2270 2158 2271 lapic_register_intr(0); 2159 2272 apic_write(APIC_LVT0, APIC_DM_FIXED | cfg->vector); /* Fixed mode */ 2160 2273 legacy_pic->unmask(0); 2161 2274 2162 2275 if (timer_irq_works()) { 2163 - apic_printk(APIC_QUIET, KERN_INFO "..... works.\n"); 2276 + pr_info("..... works.\n"); 2164 2277 goto out; 2165 2278 } 2166 2279 legacy_pic->mask(0); 2167 2280 apic_write(APIC_LVT0, APIC_LVT_MASKED | APIC_DM_FIXED | cfg->vector); 2168 - apic_printk(APIC_QUIET, KERN_INFO "..... failed.\n"); 2281 + pr_info("..... failed.\n"); 2169 2282 2170 - apic_printk(APIC_QUIET, KERN_INFO 2171 - "...trying to set up timer as ExtINT IRQ...\n"); 2283 + pr_info("...trying to set up timer as ExtINT IRQ...\n"); 2172 2284 2173 2285 legacy_pic->init(0); 2174 2286 legacy_pic->make_irq(0); ··· 2176 2292 unlock_ExtINT_logic(); 2177 2293 2178 2294 if (timer_irq_works()) { 2179 - apic_printk(APIC_QUIET, KERN_INFO "..... works.\n"); 2295 + pr_info("..... works.\n"); 2180 2296 goto out; 2181 2297 } 2182 - apic_printk(APIC_QUIET, KERN_INFO "..... failed :(.\n"); 2183 - if (apic_is_x2apic_enabled()) 2184 - apic_printk(APIC_QUIET, KERN_INFO 2185 - "Perhaps problem with the pre-enabled x2apic mode\n" 2186 - "Try booting with x2apic and interrupt-remapping disabled in the bios.\n"); 2298 + 2299 + pr_info("..... failed :\n"); 2300 + if (apic_is_x2apic_enabled()) { 2301 + pr_info("Perhaps problem with the pre-enabled x2apic mode\n" 2302 + "Try booting with x2apic and interrupt-remapping disabled in the bios.\n"); 2303 + } 2187 2304 panic("IO-APIC + timer doesn't work! Boot with apic=debug and send a " 2188 2305 "report. Then try booting with the 'noapic' option.\n"); 2189 2306 out: ··· 2212 2327 2213 2328 static int mp_irqdomain_create(int ioapic) 2214 2329 { 2215 - struct irq_domain *parent; 2330 + struct mp_ioapic_gsi *gsi_cfg = mp_ioapic_gsi_routing(ioapic); 2216 2331 int hwirqs = mp_ioapic_pin_count(ioapic); 2217 2332 struct ioapic *ip = &ioapics[ioapic]; 2218 2333 struct ioapic_domain_cfg *cfg = &ip->irqdomain_cfg; 2219 - struct mp_ioapic_gsi *gsi_cfg = mp_ioapic_gsi_routing(ioapic); 2334 + struct irq_domain *parent; 2220 2335 struct fwnode_handle *fn; 2221 2336 struct irq_fwspec fwspec; 2222 2337 ··· 2252 2367 return -ENOMEM; 2253 2368 } 2254 2369 2255 - if (cfg->type == IOAPIC_DOMAIN_LEGACY || 2256 - cfg->type == IOAPIC_DOMAIN_STRICT) 2257 - ioapic_dynirq_base = max(ioapic_dynirq_base, 2258 - gsi_cfg->gsi_end + 1); 2370 + if (cfg->type == IOAPIC_DOMAIN_LEGACY || cfg->type == IOAPIC_DOMAIN_STRICT) 2371 + ioapic_dynirq_base = max(ioapic_dynirq_base, gsi_cfg->gsi_end + 1); 2259 2372 2260 2373 return 0; 2261 2374 } ··· 2280 2397 2281 2398 io_apic_irqs = nr_legacy_irqs() ? ~PIC_IRQS : ~0UL; 2282 2399 2283 - apic_printk(APIC_VERBOSE, "ENABLING IO-APIC IRQs\n"); 2400 + apic_pr_verbose("ENABLING IO-APIC IRQs\n"); 2284 2401 for_each_ioapic(ioapic) 2285 2402 BUG_ON(mp_irqdomain_create(ioapic)); 2286 2403 2287 - /* 2288 - * Set up IO-APIC IRQ routing. 2289 - */ 2404 + /* Set up IO-APIC IRQ routing. */ 2290 2405 x86_init.mpparse.setup_ioapic_ids(); 2291 2406 2292 2407 sync_Arb_IDs(); ··· 2298 2417 2299 2418 static void resume_ioapic_id(int ioapic_idx) 2300 2419 { 2301 - unsigned long flags; 2302 2420 union IO_APIC_reg_00 reg_00; 2303 2421 2304 - raw_spin_lock_irqsave(&ioapic_lock, flags); 2422 + guard(raw_spinlock_irqsave)(&ioapic_lock); 2305 2423 reg_00.raw = io_apic_read(ioapic_idx, 0); 2306 2424 if (reg_00.bits.ID != mpc_ioapic_id(ioapic_idx)) { 2307 2425 reg_00.bits.ID = mpc_ioapic_id(ioapic_idx); 2308 2426 io_apic_write(ioapic_idx, 0, reg_00.raw); 2309 2427 } 2310 - raw_spin_unlock_irqrestore(&ioapic_lock, flags); 2311 2428 } 2312 2429 2313 2430 static void ioapic_resume(void) ··· 2319 2440 } 2320 2441 2321 2442 static struct syscore_ops ioapic_syscore_ops = { 2322 - .suspend = save_ioapic_entries, 2323 - .resume = ioapic_resume, 2443 + .suspend = save_ioapic_entries, 2444 + .resume = ioapic_resume, 2324 2445 }; 2325 2446 2326 2447 static int __init ioapic_init_ops(void) ··· 2335 2456 static int io_apic_get_redir_entries(int ioapic) 2336 2457 { 2337 2458 union IO_APIC_reg_01 reg_01; 2338 - unsigned long flags; 2339 2459 2340 - raw_spin_lock_irqsave(&ioapic_lock, flags); 2460 + guard(raw_spinlock_irqsave)(&ioapic_lock); 2341 2461 reg_01.raw = io_apic_read(ioapic, 1); 2342 - raw_spin_unlock_irqrestore(&ioapic_lock, flags); 2343 2462 2344 - /* The register returns the maximum index redir index 2345 - * supported, which is one less than the total number of redir 2346 - * entries. 2463 + /* 2464 + * The register returns the maximum index redir index supported, 2465 + * which is one less than the total number of redir entries. 2347 2466 */ 2348 2467 return reg_01.bits.entries + 1; 2349 2468 } ··· 2371 2494 static DECLARE_BITMAP(apic_id_map, MAX_LOCAL_APIC); 2372 2495 const u32 broadcast_id = 0xF; 2373 2496 union IO_APIC_reg_00 reg_00; 2374 - unsigned long flags; 2375 2497 int i = 0; 2376 2498 2377 2499 /* Initialize the ID map */ 2378 2500 if (bitmap_empty(apic_id_map, MAX_LOCAL_APIC)) 2379 2501 copy_phys_cpu_present_map(apic_id_map); 2380 2502 2381 - raw_spin_lock_irqsave(&ioapic_lock, flags); 2382 - reg_00.raw = io_apic_read(ioapic, 0); 2383 - raw_spin_unlock_irqrestore(&ioapic_lock, flags); 2503 + scoped_guard (raw_spinlock_irqsave, &ioapic_lock) 2504 + reg_00.raw = io_apic_read(ioapic, 0); 2384 2505 2385 2506 if (apic_id >= broadcast_id) { 2386 2507 pr_warn("IOAPIC[%d]: Invalid apic_id %d, trying %d\n", ··· 2405 2530 if (reg_00.bits.ID != apic_id) { 2406 2531 reg_00.bits.ID = apic_id; 2407 2532 2408 - raw_spin_lock_irqsave(&ioapic_lock, flags); 2409 - io_apic_write(ioapic, 0, reg_00.raw); 2410 - reg_00.raw = io_apic_read(ioapic, 0); 2411 - raw_spin_unlock_irqrestore(&ioapic_lock, flags); 2533 + scoped_guard (raw_spinlock_irqsave, &ioapic_lock) { 2534 + io_apic_write(ioapic, 0, reg_00.raw); 2535 + reg_00.raw = io_apic_read(ioapic, 0); 2536 + } 2412 2537 2413 2538 /* Sanity check */ 2414 2539 if (reg_00.bits.ID != apic_id) { 2415 - pr_err("IOAPIC[%d]: Unable to change apic_id!\n", 2416 - ioapic); 2540 + pr_err("IOAPIC[%d]: Unable to change apic_id!\n", ioapic); 2417 2541 return -1; 2418 2542 } 2419 2543 } 2420 2544 2421 - apic_printk(APIC_VERBOSE, KERN_INFO 2422 - "IOAPIC[%d]: Assigned apic_id %d\n", ioapic, apic_id); 2545 + apic_pr_verbose("IOAPIC[%d]: Assigned apic_id %d\n", ioapic, apic_id); 2423 2546 2424 2547 return apic_id; 2425 2548 } ··· 2433 2560 { 2434 2561 union IO_APIC_reg_00 reg_00; 2435 2562 DECLARE_BITMAP(used, 256); 2436 - unsigned long flags; 2437 2563 u8 new_id; 2438 2564 int i; 2439 2565 ··· 2448 2576 * Read the current id from the ioapic and keep it if 2449 2577 * available. 2450 2578 */ 2451 - raw_spin_lock_irqsave(&ioapic_lock, flags); 2452 - reg_00.raw = io_apic_read(idx, 0); 2453 - raw_spin_unlock_irqrestore(&ioapic_lock, flags); 2579 + scoped_guard (raw_spinlock_irqsave, &ioapic_lock) 2580 + reg_00.raw = io_apic_read(idx, 0); 2581 + 2454 2582 new_id = reg_00.bits.ID; 2455 2583 if (!test_bit(new_id, used)) { 2456 - apic_printk(APIC_VERBOSE, KERN_INFO 2457 - "IOAPIC[%d]: Using reg apic_id %d instead of %d\n", 2458 - idx, new_id, id); 2584 + apic_pr_verbose("IOAPIC[%d]: Using reg apic_id %d instead of %d\n", 2585 + idx, new_id, id); 2459 2586 return new_id; 2460 2587 } 2461 2588 2462 - /* 2463 - * Get the next free id and write it to the ioapic. 2464 - */ 2589 + /* Get the next free id and write it to the ioapic. */ 2465 2590 new_id = find_first_zero_bit(used, 256); 2466 2591 reg_00.bits.ID = new_id; 2467 - raw_spin_lock_irqsave(&ioapic_lock, flags); 2468 - io_apic_write(idx, 0, reg_00.raw); 2469 - reg_00.raw = io_apic_read(idx, 0); 2470 - raw_spin_unlock_irqrestore(&ioapic_lock, flags); 2592 + scoped_guard (raw_spinlock_irqsave, &ioapic_lock) { 2593 + io_apic_write(idx, 0, reg_00.raw); 2594 + reg_00.raw = io_apic_read(idx, 0); 2595 + } 2471 2596 /* Sanity check */ 2472 2597 BUG_ON(reg_00.bits.ID != new_id); 2473 2598 ··· 2474 2605 2475 2606 static int io_apic_get_version(int ioapic) 2476 2607 { 2477 - union IO_APIC_reg_01 reg_01; 2478 - unsigned long flags; 2608 + union IO_APIC_reg_01 reg_01; 2479 2609 2480 - raw_spin_lock_irqsave(&ioapic_lock, flags); 2610 + guard(raw_spinlock_irqsave)(&ioapic_lock); 2481 2611 reg_01.raw = io_apic_read(ioapic, 1); 2482 - raw_spin_unlock_irqrestore(&ioapic_lock, flags); 2483 2612 2484 2613 return reg_01.bits.version; 2485 2614 } ··· 2492 2625 2493 2626 static struct resource * __init ioapic_setup_resources(void) 2494 2627 { 2495 - unsigned long n; 2496 2628 struct resource *res; 2629 + unsigned long n; 2497 2630 char *mem; 2498 2631 int i; 2499 2632 ··· 2553 2686 ioapic_phys = mpc_ioapic_addr(i); 2554 2687 #ifdef CONFIG_X86_32 2555 2688 if (!ioapic_phys) { 2556 - printk(KERN_ERR 2557 - "WARNING: bogus zero IO-APIC " 2558 - "address found in MPTABLE, " 2689 + pr_err("WARNING: bogus zero IO-APIC address found in MPTABLE, " 2559 2690 "disabling IO/APIC support!\n"); 2560 2691 smp_found_config = 0; 2561 2692 ioapic_is_disabled = true; ··· 2572 2707 ioapic_phys = __pa(ioapic_phys); 2573 2708 } 2574 2709 io_apic_set_fixmap(idx, ioapic_phys); 2575 - apic_printk(APIC_VERBOSE, "mapped IOAPIC to %08lx (%08lx)\n", 2576 - __fix_to_virt(idx) + (ioapic_phys & ~PAGE_MASK), 2577 - ioapic_phys); 2710 + apic_pr_verbose("mapped IOAPIC to %08lx (%08lx)\n", 2711 + __fix_to_virt(idx) + (ioapic_phys & ~PAGE_MASK), ioapic_phys); 2578 2712 idx++; 2579 2713 2580 2714 ioapic_res->start = ioapic_phys; ··· 2584 2720 2585 2721 void __init ioapic_insert_resources(void) 2586 2722 { 2587 - int i; 2588 2723 struct resource *r = ioapic_resources; 2724 + int i; 2589 2725 2590 2726 if (!r) { 2591 2727 if (nr_ioapics > 0) 2592 - printk(KERN_ERR 2593 - "IO APIC resources couldn't be allocated.\n"); 2728 + pr_err("IO APIC resources couldn't be allocated.\n"); 2594 2729 return; 2595 2730 } 2596 2731 ··· 2609 2746 /* Find the IOAPIC that manages this GSI. */ 2610 2747 for_each_ioapic(i) { 2611 2748 struct mp_ioapic_gsi *gsi_cfg = mp_ioapic_gsi_routing(i); 2749 + 2612 2750 if (gsi >= gsi_cfg->gsi_base && gsi <= gsi_cfg->gsi_end) 2613 2751 return i; 2614 2752 } 2615 2753 2616 - printk(KERN_ERR "ERROR: Unable to locate IOAPIC for GSI %d\n", gsi); 2754 + pr_err("ERROR: Unable to locate IOAPIC for GSI %d\n", gsi); 2617 2755 return -1; 2618 2756 } 2619 2757 ··· 2653 2789 2654 2790 static int find_free_ioapic_entry(void) 2655 2791 { 2656 - int idx; 2657 - 2658 - for (idx = 0; idx < MAX_IO_APICS; idx++) 2792 + for (int idx = 0; idx < MAX_IO_APICS; idx++) { 2659 2793 if (ioapics[idx].nr_registers == 0) 2660 2794 return idx; 2661 - 2795 + } 2662 2796 return MAX_IO_APICS; 2663 2797 } 2664 2798 ··· 2667 2805 * @gsi_base: base of GSI associated with the IOAPIC 2668 2806 * @cfg: configuration information for the IOAPIC 2669 2807 */ 2670 - int mp_register_ioapic(int id, u32 address, u32 gsi_base, 2671 - struct ioapic_domain_cfg *cfg) 2808 + int mp_register_ioapic(int id, u32 address, u32 gsi_base, struct ioapic_domain_cfg *cfg) 2672 2809 { 2673 2810 bool hotplug = !!ioapic_initialized; 2674 2811 struct mp_ioapic_gsi *gsi_cfg; ··· 2678 2817 pr_warn("Bogus (zero) I/O APIC address found, skipping!\n"); 2679 2818 return -EINVAL; 2680 2819 } 2681 - for_each_ioapic(ioapic) 2820 + 2821 + for_each_ioapic(ioapic) { 2682 2822 if (ioapics[ioapic].mp_config.apicaddr == address) { 2683 - pr_warn("address 0x%x conflicts with IOAPIC%d\n", 2684 - address, ioapic); 2823 + pr_warn("address 0x%x conflicts with IOAPIC%d\n", address, ioapic); 2685 2824 return -EEXIST; 2686 2825 } 2826 + } 2687 2827 2688 2828 idx = find_free_ioapic_entry(); 2689 2829 if (idx >= MAX_IO_APICS) { ··· 2719 2857 (gsi_end >= gsi_cfg->gsi_base && 2720 2858 gsi_end <= gsi_cfg->gsi_end)) { 2721 2859 pr_warn("GSI range [%u-%u] for new IOAPIC conflicts with GSI[%u-%u]\n", 2722 - gsi_base, gsi_end, 2723 - gsi_cfg->gsi_base, gsi_cfg->gsi_end); 2860 + gsi_base, gsi_end, gsi_cfg->gsi_base, gsi_cfg->gsi_end); 2724 2861 clear_fixmap(FIX_IO_APIC_BASE_0 + idx); 2725 2862 return -ENOSPC; 2726 2863 } ··· 2753 2892 ioapics[idx].nr_registers = entries; 2754 2893 2755 2894 pr_info("IOAPIC[%d]: apic_id %d, version %d, address 0x%x, GSI %d-%d\n", 2756 - idx, mpc_ioapic_id(idx), 2757 - mpc_ioapic_ver(idx), mpc_ioapic_addr(idx), 2895 + idx, mpc_ioapic_id(idx), mpc_ioapic_ver(idx), mpc_ioapic_addr(idx), 2758 2896 gsi_cfg->gsi_base, gsi_cfg->gsi_end); 2759 2897 2760 2898 return 0; ··· 2764 2904 int ioapic, pin; 2765 2905 int found = 0; 2766 2906 2767 - for_each_ioapic(ioapic) 2907 + for_each_ioapic(ioapic) { 2768 2908 if (ioapics[ioapic].gsi_config.gsi_base == gsi_base) { 2769 2909 found = 1; 2770 2910 break; 2771 2911 } 2912 + } 2913 + 2772 2914 if (!found) { 2773 2915 pr_warn("can't find IOAPIC for GSI %d\n", gsi_base); 2774 2916 return -ENODEV; ··· 2784 2922 if (irq >= 0) { 2785 2923 data = irq_get_chip_data(irq); 2786 2924 if (data && data->count) { 2787 - pr_warn("pin%d on IOAPIC%d is still in use.\n", 2788 - pin, ioapic); 2925 + pr_warn("pin%d on IOAPIC%d is still in use.\n", pin, ioapic); 2789 2926 return -EBUSY; 2790 2927 } 2791 2928 } ··· 2819 2958 if (info && info->ioapic.valid) { 2820 2959 data->is_level = info->ioapic.is_level; 2821 2960 data->active_low = info->ioapic.active_low; 2822 - } else if (__acpi_get_override_irq(gsi, &data->is_level, 2823 - &data->active_low) < 0) { 2961 + } else if (__acpi_get_override_irq(gsi, &data->is_level, &data->active_low) < 0) { 2824 2962 /* PCI interrupts are always active low level triggered. */ 2825 2963 data->is_level = true; 2826 2964 data->active_low = true; ··· 2877 3017 return -ENOMEM; 2878 3018 2879 3019 ret = irq_domain_alloc_irqs_parent(domain, virq, nr_irqs, info); 2880 - if (ret < 0) { 2881 - kfree(data); 2882 - return ret; 2883 - } 3020 + if (ret < 0) 3021 + goto free_data; 2884 3022 2885 3023 INIT_LIST_HEAD(&data->irq_2_pin); 2886 3024 irq_data->hwirq = info->ioapic.pin; ··· 2887 3029 irq_data->chip_data = data; 2888 3030 mp_irqdomain_get_attr(mp_pin_to_gsi(ioapic, pin), data, info); 2889 3031 2890 - add_pin_to_irq_node(data, ioapic_alloc_attr_node(info), ioapic, pin); 3032 + if (!add_pin_to_irq_node(data, ioapic_alloc_attr_node(info), ioapic, pin)) { 3033 + ret = -ENOMEM; 3034 + goto free_irqs; 3035 + } 2891 3036 2892 3037 mp_preconfigure_entry(data); 2893 3038 mp_register_handler(virq, data->is_level); ··· 2900 3039 legacy_pic->mask(virq); 2901 3040 local_irq_restore(flags); 2902 3041 2903 - apic_printk(APIC_VERBOSE, KERN_DEBUG 2904 - "IOAPIC[%d]: Preconfigured routing entry (%d-%d -> IRQ %d Level:%i ActiveLow:%i)\n", 2905 - ioapic, mpc_ioapic_id(ioapic), pin, virq, 2906 - data->is_level, data->active_low); 3042 + apic_pr_verbose("IOAPIC[%d]: Preconfigured routing entry (%d-%d -> IRQ %d Level:%i ActiveLow:%i)\n", 3043 + ioapic, mpc_ioapic_id(ioapic), pin, virq, data->is_level, data->active_low); 2907 3044 return 0; 3045 + 3046 + free_irqs: 3047 + irq_domain_free_irqs_parent(domain, virq, nr_irqs); 3048 + free_data: 3049 + kfree(data); 3050 + return ret; 2908 3051 } 2909 3052 2910 3053 void mp_irqdomain_free(struct irq_domain *domain, unsigned int virq, ··· 2921 3056 irq_data = irq_domain_get_irq_data(domain, virq); 2922 3057 if (irq_data && irq_data->chip_data) { 2923 3058 data = irq_data->chip_data; 2924 - __remove_pin_from_irq(data, mp_irqdomain_ioapic_idx(domain), 2925 - (int)irq_data->hwirq); 3059 + __remove_pin_from_irq(data, mp_irqdomain_ioapic_idx(domain), (int)irq_data->hwirq); 2926 3060 WARN_ON(!list_empty(&data->irq_2_pin)); 2927 3061 kfree(irq_data->chip_data); 2928 3062 } 2929 3063 irq_domain_free_irqs_top(domain, virq, nr_irqs); 2930 3064 } 2931 3065 2932 - int mp_irqdomain_activate(struct irq_domain *domain, 2933 - struct irq_data *irq_data, bool reserve) 3066 + int mp_irqdomain_activate(struct irq_domain *domain, struct irq_data *irq_data, bool reserve) 2934 3067 { 2935 - unsigned long flags; 2936 - 2937 - raw_spin_lock_irqsave(&ioapic_lock, flags); 3068 + guard(raw_spinlock_irqsave)(&ioapic_lock); 2938 3069 ioapic_configure_entry(irq_data); 2939 - raw_spin_unlock_irqrestore(&ioapic_lock, flags); 2940 3070 return 0; 2941 3071 } 2942 3072 ··· 2939 3079 struct irq_data *irq_data) 2940 3080 { 2941 3081 /* It won't be called for IRQ with multiple IOAPIC pins associated */ 2942 - ioapic_mask_entry(mp_irqdomain_ioapic_idx(domain), 2943 - (int)irq_data->hwirq); 3082 + ioapic_mask_entry(mp_irqdomain_ioapic_idx(domain), (int)irq_data->hwirq); 2944 3083 } 2945 3084 2946 3085 int mp_irqdomain_ioapic_idx(struct irq_domain *domain)

+6 -7

arch/x86/kernel/mpparse.c

··· 68 68 { 69 69 memcpy(str, m->bustype, 6); 70 70 str[6] = 0; 71 - apic_printk(APIC_VERBOSE, "Bus #%d is %s\n", m->busid, str); 71 + apic_pr_verbose("Bus #%d is %s\n", m->busid, str); 72 72 } 73 73 74 74 static void __init MP_bus_info(struct mpc_bus *m) ··· 417 417 mpc = early_memremap(physptr, PAGE_SIZE); 418 418 size = mpc->length; 419 419 early_memunmap(mpc, PAGE_SIZE); 420 - apic_printk(APIC_VERBOSE, " mpc: %lx-%lx\n", physptr, physptr + size); 420 + apic_pr_verbose(" mpc: %lx-%lx\n", physptr, physptr + size); 421 421 422 422 return size; 423 423 } ··· 560 560 struct mpf_intel *mpf; 561 561 int ret = 0; 562 562 563 - apic_printk(APIC_VERBOSE, "Scan for SMP in [mem %#010lx-%#010lx]\n", 564 - base, base + length - 1); 563 + apic_pr_verbose("Scan for SMP in [mem %#010lx-%#010lx]\n", base, base + length - 1); 565 564 BUILD_BUG_ON(sizeof(*mpf) != 16); 566 565 567 566 while (length > 0) { ··· 682 683 { 683 684 int i; 684 685 685 - apic_printk(APIC_VERBOSE, "OLD "); 686 + apic_pr_verbose("OLD "); 686 687 print_mp_irq_info(m); 687 688 688 689 i = get_MP_intsrc_index(m); 689 690 if (i > 0) { 690 691 memcpy(m, &mp_irqs[i], sizeof(*m)); 691 - apic_printk(APIC_VERBOSE, "NEW "); 692 + apic_pr_verbose("NEW "); 692 693 print_mp_irq_info(&mp_irqs[i]); 693 694 return; 694 695 } ··· 771 772 continue; 772 773 773 774 if (nr_m_spare > 0) { 774 - apic_printk(APIC_VERBOSE, "*NEW* found\n"); 775 + apic_pr_verbose("*NEW* found\n"); 775 776 nr_m_spare--; 776 777 memcpy(m_spare[nr_m_spare], &mp_irqs[i], sizeof(mp_irqs[i])); 777 778 m_spare[nr_m_spare] = NULL;

+5 -6

drivers/iommu/intel/irq_remapping.c

··· 1352 1352 case X86_IRQ_ALLOC_TYPE_IOAPIC: 1353 1353 /* Set source-id of interrupt request */ 1354 1354 set_ioapic_sid(irte, info->devid); 1355 - apic_printk(APIC_VERBOSE, KERN_DEBUG "IOAPIC[%d]: Set IRTE entry (P:%d FPD:%d Dst_Mode:%d Redir_hint:%d Trig_Mode:%d Dlvry_Mode:%X Avail:%X Vector:%02X Dest:%08X SID:%04X SQ:%X SVT:%X)\n", 1356 - info->devid, irte->present, irte->fpd, 1357 - irte->dst_mode, irte->redir_hint, 1358 - irte->trigger_mode, irte->dlvry_mode, 1359 - irte->avail, irte->vector, irte->dest_id, 1360 - irte->sid, irte->sq, irte->svt); 1355 + apic_pr_verbose("IOAPIC[%d]: Set IRTE entry (P:%d FPD:%d Dst_Mode:%d Redir_hint:%d Trig_Mode:%d Dlvry_Mode:%X Avail:%X Vector:%02X Dest:%08X SID:%04X SQ:%X SVT:%X)\n", 1356 + info->devid, irte->present, irte->fpd, irte->dst_mode, 1357 + irte->redir_hint, irte->trigger_mode, irte->dlvry_mode, 1358 + irte->avail, irte->vector, irte->dest_id, irte->sid, 1359 + irte->sq, irte->svt); 1361 1360 sub_handle = info->ioapic.pin; 1362 1361 break; 1363 1362 case X86_IRQ_ALLOC_TYPE_HPET:

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