Linux kernel mirror (for testing)
git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git
kernel
os
linux
Merge branch 'nte-stmmac-visconti-cleanups'
Russell King says:
====================
net: stmmac: visconti: cleanups
A short series of cleanups to the visconti dwmac glue.
====================
Link: https://patch.msgid.link/aFCHJWXSLbUoogi6@shell.armlinux.org.uk
Signed-off-by: Jakub Kicinski <kuba@kernel.org>
+72
-53
+72
-53
drivers/net/ethernet/stmicro/stmmac/dwmac-visconti.c
+72
-53
drivers/net/ethernet/stmicro/stmmac/dwmac-visconti.c
···
48
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struct visconti_eth {
50
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void __iomem *reg;
51
-
u32 phy_intf_sel;
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struct clk *phy_ref_clk;
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struct device *dev;
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};
···
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phy_interface_t interface, int speed)
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{
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struct visconti_eth *dwmac = bsp_priv;
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-
struct net_device *netdev = dev_get_drvdata(dwmac->dev);
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-
unsigned int val, clk_sel_val = 0;
60
+
unsigned long clk_sel, val;
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62
-
switch (speed) {
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-
case SPEED_1000:
64
-
if (dwmac->phy_intf_sel == ETHER_CONFIG_INTF_RGMII)
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-
clk_sel_val = ETHER_CLK_SEL_FREQ_SEL_125M;
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-
break;
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-
case SPEED_100:
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-
if (dwmac->phy_intf_sel == ETHER_CONFIG_INTF_RGMII)
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-
clk_sel_val = ETHER_CLK_SEL_FREQ_SEL_25M;
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-
if (dwmac->phy_intf_sel == ETHER_CONFIG_INTF_RMII)
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-
clk_sel_val = ETHER_CLK_SEL_DIV_SEL_2;
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-
break;
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-
case SPEED_10:
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-
if (dwmac->phy_intf_sel == ETHER_CONFIG_INTF_RGMII)
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-
clk_sel_val = ETHER_CLK_SEL_FREQ_SEL_2P5M;
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-
if (dwmac->phy_intf_sel == ETHER_CONFIG_INTF_RMII)
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-
clk_sel_val = ETHER_CLK_SEL_DIV_SEL_20;
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-
break;
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-
default:
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-
/* No bit control */
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-
netdev_err(netdev, "Unsupported speed request (%d)", speed);
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-
return -EINVAL;
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-
}
62
+
if (phy_interface_mode_is_rgmii(interface)) {
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+
switch (speed) {
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+
case SPEED_1000:
65
+
clk_sel = ETHER_CLK_SEL_FREQ_SEL_125M;
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+
break;
84
67
85
-
/* Stop internal clock */
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-
val = readl(dwmac->reg + REG_ETHER_CLOCK_SEL);
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-
val &= ~(ETHER_CLK_SEL_RMII_CLK_EN | ETHER_CLK_SEL_RX_TX_CLK_EN);
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-
val |= ETHER_CLK_SEL_TX_O_E_N_IN;
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-
writel(val, dwmac->reg + REG_ETHER_CLOCK_SEL);
68
+
case SPEED_100:
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+
clk_sel = ETHER_CLK_SEL_FREQ_SEL_25M;
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+
break;
90
71
91
-
/* Set Clock-Mux, Start clock, Set TX_O direction */
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-
switch (dwmac->phy_intf_sel) {
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-
case ETHER_CONFIG_INTF_RGMII:
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-
val = clk_sel_val | ETHER_CLK_SEL_RX_CLK_EXT_SEL_RXC;
72
+
case SPEED_10:
73
+
clk_sel = ETHER_CLK_SEL_FREQ_SEL_2P5M;
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+
break;
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+
76
+
default:
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+
return -EINVAL;
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+
}
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+
80
+
/* Stop internal clock */
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+
val = readl(dwmac->reg + REG_ETHER_CLOCK_SEL);
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+
val &= ~(ETHER_CLK_SEL_RMII_CLK_EN |
83
+
ETHER_CLK_SEL_RX_TX_CLK_EN);
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+
val |= ETHER_CLK_SEL_TX_O_E_N_IN;
85
+
writel(val, dwmac->reg + REG_ETHER_CLOCK_SEL);
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+
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+
/* Set Clock-Mux, Start clock, Set TX_O direction */
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+
val = clk_sel | ETHER_CLK_SEL_RX_CLK_EXT_SEL_RXC;
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writel(val, dwmac->reg + REG_ETHER_CLOCK_SEL);
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val |= ETHER_CLK_SEL_RX_TX_CLK_EN;
···
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val &= ~ETHER_CLK_SEL_TX_O_E_N_IN;
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writel(val, dwmac->reg + REG_ETHER_CLOCK_SEL);
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-
break;
96
-
case ETHER_CONFIG_INTF_RMII:
97
-
val = clk_sel_val | ETHER_CLK_SEL_RX_CLK_EXT_SEL_DIV |
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-
ETHER_CLK_SEL_TX_CLK_EXT_SEL_DIV | ETHER_CLK_SEL_TX_O_E_N_IN |
99
-
ETHER_CLK_SEL_RMII_CLK_SEL_RX_C;
103
+
} else if (interface == PHY_INTERFACE_MODE_RMII) {
104
+
switch (speed) {
105
+
case SPEED_100:
106
+
clk_sel = ETHER_CLK_SEL_DIV_SEL_2;
107
+
break;
108
+
109
+
case SPEED_10:
110
+
clk_sel = ETHER_CLK_SEL_DIV_SEL_20;
111
+
break;
112
+
113
+
default:
114
+
return -EINVAL;
115
+
}
116
+
117
+
/* Stop internal clock */
118
+
val = readl(dwmac->reg + REG_ETHER_CLOCK_SEL);
119
+
val &= ~(ETHER_CLK_SEL_RMII_CLK_EN |
120
+
ETHER_CLK_SEL_RX_TX_CLK_EN);
121
+
val |= ETHER_CLK_SEL_TX_O_E_N_IN;
122
+
writel(val, dwmac->reg + REG_ETHER_CLOCK_SEL);
123
+
124
+
/* Set Clock-Mux, Start clock, Set TX_O direction */
125
+
val = clk_sel | ETHER_CLK_SEL_RX_CLK_EXT_SEL_DIV |
126
+
ETHER_CLK_SEL_TX_CLK_EXT_SEL_DIV |
127
+
ETHER_CLK_SEL_TX_O_E_N_IN |
128
+
ETHER_CLK_SEL_RMII_CLK_SEL_RX_C;
100
129
writel(val, dwmac->reg + REG_ETHER_CLOCK_SEL);
101
130
102
131
val |= ETHER_CLK_SEL_RMII_CLK_RST;
···
125
112
126
113
val |= ETHER_CLK_SEL_RMII_CLK_EN | ETHER_CLK_SEL_RX_TX_CLK_EN;
127
114
writel(val, dwmac->reg + REG_ETHER_CLOCK_SEL);
128
-
break;
129
-
case ETHER_CONFIG_INTF_MII:
130
-
default:
131
-
val = clk_sel_val | ETHER_CLK_SEL_RX_CLK_EXT_SEL_RXC |
132
-
ETHER_CLK_SEL_TX_CLK_EXT_SEL_TXC | ETHER_CLK_SEL_TX_O_E_N_IN;
115
+
} else {
116
+
/* Stop internal clock */
117
+
val = readl(dwmac->reg + REG_ETHER_CLOCK_SEL);
118
+
val &= ~(ETHER_CLK_SEL_RMII_CLK_EN |
119
+
ETHER_CLK_SEL_RX_TX_CLK_EN);
120
+
val |= ETHER_CLK_SEL_TX_O_E_N_IN;
121
+
writel(val, dwmac->reg + REG_ETHER_CLOCK_SEL);
122
+
123
+
/* Set Clock-Mux, Start clock, Set TX_O direction */
124
+
val = ETHER_CLK_SEL_RX_CLK_EXT_SEL_RXC |
125
+
ETHER_CLK_SEL_TX_CLK_EXT_SEL_TXC |
126
+
ETHER_CLK_SEL_TX_O_E_N_IN;
133
127
writel(val, dwmac->reg + REG_ETHER_CLOCK_SEL);
134
128
135
129
val |= ETHER_CLK_SEL_RX_TX_CLK_EN;
136
130
writel(val, dwmac->reg + REG_ETHER_CLOCK_SEL);
137
-
break;
138
131
}
139
132
140
133
return 0;
···
149
130
static int visconti_eth_init_hw(struct platform_device *pdev, struct plat_stmmacenet_data *plat_dat)
150
131
{
151
132
struct visconti_eth *dwmac = plat_dat->bsp_priv;
152
-
unsigned int reg_val, clk_sel_val;
133
+
unsigned int clk_sel_val;
134
+
u32 phy_intf_sel;
153
135
154
136
switch (plat_dat->phy_interface) {
155
137
case PHY_INTERFACE_MODE_RGMII:
156
138
case PHY_INTERFACE_MODE_RGMII_ID:
157
139
case PHY_INTERFACE_MODE_RGMII_RXID:
158
140
case PHY_INTERFACE_MODE_RGMII_TXID:
159
-
dwmac->phy_intf_sel = ETHER_CONFIG_INTF_RGMII;
141
+
phy_intf_sel = ETHER_CONFIG_INTF_RGMII;
160
142
break;
161
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case PHY_INTERFACE_MODE_MII:
162
-
dwmac->phy_intf_sel = ETHER_CONFIG_INTF_MII;
144
+
phy_intf_sel = ETHER_CONFIG_INTF_MII;
163
145
break;
164
146
case PHY_INTERFACE_MODE_RMII:
165
-
dwmac->phy_intf_sel = ETHER_CONFIG_INTF_RMII;
147
+
phy_intf_sel = ETHER_CONFIG_INTF_RMII;
166
148
break;
167
149
default:
168
150
dev_err(&pdev->dev, "Unsupported phy-mode (%d)\n", plat_dat->phy_interface);
169
151
return -EOPNOTSUPP;
170
152
}
171
153
172
-
reg_val = dwmac->phy_intf_sel;
173
-
writel(reg_val, dwmac->reg + REG_ETHER_CONTROL);
154
+
writel(phy_intf_sel, dwmac->reg + REG_ETHER_CONTROL);
174
155
175
156
/* Enable TX/RX clock */
176
157
clk_sel_val = ETHER_CLK_SEL_FREQ_SEL_125M;
···
180
161
dwmac->reg + REG_ETHER_CLOCK_SEL);
181
162
182
163
/* release internal-reset */
183
-
reg_val |= ETHER_ETH_CONTROL_RESET;
184
-
writel(reg_val, dwmac->reg + REG_ETHER_CONTROL);
164
+
phy_intf_sel |= ETHER_ETH_CONTROL_RESET;
165
+
writel(phy_intf_sel, dwmac->reg + REG_ETHER_CONTROL);
185
166
186
167
return 0;
187
168
}