drm/msm/dpu: Filter modes based on adjusted mode clock

Filter out modes that have a clock rate greater than the max core clock
rate when adjusted for the perf clock factor

This is especially important for chipsets such as QCS615 that have lower
limits for the MDP max core clock.

Since the core CRTC clock is at least the mode clock (adjusted for the
perf clock factor) [1], the modes supported by the driver should be less
than the max core clock rate.

[1] https://elixir.bootlin.com/linux/v6.12.4/source/drivers/gpu/drm/msm/disp/dpu1/dpu_core_perf.c#L83

Reviewed-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
Signed-off-by: Jessica Zhang <jessica.zhang@oss.qualcomm.com>
Patchwork: https://patchwork.freedesktop.org/patch/652041/
Link: https://lore.kernel.org/r/20250506-filter-modes-v2-1-c20a0b7aa241@oss.qualcomm.com
Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@oss.qualcomm.com>

authored by

Jessica Zhang and committed by

Dmitry Baryshkov 8 months ago 62b7d683 12c3c6c4

+39 -11

3 changed files

expand all

drivers

gpu

drm

msm

disp

dpu1

dpu_core_perf.c

dpu_core_perf.h

dpu_crtc.c

+24 -11

drivers/gpu/drm/msm/disp/dpu1/dpu_core_perf.c

··· 32 32 }; 33 33 34 34 /** 35 + * dpu_core_perf_adjusted_mode_clk - Adjust given mode clock rate according to 36 + * the perf clock factor. 37 + * @crtc_clk_rate - Unadjusted mode clock rate 38 + * @perf_cfg: performance configuration 39 + */ 40 + u64 dpu_core_perf_adjusted_mode_clk(u64 mode_clk_rate, 41 + const struct dpu_perf_cfg *perf_cfg) 42 + { 43 + u32 clk_factor; 44 + 45 + clk_factor = perf_cfg->clk_inefficiency_factor; 46 + if (clk_factor) { 47 + mode_clk_rate *= clk_factor; 48 + do_div(mode_clk_rate, 100); 49 + } 50 + 51 + return mode_clk_rate; 52 + } 53 + 54 + /** 35 55 * _dpu_core_perf_calc_bw() - to calculate BW per crtc 36 56 * @perf_cfg: performance configuration 37 57 * @crtc: pointer to a crtc ··· 95 75 struct drm_plane *plane; 96 76 struct dpu_plane_state *pstate; 97 77 struct drm_display_mode *mode; 98 - u64 crtc_clk; 99 - u32 clk_factor; 78 + u64 mode_clk; 100 79 101 80 mode = &state->adjusted_mode; 102 81 103 - crtc_clk = (u64)mode->vtotal * mode->hdisplay * drm_mode_vrefresh(mode); 82 + mode_clk = (u64)mode->vtotal * mode->hdisplay * drm_mode_vrefresh(mode); 104 83 105 84 drm_atomic_crtc_for_each_plane(plane, crtc) { 106 85 pstate = to_dpu_plane_state(plane->state); 107 86 if (!pstate) 108 87 continue; 109 88 110 - crtc_clk = max(pstate->plane_clk, crtc_clk); 89 + mode_clk = max(pstate->plane_clk, mode_clk); 111 90 } 112 91 113 - clk_factor = perf_cfg->clk_inefficiency_factor; 114 - if (clk_factor) { 115 - crtc_clk *= clk_factor; 116 - do_div(crtc_clk, 100); 117 - } 118 - 119 - return crtc_clk; 92 + return dpu_core_perf_adjusted_mode_clk(mode_clk, perf_cfg); 120 93 } 121 94 122 95 static struct dpu_kms *_dpu_crtc_get_kms(struct drm_crtc *crtc)

drivers/gpu/drm/msm/disp/dpu1/dpu_core_perf.h

··· 54 54 u32 fix_core_ab_vote; 55 55 }; 56 56 57 + u64 dpu_core_perf_adjusted_mode_clk(u64 clk_rate, 58 + const struct dpu_perf_cfg *perf_cfg); 59 + 57 60 int dpu_core_perf_crtc_check(struct drm_crtc *crtc, 58 61 struct drm_crtc_state *state); 59 62

+12

drivers/gpu/drm/msm/disp/dpu1/dpu_crtc.c

··· 1534 1534 const struct drm_display_mode *mode) 1535 1535 { 1536 1536 struct dpu_kms *dpu_kms = _dpu_crtc_get_kms(crtc); 1537 + u64 adjusted_mode_clk; 1537 1538 1538 1539 /* if there is no 3d_mux block we cannot merge LMs so we cannot 1539 1540 * split the large layer into 2 LMs, filter out such modes ··· 1542 1541 if (!dpu_kms->catalog->caps->has_3d_merge && 1543 1542 mode->hdisplay > dpu_kms->catalog->caps->max_mixer_width) 1544 1543 return MODE_BAD_HVALUE; 1544 + 1545 + adjusted_mode_clk = dpu_core_perf_adjusted_mode_clk(mode->clock, 1546 + dpu_kms->perf.perf_cfg); 1547 + 1548 + /* 1549 + * The given mode, adjusted for the perf clock factor, should not exceed 1550 + * the max core clock rate 1551 + */ 1552 + if (dpu_kms->perf.max_core_clk_rate < adjusted_mode_clk * 1000) 1553 + return MODE_CLOCK_HIGH; 1554 + 1545 1555 /* 1546 1556 * max crtc width is equal to the max mixer width * 2 and max height is 4K 1547 1557 */

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