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dt-bindings: phy: ti,phy-usb3: convert to DT schema
Convert TI PIPE3 PHY binding to DT schema.
Changes during conversion:
- Define a new pattern 'pcie-phy' to match nodes defined in DT.
- Drop obsolete "id" property from the schema.
Signed-off-by: Charan Pedumuru <charan.pedumuru@gmail.com>
Reviewed-by: Rob Herring (Arm) <robh@kernel.org>
Link: https://patch.msgid.link/20260123-ti-phy-v4-2-b557e2c46e6f@gmail.com
Signed-off-by: Vinod Koul <vkoul@kernel.org>
authored by
Charan Pedumuru
and committed by
Vinod Koul
62c9ff8f
eeca25fe
+138
+138
Documentation/devicetree/bindings/phy/ti,phy-usb3.yaml
+138
Documentation/devicetree/bindings/phy/ti,phy-usb3.yaml
···
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# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
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%YAML 1.2
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---
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$id: http://devicetree.org/schemas/phy/ti,phy-usb3.yaml#
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$schema: http://devicetree.org/meta-schemas/core.yaml#
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title: TI PIPE3 PHY Module
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maintainers:
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- Roger Quadros <rogerq@ti.com>
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description:
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The TI PIPE3 PHY is a high-speed SerDes (Serializer/Deserializer)
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transceiver integrated in OMAP5, DRA7xx/AM57xx, and similar SoCs.
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It supports multiple protocols (USB3, SATA, PCIe) using the PIPE3
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interface standard, which defines a common physical layer for
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high-speed serial interfaces.
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properties:
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$nodename:
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pattern: "^(pcie-phy|usb3-phy|phy)@[0-9a-f]+$"
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compatible:
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enum:
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- ti,omap-usb3
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- ti,phy-pipe3-pcie
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- ti,phy-pipe3-sata
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- ti,phy-usb3
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reg:
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minItems: 2
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maxItems: 3
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reg-names:
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minItems: 2
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items:
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- const: phy_rx
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- const: phy_tx
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- const: pll_ctrl
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"#phy-cells":
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const: 0
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clocks:
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minItems: 2
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maxItems: 7
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clock-names:
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minItems: 2
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maxItems: 7
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items:
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enum: [wkupclk, sysclk, refclk, dpll_ref,
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dpll_ref_m2, phy-div, div-clk]
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syscon-phy-power:
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$ref: /schemas/types.yaml#/definitions/phandle-array
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maxItems: 1
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items:
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items:
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- description: Phandle to the system control module
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- description: Register offset controlling PHY power
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syscon-pllreset:
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$ref: /schemas/types.yaml#/definitions/phandle-array
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maxItems: 1
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items:
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items:
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- description: Phandle to the system control module
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- description: Register offset of CTRL_CORE_SMA_SW_0
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syscon-pcs:
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$ref: /schemas/types.yaml#/definitions/phandle-array
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maxItems: 1
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items:
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items:
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- description: Phandle to the system control module
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- description: Register offset for PCS delay programming
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ctrl-module:
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$ref: /schemas/types.yaml#/definitions/phandle
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description:
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Phandle of control module for PHY power on.
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deprecated: true
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allOf:
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- if:
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properties:
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compatible:
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contains:
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const: ti,phy-pipe3-sata
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then:
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properties:
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syscon-pllreset: true
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else:
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properties:
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syscon-pllreset: false
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required:
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- reg
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- compatible
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- reg-names
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- "#phy-cells"
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- clocks
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- clock-names
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unevaluatedProperties: false
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examples:
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- |
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/* TI PIPE3 USB3 PHY */
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usb3-phy@4a084400 {
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compatible = "ti,phy-usb3";
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reg = <0x4a084400 0x80>,
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<0x4a084800 0x64>,
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<0x4a084c00 0x40>;
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reg-names = "phy_rx", "phy_tx", "pll_ctrl";
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#phy-cells = <0>;
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clocks = <&usb_phy_cm_clk32k>,
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<&sys_clkin>,
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<&usb_otg_ss_refclk960m>;
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clock-names = "wkupclk", "sysclk", "refclk";
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ctrl-module = <&omap_control_usb>;
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};
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- |
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/* TI PIPE3 SATA PHY */
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phy@4a096000 {
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compatible = "ti,phy-pipe3-sata";
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reg = <0x4a096000 0x80>, /* phy_rx */
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<0x4a096400 0x64>, /* phy_tx */
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<0x4a096800 0x40>; /* pll_ctrl */
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reg-names = "phy_rx", "phy_tx", "pll_ctrl";
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clocks = <&sys_clkin1>, <&sata_ref_clk>;
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clock-names = "sysclk", "refclk";
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syscon-pllreset = <&scm_conf 0x3fc>;
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#phy-cells = <0>;
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};
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...