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drm/amd/pp: Use gfx rlc funcs directly in powerplay

In order to remove cgs interfaces:
cgs_enter_safe_mode
cgs_lock_grbm_idx

Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
Acked-by: Christian König <christian.koenig@amd.com>
Signed-off-by: Rex Zhu <Rex.Zhu@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>

authored by

Rex Zhu and committed by
Alex Deucher 62fd5127 986567e4

+46 -38
+7 -6
drivers/gpu/drm/amd/powerplay/hwmgr/smu7_powertune.c
··· 740 740 PP_CAP(PHM_PlatformCaps_TDRamping) || 741 741 PP_CAP(PHM_PlatformCaps_TCPRamping)) { 742 742 743 - cgs_enter_safe_mode(hwmgr->device, true); 744 - cgs_lock_grbm_idx(hwmgr->device, true); 743 + adev->gfx.rlc.funcs->enter_safe_mode(adev); 744 + mutex_lock(&adev->grbm_idx_mutex); 745 745 value = 0; 746 746 value2 = cgs_read_register(hwmgr->device, mmGRBM_GFX_INDEX); 747 747 for (count = 0; count < num_se; count++) { ··· 781 781 PP_ASSERT_WITH_CODE((0 == result), 782 782 "Failed to enable DPM DIDT.", return result); 783 783 } 784 - cgs_lock_grbm_idx(hwmgr->device, false); 785 - cgs_enter_safe_mode(hwmgr->device, false); 784 + mutex_unlock(&adev->grbm_idx_mutex); 785 + adev->gfx.rlc.funcs->exit_safe_mode(adev); 786 786 } 787 787 788 788 return 0; ··· 791 791 int smu7_disable_didt_config(struct pp_hwmgr *hwmgr) 792 792 { 793 793 int result; 794 + struct amdgpu_device *adev = hwmgr->adev; 794 795 795 796 if (PP_CAP(PHM_PlatformCaps_SQRamping) || 796 797 PP_CAP(PHM_PlatformCaps_DBRamping) || 797 798 PP_CAP(PHM_PlatformCaps_TDRamping) || 798 799 PP_CAP(PHM_PlatformCaps_TCPRamping)) { 799 800 800 - cgs_enter_safe_mode(hwmgr->device, true); 801 + adev->gfx.rlc.funcs->enter_safe_mode(adev); 801 802 802 803 result = smu7_enable_didt(hwmgr, false); 803 804 PP_ASSERT_WITH_CODE((result == 0), ··· 810 809 PP_ASSERT_WITH_CODE((0 == result), 811 810 "Failed to disable DPM DIDT.", return result); 812 811 } 813 - cgs_enter_safe_mode(hwmgr->device, false); 812 + adev->gfx.rlc.funcs->exit_safe_mode(adev); 814 813 } 815 814 816 815 return 0;
+39 -32
drivers/gpu/drm/amd/powerplay/hwmgr/vega10_powertune.c
··· 930 930 931 931 static int vega10_enable_cac_driving_se_didt_config(struct pp_hwmgr *hwmgr) 932 932 { 933 + struct amdgpu_device *adev = hwmgr->adev; 933 934 int result; 934 935 uint32_t num_se = 0, count, data; 935 - struct amdgpu_device *adev = hwmgr->adev; 936 936 uint32_t reg; 937 937 938 938 num_se = adev->gfx.config.max_shader_engines; 939 939 940 - cgs_enter_safe_mode(hwmgr->device, true); 940 + adev->gfx.rlc.funcs->enter_safe_mode(adev); 941 941 942 - cgs_lock_grbm_idx(hwmgr->device, true); 942 + mutex_lock(&adev->grbm_idx_mutex); 943 943 reg = soc15_get_register_offset(GC_HWID, 0, mmGRBM_GFX_INDEX_BASE_IDX, mmGRBM_GFX_INDEX); 944 944 for (count = 0; count < num_se; count++) { 945 945 data = GRBM_GFX_INDEX__INSTANCE_BROADCAST_WRITES_MASK | GRBM_GFX_INDEX__SH_BROADCAST_WRITES_MASK | ( count << GRBM_GFX_INDEX__SE_INDEX__SHIFT); ··· 959 959 break; 960 960 } 961 961 cgs_write_register(hwmgr->device, reg, 0xE0000000); 962 - cgs_lock_grbm_idx(hwmgr->device, false); 962 + mutex_unlock(&adev->grbm_idx_mutex); 963 963 964 964 vega10_didt_set_mask(hwmgr, true); 965 965 966 - cgs_enter_safe_mode(hwmgr->device, false); 966 + adev->gfx.rlc.funcs->exit_safe_mode(adev); 967 967 968 968 return 0; 969 969 } 970 970 971 971 static int vega10_disable_cac_driving_se_didt_config(struct pp_hwmgr *hwmgr) 972 972 { 973 - cgs_enter_safe_mode(hwmgr->device, true); 973 + struct amdgpu_device *adev = hwmgr->adev; 974 + 975 + adev->gfx.rlc.funcs->enter_safe_mode(adev); 974 976 975 977 vega10_didt_set_mask(hwmgr, false); 976 978 977 - cgs_enter_safe_mode(hwmgr->device, false); 979 + adev->gfx.rlc.funcs->exit_safe_mode(adev); 978 980 979 981 return 0; 980 982 } 981 983 982 984 static int vega10_enable_psm_gc_didt_config(struct pp_hwmgr *hwmgr) 983 985 { 986 + struct amdgpu_device *adev = hwmgr->adev; 984 987 int result; 985 988 uint32_t num_se = 0, count, data; 986 - struct amdgpu_device *adev = hwmgr->adev; 987 989 uint32_t reg; 988 990 989 991 num_se = adev->gfx.config.max_shader_engines; 990 992 991 - cgs_enter_safe_mode(hwmgr->device, true); 993 + adev->gfx.rlc.funcs->enter_safe_mode(adev); 992 994 993 - cgs_lock_grbm_idx(hwmgr->device, true); 995 + mutex_lock(&adev->grbm_idx_mutex); 994 996 reg = soc15_get_register_offset(GC_HWID, 0, mmGRBM_GFX_INDEX_BASE_IDX, mmGRBM_GFX_INDEX); 995 997 for (count = 0; count < num_se; count++) { 996 998 data = GRBM_GFX_INDEX__INSTANCE_BROADCAST_WRITES_MASK | GRBM_GFX_INDEX__SH_BROADCAST_WRITES_MASK | ( count << GRBM_GFX_INDEX__SE_INDEX__SHIFT); ··· 1006 1004 break; 1007 1005 } 1008 1006 cgs_write_register(hwmgr->device, reg, 0xE0000000); 1009 - cgs_lock_grbm_idx(hwmgr->device, false); 1007 + mutex_unlock(&adev->grbm_idx_mutex); 1010 1008 1011 1009 vega10_didt_set_mask(hwmgr, true); 1012 1010 1013 - cgs_enter_safe_mode(hwmgr->device, false); 1011 + adev->gfx.rlc.funcs->exit_safe_mode(adev); 1014 1012 1015 1013 vega10_program_gc_didt_config_registers(hwmgr, GCDiDtDroopCtrlConfig_vega10); 1016 1014 if (PP_CAP(PHM_PlatformCaps_GCEDC)) ··· 1024 1022 1025 1023 static int vega10_disable_psm_gc_didt_config(struct pp_hwmgr *hwmgr) 1026 1024 { 1025 + struct amdgpu_device *adev = hwmgr->adev; 1027 1026 uint32_t data; 1028 1027 1029 - cgs_enter_safe_mode(hwmgr->device, true); 1028 + adev->gfx.rlc.funcs->enter_safe_mode(adev); 1030 1029 1031 1030 vega10_didt_set_mask(hwmgr, false); 1032 1031 1033 - cgs_enter_safe_mode(hwmgr->device, false); 1032 + adev->gfx.rlc.funcs->exit_safe_mode(adev); 1034 1033 1035 1034 if (PP_CAP(PHM_PlatformCaps_GCEDC)) { 1036 1035 data = 0x00000000; ··· 1046 1043 1047 1044 static int vega10_enable_se_edc_config(struct pp_hwmgr *hwmgr) 1048 1045 { 1046 + struct amdgpu_device *adev = hwmgr->adev; 1049 1047 int result; 1050 1048 uint32_t num_se = 0, count, data; 1051 - struct amdgpu_device *adev = hwmgr->adev; 1052 1049 uint32_t reg; 1053 1050 1054 1051 num_se = adev->gfx.config.max_shader_engines; 1055 1052 1056 - cgs_enter_safe_mode(hwmgr->device, true); 1053 + adev->gfx.rlc.funcs->enter_safe_mode(adev); 1057 1054 1058 - cgs_lock_grbm_idx(hwmgr->device, true); 1055 + mutex_lock(&adev->grbm_idx_mutex); 1059 1056 reg = soc15_get_register_offset(GC_HWID, 0, mmGRBM_GFX_INDEX_BASE_IDX, mmGRBM_GFX_INDEX); 1060 1057 for (count = 0; count < num_se; count++) { 1061 1058 data = GRBM_GFX_INDEX__INSTANCE_BROADCAST_WRITES_MASK | GRBM_GFX_INDEX__SH_BROADCAST_WRITES_MASK | ( count << GRBM_GFX_INDEX__SE_INDEX__SHIFT); ··· 1071 1068 break; 1072 1069 } 1073 1070 cgs_write_register(hwmgr->device, reg, 0xE0000000); 1074 - cgs_lock_grbm_idx(hwmgr->device, false); 1071 + mutex_unlock(&adev->grbm_idx_mutex); 1075 1072 1076 1073 vega10_didt_set_mask(hwmgr, true); 1077 1074 1078 - cgs_enter_safe_mode(hwmgr->device, false); 1075 + adev->gfx.rlc.funcs->exit_safe_mode(adev); 1079 1076 1080 1077 return 0; 1081 1078 } 1082 1079 1083 1080 static int vega10_disable_se_edc_config(struct pp_hwmgr *hwmgr) 1084 1081 { 1085 - cgs_enter_safe_mode(hwmgr->device, true); 1082 + struct amdgpu_device *adev = hwmgr->adev; 1083 + 1084 + adev->gfx.rlc.funcs->enter_safe_mode(adev); 1086 1085 1087 1086 vega10_didt_set_mask(hwmgr, false); 1088 1087 1089 - cgs_enter_safe_mode(hwmgr->device, false); 1088 + adev->gfx.rlc.funcs->exit_safe_mode(adev); 1090 1089 1091 1090 return 0; 1092 1091 } 1093 1092 1094 1093 static int vega10_enable_psm_gc_edc_config(struct pp_hwmgr *hwmgr) 1095 1094 { 1095 + struct amdgpu_device *adev = hwmgr->adev; 1096 1096 int result; 1097 1097 uint32_t num_se = 0; 1098 1098 uint32_t count, data; 1099 - struct amdgpu_device *adev = hwmgr->adev; 1100 1099 uint32_t reg; 1101 1100 1102 1101 num_se = adev->gfx.config.max_shader_engines; 1103 1102 1104 - cgs_enter_safe_mode(hwmgr->device, true); 1103 + adev->gfx.rlc.funcs->enter_safe_mode(adev); 1105 1104 1106 1105 vega10_program_gc_didt_config_registers(hwmgr, AvfsPSMResetConfig_vega10); 1107 1106 1108 - cgs_lock_grbm_idx(hwmgr->device, true); 1107 + mutex_lock(&adev->grbm_idx_mutex); 1109 1108 reg = soc15_get_register_offset(GC_HWID, 0, mmGRBM_GFX_INDEX_BASE_IDX, mmGRBM_GFX_INDEX); 1110 1109 for (count = 0; count < num_se; count++) { 1111 1110 data = GRBM_GFX_INDEX__INSTANCE_BROADCAST_WRITES_MASK | GRBM_GFX_INDEX__SH_BROADCAST_WRITES_MASK | ( count << GRBM_GFX_INDEX__SE_INDEX__SHIFT); ··· 1121 1116 break; 1122 1117 } 1123 1118 cgs_write_register(hwmgr->device, reg, 0xE0000000); 1124 - cgs_lock_grbm_idx(hwmgr->device, false); 1119 + mutex_unlock(&adev->grbm_idx_mutex); 1125 1120 1126 1121 vega10_didt_set_mask(hwmgr, true); 1127 1122 1128 - cgs_enter_safe_mode(hwmgr->device, false); 1123 + adev->gfx.rlc.funcs->exit_safe_mode(adev); 1129 1124 1130 1125 vega10_program_gc_didt_config_registers(hwmgr, PSMGCEDCDroopCtrlConfig_vega10); 1131 1126 ··· 1142 1137 1143 1138 static int vega10_disable_psm_gc_edc_config(struct pp_hwmgr *hwmgr) 1144 1139 { 1140 + struct amdgpu_device *adev = hwmgr->adev; 1145 1141 uint32_t data; 1146 1142 1147 - cgs_enter_safe_mode(hwmgr->device, true); 1143 + adev->gfx.rlc.funcs->enter_safe_mode(adev); 1148 1144 1149 1145 vega10_didt_set_mask(hwmgr, false); 1150 1146 1151 - cgs_enter_safe_mode(hwmgr->device, false); 1147 + adev->gfx.rlc.funcs->exit_safe_mode(adev); 1152 1148 1153 1149 if (PP_CAP(PHM_PlatformCaps_GCEDC)) { 1154 1150 data = 0x00000000; ··· 1164 1158 1165 1159 static int vega10_enable_se_edc_force_stall_config(struct pp_hwmgr *hwmgr) 1166 1160 { 1161 + struct amdgpu_device *adev = hwmgr->adev; 1167 1162 uint32_t reg; 1168 1163 int result; 1169 1164 1170 - cgs_enter_safe_mode(hwmgr->device, true); 1165 + adev->gfx.rlc.funcs->enter_safe_mode(adev); 1171 1166 1172 - cgs_lock_grbm_idx(hwmgr->device, true); 1167 + mutex_lock(&adev->grbm_idx_mutex); 1173 1168 reg = soc15_get_register_offset(GC_HWID, 0, mmGRBM_GFX_INDEX_BASE_IDX, mmGRBM_GFX_INDEX); 1174 1169 cgs_write_register(hwmgr->device, reg, 0xE0000000); 1175 - cgs_lock_grbm_idx(hwmgr->device, false); 1170 + mutex_unlock(&adev->grbm_idx_mutex); 1176 1171 1177 1172 result = vega10_program_didt_config_registers(hwmgr, SEEDCForceStallPatternConfig_Vega10, VEGA10_CONFIGREG_DIDT); 1178 1173 result |= vega10_program_didt_config_registers(hwmgr, SEEDCCtrlForceStallConfig_Vega10, VEGA10_CONFIGREG_DIDT); ··· 1182 1175 1183 1176 vega10_didt_set_mask(hwmgr, false); 1184 1177 1185 - cgs_enter_safe_mode(hwmgr->device, false); 1178 + adev->gfx.rlc.funcs->exit_safe_mode(adev); 1186 1179 1187 1180 return 0; 1188 1181 }