Merge tag 'pinctrl-v6.1-5' of git://git.kernel.org/pub/scm/linux/kernel/git/linusw/linux-pinctrl

Pull pin control fixes from Linus Walleij:
"Three driver fixes. The Intel fix looks like the most important.

- Fix a potential divide by zero in pinctrl-singe (OMAP and
HiSilicon)

- Disable IRQs on startup in the Mediatek driver. This is a classic,
we should be looking out for this more.

- Save and restore pins in 'direct IRQ' mode in the Intel driver,
this works around firmware bugs"

* tag 'pinctrl-v6.1-5' of git://git.kernel.org/pub/scm/linux/kernel/git/linusw/linux-pinctrl:
pinctrl: intel: Save and restore pins in "direct IRQ" mode
pinctrl: meditatek: Startup with the IRQs disabled
pinctrl: single: Fix potential division by zero

Linus Torvalds 3 years ago 63050a5c 0e15c3c7

+33 -5

3 changed files

expand all

drivers

pinctrl

intel

pinctrl-intel.c

mediatek

mtk-eint.c

pinctrl-single.c

+26 -1

drivers/pinctrl/intel/pinctrl-intel.c

··· 436 436 writel(value, padcfg0); 437 437 } 438 438 439 + static int __intel_gpio_get_gpio_mode(u32 value) 440 + { 441 + return (value & PADCFG0_PMODE_MASK) >> PADCFG0_PMODE_SHIFT; 442 + } 443 + 439 444 static int intel_gpio_get_gpio_mode(void __iomem *padcfg0) 440 445 { 441 - return (readl(padcfg0) & PADCFG0_PMODE_MASK) >> PADCFG0_PMODE_SHIFT; 446 + return __intel_gpio_get_gpio_mode(readl(padcfg0)); 442 447 } 443 448 444 449 static void intel_gpio_set_gpio_mode(void __iomem *padcfg0) ··· 1679 1674 static bool intel_pinctrl_should_save(struct intel_pinctrl *pctrl, unsigned int pin) 1680 1675 { 1681 1676 const struct pin_desc *pd = pin_desc_get(pctrl->pctldev, pin); 1677 + u32 value; 1682 1678 1683 1679 if (!pd || !intel_pad_usable(pctrl, pin)) 1684 1680 return false; ··· 1692 1686 */ 1693 1687 if (pd->mux_owner || pd->gpio_owner || 1694 1688 gpiochip_line_is_irq(&pctrl->chip, intel_pin_to_gpio(pctrl, pin))) 1689 + return true; 1690 + 1691 + /* 1692 + * The firmware on some systems may configure GPIO pins to be 1693 + * an interrupt source in so called "direct IRQ" mode. In such 1694 + * cases the GPIO controller driver has no idea if those pins 1695 + * are being used or not. At the same time, there is a known bug 1696 + * in the firmwares that don't restore the pin settings correctly 1697 + * after suspend, i.e. by an unknown reason the Rx value becomes 1698 + * inverted. 1699 + * 1700 + * Hence, let's save and restore the pins that are configured 1701 + * as GPIOs in the input mode with GPIROUTIOXAPIC bit set. 1702 + * 1703 + * See https://bugzilla.kernel.org/show_bug.cgi?id=214749. 1704 + */ 1705 + value = readl(intel_get_padcfg(pctrl, pin, PADCFG0)); 1706 + if ((value & PADCFG0_GPIROUTIOXAPIC) && (value & PADCFG0_GPIOTXDIS) && 1707 + (__intel_gpio_get_gpio_mode(value) == PADCFG0_PMODE_GPIO)) 1695 1708 return true; 1696 1709 1697 1710 return false;

+6 -3

drivers/pinctrl/mediatek/mtk-eint.c

··· 303 303 304 304 static unsigned int mtk_eint_hw_init(struct mtk_eint *eint) 305 305 { 306 - void __iomem *reg = eint->base + eint->regs->dom_en; 306 + void __iomem *dom_en = eint->base + eint->regs->dom_en; 307 + void __iomem *mask_set = eint->base + eint->regs->mask_set; 307 308 unsigned int i; 308 309 309 310 for (i = 0; i < eint->hw->ap_num; i += 32) { 310 - writel(0xffffffff, reg); 311 - reg += 4; 311 + writel(0xffffffff, dom_en); 312 + writel(0xffffffff, mask_set); 313 + dom_en += 4; 314 + mask_set += 4; 312 315 } 313 316 314 317 return 0;

+1 -1

drivers/pinctrl/pinctrl-single.c

··· 727 727 728 728 mux_bytes = pcs->width / BITS_PER_BYTE; 729 729 730 - if (pcs->bits_per_mux) { 730 + if (pcs->bits_per_mux && pcs->fmask) { 731 731 pcs->bits_per_pin = fls(pcs->fmask); 732 732 nr_pins = (pcs->size * BITS_PER_BYTE) / pcs->bits_per_pin; 733 733 } else {

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