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Merge tag 'arm-fixes-5.8-2' of git://git.kernel.org/pub/scm/linux/kernel/git/soc/soc into master

Pull ARM SoC fixes from Arnd Bergmann:
"This time there are a number of actual code fixes, plus a small set of
device tree issues getting addressed:

Renesas:

- one defconfig cleanup to allow a later Kconfig change

Intel socfpga:

- enable QSPI devices on some machines

- fix DTC validation warnings

TI OMAP:

- Two DEBUG_ATOMIC_SLEEP fixes for ti-sysc interconnect target
module driver

- A regression fix for ti-sysc no-idle handling that caused issues
compared to earlier platform data based booting

- A fix for memory leak for omap_hwmod_allocate_module

- Fix d_can driver probe for am437x

NXP i.MX:

- A couple of fixes on i.MX platform device registration code to
stop the use of invalid IRQ 0.

- Fix a regression seen on ls1021a platform, caused by commit
52102a3ba6a61 ("soc: imx: move cpu code to drivers/soc/imx").

- Fix a misconfiguration of audio SSI on imx6qdl-gw551x board.

Amlogic Meson:

- misc DT fixes

- SoC ID fixes to detect all chips correctly"

* tag 'arm-fixes-5.8-2' of git://git.kernel.org/pub/scm/linux/kernel/git/soc/soc:
arm64: dts: spcfpga: Align GIC, NAND and UART nodenames with dtschema
ARM: dts: socfpga: Align L2 cache-controller nodename with dtschema
arm64: dts: stratix10: increase QSPI reg address in nand dts file
arm64: dts: stratix10: add status to qspi dts node
arm64: dts: agilex: add status to qspi dts node
ARM: dts: Fix dcan driver probe failed on am437x platform
ARM: OMAP2+: Fix possible memory leak in omap_hwmod_allocate_module
arm64: defconfig: Enable CONFIG_PCIE_RCAR_HOST
soc: imx: check ls1021a
ARM: imx: Remove imx_add_imx_dma() unused irq_err argument
ARM: imx: Provide correct number of resources when registering gpio devices
ARM: dts: imx6qdl-gw551x: fix audio SSI
bus: ti-sysc: Do not disable on suspend for no-idle
bus: ti-sysc: Fix sleeping function called from invalid context for RTC quirk
bus: ti-sysc: Fix wakeirq sleeping function called from invalid context
ARM: dts: meson: Align L2 cache-controller nodename with dtschema
arm64: dts: meson-gxl-s805x: reduce initial Mali450 core frequency
arm64: dts: meson: add missing gxl rng clock
soc: amlogic: meson-gx-socinfo: Fix S905X3 and S905D3 ID's

+94 -47
+10 -4
arch/arm/boot/dts/am437x-l4.dtsi
··· 1540 1540 reg = <0xcc020 0x4>; 1541 1541 reg-names = "rev"; 1542 1542 /* Domains (P, C): per_pwrdm, l4ls_clkdm */ 1543 - clocks = <&l4ls_clkctrl AM4_L4LS_D_CAN0_CLKCTRL 0>; 1544 - clock-names = "fck"; 1543 + clocks = <&l4ls_clkctrl AM4_L4LS_D_CAN0_CLKCTRL 0>, 1544 + <&dcan0_fck>; 1545 + clock-names = "fck", "osc"; 1545 1546 #address-cells = <1>; 1546 1547 #size-cells = <1>; 1547 1548 ranges = <0x0 0xcc000 0x2000>; ··· 1550 1549 dcan0: can@0 { 1551 1550 compatible = "ti,am4372-d_can", "ti,am3352-d_can"; 1552 1551 reg = <0x0 0x2000>; 1552 + clocks = <&dcan0_fck>; 1553 + clock-names = "fck"; 1553 1554 syscon-raminit = <&scm_conf 0x644 0>; 1554 1555 interrupts = <GIC_SPI 52 IRQ_TYPE_LEVEL_HIGH>; 1555 1556 status = "disabled"; ··· 1563 1560 reg = <0xd0020 0x4>; 1564 1561 reg-names = "rev"; 1565 1562 /* Domains (P, C): per_pwrdm, l4ls_clkdm */ 1566 - clocks = <&l4ls_clkctrl AM4_L4LS_D_CAN1_CLKCTRL 0>; 1567 - clock-names = "fck"; 1563 + clocks = <&l4ls_clkctrl AM4_L4LS_D_CAN1_CLKCTRL 0>, 1564 + <&dcan1_fck>; 1565 + clock-names = "fck", "osc"; 1568 1566 #address-cells = <1>; 1569 1567 #size-cells = <1>; 1570 1568 ranges = <0x0 0xd0000 0x2000>; ··· 1573 1569 dcan1: can@0 { 1574 1570 compatible = "ti,am4372-d_can", "ti,am3352-d_can"; 1575 1571 reg = <0x0 0x2000>; 1572 + clocks = <&dcan1_fck>; 1573 + clock-name = "fck"; 1576 1574 syscon-raminit = <&scm_conf 0x644 1>; 1577 1575 interrupts = <GIC_SPI 49 IRQ_TYPE_LEVEL_HIGH>; 1578 1576 status = "disabled";
+1 -1
arch/arm/boot/dts/imx6qdl-gw551x.dtsi
··· 110 110 simple-audio-card,frame-master = <&sound_codec>; 111 111 112 112 sound_cpu: simple-audio-card,cpu { 113 - sound-dai = <&ssi2>; 113 + sound-dai = <&ssi1>; 114 114 }; 115 115 116 116 sound_codec: simple-audio-card,codec {
+1 -1
arch/arm/boot/dts/meson.dtsi
··· 11 11 #size-cells = <1>; 12 12 interrupt-parent = <&gic>; 13 13 14 - L2: l2-cache-controller@c4200000 { 14 + L2: cache-controller@c4200000 { 15 15 compatible = "arm,pl310-cache"; 16 16 reg = <0xc4200000 0x1000>; 17 17 cache-unified;
+1 -1
arch/arm/boot/dts/socfpga.dtsi
··· 726 726 }; 727 727 }; 728 728 729 - L2: l2-cache@fffef000 { 729 + L2: cache-controller@fffef000 { 730 730 compatible = "arm,pl310-cache"; 731 731 reg = <0xfffef000 0x1000>; 732 732 interrupts = <0 38 0x04>;
+1 -1
arch/arm/boot/dts/socfpga_arria10.dtsi
··· 636 636 reg = <0xffcfb100 0x80>; 637 637 }; 638 638 639 - L2: l2-cache@fffff000 { 639 + L2: cache-controller@fffff000 { 640 640 compatible = "arm,pl310-cache"; 641 641 reg = <0xfffff000 0x1000>; 642 642 interrupts = <0 18 IRQ_TYPE_LEVEL_HIGH>;
+1 -1
arch/arm/mach-imx/devices/devices-common.h
··· 289 289 const struct spi_imx_master *pdata); 290 290 291 291 struct platform_device *imx_add_imx_dma(char *name, resource_size_t iobase, 292 - int irq, int irq_err); 292 + int irq); 293 293 struct platform_device *imx_add_imx_sdma(char *name, 294 294 resource_size_t iobase, int irq, struct sdma_platform_data *pdata);
+3 -2
arch/arm/mach-imx/devices/platform-gpio-mxc.c
··· 24 24 .flags = IORESOURCE_IRQ, 25 25 }, 26 26 }; 27 + unsigned int nres; 27 28 28 - return platform_device_register_resndata(&mxc_aips_bus, 29 - name, id, res, ARRAY_SIZE(res), NULL, 0); 29 + nres = irq_high ? ARRAY_SIZE(res) : ARRAY_SIZE(res) - 1; 30 + return platform_device_register_resndata(&mxc_aips_bus, name, id, res, nres, NULL, 0); 30 31 }
+1 -5
arch/arm/mach-imx/devices/platform-imx-dma.c
··· 6 6 #include "devices-common.h" 7 7 8 8 struct platform_device __init __maybe_unused *imx_add_imx_dma(char *name, 9 - resource_size_t iobase, int irq, int irq_err) 9 + resource_size_t iobase, int irq) 10 10 { 11 11 struct resource res[] = { 12 12 { ··· 16 16 }, { 17 17 .start = irq, 18 18 .end = irq, 19 - .flags = IORESOURCE_IRQ, 20 - }, { 21 - .start = irq_err, 22 - .end = irq_err, 23 19 .flags = IORESOURCE_IRQ, 24 20 }, 25 21 };
+1 -2
arch/arm/mach-imx/mm-imx21.c
··· 78 78 mxc_register_gpio("imx21-gpio", 5, MX21_GPIO6_BASE_ADDR, SZ_256, MX21_INT_GPIO, 0); 79 79 80 80 pinctrl_provide_dummies(); 81 - imx_add_imx_dma("imx21-dma", MX21_DMA_BASE_ADDR, 82 - MX21_INT_DMACH0, 0); /* No ERR irq */ 81 + imx_add_imx_dma("imx21-dma", MX21_DMA_BASE_ADDR, MX21_INT_DMACH0); 83 82 platform_device_register_simple("imx21-audmux", 0, imx21_audmux_res, 84 83 ARRAY_SIZE(imx21_audmux_res)); 85 84 }
+1 -2
arch/arm/mach-imx/mm-imx27.c
··· 79 79 mxc_register_gpio("imx21-gpio", 5, MX27_GPIO6_BASE_ADDR, SZ_256, MX27_INT_GPIO, 0); 80 80 81 81 pinctrl_provide_dummies(); 82 - imx_add_imx_dma("imx27-dma", MX27_DMA_BASE_ADDR, 83 - MX27_INT_DMACH0, 0); /* No ERR irq */ 82 + imx_add_imx_dma("imx27-dma", MX27_DMA_BASE_ADDR, MX27_INT_DMACH0); 84 83 /* imx27 has the imx21 type audmux */ 85 84 platform_device_register_simple("imx21-audmux", 0, imx27_audmux_res, 86 85 ARRAY_SIZE(imx27_audmux_res));
+11 -3
arch/arm/mach-omap2/omap_hwmod.c
··· 3435 3435 regs = ioremap(data->module_pa, 3436 3436 data->module_size); 3437 3437 if (!regs) 3438 - return -ENOMEM; 3438 + goto out_free_sysc; 3439 3439 } 3440 3440 3441 3441 /* ··· 3445 3445 if (oh->class->name && strcmp(oh->class->name, data->name)) { 3446 3446 class = kmemdup(oh->class, sizeof(*oh->class), GFP_KERNEL); 3447 3447 if (!class) 3448 - return -ENOMEM; 3448 + goto out_unmap; 3449 3449 } 3450 3450 3451 3451 if (list_empty(&oh->slave_ports)) { 3452 3452 oi = kcalloc(1, sizeof(*oi), GFP_KERNEL); 3453 3453 if (!oi) 3454 - return -ENOMEM; 3454 + goto out_free_class; 3455 3455 3456 3456 /* 3457 3457 * Note that we assume interconnect interface clocks will be ··· 3478 3478 spin_unlock_irqrestore(&oh->_lock, flags); 3479 3479 3480 3480 return 0; 3481 + 3482 + out_free_class: 3483 + kfree(class); 3484 + out_unmap: 3485 + iounmap(regs); 3486 + out_free_sysc: 3487 + kfree(sysc); 3488 + return -ENOMEM; 3481 3489 } 3482 3490 3483 3491 static const struct omap_hwmod_reset omap24xx_reset_quirks[] = {
+4 -4
arch/arm64/boot/dts/altera/socfpga_stratix10.dtsi
··· 77 77 method = "smc"; 78 78 }; 79 79 80 - intc: intc@fffc1000 { 80 + intc: interrupt-controller@fffc1000 { 81 81 compatible = "arm,gic-400", "arm,cortex-a15-gic"; 82 82 #interrupt-cells = <3>; 83 83 interrupt-controller; ··· 302 302 status = "disabled"; 303 303 }; 304 304 305 - nand: nand@ffb90000 { 305 + nand: nand-controller@ffb90000 { 306 306 #address-cells = <1>; 307 307 #size-cells = <0>; 308 308 compatible = "altr,socfpga-denali-nand"; ··· 445 445 clock-names = "timer"; 446 446 }; 447 447 448 - uart0: serial0@ffc02000 { 448 + uart0: serial@ffc02000 { 449 449 compatible = "snps,dw-apb-uart"; 450 450 reg = <0xffc02000 0x100>; 451 451 interrupts = <0 108 4>; ··· 456 456 status = "disabled"; 457 457 }; 458 458 459 - uart1: serial1@ffc02100 { 459 + uart1: serial@ffc02100 { 460 460 compatible = "snps,dw-apb-uart"; 461 461 reg = <0xffc02100 0x100>; 462 462 interrupts = <0 109 4>;
+1
arch/arm64/boot/dts/altera/socfpga_stratix10_socdk.dts
··· 155 155 }; 156 156 157 157 &qspi { 158 + status = "okay"; 158 159 flash@0 { 159 160 #address-cells = <1>; 160 161 #size-cells = <1>;
+4 -3
arch/arm64/boot/dts/altera/socfpga_stratix10_socdk_nand.dts
··· 188 188 }; 189 189 190 190 &qspi { 191 + status = "okay"; 191 192 flash@0 { 192 193 #address-cells = <1>; 193 194 #size-cells = <1>; ··· 212 211 213 212 qspi_boot: partition@0 { 214 213 label = "Boot and fpga data"; 215 - reg = <0x0 0x034B0000>; 214 + reg = <0x0 0x03FE0000>; 216 215 }; 217 216 218 - qspi_rootfs: partition@4000000 { 217 + qspi_rootfs: partition@3FE0000 { 219 218 label = "Root Filesystem - JFFS2"; 220 - reg = <0x034B0000 0x0EB50000>; 219 + reg = <0x03FE0000 0x0C020000>; 221 220 }; 222 221 }; 223 222 };
+1 -1
arch/arm64/boot/dts/amlogic/meson-gxl-s805x-libretech-ac.dts
··· 10 10 #include <dt-bindings/input/input.h> 11 11 #include <dt-bindings/sound/meson-aiu.h> 12 12 13 - #include "meson-gxl-s905x.dtsi" 13 + #include "meson-gxl-s805x.dtsi" 14 14 15 15 / { 16 16 compatible = "libretech,aml-s805x-ac", "amlogic,s805x",
+1 -1
arch/arm64/boot/dts/amlogic/meson-gxl-s805x-p241.dts
··· 9 9 10 10 #include <dt-bindings/input/input.h> 11 11 12 - #include "meson-gxl-s905x.dtsi" 12 + #include "meson-gxl-s805x.dtsi" 13 13 14 14 / { 15 15 compatible = "amlogic,p241", "amlogic,s805x", "amlogic,meson-gxl";
+24
arch/arm64/boot/dts/amlogic/meson-gxl-s805x.dtsi
··· 1 + // SPDX-License-Identifier: (GPL-2.0+ OR MIT) 2 + /* 3 + * Copyright (c) 2020 BayLibre SAS 4 + * Author: Neil Armstrong <narmstrong@baylibre.com> 5 + */ 6 + 7 + #include "meson-gxl-s905x.dtsi" 8 + 9 + / { 10 + compatible = "amlogic,s805x", "amlogic,meson-gxl"; 11 + }; 12 + 13 + /* The S805X Package doesn't seem to handle the 744MHz OPP correctly */ 14 + &mali { 15 + assigned-clocks = <&clkc CLKID_MALI_0_SEL>, 16 + <&clkc CLKID_MALI_0>, 17 + <&clkc CLKID_MALI>; /* Glitch free mux */ 18 + assigned-clock-parents = <&clkc CLKID_FCLK_DIV3>, 19 + <0>, /* Do Nothing */ 20 + <&clkc CLKID_MALI_0>; 21 + assigned-clock-rates = <0>, /* Do Nothing */ 22 + <666666666>, 23 + <0>; /* Do Nothing */ 24 + };
+5
arch/arm64/boot/dts/amlogic/meson-gxl.dtsi
··· 337 337 }; 338 338 }; 339 339 340 + &hwrng { 341 + clocks = <&clkc CLKID_RNG0>; 342 + clock-names = "core"; 343 + }; 344 + 340 345 &i2c_A { 341 346 clocks = <&clkc CLKID_I2C>; 342 347 };
+1
arch/arm64/boot/dts/intel/socfpga_agilex_socdk.dts
··· 98 98 }; 99 99 100 100 &qspi { 101 + status = "okay"; 101 102 flash@0 { 102 103 #address-cells = <1>; 103 104 #size-cells = <1>;
+1 -1
arch/arm64/configs/defconfig
··· 194 194 CONFIG_HOTPLUG_PCI_ACPI=y 195 195 CONFIG_PCI_AARDVARK=y 196 196 CONFIG_PCI_TEGRA=y 197 - CONFIG_PCIE_RCAR=y 197 + CONFIG_PCIE_RCAR_HOST=y 198 198 CONFIG_PCI_HOST_GENERIC=y 199 199 CONFIG_PCI_XGENE=y 200 200 CONFIG_PCIE_ALTERA=y
+12 -11
drivers/bus/ti-sysc.c
··· 236 236 syss_done = ddata->cfg.syss_mask; 237 237 238 238 if (syss_offset >= 0) { 239 - error = readx_poll_timeout(sysc_read_sysstatus, ddata, rstval, 240 - (rstval & ddata->cfg.syss_mask) == 241 - syss_done, 242 - 100, MAX_MODULE_SOFTRESET_WAIT); 239 + error = readx_poll_timeout_atomic(sysc_read_sysstatus, ddata, 240 + rstval, (rstval & ddata->cfg.syss_mask) == 241 + syss_done, 100, MAX_MODULE_SOFTRESET_WAIT); 243 242 244 243 } else if (ddata->cfg.quirks & SYSC_QUIRK_RESET_STATUS) { 245 - error = readx_poll_timeout(sysc_read_sysconfig, ddata, rstval, 246 - !(rstval & sysc_mask), 247 - 100, MAX_MODULE_SOFTRESET_WAIT); 244 + error = readx_poll_timeout_atomic(sysc_read_sysconfig, ddata, 245 + rstval, !(rstval & sysc_mask), 246 + 100, MAX_MODULE_SOFTRESET_WAIT); 248 247 } 249 248 250 249 return error; ··· 1278 1279 1279 1280 ddata = dev_get_drvdata(dev); 1280 1281 1281 - if (ddata->cfg.quirks & SYSC_QUIRK_LEGACY_IDLE) 1282 + if (ddata->cfg.quirks & 1283 + (SYSC_QUIRK_LEGACY_IDLE | SYSC_QUIRK_NO_IDLE)) 1282 1284 return 0; 1283 1285 1284 1286 return pm_runtime_force_suspend(dev); ··· 1291 1291 1292 1292 ddata = dev_get_drvdata(dev); 1293 1293 1294 - if (ddata->cfg.quirks & SYSC_QUIRK_LEGACY_IDLE) 1294 + if (ddata->cfg.quirks & 1295 + (SYSC_QUIRK_LEGACY_IDLE | SYSC_QUIRK_NO_IDLE)) 1295 1296 return 0; 1296 1297 1297 1298 return pm_runtime_force_resume(dev); ··· 1729 1728 1730 1729 local_irq_save(flags); 1731 1730 /* RTC_STATUS BUSY bit may stay active for 1/32768 seconds (~30 usec) */ 1732 - error = readl_poll_timeout(ddata->module_va + 0x44, val, 1733 - !(val & BIT(0)), 100, 50); 1731 + error = readl_poll_timeout_atomic(ddata->module_va + 0x44, val, 1732 + !(val & BIT(0)), 100, 50); 1734 1733 if (error) 1735 1734 dev_warn(ddata->dev, "rtc busy timeout\n"); 1736 1735 /* Now we have ~15 microseconds to read/write various registers */
+5 -3
drivers/soc/amlogic/meson-gx-socinfo.c
··· 66 66 { "A113D", 0x25, 0x22, 0xff }, 67 67 { "S905D2", 0x28, 0x10, 0xf0 }, 68 68 { "S905X2", 0x28, 0x40, 0xf0 }, 69 - { "S922X", 0x29, 0x40, 0xf0 }, 70 69 { "A311D", 0x29, 0x10, 0xf0 }, 71 - { "S905X3", 0x2b, 0x5, 0xf }, 72 - { "S905D3", 0x2b, 0xb0, 0xf0 }, 70 + { "S922X", 0x29, 0x40, 0xf0 }, 71 + { "S905D3", 0x2b, 0x4, 0xf5 }, 72 + { "S905X3", 0x2b, 0x5, 0xf5 }, 73 + { "S905X3", 0x2b, 0x10, 0x3f }, 74 + { "S905D3", 0x2b, 0x30, 0x3f }, 73 75 { "A113L", 0x2c, 0x0, 0xf8 }, 74 76 }; 75 77
+3
drivers/soc/imx/soc-imx.c
··· 33 33 u32 val; 34 34 int ret; 35 35 36 + if (of_machine_is_compatible("fsl,ls1021a")) 37 + return 0; 38 + 36 39 soc_dev_attr = kzalloc(sizeof(*soc_dev_attr), GFP_KERNEL); 37 40 if (!soc_dev_attr) 38 41 return -ENOMEM;