tjh.dev / kernel
Linux kernel mirror (for testing) git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git
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Merge tag 'fixes-for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/arm/arm-soc

Pull arm-soc bug fixes from Olof Johansson:
"A couple of samsung clock locking fixes, at91 device tree gpio
configuration fix and a couple more for shmobile and i.MX.

All small targeted fixes."

* tag 'fixes-for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/arm/arm-soc:
ARM i.MX25: Make timer irq work again
ARM: imx: armadillo5x0: Fix illegal register access
ARM: shmobile: kzm9g: bugfix: correct mmcif interrupt settings
ARM: SAMSUNG: Use spin_lock_{irqsave,irqrestore} in clk_set_rate
ARM: at91: fix missing #interrupt-cells on gpio-controller
ARM: SAMSUNG: use spin_lock_irqsave() in clk_set_parent

Linus Torvalds 63365013 267b50fe

+33 -8
+3
arch/arm/boot/dts/at91sam9260.dtsi
··· 104 104 #gpio-cells = <2>; 105 105 gpio-controller; 106 106 interrupt-controller; 107 + #interrupt-cells = <2>; 107 108 }; 108 109 109 110 pioB: gpio@fffff600 { ··· 114 113 #gpio-cells = <2>; 115 114 gpio-controller; 116 115 interrupt-controller; 116 + #interrupt-cells = <2>; 117 117 }; 118 118 119 119 pioC: gpio@fffff800 { ··· 124 122 #gpio-cells = <2>; 125 123 gpio-controller; 126 124 interrupt-controller; 125 + #interrupt-cells = <2>; 127 126 }; 128 127 129 128 dbgu: serial@fffff200 {
+5
arch/arm/boot/dts/at91sam9263.dtsi
··· 95 95 #gpio-cells = <2>; 96 96 gpio-controller; 97 97 interrupt-controller; 98 + #interrupt-cells = <2>; 98 99 }; 99 100 100 101 pioB: gpio@fffff400 { ··· 105 104 #gpio-cells = <2>; 106 105 gpio-controller; 107 106 interrupt-controller; 107 + #interrupt-cells = <2>; 108 108 }; 109 109 110 110 pioC: gpio@fffff600 { ··· 115 113 #gpio-cells = <2>; 116 114 gpio-controller; 117 115 interrupt-controller; 116 + #interrupt-cells = <2>; 118 117 }; 119 118 120 119 pioD: gpio@fffff800 { ··· 125 122 #gpio-cells = <2>; 126 123 gpio-controller; 127 124 interrupt-controller; 125 + #interrupt-cells = <2>; 128 126 }; 129 127 130 128 pioE: gpio@fffffa00 { ··· 135 131 #gpio-cells = <2>; 136 132 gpio-controller; 137 133 interrupt-controller; 134 + #interrupt-cells = <2>; 138 135 }; 139 136 140 137 dbgu: serial@ffffee00 {
+5
arch/arm/boot/dts/at91sam9g45.dtsi
··· 113 113 #gpio-cells = <2>; 114 114 gpio-controller; 115 115 interrupt-controller; 116 + #interrupt-cells = <2>; 116 117 }; 117 118 118 119 pioB: gpio@fffff400 { ··· 123 122 #gpio-cells = <2>; 124 123 gpio-controller; 125 124 interrupt-controller; 125 + #interrupt-cells = <2>; 126 126 }; 127 127 128 128 pioC: gpio@fffff600 { ··· 133 131 #gpio-cells = <2>; 134 132 gpio-controller; 135 133 interrupt-controller; 134 + #interrupt-cells = <2>; 136 135 }; 137 136 138 137 pioD: gpio@fffff800 { ··· 143 140 #gpio-cells = <2>; 144 141 gpio-controller; 145 142 interrupt-controller; 143 + #interrupt-cells = <2>; 146 144 }; 147 145 148 146 pioE: gpio@fffffa00 { ··· 153 149 #gpio-cells = <2>; 154 150 gpio-controller; 155 151 interrupt-controller; 152 + #interrupt-cells = <2>; 156 153 }; 157 154 158 155 dbgu: serial@ffffee00 {
+4
arch/arm/boot/dts/at91sam9n12.dtsi
··· 107 107 #gpio-cells = <2>; 108 108 gpio-controller; 109 109 interrupt-controller; 110 + #interrupt-cells = <2>; 110 111 }; 111 112 112 113 pioB: gpio@fffff600 { ··· 117 116 #gpio-cells = <2>; 118 117 gpio-controller; 119 118 interrupt-controller; 119 + #interrupt-cells = <2>; 120 120 }; 121 121 122 122 pioC: gpio@fffff800 { ··· 127 125 #gpio-cells = <2>; 128 126 gpio-controller; 129 127 interrupt-controller; 128 + #interrupt-cells = <2>; 130 129 }; 131 130 132 131 pioD: gpio@fffffa00 { ··· 137 134 #gpio-cells = <2>; 138 135 gpio-controller; 139 136 interrupt-controller; 137 + #interrupt-cells = <2>; 140 138 }; 141 139 142 140 dbgu: serial@fffff200 {
+4
arch/arm/boot/dts/at91sam9x5.dtsi
··· 115 115 #gpio-cells = <2>; 116 116 gpio-controller; 117 117 interrupt-controller; 118 + #interrupt-cells = <2>; 118 119 }; 119 120 120 121 pioB: gpio@fffff600 { ··· 125 124 #gpio-cells = <2>; 126 125 gpio-controller; 127 126 interrupt-controller; 127 + #interrupt-cells = <2>; 128 128 }; 129 129 130 130 pioC: gpio@fffff800 { ··· 135 133 #gpio-cells = <2>; 136 134 gpio-controller; 137 135 interrupt-controller; 136 + #interrupt-cells = <2>; 138 137 }; 139 138 140 139 pioD: gpio@fffffa00 { ··· 145 142 #gpio-cells = <2>; 146 143 gpio-controller; 147 144 interrupt-controller; 145 + #interrupt-cells = <2>; 148 146 }; 149 147 150 148 dbgu: serial@fffff200 {
+1 -1
arch/arm/mach-imx/clk-imx25.c
··· 241 241 clk_register_clkdev(clk[sdma_ahb], "ahb", "imx35-sdma"); 242 242 clk_register_clkdev(clk[iim_ipg], "iim", NULL); 243 243 244 - mxc_timer_init(MX25_IO_ADDRESS(MX25_GPT1_BASE_ADDR), 54); 244 + mxc_timer_init(MX25_IO_ADDRESS(MX25_GPT1_BASE_ADDR), MX25_INT_GPT1); 245 245 return 0; 246 246 }
+2 -1
arch/arm/mach-imx/mach-armadillo5x0.c
··· 526 526 imx31_add_mxc_nand(&armadillo5x0_nand_board_info); 527 527 528 528 /* set NAND page size to 2k if not configured via boot mode pins */ 529 - __raw_writel(__raw_readl(MXC_CCM_RCSR) | (1 << 30), MXC_CCM_RCSR); 529 + __raw_writel(__raw_readl(mx3_ccm_base + MXC_CCM_RCSR) | 530 + (1 << 30), mx3_ccm_base + MXC_CCM_RCSR); 530 531 531 532 /* RTC */ 532 533 /* Get RTC IRQ and register the chip */
+2 -2
arch/arm/mach-shmobile/board-kzm9g.c
··· 346 346 .flags = IORESOURCE_MEM, 347 347 }, 348 348 [1] = { 349 - .start = gic_spi(141), 349 + .start = gic_spi(140), 350 350 .flags = IORESOURCE_IRQ, 351 351 }, 352 352 [2] = { 353 - .start = gic_spi(140), 353 + .start = gic_spi(141), 354 354 .flags = IORESOURCE_IRQ, 355 355 }, 356 356 };
+1
arch/arm/plat-mxc/include/mach/mx25.h
··· 98 98 #define MX25_INT_UART1 (NR_IRQS_LEGACY + 45) 99 99 #define MX25_INT_GPIO2 (NR_IRQS_LEGACY + 51) 100 100 #define MX25_INT_GPIO1 (NR_IRQS_LEGACY + 52) 101 + #define MX25_INT_GPT1 (NR_IRQS_LEGACY + 54) 101 102 #define MX25_INT_FEC (NR_IRQS_LEGACY + 57) 102 103 103 104 #define MX25_DMA_REQ_SSI2_RX1 22
+6 -4
arch/arm/plat-samsung/clock.c
··· 144 144 145 145 int clk_set_rate(struct clk *clk, unsigned long rate) 146 146 { 147 + unsigned long flags; 147 148 int ret; 148 149 149 150 if (IS_ERR(clk)) ··· 160 159 if (clk->ops == NULL || clk->ops->set_rate == NULL) 161 160 return -EINVAL; 162 161 163 - spin_lock(&clocks_lock); 162 + spin_lock_irqsave(&clocks_lock, flags); 164 163 ret = (clk->ops->set_rate)(clk, rate); 165 - spin_unlock(&clocks_lock); 164 + spin_unlock_irqrestore(&clocks_lock, flags); 166 165 167 166 return ret; 168 167 } ··· 174 173 175 174 int clk_set_parent(struct clk *clk, struct clk *parent) 176 175 { 176 + unsigned long flags; 177 177 int ret = 0; 178 178 179 179 if (IS_ERR(clk)) 180 180 return -EINVAL; 181 181 182 - spin_lock(&clocks_lock); 182 + spin_lock_irqsave(&clocks_lock, flags); 183 183 184 184 if (clk->ops && clk->ops->set_parent) 185 185 ret = (clk->ops->set_parent)(clk, parent); 186 186 187 - spin_unlock(&clocks_lock); 187 + spin_unlock_irqrestore(&clocks_lock, flags); 188 188 189 189 return ret; 190 190 }