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Merge tag 'arm64-fixes' of git://git.kernel.org/pub/scm/linux/kernel/git/arm64/linux

Pull arm64 fixes (and cleanups) from Catalin Marinas:
"Various arm64 fixes:

- suspicious RCU usage warning
- BPF (out of bounds array read and endianness conversion)
- perf (of_node usage after of_node_put, cpu_pmu->plat_device
assignment)
- huge pmd/pud check for value 0
- rate-limiting should only take unhandled signals into account

Clean-up:

- incorrect use of pgprot_t type
- unused header include
- __init annotation to arm_cpuidle_init
- pr_debug instead of pr_error for disabled GICC entries in
ACPI/MADT"

* tag 'arm64-fixes' of git://git.kernel.org/pub/scm/linux/kernel/git/arm64/linux:
arm64: Fix show_unhandled_signal_ratelimited usage
ARM64 / SMP: Switch pr_err() to pr_debug() for disabled GICC entry
arm64: cpuidle: add __init section marker to arm_cpuidle_init
arm64: Don't report clear pmds and puds as huge
arm64: perf: fix unassigned cpu_pmu->plat_device when probing PMU PPIs
arm64: perf: Don't use of_node after putting it
arm64: fix incorrect use of pgprot_t variable
arm64/hw_breakpoint.c: remove unnecessary header
arm64: bpf: fix endianness conversion bugs
arm64: bpf: fix out-of-bounds read in bpf2a64_offset()
ARM64: smp: Fix suspicious RCU usage with ipi tracepoints

+44 -20
+1 -1
arch/arm64/kernel/cpuidle.c
··· 15 15 #include <asm/cpuidle.h> 16 16 #include <asm/cpu_ops.h> 17 17 18 - int arm_cpuidle_init(unsigned int cpu) 18 + int __init arm_cpuidle_init(unsigned int cpu) 19 19 { 20 20 int ret = -EOPNOTSUPP; 21 21
-1
arch/arm64/kernel/hw_breakpoint.c
··· 31 31 #include <asm/current.h> 32 32 #include <asm/debug-monitors.h> 33 33 #include <asm/hw_breakpoint.h> 34 - #include <asm/kdebug.h> 35 34 #include <asm/traps.h> 36 35 #include <asm/cputype.h> 37 36 #include <asm/system_misc.h>
+4 -2
arch/arm64/kernel/perf_event.c
··· 1318 1318 /* Don't bother with PPIs; they're already affine */ 1319 1319 irq = platform_get_irq(pdev, 0); 1320 1320 if (irq >= 0 && irq_is_percpu(irq)) 1321 - return 0; 1321 + goto out; 1322 1322 1323 1323 irqs = kcalloc(pdev->num_resources, sizeof(*irqs), GFP_KERNEL); 1324 1324 if (!irqs) ··· 1340 1340 if (arch_find_n_match_cpu_physical_id(dn, cpu, NULL)) 1341 1341 break; 1342 1342 1343 - of_node_put(dn); 1344 1343 if (cpu >= nr_cpu_ids) { 1345 1344 pr_warn("Failed to find logical CPU for %s\n", 1346 1345 dn->name); 1346 + of_node_put(dn); 1347 1347 break; 1348 1348 } 1349 + of_node_put(dn); 1349 1350 1350 1351 irqs[i] = cpu; 1351 1352 } ··· 1356 1355 else 1357 1356 kfree(irqs); 1358 1357 1358 + out: 1359 1359 cpu_pmu->plat_device = pdev; 1360 1360 return 0; 1361 1361 }
+6 -6
arch/arm64/kernel/smp.c
··· 396 396 { 397 397 u64 hwid = processor->arm_mpidr; 398 398 399 - if (hwid & ~MPIDR_HWID_BITMASK || hwid == INVALID_HWID) { 400 - pr_err("skipping CPU entry with invalid MPIDR 0x%llx\n", hwid); 399 + if (!(processor->flags & ACPI_MADT_ENABLED)) { 400 + pr_debug("skipping disabled CPU entry with 0x%llx MPIDR\n", hwid); 401 401 return; 402 402 } 403 403 404 - if (!(processor->flags & ACPI_MADT_ENABLED)) { 405 - pr_err("skipping disabled CPU entry with 0x%llx MPIDR\n", hwid); 404 + if (hwid & ~MPIDR_HWID_BITMASK || hwid == INVALID_HWID) { 405 + pr_err("skipping CPU entry with invalid MPIDR 0x%llx\n", hwid); 406 406 return; 407 407 } 408 408 ··· 693 693 struct pt_regs *old_regs = set_irq_regs(regs); 694 694 695 695 if ((unsigned)ipinr < NR_IPI) { 696 - trace_ipi_entry(ipi_types[ipinr]); 696 + trace_ipi_entry_rcuidle(ipi_types[ipinr]); 697 697 __inc_irq_stat(cpu, ipi_irqs[ipinr]); 698 698 } 699 699 ··· 736 736 } 737 737 738 738 if ((unsigned)ipinr < NR_IPI) 739 - trace_ipi_exit(ipi_types[ipinr]); 739 + trace_ipi_exit_rcuidle(ipi_types[ipinr]); 740 740 set_irq_regs(old_regs); 741 741 } 742 742
+1 -1
arch/arm64/kernel/traps.c
··· 335 335 if (call_undef_hook(regs) == 0) 336 336 return; 337 337 338 - if (show_unhandled_signals_ratelimited() && unhandled_signal(current, SIGILL)) { 338 + if (unhandled_signal(current, SIGILL) && show_unhandled_signals_ratelimited()) { 339 339 pr_info("%s[%d]: undefined instruction: pc=%p\n", 340 340 current->comm, task_pid_nr(current), pc); 341 341 dump_instr(KERN_INFO, regs);
+1 -1
arch/arm64/mm/fault.c
··· 115 115 { 116 116 struct siginfo si; 117 117 118 - if (show_unhandled_signals_ratelimited() && unhandled_signal(tsk, sig)) { 118 + if (unhandled_signal(tsk, sig) && show_unhandled_signals_ratelimited()) { 119 119 pr_info("%s[%d]: unhandled %s (%d) at 0x%08lx, esr 0x%03x\n", 120 120 tsk->comm, task_pid_nr(tsk), fault_name(esr), sig, 121 121 addr, esr);
+2 -2
arch/arm64/mm/hugetlbpage.c
··· 33 33 34 34 int pmd_huge(pmd_t pmd) 35 35 { 36 - return !(pmd_val(pmd) & PMD_TABLE_BIT); 36 + return pmd_val(pmd) && !(pmd_val(pmd) & PMD_TABLE_BIT); 37 37 } 38 38 39 39 int pud_huge(pud_t pud) 40 40 { 41 41 #ifndef __PAGETABLE_PMD_FOLDED 42 - return !(pud_val(pud) & PUD_TABLE_BIT); 42 + return pud_val(pud) && !(pud_val(pud) & PUD_TABLE_BIT); 43 43 #else 44 44 return 0; 45 45 #endif
+1 -1
arch/arm64/mm/mmu.c
··· 117 117 int i = 0; 118 118 119 119 do { 120 - set_pmd(pmd, __pmd(addr | prot)); 120 + set_pmd(pmd, __pmd(addr | pgprot_val(prot))); 121 121 addr += PMD_SIZE; 122 122 } while (pmd++, i++, i < PTRS_PER_PMD); 123 123 }
+4
arch/arm64/net/bpf_jit.h
··· 110 110 /* Rd = Rn >> shift; signed */ 111 111 #define A64_ASR(sf, Rd, Rn, shift) A64_SBFM(sf, Rd, Rn, shift, (sf) ? 63 : 31) 112 112 113 + /* Zero extend */ 114 + #define A64_UXTH(sf, Rd, Rn) A64_UBFM(sf, Rd, Rn, 0, 15) 115 + #define A64_UXTW(sf, Rd, Rn) A64_UBFM(sf, Rd, Rn, 0, 31) 116 + 113 117 /* Move wide (immediate) */ 114 118 #define A64_MOVEW(sf, Rd, imm16, shift, type) \ 115 119 aarch64_insn_gen_movewide(Rd, imm16, shift, \
+24 -5
arch/arm64/net/bpf_jit_comp.c
··· 113 113 static inline int bpf2a64_offset(int bpf_to, int bpf_from, 114 114 const struct jit_ctx *ctx) 115 115 { 116 - int to = ctx->offset[bpf_to + 1]; 116 + int to = ctx->offset[bpf_to]; 117 117 /* -1 to account for the Branch instruction */ 118 - int from = ctx->offset[bpf_from + 1] - 1; 118 + int from = ctx->offset[bpf_from] - 1; 119 119 120 120 return to - from; 121 121 } ··· 289 289 case BPF_ALU | BPF_END | BPF_FROM_BE: 290 290 #ifdef CONFIG_CPU_BIG_ENDIAN 291 291 if (BPF_SRC(code) == BPF_FROM_BE) 292 - break; 292 + goto emit_bswap_uxt; 293 293 #else /* !CONFIG_CPU_BIG_ENDIAN */ 294 294 if (BPF_SRC(code) == BPF_FROM_LE) 295 - break; 295 + goto emit_bswap_uxt; 296 296 #endif 297 297 switch (imm) { 298 298 case 16: 299 299 emit(A64_REV16(is64, dst, dst), ctx); 300 + /* zero-extend 16 bits into 64 bits */ 301 + emit(A64_UXTH(is64, dst, dst), ctx); 300 302 break; 301 303 case 32: 302 304 emit(A64_REV32(is64, dst, dst), ctx); 305 + /* upper 32 bits already cleared */ 303 306 break; 304 307 case 64: 305 308 emit(A64_REV64(dst, dst), ctx); 309 + break; 310 + } 311 + break; 312 + emit_bswap_uxt: 313 + switch (imm) { 314 + case 16: 315 + /* zero-extend 16 bits into 64 bits */ 316 + emit(A64_UXTH(is64, dst, dst), ctx); 317 + break; 318 + case 32: 319 + /* zero-extend 32 bits into 64 bits */ 320 + emit(A64_UXTW(is64, dst, dst), ctx); 321 + break; 322 + case 64: 323 + /* nop */ 306 324 break; 307 325 } 308 326 break; ··· 658 640 const struct bpf_insn *insn = &prog->insnsi[i]; 659 641 int ret; 660 642 643 + ret = build_insn(insn, ctx); 644 + 661 645 if (ctx->image == NULL) 662 646 ctx->offset[i] = ctx->idx; 663 647 664 - ret = build_insn(insn, ctx); 665 648 if (ret > 0) { 666 649 i++; 667 650 continue;