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dt-bindings: watchdog: aspeed,ast2400-wdt: Convert to DT schema

Squash warnings such as:

```
arch/arm/boot/dts/aspeed/aspeed-bmc-facebook-galaxy100.dtb: /ahb/apb@1e600000/watchdog@1e785000: failed to match any schema with compatible: ['aspeed,ast2400-wdt']
```

The schema binding additionally defines the clocks property over the
prose binding to align with use of the node in the DTS files.

Signed-off-by: Andrew Jeffery <andrew@codeconstruct.com.au>
Reviewed-by: Rob Herring <robh@kernel.org>
Link: https://lore.kernel.org/r/20240403020439.418788-1-andrew@codeconstruct.com.au
Signed-off-by: Rob Herring (Arm) <robh@kernel.org>

authored by

Andrew Jeffery and committed by
Rob Herring (Arm)
638887e1 d47bca77

+142 -73
+142
Documentation/devicetree/bindings/watchdog/aspeed,ast2400-wdt.yaml
··· 1 + # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) 2 + %YAML 1.2 3 + --- 4 + $id: http://devicetree.org/schemas/watchdog/aspeed,ast2400-wdt.yaml# 5 + $schema: http://devicetree.org/meta-schemas/core.yaml# 6 + 7 + title: Aspeed watchdog timer controllers 8 + 9 + maintainers: 10 + - Andrew Jeffery <andrew@codeconstruct.com.au> 11 + 12 + properties: 13 + compatible: 14 + enum: 15 + - aspeed,ast2400-wdt 16 + - aspeed,ast2500-wdt 17 + - aspeed,ast2600-wdt 18 + 19 + reg: 20 + maxItems: 1 21 + 22 + clocks: 23 + maxItems: 1 24 + description: > 25 + The clock used to drive the watchdog counter. From the AST2500 no source 26 + other than the 1MHz clock can be selected, so the clocks property is 27 + optional. 28 + 29 + aspeed,reset-type: 30 + $ref: /schemas/types.yaml#/definitions/string 31 + enum: 32 + - cpu 33 + - soc 34 + - system 35 + - none 36 + default: system 37 + description: > 38 + The watchdog can be programmed to generate one of three different types of 39 + reset when a timeout occcurs. 40 + 41 + Specifying 'cpu' will only reset the processor on a timeout event. 42 + 43 + Specifying 'soc' will reset a configurable subset of the SoC's controllers 44 + on a timeout event. Controllers critical to the SoC's operation may remain 45 + untouched. The set of SoC controllers to reset may be specified via the 46 + aspeed,reset-mask property if the node has the aspeed,ast2500-wdt or 47 + aspeed,ast2600-wdt compatible. 48 + 49 + Specifying 'system' will reset all controllers on a timeout event, as if 50 + EXTRST had been asserted. 51 + 52 + Specifying 'none' will cause the timeout event to have no reset effect. 53 + Another watchdog engine on the chip must be used for chip reset operations. 54 + 55 + aspeed,alt-boot: 56 + $ref: /schemas/types.yaml#/definitions/flag 57 + description: > 58 + Direct the watchdog to configure the SoC to boot from the alternative boot 59 + region if a timeout occurs. 60 + 61 + aspeed,external-signal: 62 + $ref: /schemas/types.yaml#/definitions/flag 63 + description: > 64 + Assert the timeout event on an external signal pin associated with the 65 + watchdog controller instance. The pin must be muxed appropriately. 66 + 67 + aspeed,ext-pulse-duration: 68 + $ref: /schemas/types.yaml#/definitions/uint32 69 + description: > 70 + The duration, in microseconds, of the pulse emitted on the external signal 71 + pin. 72 + 73 + aspeed,ext-push-pull: 74 + $ref: /schemas/types.yaml#/definitions/flag 75 + description: > 76 + If aspeed,external-signal is specified in the node, set the external 77 + signal pin's drive type to push-pull. If aspeed,ext-push-pull is not 78 + specified then the pin is configured as open-drain. 79 + 80 + aspeed,ext-active-high: 81 + $ref: /schemas/types.yaml#/definitions/flag 82 + description: > 83 + If both aspeed,external-signal and aspeed,ext-push-pull are specified in 84 + the node, set the pulse polarity to active-high. If aspeed,ext-active-high 85 + is not specified then the pin is configured as active-low. 86 + 87 + aspeed,reset-mask: 88 + $ref: /schemas/types.yaml#/definitions/uint32-array 89 + minItems: 1 90 + maxItems: 2 91 + description: > 92 + A bitmask indicating which peripherals will be reset if the watchdog 93 + timer expires. On AST2500 SoCs this should be a single word defined using 94 + the AST2500_WDT_RESET_* macros; on AST2600 SoCs this should be a two-word 95 + array with the first word defined using the AST2600_WDT_RESET1_* macros, 96 + and the second word defined using the AST2600_WDT_RESET2_* macros. 97 + 98 + required: 99 + - compatible 100 + - reg 101 + 102 + allOf: 103 + - if: 104 + anyOf: 105 + - required: 106 + - aspeed,ext-push-pull 107 + - required: 108 + - aspeed,ext-active-high 109 + - required: 110 + - aspeed,reset-mask 111 + then: 112 + properties: 113 + compatible: 114 + enum: 115 + - aspeed,ast2500-wdt 116 + - aspeed,ast2600-wdt 117 + - if: 118 + required: 119 + - aspeed,ext-active-high 120 + then: 121 + required: 122 + - aspeed,ext-push-pull 123 + 124 + additionalProperties: false 125 + 126 + examples: 127 + - | 128 + watchdog@1e785000 { 129 + compatible = "aspeed,ast2400-wdt"; 130 + reg = <0x1e785000 0x1c>; 131 + aspeed,reset-type = "system"; 132 + aspeed,external-signal; 133 + }; 134 + - | 135 + #include <dt-bindings/watchdog/aspeed-wdt.h> 136 + watchdog@1e785040 { 137 + compatible = "aspeed,ast2600-wdt"; 138 + reg = <0x1e785040 0x40>; 139 + aspeed,reset-type = "soc"; 140 + aspeed,reset-mask = <AST2600_WDT_RESET1_DEFAULT 141 + (AST2600_WDT_RESET2_DEFAULT & ~AST2600_WDT_RESET2_LPC)>; 142 + };
-73
Documentation/devicetree/bindings/watchdog/aspeed-wdt.txt
··· 1 - Aspeed Watchdog Timer 2 - 3 - Required properties: 4 - - compatible: must be one of: 5 - - "aspeed,ast2400-wdt" 6 - - "aspeed,ast2500-wdt" 7 - - "aspeed,ast2600-wdt" 8 - 9 - - reg: physical base address of the controller and length of memory mapped 10 - region 11 - 12 - Optional properties: 13 - 14 - - aspeed,reset-type = "cpu|soc|system|none" 15 - 16 - Reset behavior - Whenever a timeout occurs the watchdog can be programmed 17 - to generate one of three different, mutually exclusive, types of resets. 18 - 19 - Type "none" can be specified to indicate that no resets are to be done. 20 - This is useful in situations where another watchdog engine on chip is 21 - to perform the reset. 22 - 23 - If 'aspeed,reset-type=' is not specified the default is to enable system 24 - reset. 25 - 26 - Reset types: 27 - 28 - - cpu: Reset CPU on watchdog timeout 29 - 30 - - soc: Reset 'System on Chip' on watchdog timeout 31 - 32 - - system: Reset system on watchdog timeout 33 - 34 - - none: No reset is performed on timeout. Assumes another watchdog 35 - engine is responsible for this. 36 - 37 - - aspeed,alt-boot: If property is present then boot from alternate block. 38 - - aspeed,external-signal: If property is present then signal is sent to 39 - external reset counter (only WDT1 and WDT2). If not 40 - specified no external signal is sent. 41 - - aspeed,ext-pulse-duration: External signal pulse duration in microseconds 42 - 43 - Optional properties for AST2500-compatible watchdogs: 44 - - aspeed,ext-push-pull: If aspeed,external-signal is present, set the pin's 45 - drive type to push-pull. The default is open-drain. 46 - - aspeed,ext-active-high: If aspeed,external-signal is present and and the pin 47 - is configured as push-pull, then set the pulse 48 - polarity to active-high. The default is active-low. 49 - 50 - Optional properties for AST2500- and AST2600-compatible watchdogs: 51 - - aspeed,reset-mask: A bitmask indicating which peripherals will be reset if 52 - the watchdog timer expires. On AST2500 this should be a 53 - single word defined using the AST2500_WDT_RESET_* macros; 54 - on AST2600 this should be a two-word array with the first 55 - word defined using the AST2600_WDT_RESET1_* macros and the 56 - second word defined using the AST2600_WDT_RESET2_* macros. 57 - 58 - Examples: 59 - 60 - wdt1: watchdog@1e785000 { 61 - compatible = "aspeed,ast2400-wdt"; 62 - reg = <0x1e785000 0x1c>; 63 - aspeed,reset-type = "system"; 64 - aspeed,external-signal; 65 - }; 66 - 67 - #include <dt-bindings/watchdog/aspeed-wdt.h> 68 - wdt2: watchdog@1e785040 { 69 - compatible = "aspeed,ast2600-wdt"; 70 - reg = <0x1e785040 0x40>; 71 - aspeed,reset-mask = <AST2600_WDT_RESET1_DEFAULT 72 - (AST2600_WDT_RESET2_DEFAULT & ~AST2600_WDT_RESET2_LPC)>; 73 - };