tjh.dev / kernel
Linux kernel mirror (for testing) git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git
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Merge branch 'drm-fixes' of git://people.freedesktop.org/~airlied/linux

Pull drm fixes from Dave Airlie:
"This contains one i915 patch twice, as I merged it locally for
testing, and then pulled some stuff in on top, and then Jani sent to
me, I didn't think it was worth redoing all the merges of what I had
tested.

Summary:

- amdgpu/radeon fixes for some more power management and VM races.

- Two i915 fixes, one for the a recent regression, one another power
management fix for skylake.

- Two tegra dma mask fixes for a regression.

- One ast fix for a typo I made transcribing the userspace driver,
that I'd like to get into stable so I don't forget about it"

* 'drm-fixes' of git://people.freedesktop.org/~airlied/linux:
gpu: host1x: Set DMA ops on device creation
gpu: host1x: Set DMA mask
drm/amdgpu: return from atombios_dp_get_dpcd only when error
drm/amdgpu/cz: remove commented out call to enable vce pg
drm/amdgpu/powerplay/cz: enable/disable vce dpm independent of vce pg
drm/amdgpu/cz: enable/disable vce dpm even if vce pg is disabled
drm/amdgpu/gfx8: specify which engine to wait before vm flush
drm/amdgpu: apply gfx_v8 fixes to gfx_v7 as well
drm/amd/powerplay: send event to notify powerplay all modules are initialized.
drm/amd/powerplay: export AMD_PP_EVENT_COMPLETE_INIT task to amdgpu.
drm/radeon/pm: update current crtc info after setting the powerstate
drm/amdgpu/pm: update current crtc info after setting the powerstate
drm/i915: Balance assert_rpm_wakelock_held() for !IS_ENABLED(CONFIG_PM)
drm/i915/skl: Fix power domain suspend sequence
drm/ast: Fix incorrect register check for DRAM width
drm/i915: Balance assert_rpm_wakelock_held() for !IS_ENABLED(CONFIG_PM)

Linus Torvalds 638c201e b80e8e28

+60 -35
+1 -1
drivers/gpu/drm/amd/amdgpu/amdgpu_connectors.c
··· 77 77 } else if (amdgpu_atombios_dp_needs_link_train(amdgpu_connector)) { 78 78 /* Don't try to start link training before we 79 79 * have the dpcd */ 80 - if (!amdgpu_atombios_dp_get_dpcd(amdgpu_connector)) 80 + if (amdgpu_atombios_dp_get_dpcd(amdgpu_connector)) 81 81 return; 82 82 83 83 /* set it to OFF so that drm_helper_connector_dpms()
+3 -3
drivers/gpu/drm/amd/amdgpu/amdgpu_pm.c
··· 649 649 /* update display watermarks based on new power state */ 650 650 amdgpu_display_bandwidth_update(adev); 651 651 652 - adev->pm.dpm.current_active_crtcs = adev->pm.dpm.new_active_crtcs; 653 - adev->pm.dpm.current_active_crtc_count = adev->pm.dpm.new_active_crtc_count; 654 - 655 652 /* wait for the rings to drain */ 656 653 for (i = 0; i < AMDGPU_MAX_RINGS; i++) { 657 654 struct amdgpu_ring *ring = adev->rings[i]; ··· 666 669 667 670 /* update displays */ 668 671 amdgpu_dpm_display_configuration_changed(adev); 672 + 673 + adev->pm.dpm.current_active_crtcs = adev->pm.dpm.new_active_crtcs; 674 + adev->pm.dpm.current_active_crtc_count = adev->pm.dpm.new_active_crtc_count; 669 675 670 676 if (adev->pm.funcs->force_performance_level) { 671 677 if (adev->pm.dpm.thermal_active) {
+3 -1
drivers/gpu/drm/amd/amdgpu/amdgpu_powerplay.c
··· 143 143 adev->powerplay.pp_handle); 144 144 145 145 #ifdef CONFIG_DRM_AMD_POWERPLAY 146 - if (adev->pp_enabled) 146 + if (adev->pp_enabled) { 147 147 amdgpu_pm_sysfs_init(adev); 148 + amdgpu_dpm_dispatch_task(adev, AMD_PP_EVENT_COMPLETE_INIT, NULL, NULL); 149 + } 148 150 #endif 149 151 return ret; 150 152 }
+2 -5
drivers/gpu/drm/amd/amdgpu/cz_dpm.c
··· 2202 2202 AMD_PG_STATE_GATE); 2203 2203 2204 2204 cz_enable_vce_dpm(adev, false); 2205 - /* TODO: to figure out why vce can't be poweroff. */ 2206 - /* cz_send_msg_to_smc(adev, PPSMC_MSG_VCEPowerOFF); */ 2205 + cz_send_msg_to_smc(adev, PPSMC_MSG_VCEPowerOFF); 2207 2206 pi->vce_power_gated = true; 2208 2207 } else { 2209 2208 cz_send_msg_to_smc(adev, PPSMC_MSG_VCEPowerON); ··· 2225 2226 } 2226 2227 } else { /*pi->caps_vce_pg*/ 2227 2228 cz_update_vce_dpm(adev); 2228 - cz_enable_vce_dpm(adev, true); 2229 + cz_enable_vce_dpm(adev, !gate); 2229 2230 } 2230 - 2231 - return; 2232 2231 } 2233 2232 2234 2233 const struct amd_ip_funcs cz_dpm_ip_funcs = {
+13
drivers/gpu/drm/amd/amdgpu/gfx_v7_0.c
··· 3628 3628 unsigned vm_id, uint64_t pd_addr) 3629 3629 { 3630 3630 int usepfp = (ring->type == AMDGPU_RING_TYPE_GFX); 3631 + uint32_t seq = ring->fence_drv.sync_seq; 3632 + uint64_t addr = ring->fence_drv.gpu_addr; 3633 + 3634 + amdgpu_ring_write(ring, PACKET3(PACKET3_WAIT_REG_MEM, 5)); 3635 + amdgpu_ring_write(ring, (WAIT_REG_MEM_MEM_SPACE(1) | /* memory */ 3636 + WAIT_REG_MEM_FUNCTION(3) | /* equal */ 3637 + WAIT_REG_MEM_ENGINE(usepfp))); /* pfp or me */ 3638 + amdgpu_ring_write(ring, addr & 0xfffffffc); 3639 + amdgpu_ring_write(ring, upper_32_bits(addr) & 0xffffffff); 3640 + amdgpu_ring_write(ring, seq); 3641 + amdgpu_ring_write(ring, 0xffffffff); 3642 + amdgpu_ring_write(ring, 4); /* poll interval */ 3643 + 3631 3644 if (usepfp) { 3632 3645 /* synce CE with ME to prevent CE fetch CEIB before context switch done */ 3633 3646 amdgpu_ring_write(ring, PACKET3(PACKET3_SWITCH_BUFFER, 0));
+2 -1
drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c
··· 4809 4809 4810 4810 amdgpu_ring_write(ring, PACKET3(PACKET3_WAIT_REG_MEM, 5)); 4811 4811 amdgpu_ring_write(ring, (WAIT_REG_MEM_MEM_SPACE(1) | /* memory */ 4812 - WAIT_REG_MEM_FUNCTION(3))); /* equal */ 4812 + WAIT_REG_MEM_FUNCTION(3) | /* equal */ 4813 + WAIT_REG_MEM_ENGINE(usepfp))); /* pfp or me */ 4813 4814 amdgpu_ring_write(ring, addr & 0xfffffffc); 4814 4815 amdgpu_ring_write(ring, upper_32_bits(addr) & 0xffffffff); 4815 4816 amdgpu_ring_write(ring, seq);
+4 -1
drivers/gpu/drm/amd/powerplay/amd_powerplay.c
··· 402 402 403 403 data.requested_ui_label = power_state_convert(ps); 404 404 ret = pem_handle_event(pp_handle->eventmgr, event_id, &data); 405 + break; 405 406 } 406 - break; 407 + case AMD_PP_EVENT_COMPLETE_INIT: 408 + ret = pem_handle_event(pp_handle->eventmgr, event_id, &data); 409 + break; 407 410 default: 408 411 break; 409 412 }
+1
drivers/gpu/drm/amd/powerplay/eventmgr/eventactionchains.c
··· 165 165 }; 166 166 167 167 static const pem_event_action *complete_init_event[] = { 168 + unblock_adjust_power_state_tasks, 168 169 adjust_power_state_tasks, 169 170 enable_gfx_clock_gating_tasks, 170 171 enable_gfx_voltage_island_power_gating_tasks,
+1 -1
drivers/gpu/drm/amd/powerplay/hwmgr/cz_clockpowergating.c
··· 226 226 } 227 227 } else { 228 228 cz_dpm_update_vce_dpm(hwmgr); 229 - cz_enable_disable_vce_dpm(hwmgr, true); 229 + cz_enable_disable_vce_dpm(hwmgr, !bgate); 230 230 return 0; 231 231 } 232 232
+1 -1
drivers/gpu/drm/ast/ast_main.c
··· 227 227 } while (ast_read32(ast, 0x10000) != 0x01); 228 228 data = ast_read32(ast, 0x10004); 229 229 230 - if (data & 0x400) 230 + if (data & 0x40) 231 231 ast->dram_bus_width = 16; 232 232 else 233 233 ast->dram_bus_width = 32;
+15 -17
drivers/gpu/drm/i915/intel_runtime_pm.c
··· 2303 2303 */ 2304 2304 void intel_power_domains_suspend(struct drm_i915_private *dev_priv) 2305 2305 { 2306 - if (IS_SKYLAKE(dev_priv) || IS_KABYLAKE(dev_priv)) 2307 - skl_display_core_uninit(dev_priv); 2308 - 2309 2306 /* 2310 2307 * Even if power well support was disabled we still want to disable 2311 2308 * power wells while we are system suspended. 2312 2309 */ 2313 2310 if (!i915.disable_power_well) 2314 2311 intel_display_power_put(dev_priv, POWER_DOMAIN_INIT); 2312 + 2313 + if (IS_SKYLAKE(dev_priv) || IS_KABYLAKE(dev_priv)) 2314 + skl_display_core_uninit(dev_priv); 2315 2315 } 2316 2316 2317 2317 /** ··· 2349 2349 { 2350 2350 struct drm_device *dev = dev_priv->dev; 2351 2351 struct device *device = &dev->pdev->dev; 2352 - int ret; 2353 2352 2354 - if (!IS_ENABLED(CONFIG_PM)) 2355 - return true; 2353 + if (IS_ENABLED(CONFIG_PM)) { 2354 + int ret = pm_runtime_get_if_in_use(device); 2356 2355 2357 - ret = pm_runtime_get_if_in_use(device); 2358 - 2359 - /* 2360 - * In cases runtime PM is disabled by the RPM core and we get an 2361 - * -EINVAL return value we are not supposed to call this function, 2362 - * since the power state is undefined. This applies atm to the 2363 - * late/early system suspend/resume handlers. 2364 - */ 2365 - WARN_ON_ONCE(ret < 0); 2366 - if (ret <= 0) 2367 - return false; 2356 + /* 2357 + * In cases runtime PM is disabled by the RPM core and we get 2358 + * an -EINVAL return value we are not supposed to call this 2359 + * function, since the power state is undefined. This applies 2360 + * atm to the late/early system suspend/resume handlers. 2361 + */ 2362 + WARN_ON_ONCE(ret < 0); 2363 + if (ret <= 0) 2364 + return false; 2365 + } 2368 2366 2369 2367 atomic_inc(&dev_priv->pm.wakeref_count); 2370 2368 assert_rpm_wakelock_held(dev_priv);
+4 -4
drivers/gpu/drm/radeon/radeon_pm.c
··· 1080 1080 /* update display watermarks based on new power state */ 1081 1081 radeon_bandwidth_update(rdev); 1082 1082 1083 - rdev->pm.dpm.current_active_crtcs = rdev->pm.dpm.new_active_crtcs; 1084 - rdev->pm.dpm.current_active_crtc_count = rdev->pm.dpm.new_active_crtc_count; 1085 - rdev->pm.dpm.single_display = single_display; 1086 - 1087 1083 /* wait for the rings to drain */ 1088 1084 for (i = 0; i < RADEON_NUM_RINGS; i++) { 1089 1085 struct radeon_ring *ring = &rdev->ring[i]; ··· 1097 1101 1098 1102 /* update displays */ 1099 1103 radeon_dpm_display_configuration_changed(rdev); 1104 + 1105 + rdev->pm.dpm.current_active_crtcs = rdev->pm.dpm.new_active_crtcs; 1106 + rdev->pm.dpm.current_active_crtc_count = rdev->pm.dpm.new_active_crtc_count; 1107 + rdev->pm.dpm.single_display = single_display; 1100 1108 1101 1109 if (rdev->asic->dpm.force_performance_level) { 1102 1110 if (rdev->pm.dpm.thermal_active) {
+2
drivers/gpu/host1x/bus.c
··· 18 18 #include <linux/host1x.h> 19 19 #include <linux/of.h> 20 20 #include <linux/slab.h> 21 + #include <linux/of_device.h> 21 22 22 23 #include "bus.h" 23 24 #include "dev.h" ··· 395 394 device->dev.coherent_dma_mask = host1x->dev->coherent_dma_mask; 396 395 device->dev.dma_mask = &device->dev.coherent_dma_mask; 397 396 dev_set_name(&device->dev, "%s", driver->driver.name); 397 + of_dma_configure(&device->dev, host1x->dev->of_node); 398 398 device->dev.release = host1x_device_release; 399 399 device->dev.bus = &host1x_bus_type; 400 400 device->dev.parent = host1x->dev;
+7
drivers/gpu/host1x/dev.c
··· 23 23 #include <linux/of_device.h> 24 24 #include <linux/clk.h> 25 25 #include <linux/io.h> 26 + #include <linux/dma-mapping.h> 26 27 27 28 #define CREATE_TRACE_POINTS 28 29 #include <trace/events/host1x.h> ··· 69 68 .nb_bases = 8, 70 69 .init = host1x01_init, 71 70 .sync_offset = 0x3000, 71 + .dma_mask = DMA_BIT_MASK(32), 72 72 }; 73 73 74 74 static const struct host1x_info host1x02_info = { ··· 79 77 .nb_bases = 12, 80 78 .init = host1x02_init, 81 79 .sync_offset = 0x3000, 80 + .dma_mask = DMA_BIT_MASK(32), 82 81 }; 83 82 84 83 static const struct host1x_info host1x04_info = { ··· 89 86 .nb_bases = 64, 90 87 .init = host1x04_init, 91 88 .sync_offset = 0x2100, 89 + .dma_mask = DMA_BIT_MASK(34), 92 90 }; 93 91 94 92 static const struct host1x_info host1x05_info = { ··· 99 95 .nb_bases = 64, 100 96 .init = host1x05_init, 101 97 .sync_offset = 0x2100, 98 + .dma_mask = DMA_BIT_MASK(34), 102 99 }; 103 100 104 101 static struct of_device_id host1x_of_match[] = { ··· 152 147 host->regs = devm_ioremap_resource(&pdev->dev, regs); 153 148 if (IS_ERR(host->regs)) 154 149 return PTR_ERR(host->regs); 150 + 151 + dma_set_mask_and_coherent(host->dev, host->info->dma_mask); 155 152 156 153 if (host->info->init) { 157 154 err = host->info->init(host);
+1
drivers/gpu/host1x/dev.h
··· 96 96 int nb_mlocks; /* host1x: number of mlocks */ 97 97 int (*init)(struct host1x *); /* initialize per SoC ops */ 98 98 int sync_offset; 99 + u64 dma_mask; /* mask of addressable memory */ 99 100 }; 100 101 101 102 struct host1x {