tjh.dev / kernel
Linux kernel mirror (for testing) git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git
kernel os linux
1
fork

Configure Feed

Select the types of activity you want to include in your feed.

drm/amdgpu: Enable devcoredump for JPEG2_0_0

Add register list and enable devcoredump for JPEG2_0_0

V2: (Lijo)
- remove version specific callbacks and use simplified helper functions

V3: (Lijo)
- move amdgpu_jpeg_reg_dump_fini() to sw_fini() and avoid the call here

Signed-off-by: Sathishkumar S <sathishkumar.sundararaju@amd.com>
Reviewed-by: Leo Liu <leo.liu@amd.com>
Acked-by: Lijo Lazar <lijo.lazar@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>

authored by

Sathishkumar S and committed by
Alex Deucher 63d5f8db d949e91b

+22
+22
drivers/gpu/drm/amd/amdgpu/jpeg_v2_0.c
··· 33 33 #include "vcn/vcn_2_0_0_sh_mask.h" 34 34 #include "ivsrcid/vcn/irqsrcs_vcn_2_0.h" 35 35 36 + static const struct amdgpu_hwip_reg_entry jpeg_reg_list_2_0[] = { 37 + SOC15_REG_ENTRY_STR(JPEG, 0, mmUVD_JPEG_POWER_STATUS), 38 + SOC15_REG_ENTRY_STR(JPEG, 0, mmUVD_JPEG_INT_STAT), 39 + SOC15_REG_ENTRY_STR(JPEG, 0, mmUVD_JRBC_RB_RPTR), 40 + SOC15_REG_ENTRY_STR(JPEG, 0, mmUVD_JRBC_RB_WPTR), 41 + SOC15_REG_ENTRY_STR(JPEG, 0, mmUVD_JRBC_RB_CNTL), 42 + SOC15_REG_ENTRY_STR(JPEG, 0, mmUVD_JRBC_RB_SIZE), 43 + SOC15_REG_ENTRY_STR(JPEG, 0, mmUVD_JRBC_STATUS), 44 + SOC15_REG_ENTRY_STR(JPEG, 0, mmJPEG_DEC_ADDR_MODE), 45 + SOC15_REG_ENTRY_STR(JPEG, 0, mmJPEG_DEC_GFX10_ADDR_CONFIG), 46 + SOC15_REG_ENTRY_STR(JPEG, 0, mmJPEG_DEC_Y_GFX10_TILING_SURFACE), 47 + SOC15_REG_ENTRY_STR(JPEG, 0, mmJPEG_DEC_UV_GFX10_TILING_SURFACE), 48 + SOC15_REG_ENTRY_STR(JPEG, 0, mmUVD_JPEG_PITCH), 49 + SOC15_REG_ENTRY_STR(JPEG, 0, mmUVD_JPEG_UV_PITCH), 50 + }; 51 + 36 52 static void jpeg_v2_0_set_dec_ring_funcs(struct amdgpu_device *adev); 37 53 static void jpeg_v2_0_set_irq_funcs(struct amdgpu_device *adev); 38 54 static int jpeg_v2_0_set_powergating_state(struct amdgpu_ip_block *ip_block, ··· 113 97 114 98 adev->jpeg.internal.jpeg_pitch[0] = mmUVD_JPEG_PITCH_INTERNAL_OFFSET; 115 99 adev->jpeg.inst->external.jpeg_pitch[0] = SOC15_REG_OFFSET(JPEG, 0, mmUVD_JPEG_PITCH); 100 + 101 + r = amdgpu_jpeg_reg_dump_init(adev, jpeg_reg_list_2_0, ARRAY_SIZE(jpeg_reg_list_2_0)); 102 + if (r) 103 + return r; 116 104 117 105 return 0; 118 106 } ··· 772 752 .wait_for_idle = jpeg_v2_0_wait_for_idle, 773 753 .set_clockgating_state = jpeg_v2_0_set_clockgating_state, 774 754 .set_powergating_state = jpeg_v2_0_set_powergating_state, 755 + .dump_ip_state = amdgpu_jpeg_dump_ip_state, 756 + .print_ip_state = amdgpu_jpeg_print_ip_state, 775 757 }; 776 758 777 759 static const struct amdgpu_ring_funcs jpeg_v2_0_dec_ring_vm_funcs = {