x86/xen: Build identity mapping page tables dynamically for XENPV

After commit 47ffe0578aee ("x86/pvh: Add 64bit relocation page tables"),
the PVH entry uses a new set of page tables instead of the
preconstructed page tables in head64.S. Since those preconstructed page
tables are only used in XENPV now and XENPV does not actually need the
preconstructed identity page tables directly, they can be filled in
xen_setup_kernel_pagetable(). Therefore, build the identity mapping page
table dynamically to remove the preconstructed page tables and make the
code cleaner.

Signed-off-by: Hou Wenlong <houwenlong.hwl@antgroup.com>
Reviewed-by: Juergen Gross <jgross@suse.com>
Acked-by: "Borislav Petkov (AMD)" <bp@alien8.de>
Signed-off-by: Juergen Gross <jgross@suse.com>
Message-ID: <453981eae7e8158307f971d1632d5023adbe03c3.1769074722.git.houwenlong.hwl@antgroup.com>

authored by

Hou Wenlong and committed by

Juergen Gross 3 months ago 63dc2c34 5043d7ed

+9 -30

3 changed files

expand all

arch

x86

include

asm

pgtable_64.h

kernel

head_64.S

xen

mmu_pv.c

-2

arch/x86/include/asm/pgtable_64.h

··· 19 19 extern p4d_t level4_kernel_pgt[512]; 20 20 extern p4d_t level4_ident_pgt[512]; 21 21 extern pud_t level3_kernel_pgt[512]; 22 - extern pud_t level3_ident_pgt[512]; 23 22 extern pmd_t level2_kernel_pgt[512]; 24 23 extern pmd_t level2_fixmap_pgt[512]; 25 - extern pmd_t level2_ident_pgt[512]; 26 24 extern pte_t level1_fixmap_pgt[512 * FIXMAP_PMD_NUM]; 27 25 extern pgd_t init_top_pgt[]; 28 26

-28

arch/x86/kernel/head_64.S

··· 616 616 617 617 .data 618 618 619 - #if defined(CONFIG_XEN_PV) || defined(CONFIG_PVH) 620 - SYM_DATA_START_PTI_ALIGNED(init_top_pgt) 621 - .quad level3_ident_pgt - __START_KERNEL_map + _KERNPG_TABLE_NOENC 622 - .org init_top_pgt + L4_PAGE_OFFSET*8, 0 623 - .quad level3_ident_pgt - __START_KERNEL_map + _KERNPG_TABLE_NOENC 624 - .org init_top_pgt + L4_START_KERNEL*8, 0 625 - /* (2^48-(2*1024*1024*1024))/(2^39) = 511 */ 626 - .quad level3_kernel_pgt - __START_KERNEL_map + _PAGE_TABLE_NOENC 627 - .fill PTI_USER_PGD_FILL,8,0 628 - SYM_DATA_END(init_top_pgt) 629 - 630 - SYM_DATA_START_PAGE_ALIGNED(level3_ident_pgt) 631 - .quad level2_ident_pgt - __START_KERNEL_map + _KERNPG_TABLE_NOENC 632 - .fill 511, 8, 0 633 - SYM_DATA_END(level3_ident_pgt) 634 - SYM_DATA_START_PAGE_ALIGNED(level2_ident_pgt) 635 - /* 636 - * Since I easily can, map the first 1G. 637 - * Don't set NX because code runs from these pages. 638 - * 639 - * Note: This sets _PAGE_GLOBAL despite whether 640 - * the CPU supports it or it is enabled. But, 641 - * the CPU should ignore the bit. 642 - */ 643 - PMDS(0, __PAGE_KERNEL_IDENT_LARGE_EXEC, PTRS_PER_PMD) 644 - SYM_DATA_END(level2_ident_pgt) 645 - #else 646 619 SYM_DATA_START_PTI_ALIGNED(init_top_pgt) 647 620 .fill 512,8,0 648 621 .fill PTI_USER_PGD_FILL,8,0 649 622 SYM_DATA_END(init_top_pgt) 650 - #endif 651 623 652 624 SYM_DATA_START_PAGE_ALIGNED(level4_kernel_pgt) 653 625 .fill 511,8,0

arch/x86/xen/mmu_pv.c

··· 105 105 static pud_t level3_user_vsyscall[PTRS_PER_PUD] __page_aligned_bss; 106 106 #endif 107 107 108 + static pud_t level3_ident_pgt[PTRS_PER_PUD] __page_aligned_bss; 109 + static pmd_t level2_ident_pgt[PTRS_PER_PMD] __page_aligned_bss; 110 + 108 111 /* 109 112 * Protects atomic reservation decrease/increase against concurrent increases. 110 113 * Also protects non-atomic updates of current_pages and balloon lists. ··· 1779 1776 1780 1777 /* Zap identity mapping */ 1781 1778 init_top_pgt[0] = __pgd(0); 1779 + 1780 + init_top_pgt[pgd_index(__PAGE_OFFSET_BASE_L4)].pgd = 1781 + __pa_symbol(level3_ident_pgt) + _KERNPG_TABLE_NOENC; 1782 + init_top_pgt[pgd_index(__START_KERNEL_map)].pgd = 1783 + __pa_symbol(level3_kernel_pgt) + _PAGE_TABLE_NOENC; 1784 + level3_ident_pgt[0].pud = __pa_symbol(level2_ident_pgt) + _KERNPG_TABLE_NOENC; 1782 1785 1783 1786 /* Pre-constructed entries are in pfn, so convert to mfn */ 1784 1787 /* L4[273] -> level3_ident_pgt */

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