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drm/rockchip: dw_hdmi: switch to FIELD_PREP_WM16* macros

The era of hand-rolled HIWORD_UPDATE macros is over, at least for those
drivers that use constant masks.

Remove this driver's very own HIWORD_UPDATE macro, and replace all
instances of it with equivalent instantiations of FIELD_PREP_WM16 or
FIELD_PREP_WM16_CONST, depending on whether it's in an initializer.

This gives us better error checking, and a centrally agreed upon
signature for this macro, to ease in code comprehension.

Because FIELD_PREP_WM16/FIELD_PREP_WM16_CONST shifts the value to the
mask (like FIELD_PREP et al do), a lot of macro instantiations get
easier to read.

This was tested on an RK3568 ODROID M1, as well as an RK3399 ROCKPro64.

Reviewed-by: Cristian Ciocaltea <cristian.ciocaltea@collabora.com>
Tested-by: Cristian Ciocaltea <cristian.ciocaltea@collabora.com>
Signed-off-by: Nicolas Frattaroli <nicolas.frattaroli@collabora.com>
Reviewed-by: Heiko Stuebner <heiko@sntech.de>
Signed-off-by: Yury Norov (NVIDIA) <yury.norov@gmail.com>

authored by

Nicolas Frattaroli and committed by
Yury Norov 63df37f3 a104de64

+35 -43
+35 -43
drivers/gpu/drm/rockchip/dw_hdmi-rockchip.c
··· 4 4 */ 5 5 6 6 #include <linux/clk.h> 7 + #include <linux/hw_bitfield.h> 7 8 #include <linux/mfd/syscon.h> 8 9 #include <linux/module.h> 9 10 #include <linux/platform_device.h> ··· 54 53 #define RK3568_GRF_VO_CON1 0x0364 55 54 #define RK3568_HDMI_SDAIN_MSK BIT(15) 56 55 #define RK3568_HDMI_SCLIN_MSK BIT(14) 57 - 58 - #define HIWORD_UPDATE(val, mask) (val | (mask) << 16) 59 56 60 57 /** 61 58 * struct rockchip_hdmi_chip_data - splite the grf setting of kind of chips ··· 354 355 355 356 dw_hdmi_phy_setup_hpd(dw_hdmi, data); 356 357 357 - regmap_write(hdmi->regmap, 358 - RK3228_GRF_SOC_CON6, 359 - HIWORD_UPDATE(RK3228_HDMI_HPD_VSEL | RK3228_HDMI_SDA_VSEL | 360 - RK3228_HDMI_SCL_VSEL, 361 - RK3228_HDMI_HPD_VSEL | RK3228_HDMI_SDA_VSEL | 362 - RK3228_HDMI_SCL_VSEL)); 358 + regmap_write(hdmi->regmap, RK3228_GRF_SOC_CON6, 359 + FIELD_PREP_WM16(RK3228_HDMI_HPD_VSEL, 1) | 360 + FIELD_PREP_WM16(RK3228_HDMI_SDA_VSEL, 1) | 361 + FIELD_PREP_WM16(RK3228_HDMI_SCL_VSEL, 1)); 363 362 364 - regmap_write(hdmi->regmap, 365 - RK3228_GRF_SOC_CON2, 366 - HIWORD_UPDATE(RK3228_HDMI_SDAIN_MSK | RK3228_HDMI_SCLIN_MSK, 367 - RK3228_HDMI_SDAIN_MSK | RK3228_HDMI_SCLIN_MSK)); 363 + regmap_write(hdmi->regmap, RK3228_GRF_SOC_CON2, 364 + FIELD_PREP_WM16(RK3228_HDMI_SDAIN_MSK, 1) | 365 + FIELD_PREP_WM16(RK3328_HDMI_SCLIN_MSK, 1)); 368 366 } 369 367 370 368 static enum drm_connector_status ··· 373 377 status = dw_hdmi_phy_read_hpd(dw_hdmi, data); 374 378 375 379 if (status == connector_status_connected) 376 - regmap_write(hdmi->regmap, 377 - RK3328_GRF_SOC_CON4, 378 - HIWORD_UPDATE(RK3328_HDMI_SDA_5V | RK3328_HDMI_SCL_5V, 379 - RK3328_HDMI_SDA_5V | RK3328_HDMI_SCL_5V)); 380 + regmap_write(hdmi->regmap, RK3328_GRF_SOC_CON4, 381 + FIELD_PREP_WM16(RK3328_HDMI_SDA_5V, 1) | 382 + FIELD_PREP_WM16(RK3328_HDMI_SCL_5V, 1)); 380 383 else 381 - regmap_write(hdmi->regmap, 382 - RK3328_GRF_SOC_CON4, 383 - HIWORD_UPDATE(0, RK3328_HDMI_SDA_5V | 384 - RK3328_HDMI_SCL_5V)); 384 + regmap_write(hdmi->regmap, RK3328_GRF_SOC_CON4, 385 + FIELD_PREP_WM16(RK3328_HDMI_SDA_5V, 0) | 386 + FIELD_PREP_WM16(RK3328_HDMI_SCL_5V, 0)); 385 387 return status; 386 388 } 387 389 ··· 390 396 dw_hdmi_phy_setup_hpd(dw_hdmi, data); 391 397 392 398 /* Enable and map pins to 3V grf-controlled io-voltage */ 393 - regmap_write(hdmi->regmap, 394 - RK3328_GRF_SOC_CON4, 395 - HIWORD_UPDATE(0, RK3328_HDMI_HPD_SARADC | RK3328_HDMI_CEC_5V | 396 - RK3328_HDMI_SDA_5V | RK3328_HDMI_SCL_5V | 397 - RK3328_HDMI_HPD_5V)); 398 - regmap_write(hdmi->regmap, 399 - RK3328_GRF_SOC_CON3, 400 - HIWORD_UPDATE(0, RK3328_HDMI_SDA5V_GRF | RK3328_HDMI_SCL5V_GRF | 401 - RK3328_HDMI_HPD5V_GRF | 402 - RK3328_HDMI_CEC5V_GRF)); 403 - regmap_write(hdmi->regmap, 404 - RK3328_GRF_SOC_CON2, 405 - HIWORD_UPDATE(RK3328_HDMI_SDAIN_MSK | RK3328_HDMI_SCLIN_MSK, 406 - RK3328_HDMI_SDAIN_MSK | RK3328_HDMI_SCLIN_MSK | 407 - RK3328_HDMI_HPD_IOE)); 399 + regmap_write(hdmi->regmap, RK3328_GRF_SOC_CON4, 400 + FIELD_PREP_WM16(RK3328_HDMI_HPD_SARADC, 0) | 401 + FIELD_PREP_WM16(RK3328_HDMI_CEC_5V, 0) | 402 + FIELD_PREP_WM16(RK3328_HDMI_SDA_5V, 0) | 403 + FIELD_PREP_WM16(RK3328_HDMI_SCL_5V, 0) | 404 + FIELD_PREP_WM16(RK3328_HDMI_HPD_5V, 0)); 405 + regmap_write(hdmi->regmap, RK3328_GRF_SOC_CON3, 406 + FIELD_PREP_WM16(RK3328_HDMI_SDA5V_GRF, 0) | 407 + FIELD_PREP_WM16(RK3328_HDMI_SCL5V_GRF, 0) | 408 + FIELD_PREP_WM16(RK3328_HDMI_HPD5V_GRF, 0) | 409 + FIELD_PREP_WM16(RK3328_HDMI_CEC5V_GRF, 0)); 410 + regmap_write(hdmi->regmap, RK3328_GRF_SOC_CON2, 411 + FIELD_PREP_WM16(RK3328_HDMI_SDAIN_MSK, 1) | 412 + FIELD_PREP_WM16(RK3328_HDMI_SCLIN_MSK, 1) | 413 + FIELD_PREP_WM16(RK3328_HDMI_HPD_IOE, 0)); 408 414 409 415 dw_hdmi_rk3328_read_hpd(dw_hdmi, data); 410 416 } ··· 432 438 433 439 static struct rockchip_hdmi_chip_data rk3288_chip_data = { 434 440 .lcdsel_grf_reg = RK3288_GRF_SOC_CON6, 435 - .lcdsel_big = HIWORD_UPDATE(0, RK3288_HDMI_LCDC_SEL), 436 - .lcdsel_lit = HIWORD_UPDATE(RK3288_HDMI_LCDC_SEL, RK3288_HDMI_LCDC_SEL), 441 + .lcdsel_big = FIELD_PREP_WM16_CONST(RK3288_HDMI_LCDC_SEL, 0), 442 + .lcdsel_lit = FIELD_PREP_WM16_CONST(RK3288_HDMI_LCDC_SEL, 1), 437 443 .max_tmds_clock = 340000, 438 444 }; 439 445 ··· 469 475 470 476 static struct rockchip_hdmi_chip_data rk3399_chip_data = { 471 477 .lcdsel_grf_reg = RK3399_GRF_SOC_CON20, 472 - .lcdsel_big = HIWORD_UPDATE(0, RK3399_HDMI_LCDC_SEL), 473 - .lcdsel_lit = HIWORD_UPDATE(RK3399_HDMI_LCDC_SEL, RK3399_HDMI_LCDC_SEL), 478 + .lcdsel_big = FIELD_PREP_WM16_CONST(RK3399_HDMI_LCDC_SEL, 0), 479 + .lcdsel_lit = FIELD_PREP_WM16_CONST(RK3399_HDMI_LCDC_SEL, 1), 474 480 .max_tmds_clock = 594000, 475 481 }; 476 482 ··· 583 589 584 590 if (hdmi->chip_data == &rk3568_chip_data) { 585 591 regmap_write(hdmi->regmap, RK3568_GRF_VO_CON1, 586 - HIWORD_UPDATE(RK3568_HDMI_SDAIN_MSK | 587 - RK3568_HDMI_SCLIN_MSK, 588 - RK3568_HDMI_SDAIN_MSK | 589 - RK3568_HDMI_SCLIN_MSK)); 592 + FIELD_PREP_WM16(RK3568_HDMI_SDAIN_MSK, 1) | 593 + FIELD_PREP_WM16(RK3568_HDMI_SCLIN_MSK, 1)); 590 594 } 591 595 592 596 drm_encoder_helper_add(encoder, &dw_hdmi_rockchip_encoder_helper_funcs);