Linux kernel mirror (for testing)
git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git
kernel
os
linux
dt-bindings: clock: tegra124-dfll: Convert to json-schema
Convert the Tegra124 (and later) DFLL bindings from the free-form text
format to json-schema.
Co-developed-by: Rob Herring (Arm) <robh@kernel.org>
Signed-off-by: Rob Herring (Arm) <robh@kernel.org>
Reviewed-by: Rob Herring (Arm) <robh@kernel.org>
Signed-off-by: Thierry Reding <treding@nvidia.com>
+290
-155
-155
Documentation/devicetree/bindings/clock/nvidia,tegra124-dfll.txt
-155
Documentation/devicetree/bindings/clock/nvidia,tegra124-dfll.txt
···
1
-
NVIDIA Tegra124 DFLL FCPU clocksource
2
-
3
-
This binding uses the common clock binding:
4
-
Documentation/devicetree/bindings/clock/clock-bindings.txt
5
-
6
-
The DFLL IP block on Tegra is a root clocksource designed for clocking
7
-
the fast CPU cluster. It consists of a free-running voltage controlled
8
-
oscillator connected to the CPU voltage rail (VDD_CPU), and a closed loop
9
-
control module that will automatically adjust the VDD_CPU voltage by
10
-
communicating with an off-chip PMIC either via an I2C bus or via PWM signals.
11
-
12
-
Required properties:
13
-
- compatible : should be one of:
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- "nvidia,tegra124-dfll": for Tegra124
15
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- "nvidia,tegra210-dfll": for Tegra210
16
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- reg : Defines the following set of registers, in the order listed:
17
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- registers for the DFLL control logic.
18
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- registers for the I2C output logic.
19
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- registers for the integrated I2C master controller.
20
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- look-up table RAM for voltage register values.
21
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- interrupts: Should contain the DFLL block interrupt.
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-
- clocks: Must contain an entry for each entry in clock-names.
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See clock-bindings.txt for details.
24
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- clock-names: Must include the following entries:
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- soc: Clock source for the DFLL control logic.
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-
- ref: The closed loop reference clock
27
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- i2c: Clock source for the integrated I2C master.
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-
- resets: Must contain an entry for each entry in reset-names.
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See ../reset/reset.txt for details.
30
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- reset-names: Must include the following entries:
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- dvco: Reset control for the DFLL DVCO.
32
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- #clock-cells: Must be 0.
33
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- clock-output-names: Name of the clock output.
34
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- vdd-cpu-supply: Regulator for the CPU voltage rail that the DFLL
35
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hardware will start controlling. The regulator will be queried for
36
-
the I2C register, control values and supported voltages.
37
-
38
-
Required properties for the control loop parameters:
39
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- nvidia,sample-rate: Sample rate of the DFLL control loop.
40
-
- nvidia,droop-ctrl: See the register CL_DVFS_DROOP_CTRL in the TRM.
41
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- nvidia,force-mode: See the field DFLL_PARAMS_FORCE_MODE in the TRM.
42
-
- nvidia,cf: Numeric value, see the field DFLL_PARAMS_CF_PARAM in the TRM.
43
-
- nvidia,ci: Numeric value, see the field DFLL_PARAMS_CI_PARAM in the TRM.
44
-
- nvidia,cg: Numeric value, see the field DFLL_PARAMS_CG_PARAM in the TRM.
45
-
46
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Optional properties for the control loop parameters:
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- nvidia,cg-scale: Boolean value, see the field DFLL_PARAMS_CG_SCALE in the TRM.
48
-
49
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Optional properties for mode selection:
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- nvidia,pwm-to-pmic: Use PWM to control regulator rather then I2C.
51
-
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Required properties for I2C mode:
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- nvidia,i2c-fs-rate: I2C transfer rate, if using full speed mode.
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-
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Required properties for PWM mode:
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- nvidia,pwm-period-nanoseconds: period of PWM square wave in nanoseconds.
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-
- nvidia,pwm-tristate-microvolts: Regulator voltage in micro volts when PWM
58
-
control is disabled and the PWM output is tristated. Note that this voltage is
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configured in hardware, typically via a resistor divider.
60
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- nvidia,pwm-min-microvolts: Regulator voltage in micro volts when PWM control
61
-
is enabled and PWM output is low. Hence, this is the minimum output voltage
62
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that the regulator supports when PWM control is enabled.
63
-
- nvidia,pwm-voltage-step-microvolts: Voltage increase in micro volts
64
-
corresponding to a 1/33th increase in duty cycle. Eg the voltage for 2/33th
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duty cycle would be: nvidia,pwm-min-microvolts +
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nvidia,pwm-voltage-step-microvolts * 2.
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- pinctrl-0: I/O pad configuration when PWM control is enabled.
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- pinctrl-1: I/O pad configuration when PWM control is disabled.
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- pinctrl-names: must include the following entries:
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- dvfs_pwm_enable: I/O pad configuration when PWM control is enabled.
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- dvfs_pwm_disable: I/O pad configuration when PWM control is disabled.
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-
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Example for I2C:
74
-
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clock@70110000 {
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compatible = "nvidia,tegra124-dfll";
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reg = <0 0x70110000 0 0x100>, /* DFLL control */
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<0 0x70110000 0 0x100>, /* I2C output control */
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<0 0x70110100 0 0x100>, /* Integrated I2C controller */
80
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<0 0x70110200 0 0x100>; /* Look-up table RAM */
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interrupts = <GIC_SPI 62 IRQ_TYPE_LEVEL_HIGH>;
82
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clocks = <&tegra_car TEGRA124_CLK_DFLL_SOC>,
83
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<&tegra_car TEGRA124_CLK_DFLL_REF>,
84
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<&tegra_car TEGRA124_CLK_I2C5>;
85
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clock-names = "soc", "ref", "i2c";
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resets = <&tegra_car TEGRA124_RST_DFLL_DVCO>;
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reset-names = "dvco";
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#clock-cells = <0>;
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clock-output-names = "dfllCPU_out";
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vdd-cpu-supply = <&vdd_cpu>;
91
-
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nvidia,sample-rate = <12500>;
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nvidia,droop-ctrl = <0x00000f00>;
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nvidia,force-mode = <1>;
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nvidia,cf = <10>;
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nvidia,ci = <0>;
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nvidia,cg = <2>;
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-
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nvidia,i2c-fs-rate = <400000>;
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};
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-
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Example for PWM:
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-
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clock@70110000 {
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compatible = "nvidia,tegra124-dfll";
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reg = <0 0x70110000 0 0x100>, /* DFLL control */
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<0 0x70110000 0 0x100>, /* I2C output control */
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<0 0x70110100 0 0x100>, /* Integrated I2C controller */
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<0 0x70110200 0 0x100>; /* Look-up table RAM */
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interrupts = <GIC_SPI 62 IRQ_TYPE_LEVEL_HIGH>;
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clocks = <&tegra_car TEGRA210_CLK_DFLL_SOC>,
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<&tegra_car TEGRA210_CLK_DFLL_REF>,
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<&tegra_car TEGRA124_CLK_I2C5>;;
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clock-names = "soc", "ref", "i2c";
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resets = <&tegra_car TEGRA124_RST_DFLL_DVCO>;
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reset-names = "dvco";
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#clock-cells = <0>;
118
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clock-output-names = "dfllCPU_out";
119
-
120
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nvidia,sample-rate = <25000>;
121
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nvidia,droop-ctrl = <0x00000f00>;
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nvidia,force-mode = <1>;
123
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nvidia,cf = <6>;
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nvidia,ci = <0>;
125
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nvidia,cg = <2>;
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-
127
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nvidia,pwm-min-microvolts = <708000>; /* 708mV */
128
-
nvidia,pwm-period-nanoseconds = <2500>; /* 2.5us */
129
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nvidia,pwm-to-pmic;
130
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nvidia,pwm-tristate-microvolts = <1000000>;
131
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nvidia,pwm-voltage-step-microvolts = <19200>; /* 19.2mV */
132
-
133
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pinctrl-names = "dvfs_pwm_enable", "dvfs_pwm_disable";
134
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pinctrl-0 = <&dvfs_pwm_active_state>;
135
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pinctrl-1 = <&dvfs_pwm_inactive_state>;
136
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};
137
-
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/* pinmux nodes added for completeness. Binding doc can be found in:
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* Documentation/devicetree/bindings/pinctrl/nvidia,tegra210-pinmux.yaml
140
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*/
141
-
142
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pinmux: pinmux@700008d4 {
143
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dvfs_pwm_active_state: dvfs_pwm_active {
144
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dvfs_pwm_pbb1 {
145
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nvidia,pins = "dvfs_pwm_pbb1";
146
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nvidia,tristate = <TEGRA_PIN_DISABLE>;
147
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};
148
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};
149
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dvfs_pwm_inactive_state: dvfs_pwm_inactive {
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dvfs_pwm_pbb1 {
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nvidia,pins = "dvfs_pwm_pbb1";
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nvidia,tristate = <TEGRA_PIN_ENABLE>;
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};
154
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};
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};
+290
Documentation/devicetree/bindings/clock/nvidia,tegra124-dfll.yaml
+290
Documentation/devicetree/bindings/clock/nvidia,tegra124-dfll.yaml
···
1
+
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
2
+
%YAML 1.2
3
+
---
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$id: http://devicetree.org/schemas/clock/nvidia,tegra124-dfll.yaml#
5
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$schema: http://devicetree.org/meta-schemas/core.yaml#
6
+
7
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title: NVIDIA Tegra124 (and later) DFLL FCPU clocksource
8
+
9
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maintainers:
10
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- Thierry Reding <thierry.reding@gmail.com>
11
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- Jon Hunter <jonathanh@nvidia.com>
12
+
13
+
description:
14
+
The DFLL IP block on Tegra is a root clocksource designed for clocking
15
+
the fast CPU cluster. It consists of a free-running voltage controlled
16
+
oscillator connected to the CPU voltage rail (VDD_CPU), and a closed
17
+
loop control module that will automatically adjust the VDD_CPU voltage
18
+
by communicating with an off-chip PMIC either via an I2C bus or via
19
+
PWM signals.
20
+
21
+
properties:
22
+
compatible:
23
+
enum:
24
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- nvidia,tegra124-dfll
25
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- nvidia,tegra210-dfll
26
+
27
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reg:
28
+
items:
29
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- description: DFLL control logic
30
+
- description: I2C output logic
31
+
- description: Integrated I2C controller
32
+
- description: Look-up table RAM for voltage register values
33
+
34
+
interrupts:
35
+
maxItems: 1
36
+
37
+
"#clock-cells":
38
+
const: 0
39
+
40
+
clocks:
41
+
items:
42
+
- description: Clock source for the DFLL control logic
43
+
- description: Closed loop reference clock
44
+
- description: Clock source for the integrated I2C controller
45
+
46
+
clock-names:
47
+
items:
48
+
- const: soc
49
+
- const: ref
50
+
- const: i2c
51
+
52
+
clock-output-names:
53
+
description: Name of the clock output
54
+
items:
55
+
- const: dfllCPU_out
56
+
57
+
resets:
58
+
minItems: 1
59
+
maxItems: 2
60
+
61
+
reset-names:
62
+
minItems: 1
63
+
items:
64
+
- const: dvco
65
+
- const: dfll
66
+
67
+
vdd-cpu-supply:
68
+
description: Regulator for the CPU voltage rail that the DFLL
69
+
hardware will start controlling. The regulator will be queried for
70
+
the I2C register, control values and supported voltages.
71
+
72
+
nvidia,sample-rate:
73
+
description: Sample rate of the DFLL control loop
74
+
$ref: /schemas/types.yaml#/definitions/uint32
75
+
minimum: 12500
76
+
maximum: 25000
77
+
78
+
nvidia,droop-ctrl:
79
+
description: Droop control parameter (CL_DVFS_DROOP_CTRL) in the TRM
80
+
$ref: /schemas/types.yaml#/definitions/uint32
81
+
82
+
nvidia,force-mode:
83
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description: See the field DFLL_PARAMS_FORCE_MODE in the TRM
84
+
$ref: /schemas/types.yaml#/definitions/uint32
85
+
oneOf:
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+
- description: disabled
87
+
const: 0
88
+
- description: fixed delay mode
89
+
const: 1
90
+
- description: auto mode
91
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const: 2
92
+
93
+
nvidia,cf:
94
+
description: Numeric value, see the field DFLL_PARAMS_CF_PARAM in the TRM
95
+
$ref: /schemas/types.yaml#/definitions/uint32
96
+
minimum: 0
97
+
maximum: 63
98
+
99
+
nvidia,ci:
100
+
description: Numeric value, see the field DFLL_PARAMS_CI_PARAM in the TRM
101
+
$ref: /schemas/types.yaml#/definitions/uint32
102
+
minimum: 0
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+
maximum: 7
104
+
105
+
nvidia,cg:
106
+
description: Numeric value, see the field DFLL_PARAMS_CG_PARAM in the TRM
107
+
$ref: /schemas/types.yaml#/definitions/uint32
108
+
minimum: 0
109
+
maximum: 255
110
+
111
+
# optional properties
112
+
nvidia,cg-scale:
113
+
description: Boolean value, see the field DFLL_PARAMS_CG_SCALE in the TRM
114
+
$ref: /schemas/types.yaml#/definitions/flag
115
+
116
+
nvidia,pwm-to-pmic:
117
+
description: Use PWM to control regulator rather than I2C
118
+
$ref: /schemas/types.yaml#/definitions/flag
119
+
120
+
nvidia,i2c-fs-rate:
121
+
description: I2C transfer rate, if using full speed mode
122
+
$ref: /schemas/types.yaml#/definitions/uint32
123
+
enum: [100000, 400000]
124
+
125
+
# required properties for PWM mode
126
+
nvidia,pwm-period-nanoseconds:
127
+
description: Period of PWM square wave in nanoseconds
128
+
$ref: /schemas/types.yaml#/definitions/uint32
129
+
minimum: 1000
130
+
maximum: 1000000000
131
+
132
+
nvidia,pwm-tristate-microvolts:
133
+
description: Regulator voltage in microvolts when PWM control is disabled
134
+
and the PWM output is tristated. Note that this voltage is configured in
135
+
hardware, typically via a resistor divider.
136
+
$ref: /schemas/types.yaml#/definitions/uint32
137
+
minimum: 0
138
+
maximum: 3300000
139
+
140
+
nvidia,pwm-min-microvolts:
141
+
description: Regulator voltage in microvolts when PWM control is enabled
142
+
and PWM output is low. Hence, this is the minimum output voltage that
143
+
the regulator supports when PWM control is enabled.
144
+
$ref: /schemas/types.yaml#/definitions/uint32
145
+
minimum: 0
146
+
maximum: 3300000
147
+
148
+
nvidia,pwm-voltage-step-microvolts:
149
+
description: |
150
+
Voltage increase in micro volts corresponding to a 1/33th increase
151
+
in duty cycle. For example, the voltage for 2/33th duty cycle would be:
152
+
153
+
nvidia,pwm-min-microvolts + nvidia,pwm-voltage-step-microvolts * 2
154
+
$ref: /schemas/types.yaml#/definitions/uint32
155
+
minimum: 0
156
+
maximum: 100000
157
+
158
+
pinctrl-0:
159
+
description: I/O pad configuration when PWM control is enabled
160
+
161
+
pinctrl-1:
162
+
description: I/O pad configuration when PWM control is disabled
163
+
164
+
pinctrl-names:
165
+
items:
166
+
- const: dvfs_pwm_enable
167
+
- const: dvfs_pwm_disable
168
+
169
+
required:
170
+
- compatible
171
+
- reg
172
+
- interrupts
173
+
- "#clock-cells"
174
+
- clocks
175
+
- clock-names
176
+
- clock-output-names
177
+
- resets
178
+
- reset-names
179
+
- nvidia,sample-rate
180
+
- nvidia,droop-ctrl
181
+
- nvidia,force-mode
182
+
- nvidia,cf
183
+
- nvidia,ci
184
+
- nvidia,cg
185
+
186
+
additionalProperties: false
187
+
188
+
allOf:
189
+
- if:
190
+
properties:
191
+
compatible:
192
+
contains:
193
+
const: nvidia,tegra124-dfll
194
+
then:
195
+
properties:
196
+
resets:
197
+
maxItems: 1
198
+
199
+
reset-names:
200
+
maxItems: 1
201
+
else:
202
+
properties:
203
+
resets:
204
+
minItems: 2
205
+
206
+
reset-names:
207
+
minItems: 2
208
+
209
+
- if:
210
+
required:
211
+
- nvidia,pwm-to-pmic
212
+
then:
213
+
required:
214
+
- nvidia,pwm-min-microvolts
215
+
- nvidia,pwm-period-nanoseconds
216
+
- nvidia,pwm-tristate-microvolts
217
+
- nvidia,pwm-voltage-step-microvolts
218
+
else:
219
+
required:
220
+
- vdd-cpu-supply
221
+
222
+
examples:
223
+
- |
224
+
#include <dt-bindings/clock/tegra124-car.h>
225
+
#include <dt-bindings/interrupt-controller/arm-gic.h>
226
+
#include <dt-bindings/reset/tegra124-car.h>
227
+
228
+
clock@70110000 {
229
+
compatible = "nvidia,tegra124-dfll";
230
+
reg = <0x70110000 0x100>, /* DFLL control */
231
+
<0x70110000 0x100>, /* I2C output control */
232
+
<0x70110100 0x100>, /* Integrated I2C controller */
233
+
<0x70110200 0x100>; /* Look-up table RAM */
234
+
interrupts = <GIC_SPI 62 IRQ_TYPE_LEVEL_HIGH>;
235
+
clocks = <&tegra_car TEGRA124_CLK_DFLL_SOC>,
236
+
<&tegra_car TEGRA124_CLK_DFLL_REF>,
237
+
<&tegra_car TEGRA124_CLK_I2C5>;
238
+
clock-names = "soc", "ref", "i2c";
239
+
resets = <&tegra_car TEGRA124_RST_DFLL_DVCO>;
240
+
reset-names = "dvco";
241
+
#clock-cells = <0>;
242
+
clock-output-names = "dfllCPU_out";
243
+
vdd-cpu-supply = <&vdd_cpu>;
244
+
245
+
nvidia,sample-rate = <12500>;
246
+
nvidia,droop-ctrl = <0x00000f00>;
247
+
nvidia,force-mode = <1>;
248
+
nvidia,cf = <10>;
249
+
nvidia,ci = <0>;
250
+
nvidia,cg = <2>;
251
+
252
+
nvidia,i2c-fs-rate = <400000>;
253
+
};
254
+
255
+
- |
256
+
#include <dt-bindings/clock/tegra210-car.h>
257
+
#include <dt-bindings/interrupt-controller/arm-gic.h>
258
+
#include <dt-bindings/reset/tegra210-car.h>
259
+
260
+
clock@70110000 {
261
+
compatible = "nvidia,tegra210-dfll";
262
+
reg = <0x70110000 0x100>, /* DFLL control */
263
+
<0x70110000 0x100>, /* I2C output control */
264
+
<0x70110100 0x100>, /* Integrated I2C controller */
265
+
<0x70110200 0x100>; /* Look-up table RAM */
266
+
interrupts = <GIC_SPI 62 IRQ_TYPE_LEVEL_HIGH>;
267
+
clocks = <&tegra_car TEGRA210_CLK_DFLL_SOC>,
268
+
<&tegra_car TEGRA210_CLK_DFLL_REF>,
269
+
<&tegra_car TEGRA210_CLK_I2C5>;
270
+
clock-names = "soc", "ref", "i2c";
271
+
resets = <&tegra_car TEGRA210_RST_DFLL_DVCO>,
272
+
<&tegra_car 155>;
273
+
reset-names = "dvco", "dfll";
274
+
#clock-cells = <0>;
275
+
clock-output-names = "dfllCPU_out";
276
+
vdd-cpu-supply = <&vdd_cpu>;
277
+
278
+
nvidia,sample-rate = <25000>;
279
+
nvidia,droop-ctrl = <0x00000f00>;
280
+
nvidia,force-mode = <1>;
281
+
nvidia,cf = <6>;
282
+
nvidia,ci = <0>;
283
+
nvidia,cg = <2>;
284
+
285
+
nvidia,pwm-min-microvolts = <708000>; /* 708mV */
286
+
nvidia,pwm-period-nanoseconds = <2500>; /* 2.5us */
287
+
nvidia,pwm-to-pmic;
288
+
nvidia,pwm-tristate-microvolts = <1000000>;
289
+
nvidia,pwm-voltage-step-microvolts = <19200>; /* 19.2mV */
290
+
};