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arm64: mm: Refactor flush_tlb_page() to use __tlbi_level_asid()

Now that we have __tlbi_level_asid(), let's refactor the
*flush_tlb_page*() variants to use it rather than open coding.

The emitted tlbi(s) is/are intended to be exactly the same as before; no
TTL hint is provided. Although the spec for flush_tlb_page() allows for
setting the TTL hint to 3, it turns out that
flush_tlb_fix_spurious_fault_pmd() depends on
local_flush_tlb_page_nonotify() to invalidate the level 2 entry. This
will be fixed separately.

Reviewed-by: Linu Cherian <linu.cherian@arm.com>
Reviewed-by: Jonathan Cameron <jonathan.cameron@huawei.com>
Signed-off-by: Ryan Roberts <ryan.roberts@arm.com>
Signed-off-by: Catalin Marinas <catalin.marinas@arm.com>

authored by

Ryan Roberts and committed by
Catalin Marinas 64212d68 c753d667

+2 -10
+2 -10
arch/arm64/include/asm/tlbflush.h
··· 346 346 static inline void __local_flush_tlb_page_nonotify_nosync(struct mm_struct *mm, 347 347 unsigned long uaddr) 348 348 { 349 - unsigned long addr; 350 - 351 349 dsb(nshst); 352 - addr = __TLBI_VADDR(uaddr, ASID(mm)); 353 - __tlbi(vale1, addr); 354 - __tlbi_user(vale1, addr); 350 + __tlbi_level_asid(vale1, uaddr, TLBI_TTL_UNKNOWN, ASID(mm)); 355 351 } 356 352 357 353 static inline void local_flush_tlb_page_nonotify(struct vm_area_struct *vma, ··· 369 373 static inline void __flush_tlb_page_nosync(struct mm_struct *mm, 370 374 unsigned long uaddr) 371 375 { 372 - unsigned long addr; 373 - 374 376 dsb(ishst); 375 - addr = __TLBI_VADDR(uaddr, ASID(mm)); 376 - __tlbi(vale1is, addr); 377 - __tlbi_user(vale1is, addr); 377 + __tlbi_level_asid(vale1is, uaddr, TLBI_TTL_UNKNOWN, ASID(mm)); 378 378 mmu_notifier_arch_invalidate_secondary_tlbs(mm, uaddr & PAGE_MASK, 379 379 (uaddr & PAGE_MASK) + PAGE_SIZE); 380 380 }