Linux kernel mirror (for testing)
git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git
kernel
os
linux
Merge tag 'drm-fixes-2021-10-22' of git://anongit.freedesktop.org/drm/drm
Pull drm fixes from Dave Airlie:
"Nothing too crazy at the end of the cycle, the kmb modesetting fixes
are probably a bit large but it's not a major driver, and its fixing
monitor doesn't turn on type problems.
Otherwise it's just a few minor patches, one ast regression revert, an
msm power stability fix.
ast:
- fix regression with connector detect
msm:
- fix power stability issue
msxfb:
- fix crash on unload
panel:
- sync fix
kmb:
- modesetting fixes"
* tag 'drm-fixes-2021-10-22' of git://anongit.freedesktop.org/drm/drm:
Revert "drm/ast: Add detect function support"
drm/kmb: Enable ADV bridge after modeset
drm/kmb: Corrected typo in handle_lcd_irq
drm/kmb: Disable change of plane parameters
drm/kmb: Remove clearing DPHY regs
drm/kmb: Limit supported mode to 1080p
drm/kmb: Work around for higher system clock
drm/panel: ilitek-ili9881c: Fix sync for Feixin K101-IM2BYL02 panel
drm: mxsfb: Fix NULL pointer dereference crash on unload
drm/msm/devfreq: Restrict idle clamping to a618 for now
+137
-42
+1
-17
drivers/gpu/drm/ast/ast_mode.c
+1
-17
drivers/gpu/drm/ast/ast_mode.c
···
1300
1300
return flags;
1301
1301
}
1302
1302
1303
-
static enum drm_connector_status ast_connector_detect(struct drm_connector
1304
-
*connector, bool force)
1305
-
{
1306
-
int r;
1307
-
1308
-
r = ast_get_modes(connector);
1309
-
if (r <= 0)
1310
-
return connector_status_disconnected;
1311
-
1312
-
return connector_status_connected;
1313
-
}
1314
-
1315
1303
static void ast_connector_destroy(struct drm_connector *connector)
1316
1304
{
1317
1305
struct ast_connector *ast_connector = to_ast_connector(connector);
···
1315
1327
1316
1328
static const struct drm_connector_funcs ast_connector_funcs = {
1317
1329
.reset = drm_atomic_helper_connector_reset,
1318
-
.detect = ast_connector_detect,
1319
1330
.fill_modes = drm_helper_probe_single_connector_modes,
1320
1331
.destroy = ast_connector_destroy,
1321
1332
.atomic_duplicate_state = drm_atomic_helper_connector_duplicate_state,
···
1342
1355
connector->interlace_allowed = 0;
1343
1356
connector->doublescan_allowed = 0;
1344
1357
1345
-
connector->polled = DRM_CONNECTOR_POLL_CONNECT |
1346
-
DRM_CONNECTOR_POLL_DISCONNECT;
1358
+
connector->polled = DRM_CONNECTOR_POLL_CONNECT;
1347
1359
1348
1360
drm_connector_attach_encoder(connector, encoder);
1349
1361
···
1410
1424
ast_connector_init(dev);
1411
1425
1412
1426
drm_mode_config_reset(dev);
1413
-
1414
-
drm_kms_helper_poll_init(dev);
1415
1427
1416
1428
return 0;
1417
1429
}
+38
-3
drivers/gpu/drm/kmb/kmb_crtc.c
+38
-3
drivers/gpu/drm/kmb/kmb_crtc.c
···
66
66
.disable_vblank = kmb_crtc_disable_vblank,
67
67
};
68
68
69
-
static void kmb_crtc_set_mode(struct drm_crtc *crtc)
69
+
static void kmb_crtc_set_mode(struct drm_crtc *crtc,
70
+
struct drm_atomic_state *old_state)
70
71
{
71
72
struct drm_device *dev = crtc->dev;
72
73
struct drm_display_mode *m = &crtc->state->adjusted_mode;
···
76
75
unsigned int val = 0;
77
76
78
77
/* Initialize mipi */
79
-
kmb_dsi_mode_set(kmb->kmb_dsi, m, kmb->sys_clk_mhz);
78
+
kmb_dsi_mode_set(kmb->kmb_dsi, m, kmb->sys_clk_mhz, old_state);
80
79
drm_info(dev,
81
80
"vfp= %d vbp= %d vsync_len=%d hfp=%d hbp=%d hsync_len=%d\n",
82
81
m->crtc_vsync_start - m->crtc_vdisplay,
···
139
138
struct kmb_drm_private *kmb = crtc_to_kmb_priv(crtc);
140
139
141
140
clk_prepare_enable(kmb->kmb_clk.clk_lcd);
142
-
kmb_crtc_set_mode(crtc);
141
+
kmb_crtc_set_mode(crtc, state);
143
142
drm_crtc_vblank_on(crtc);
144
143
}
145
144
···
186
185
spin_unlock_irq(&crtc->dev->event_lock);
187
186
}
188
187
188
+
static enum drm_mode_status
189
+
kmb_crtc_mode_valid(struct drm_crtc *crtc,
190
+
const struct drm_display_mode *mode)
191
+
{
192
+
int refresh;
193
+
struct drm_device *dev = crtc->dev;
194
+
int vfp = mode->vsync_start - mode->vdisplay;
195
+
196
+
if (mode->vdisplay < KMB_CRTC_MAX_HEIGHT) {
197
+
drm_dbg(dev, "height = %d less than %d",
198
+
mode->vdisplay, KMB_CRTC_MAX_HEIGHT);
199
+
return MODE_BAD_VVALUE;
200
+
}
201
+
if (mode->hdisplay < KMB_CRTC_MAX_WIDTH) {
202
+
drm_dbg(dev, "width = %d less than %d",
203
+
mode->hdisplay, KMB_CRTC_MAX_WIDTH);
204
+
return MODE_BAD_HVALUE;
205
+
}
206
+
refresh = drm_mode_vrefresh(mode);
207
+
if (refresh < KMB_MIN_VREFRESH || refresh > KMB_MAX_VREFRESH) {
208
+
drm_dbg(dev, "refresh = %d less than %d or greater than %d",
209
+
refresh, KMB_MIN_VREFRESH, KMB_MAX_VREFRESH);
210
+
return MODE_BAD;
211
+
}
212
+
213
+
if (vfp < KMB_CRTC_MIN_VFP) {
214
+
drm_dbg(dev, "vfp = %d less than %d", vfp, KMB_CRTC_MIN_VFP);
215
+
return MODE_BAD;
216
+
}
217
+
218
+
return MODE_OK;
219
+
}
220
+
189
221
static const struct drm_crtc_helper_funcs kmb_crtc_helper_funcs = {
190
222
.atomic_begin = kmb_crtc_atomic_begin,
191
223
.atomic_enable = kmb_crtc_atomic_enable,
192
224
.atomic_disable = kmb_crtc_atomic_disable,
193
225
.atomic_flush = kmb_crtc_atomic_flush,
226
+
.mode_valid = kmb_crtc_mode_valid,
194
227
};
195
228
196
229
int kmb_setup_crtc(struct drm_device *drm)
+1
-1
drivers/gpu/drm/kmb/kmb_drv.c
+1
-1
drivers/gpu/drm/kmb/kmb_drv.c
···
380
380
if (val & LAYER3_DMA_FIFO_UNDERFLOW)
381
381
drm_dbg(&kmb->drm,
382
382
"LAYER3:GL1 DMA UNDERFLOW val = 0x%lx", val);
383
-
if (val & LAYER3_DMA_FIFO_UNDERFLOW)
383
+
if (val & LAYER3_DMA_FIFO_OVERFLOW)
384
384
drm_dbg(&kmb->drm,
385
385
"LAYER3:GL1 DMA OVERFLOW val = 0x%lx", val);
386
386
}
+9
-1
drivers/gpu/drm/kmb/kmb_drv.h
+9
-1
drivers/gpu/drm/kmb/kmb_drv.h
···
20
20
#define DRIVER_MAJOR 1
21
21
#define DRIVER_MINOR 1
22
22
23
+
/* Platform definitions */
24
+
#define KMB_CRTC_MIN_VFP 4
25
+
#define KMB_CRTC_MAX_WIDTH 1920 /* max width in pixels */
26
+
#define KMB_CRTC_MAX_HEIGHT 1080 /* max height in pixels */
27
+
#define KMB_CRTC_MIN_WIDTH 1920
28
+
#define KMB_CRTC_MIN_HEIGHT 1080
23
29
#define KMB_FB_MAX_WIDTH 1920
24
30
#define KMB_FB_MAX_HEIGHT 1080
25
31
#define KMB_FB_MIN_WIDTH 1
26
32
#define KMB_FB_MIN_HEIGHT 1
27
-
33
+
#define KMB_MIN_VREFRESH 59 /*vertical refresh in Hz */
34
+
#define KMB_MAX_VREFRESH 60 /*vertical refresh in Hz */
28
35
#define KMB_LCD_DEFAULT_CLK 200000000
29
36
#define KMB_SYS_CLK_MHZ 500
30
37
···
57
50
spinlock_t irq_lock;
58
51
int irq_lcd;
59
52
int sys_clk_mhz;
53
+
struct disp_cfg init_disp_cfg[KMB_MAX_PLANES];
60
54
struct layer_status plane_status[KMB_MAX_PLANES];
61
55
int kmb_under_flow;
62
56
int kmb_flush_done;
+15
-10
drivers/gpu/drm/kmb/kmb_dsi.c
+15
-10
drivers/gpu/drm/kmb/kmb_dsi.c
···
482
482
return 0;
483
483
}
484
484
485
+
#define CLK_DIFF_LOW 50
486
+
#define CLK_DIFF_HI 60
487
+
#define SYSCLK_500 500
488
+
485
489
static void mipi_tx_fg_cfg_regs(struct kmb_dsi *kmb_dsi, u8 frame_gen,
486
490
struct mipi_tx_frame_timing_cfg *fg_cfg)
487
491
{
···
496
492
/* 500 Mhz system clock minus 50 to account for the difference in
497
493
* MIPI clock speed in RTL tests
498
494
*/
499
-
sysclk = kmb_dsi->sys_clk_mhz - 50;
495
+
if (kmb_dsi->sys_clk_mhz == SYSCLK_500) {
496
+
sysclk = kmb_dsi->sys_clk_mhz - CLK_DIFF_LOW;
497
+
} else {
498
+
/* 700 Mhz clk*/
499
+
sysclk = kmb_dsi->sys_clk_mhz - CLK_DIFF_HI;
500
+
}
500
501
501
502
/* PPL-Pixel Packing Layer, LLP-Low Level Protocol
502
503
* Frame genartor timing parameters are clocked on the system clock,
···
1331
1322
return 0;
1332
1323
}
1333
1324
1334
-
static void connect_lcd_to_mipi(struct kmb_dsi *kmb_dsi)
1325
+
static void connect_lcd_to_mipi(struct kmb_dsi *kmb_dsi,
1326
+
struct drm_atomic_state *old_state)
1335
1327
{
1336
1328
struct regmap *msscam;
1337
1329
···
1341
1331
dev_dbg(kmb_dsi->dev, "failed to get msscam syscon");
1342
1332
return;
1343
1333
}
1344
-
1334
+
drm_atomic_bridge_chain_enable(adv_bridge, old_state);
1345
1335
/* DISABLE MIPI->CIF CONNECTION */
1346
1336
regmap_write(msscam, MSS_MIPI_CIF_CFG, 0);
1347
1337
···
1352
1342
}
1353
1343
1354
1344
int kmb_dsi_mode_set(struct kmb_dsi *kmb_dsi, struct drm_display_mode *mode,
1355
-
int sys_clk_mhz)
1345
+
int sys_clk_mhz, struct drm_atomic_state *old_state)
1356
1346
{
1357
1347
u64 data_rate;
1358
1348
···
1394
1384
mipi_tx_init_cfg.lane_rate_mbps = data_rate;
1395
1385
}
1396
1386
1397
-
kmb_write_mipi(kmb_dsi, DPHY_ENABLE, 0);
1398
-
kmb_write_mipi(kmb_dsi, DPHY_INIT_CTRL0, 0);
1399
-
kmb_write_mipi(kmb_dsi, DPHY_INIT_CTRL1, 0);
1400
-
kmb_write_mipi(kmb_dsi, DPHY_INIT_CTRL2, 0);
1401
-
1402
1387
/* Initialize mipi controller */
1403
1388
mipi_tx_init_cntrl(kmb_dsi, &mipi_tx_init_cfg);
1404
1389
1405
1390
/* Dphy initialization */
1406
1391
mipi_tx_init_dphy(kmb_dsi, &mipi_tx_init_cfg);
1407
1392
1408
-
connect_lcd_to_mipi(kmb_dsi);
1393
+
connect_lcd_to_mipi(kmb_dsi, old_state);
1409
1394
dev_info(kmb_dsi->dev, "mipi hw initialized");
1410
1395
1411
1396
return 0;
+1
-1
drivers/gpu/drm/kmb/kmb_dsi.h
+1
-1
drivers/gpu/drm/kmb/kmb_dsi.h
···
380
380
struct kmb_dsi *kmb_dsi_init(struct platform_device *pdev);
381
381
void kmb_dsi_host_unregister(struct kmb_dsi *kmb_dsi);
382
382
int kmb_dsi_mode_set(struct kmb_dsi *kmb_dsi, struct drm_display_mode *mode,
383
-
int sys_clk_mhz);
383
+
int sys_clk_mhz, struct drm_atomic_state *old_state);
384
384
int kmb_dsi_map_mmio(struct kmb_dsi *kmb_dsi);
385
385
int kmb_dsi_clk_init(struct kmb_dsi *kmb_dsi);
386
386
int kmb_dsi_encoder_init(struct drm_device *dev, struct kmb_dsi *kmb_dsi);
+42
-1
drivers/gpu/drm/kmb/kmb_plane.c
+42
-1
drivers/gpu/drm/kmb/kmb_plane.c
···
67
67
68
68
static unsigned int check_pixel_format(struct drm_plane *plane, u32 format)
69
69
{
70
+
struct kmb_drm_private *kmb;
71
+
struct kmb_plane *kmb_plane = to_kmb_plane(plane);
70
72
int i;
73
+
int plane_id = kmb_plane->id;
74
+
struct disp_cfg init_disp_cfg;
71
75
76
+
kmb = to_kmb(plane->dev);
77
+
init_disp_cfg = kmb->init_disp_cfg[plane_id];
78
+
/* Due to HW limitations, changing pixel format after initial
79
+
* plane configuration is not supported.
80
+
*/
81
+
if (init_disp_cfg.format && init_disp_cfg.format != format) {
82
+
drm_dbg(&kmb->drm, "Cannot change format after initial plane configuration");
83
+
return -EINVAL;
84
+
}
72
85
for (i = 0; i < plane->format_count; i++) {
73
86
if (plane->format_types[i] == format)
74
87
return 0;
···
94
81
{
95
82
struct drm_plane_state *new_plane_state = drm_atomic_get_new_plane_state(state,
96
83
plane);
84
+
struct kmb_drm_private *kmb;
85
+
struct kmb_plane *kmb_plane = to_kmb_plane(plane);
86
+
int plane_id = kmb_plane->id;
87
+
struct disp_cfg init_disp_cfg;
97
88
struct drm_framebuffer *fb;
98
89
int ret;
99
90
struct drm_crtc_state *crtc_state;
100
91
bool can_position;
101
92
93
+
kmb = to_kmb(plane->dev);
94
+
init_disp_cfg = kmb->init_disp_cfg[plane_id];
102
95
fb = new_plane_state->fb;
103
96
if (!fb || !new_plane_state->crtc)
104
97
return 0;
···
118
99
new_plane_state->crtc_w < KMB_FB_MIN_WIDTH ||
119
100
new_plane_state->crtc_h < KMB_FB_MIN_HEIGHT)
120
101
return -EINVAL;
102
+
103
+
/* Due to HW limitations, changing plane height or width after
104
+
* initial plane configuration is not supported.
105
+
*/
106
+
if ((init_disp_cfg.width && init_disp_cfg.height) &&
107
+
(init_disp_cfg.width != fb->width ||
108
+
init_disp_cfg.height != fb->height)) {
109
+
drm_dbg(&kmb->drm, "Cannot change plane height or width after initial configuration");
110
+
return -EINVAL;
111
+
}
121
112
can_position = (plane->type == DRM_PLANE_TYPE_OVERLAY);
122
113
crtc_state =
123
114
drm_atomic_get_existing_crtc_state(state,
···
364
335
unsigned char plane_id;
365
336
int num_planes;
366
337
static dma_addr_t addr[MAX_SUB_PLANES];
338
+
struct disp_cfg *init_disp_cfg;
367
339
368
340
if (!plane || !new_plane_state || !old_plane_state)
369
341
return;
···
387
357
}
388
358
spin_unlock_irq(&kmb->irq_lock);
389
359
390
-
src_w = (new_plane_state->src_w >> 16);
360
+
init_disp_cfg = &kmb->init_disp_cfg[plane_id];
361
+
src_w = new_plane_state->src_w >> 16;
391
362
src_h = new_plane_state->src_h >> 16;
392
363
crtc_x = new_plane_state->crtc_x;
393
364
crtc_y = new_plane_state->crtc_y;
···
531
500
532
501
/* Enable DMA */
533
502
kmb_write_lcd(kmb, LCD_LAYERn_DMA_CFG(plane_id), dma_cfg);
503
+
504
+
/* Save initial display config */
505
+
if (!init_disp_cfg->width ||
506
+
!init_disp_cfg->height ||
507
+
!init_disp_cfg->format) {
508
+
init_disp_cfg->width = width;
509
+
init_disp_cfg->height = height;
510
+
init_disp_cfg->format = fb->format->format;
511
+
}
512
+
534
513
drm_dbg(&kmb->drm, "dma_cfg=0x%x LCD_DMA_CFG=0x%x\n", dma_cfg,
535
514
kmb_read_lcd(kmb, LCD_LAYERn_DMA_CFG(plane_id)));
536
515
+6
drivers/gpu/drm/kmb/kmb_plane.h
+6
drivers/gpu/drm/kmb/kmb_plane.h
···
63
63
u32 ctrl;
64
64
};
65
65
66
+
struct disp_cfg {
67
+
unsigned int width;
68
+
unsigned int height;
69
+
unsigned int format;
70
+
};
71
+
66
72
struct kmb_plane *kmb_plane_init(struct drm_device *drm);
67
73
void kmb_plane_destroy(struct drm_plane *plane);
68
74
#endif /* __KMB_PLANE_H__ */
+7
drivers/gpu/drm/msm/adreno/a6xx_gpu.c
+7
drivers/gpu/drm/msm/adreno/a6xx_gpu.c
···
1838
1838
adreno_cmp_rev(ADRENO_REV(6, 3, 5, ANY_ID), info->rev)))
1839
1839
adreno_gpu->base.hw_apriv = true;
1840
1840
1841
+
/*
1842
+
* For now only clamp to idle freq for devices where this is known not
1843
+
* to cause power supply issues:
1844
+
*/
1845
+
if (info && (info->revn == 618))
1846
+
gpu->clamp_to_idle = true;
1847
+
1841
1848
a6xx_llc_slices_init(pdev, a6xx_gpu);
1842
1849
1843
1850
ret = a6xx_set_supported_hw(&pdev->dev, config->rev);
+4
drivers/gpu/drm/msm/msm_gpu.h
+4
drivers/gpu/drm/msm/msm_gpu.h
+2
-1
drivers/gpu/drm/msm/msm_gpu_devfreq.c
+2
-1
drivers/gpu/drm/msm/msm_gpu_devfreq.c
+5
-1
drivers/gpu/drm/mxsfb/mxsfb_drv.c
+5
-1
drivers/gpu/drm/mxsfb/mxsfb_drv.c
···
173
173
struct mxsfb_drm_private *mxsfb = drm->dev_private;
174
174
175
175
mxsfb_enable_axi_clk(mxsfb);
176
-
mxsfb->crtc.funcs->disable_vblank(&mxsfb->crtc);
176
+
177
+
/* Disable and clear VBLANK IRQ */
178
+
writel(CTRL1_CUR_FRAME_DONE_IRQ_EN, mxsfb->base + LCDC_CTRL1 + REG_CLR);
179
+
writel(CTRL1_CUR_FRAME_DONE_IRQ, mxsfb->base + LCDC_CTRL1 + REG_CLR);
180
+
177
181
mxsfb_disable_axi_clk(mxsfb);
178
182
}
179
183
+6
-6
drivers/gpu/drm/panel/panel-ilitek-ili9881c.c
+6
-6
drivers/gpu/drm/panel/panel-ilitek-ili9881c.c
···
590
590
.clock = 69700,
591
591
592
592
.hdisplay = 800,
593
-
.hsync_start = 800 + 6,
594
-
.hsync_end = 800 + 6 + 15,
595
-
.htotal = 800 + 6 + 15 + 16,
593
+
.hsync_start = 800 + 52,
594
+
.hsync_end = 800 + 52 + 8,
595
+
.htotal = 800 + 52 + 8 + 48,
596
596
597
597
.vdisplay = 1280,
598
-
.vsync_start = 1280 + 8,
599
-
.vsync_end = 1280 + 8 + 48,
600
-
.vtotal = 1280 + 8 + 48 + 52,
598
+
.vsync_start = 1280 + 16,
599
+
.vsync_end = 1280 + 16 + 6,
600
+
.vtotal = 1280 + 16 + 6 + 15,
601
601
602
602
.width_mm = 135,
603
603
.height_mm = 217,