drm/amd/display: move remaining FPU code to dml folder

In the process of enabling DCN support for arm64, I found that the
dcn10_resource_construct_fp function in dcn10/dcn10_resource.c still
needs to use FPU. This will cause compilation to fail on ARM64 platforms
because -mgeneral-regs-only is enabled by default to disable the
hardware FPU. So move dcn10_resource_construct_fp from dcn10 folder to
dml/dcn10 folder to enable hardware FPU for that function.

Reviewed-by: Rodrigo Siqueira <Rodrigo.Siqueira@amd.com>
Acked-by: Christian König <christian.koenig@amd.com>
Signed-off-by: Ao Zhong <hacc1225@gmail.com>
Signed-off-by: Rodrigo Siqueira <Rodrigo.Siqueira@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>

authored by

Ao Zhong and committed by

Alex Deucher 3 years ago 64a9f19a 6040517e

+40 -42

3 changed files

expand all

drivers

gpu

drm

amd

display

dcn10

dcn10_resource.c

dml

dcn10

dcn10_fpu.c

dcn10_fpu.h

+2 -42

drivers/gpu/drm/amd/display/dc/dcn10/dcn10_resource.c

··· 1295 1295 return value; 1296 1296 } 1297 1297 1298 - /* 1299 - * Some architectures don't support soft-float (e.g. aarch64), on those 1300 - * this function has to be called with hardfloat enabled, make sure not 1301 - * to inline it so whatever fp stuff is done stays inside 1302 - */ 1303 - static noinline void dcn10_resource_construct_fp( 1304 - struct dc *dc) 1305 - { 1306 - if (dc->ctx->dce_version == DCN_VERSION_1_01) { 1307 - struct dcn_soc_bounding_box *dcn_soc = dc->dcn_soc; 1308 - struct dcn_ip_params *dcn_ip = dc->dcn_ip; 1309 - struct display_mode_lib *dml = &dc->dml; 1310 - 1311 - dml->ip.max_num_dpp = 3; 1312 - /* TODO how to handle 23.84? */ 1313 - dcn_soc->dram_clock_change_latency = 23; 1314 - dcn_ip->max_num_dpp = 3; 1315 - } 1316 - if (ASICREV_IS_RV1_F0(dc->ctx->asic_id.hw_internal_rev)) { 1317 - dc->dcn_soc->urgent_latency = 3; 1318 - dc->debug.disable_dmcu = true; 1319 - dc->dcn_soc->fabric_and_dram_bandwidth_vmax0p9 = 41.60f; 1320 - } 1321 - 1322 - 1323 - dc->dcn_soc->number_of_channels = dc->ctx->asic_id.vram_width / ddr4_dram_width; 1324 - ASSERT(dc->dcn_soc->number_of_channels < 3); 1325 - if (dc->dcn_soc->number_of_channels == 0)/*old sbios bug*/ 1326 - dc->dcn_soc->number_of_channels = 2; 1327 - 1328 - if (dc->dcn_soc->number_of_channels == 1) { 1329 - dc->dcn_soc->fabric_and_dram_bandwidth_vmax0p9 = 19.2f; 1330 - dc->dcn_soc->fabric_and_dram_bandwidth_vnom0p8 = 17.066f; 1331 - dc->dcn_soc->fabric_and_dram_bandwidth_vmid0p72 = 14.933f; 1332 - dc->dcn_soc->fabric_and_dram_bandwidth_vmin0p65 = 12.8f; 1333 - if (ASICREV_IS_RV1_F0(dc->ctx->asic_id.hw_internal_rev)) { 1334 - dc->dcn_soc->fabric_and_dram_bandwidth_vmax0p9 = 20.80f; 1335 - } 1336 - } 1337 - } 1338 - 1339 1298 static bool verify_clock_values(struct dm_pp_clock_levels_with_voltage *clks) 1340 1299 { 1341 1300 int i; ··· 1469 1510 memcpy(dc->dcn_ip, &dcn10_ip_defaults, sizeof(dcn10_ip_defaults)); 1470 1511 memcpy(dc->dcn_soc, &dcn10_soc_defaults, sizeof(dcn10_soc_defaults)); 1471 1512 1472 - /* Other architectures we build for build this with soft-float */ 1513 + DC_FP_START(); 1473 1514 dcn10_resource_construct_fp(dc); 1515 + DC_FP_END(); 1474 1516 1475 1517 if (!dc->config.is_vmin_only_asic) 1476 1518 if (ASICREV_IS_RAVEN2(dc->ctx->asic_id.hw_internal_rev))

+36

drivers/gpu/drm/amd/display/dc/dml/dcn10/dcn10_fpu.c

··· 27 27 #include "dcn10/dcn10_resource.h" 28 28 29 29 #include "dcn10_fpu.h" 30 + #include "resource.h" 31 + #include "amdgpu_dm/dc_fpu.h" 30 32 31 33 /** 32 34 * DOC: DCN10 FPU manipulation Overview ··· 123 121 .writeback_dram_clock_change_latency_us = 23.0, 124 122 .return_bus_width_bytes = 64, 125 123 }; 124 + 125 + void dcn10_resource_construct_fp(struct dc *dc) 126 + { 127 + dc_assert_fp_enabled(); 128 + if (dc->ctx->dce_version == DCN_VERSION_1_01) { 129 + struct dcn_soc_bounding_box *dcn_soc = dc->dcn_soc; 130 + struct dcn_ip_params *dcn_ip = dc->dcn_ip; 131 + struct display_mode_lib *dml = &dc->dml; 132 + 133 + dml->ip.max_num_dpp = 3; 134 + /* TODO how to handle 23.84? */ 135 + dcn_soc->dram_clock_change_latency = 23; 136 + dcn_ip->max_num_dpp = 3; 137 + } 138 + if (ASICREV_IS_RV1_F0(dc->ctx->asic_id.hw_internal_rev)) { 139 + dc->dcn_soc->urgent_latency = 3; 140 + dc->debug.disable_dmcu = true; 141 + dc->dcn_soc->fabric_and_dram_bandwidth_vmax0p9 = 41.60f; 142 + } 143 + 144 + dc->dcn_soc->number_of_channels = dc->ctx->asic_id.vram_width / ddr4_dram_width; 145 + ASSERT(dc->dcn_soc->number_of_channels < 3); 146 + if (dc->dcn_soc->number_of_channels == 0)/*old sbios bug*/ 147 + dc->dcn_soc->number_of_channels = 2; 148 + 149 + if (dc->dcn_soc->number_of_channels == 1) { 150 + dc->dcn_soc->fabric_and_dram_bandwidth_vmax0p9 = 19.2f; 151 + dc->dcn_soc->fabric_and_dram_bandwidth_vnom0p8 = 17.066f; 152 + dc->dcn_soc->fabric_and_dram_bandwidth_vmid0p72 = 14.933f; 153 + dc->dcn_soc->fabric_and_dram_bandwidth_vmin0p65 = 12.8f; 154 + if (ASICREV_IS_RV1_F0(dc->ctx->asic_id.hw_internal_rev)) 155 + dc->dcn_soc->fabric_and_dram_bandwidth_vmax0p9 = 20.80f; 156 + } 157 + }

drivers/gpu/drm/amd/display/dc/dml/dcn10/dcn10_fpu.h

··· 27 27 #ifndef __DCN10_FPU_H__ 28 28 #define __DCN10_FPU_H__ 29 29 30 + void dcn10_resource_construct_fp(struct dc *dc); 31 + 30 32 #endif /* __DCN20_FPU_H__ */

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