Linux kernel mirror (for testing)
git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git
kernel
os
linux
Merge tag 'armsoc-fixes' of git://git.kernel.org/pub/scm/linux/kernel/git/soc/soc
Pull ARM SoC fixes from Arnd Bergmann:
"This week is a much smaller update, containing fixes only for TI OMAP,
NXP i.MX and Rockchips platforms:
omap:
- omap4 had problems with lost timer interrupts
- another IRQ handling issue with OMAP5
- A workaround for a regression in the pwm-omap-dmtimer driver
NXP i.MX:
- eMMC was broken on the new imx8mq-evk board
Rockchip:
- a fix for new dtc graph warnings and a regulator fix for rock64
- USB support broke on rk3328-rock64"
* tag 'armsoc-fixes' of git://git.kernel.org/pub/scm/linux/kernel/git/soc/soc:
ARM: OMAP2+: fix lack of timer interrupts on CPU1 after hotplug
arm64: dts: imx8mq: Fix boot from eMMC
ARM: OMAP2+: Variable "reg" in function omap4_dsi_mux_pads() could be uninitialized
ARM: dts: Configure clock parent for pwm vibra
bus: ti-sysc: Fix timer handling with drop pm_runtime_irq_safe()
arm64: dts: rockchip: enable usb-host regulators at boot on rk3328-rock64
arm64: dts: rockchip: fix graph_port warning on rk3399 bob kevin and excavator
ARM: OMAP5+: Fix inverted nirq pin interrupts with irq_set_type
clocksource: timer-ti-dm: Fix pwm dmtimer usage of fck reparenting
ARM: dts: rockchip: remove qos_cif1 from rk3188 power-domain
+109
-48
+11
arch/arm/boot/dts/omap4-droid4-xt894.dts
+11
arch/arm/boot/dts/omap4-droid4-xt894.dts
···
644
644
};
645
645
};
646
646
647
+
/* Configure pwm clock source for timers 8 & 9 */
648
+
&timer8 {
649
+
assigned-clocks = <&abe_clkctrl OMAP4_TIMER8_CLKCTRL 24>;
650
+
assigned-clock-parents = <&sys_clkin_ck>;
651
+
};
652
+
653
+
&timer9 {
654
+
assigned-clocks = <&l4_per_clkctrl OMAP4_TIMER9_CLKCTRL 24>;
655
+
assigned-clock-parents = <&sys_clkin_ck>;
656
+
};
657
+
647
658
/*
648
659
* As uart1 is wired to mdm6600 with rts and cts, we can use the cts pin for
649
660
* uart1 wakeirq.
+6
-3
arch/arm/boot/dts/omap5-board-common.dtsi
+6
-3
arch/arm/boot/dts/omap5-board-common.dtsi
···
317
317
318
318
palmas_sys_nirq_pins: pinmux_palmas_sys_nirq_pins {
319
319
pinctrl-single,pins = <
320
-
OMAP5_IOPAD(0x068, PIN_INPUT_PULLUP | MUX_MODE0) /* sys_nirq1 */
320
+
/* sys_nirq1 is pulled down as the SoC is inverting it for GIC */
321
+
OMAP5_IOPAD(0x068, PIN_INPUT_PULLUP | MUX_MODE0)
321
322
>;
322
323
};
323
324
···
386
385
387
386
palmas: palmas@48 {
388
387
compatible = "ti,palmas";
389
-
interrupts = <GIC_SPI 7 IRQ_TYPE_NONE>; /* IRQ_SYS_1N */
388
+
/* sys_nirq/ext_sys_irq pins get inverted at mpuss wakeupgen */
389
+
interrupts = <GIC_SPI 7 IRQ_TYPE_LEVEL_LOW>;
390
390
reg = <0x48>;
391
391
interrupt-controller;
392
392
#interrupt-cells = <2>;
···
653
651
pinctrl-names = "default";
654
652
pinctrl-0 = <&twl6040_pins>;
655
653
656
-
interrupts = <GIC_SPI 119 IRQ_TYPE_NONE>; /* IRQ_SYS_2N cascaded to gic */
654
+
/* sys_nirq/ext_sys_irq pins get inverted at mpuss wakeupgen */
655
+
interrupts = <GIC_SPI 119 IRQ_TYPE_LEVEL_LOW>;
657
656
658
657
/* audpwron gpio defined in the board specific dts */
659
658
+11
-1
arch/arm/boot/dts/omap5-cm-t54.dts
+11
-1
arch/arm/boot/dts/omap5-cm-t54.dts
···
181
181
OMAP5_IOPAD(0x0042, PIN_INPUT_PULLDOWN | MUX_MODE6) /* llib_wakereqin.gpio1_wk15 */
182
182
>;
183
183
};
184
+
185
+
palmas_sys_nirq_pins: pinmux_palmas_sys_nirq_pins {
186
+
pinctrl-single,pins = <
187
+
/* sys_nirq1 is pulled down as the SoC is inverting it for GIC */
188
+
OMAP5_IOPAD(0x068, PIN_INPUT_PULLUP | MUX_MODE0)
189
+
>;
190
+
};
184
191
};
185
192
186
193
&omap5_pmx_core {
···
421
414
422
415
palmas: palmas@48 {
423
416
compatible = "ti,palmas";
424
-
interrupts = <GIC_SPI 7 IRQ_TYPE_NONE>; /* IRQ_SYS_1N */
425
417
reg = <0x48>;
418
+
pinctrl-0 = <&palmas_sys_nirq_pins>;
419
+
pinctrl-names = "default";
420
+
/* sys_nirq/ext_sys_irq pins get inverted at mpuss wakeupgen */
421
+
interrupts = <GIC_SPI 7 IRQ_TYPE_LEVEL_LOW>;
426
422
interrupt-controller;
427
423
#interrupt-cells = <2>;
428
424
ti,system-power-controller;
-1
arch/arm/boot/dts/rk3188.dtsi
-1
arch/arm/boot/dts/rk3188.dtsi
+4
-12
arch/arm/mach-omap2/cpuidle44xx.c
+4
-12
arch/arm/mach-omap2/cpuidle44xx.c
···
152
152
mpuss_can_lose_context = (cx->mpu_state == PWRDM_POWER_RET) &&
153
153
(cx->mpu_logic_state == PWRDM_POWER_OFF);
154
154
155
+
/* Enter broadcast mode for periodic timers */
156
+
tick_broadcast_enable();
157
+
158
+
/* Enter broadcast mode for one-shot timers */
155
159
tick_broadcast_enter();
156
160
157
161
/*
···
220
216
cpu_done[dev->cpu] = false;
221
217
222
218
return index;
223
-
}
224
-
225
-
/*
226
-
* For each cpu, setup the broadcast timer because local timers
227
-
* stops for the states above C1.
228
-
*/
229
-
static void omap_setup_broadcast_timer(void *arg)
230
-
{
231
-
tick_broadcast_enable();
232
219
}
233
220
234
221
static struct cpuidle_driver omap4_idle_driver = {
···
313
318
cpu_clkdm[1] = clkdm_lookup("mpu1_clkdm");
314
319
if (!cpu_clkdm[0] || !cpu_clkdm[1])
315
320
return -ENODEV;
316
-
317
-
/* Configure the broadcast timer on each cpu */
318
-
on_each_cpu(omap_setup_broadcast_timer, NULL, 1);
319
321
320
322
return cpuidle_register(idle_driver, cpu_online_mask);
321
323
}
+6
-1
arch/arm/mach-omap2/display.c
+6
-1
arch/arm/mach-omap2/display.c
···
83
83
u32 enable_mask, enable_shift;
84
84
u32 pipd_mask, pipd_shift;
85
85
u32 reg;
86
+
int ret;
86
87
87
88
if (dsi_id == 0) {
88
89
enable_mask = OMAP4_DSI1_LANEENABLE_MASK;
···
99
98
return -ENODEV;
100
99
}
101
100
102
-
regmap_read(omap4_dsi_mux_syscon, OMAP4_DSIPHY_SYSCON_OFFSET, ®);
101
+
ret = regmap_read(omap4_dsi_mux_syscon,
102
+
OMAP4_DSIPHY_SYSCON_OFFSET,
103
+
®);
104
+
if (ret)
105
+
return ret;
103
106
104
107
reg &= ~enable_mask;
105
108
reg &= ~pipd_mask;
+35
-1
arch/arm/mach-omap2/omap-wakeupgen.c
+35
-1
arch/arm/mach-omap2/omap-wakeupgen.c
···
50
50
#define OMAP4_NR_BANKS 4
51
51
#define OMAP4_NR_IRQS 128
52
52
53
+
#define SYS_NIRQ1_EXT_SYS_IRQ_1 7
54
+
#define SYS_NIRQ2_EXT_SYS_IRQ_2 119
55
+
53
56
static void __iomem *wakeupgen_base;
54
57
static void __iomem *sar_base;
55
58
static DEFINE_RAW_SPINLOCK(wakeupgen_lock);
···
154
151
_wakeupgen_set(d->hwirq, irq_target_cpu[d->hwirq]);
155
152
raw_spin_unlock_irqrestore(&wakeupgen_lock, flags);
156
153
irq_chip_unmask_parent(d);
154
+
}
155
+
156
+
/*
157
+
* The sys_nirq pins bypass peripheral modules and are wired directly
158
+
* to MPUSS wakeupgen. They get automatically inverted for GIC.
159
+
*/
160
+
static int wakeupgen_irq_set_type(struct irq_data *d, unsigned int type)
161
+
{
162
+
bool inverted = false;
163
+
164
+
switch (type) {
165
+
case IRQ_TYPE_LEVEL_LOW:
166
+
type &= ~IRQ_TYPE_LEVEL_MASK;
167
+
type |= IRQ_TYPE_LEVEL_HIGH;
168
+
inverted = true;
169
+
break;
170
+
case IRQ_TYPE_EDGE_FALLING:
171
+
type &= ~IRQ_TYPE_EDGE_BOTH;
172
+
type |= IRQ_TYPE_EDGE_RISING;
173
+
inverted = true;
174
+
break;
175
+
default:
176
+
break;
177
+
}
178
+
179
+
if (inverted && d->hwirq != SYS_NIRQ1_EXT_SYS_IRQ_1 &&
180
+
d->hwirq != SYS_NIRQ2_EXT_SYS_IRQ_2)
181
+
pr_warn("wakeupgen: irq%li polarity inverted in dts\n",
182
+
d->hwirq);
183
+
184
+
return irq_chip_set_type_parent(d, type);
157
185
}
158
186
159
187
#ifdef CONFIG_HOTPLUG_CPU
···
480
446
.irq_mask = wakeupgen_mask,
481
447
.irq_unmask = wakeupgen_unmask,
482
448
.irq_retrigger = irq_chip_retrigger_hierarchy,
483
-
.irq_set_type = irq_chip_set_type_parent,
449
+
.irq_set_type = wakeupgen_irq_set_type,
484
450
.flags = IRQCHIP_SKIP_SET_WAKE | IRQCHIP_MASK_ON_SUSPEND,
485
451
#ifdef CONFIG_SMP
486
452
.irq_set_affinity = irq_chip_set_affinity_parent,
+22
-22
arch/arm64/boot/dts/freescale/imx8mq-evk.dts
+22
-22
arch/arm64/boot/dts/freescale/imx8mq-evk.dts
···
227
227
228
228
pinctrl_usdhc1_100mhz: usdhc1-100grp {
229
229
fsl,pins = <
230
-
MX8MQ_IOMUXC_SD1_CLK_USDHC1_CLK 0x85
231
-
MX8MQ_IOMUXC_SD1_CMD_USDHC1_CMD 0xc5
232
-
MX8MQ_IOMUXC_SD1_DATA0_USDHC1_DATA0 0xc5
233
-
MX8MQ_IOMUXC_SD1_DATA1_USDHC1_DATA1 0xc5
234
-
MX8MQ_IOMUXC_SD1_DATA2_USDHC1_DATA2 0xc5
235
-
MX8MQ_IOMUXC_SD1_DATA3_USDHC1_DATA3 0xc5
236
-
MX8MQ_IOMUXC_SD1_DATA4_USDHC1_DATA4 0xc5
237
-
MX8MQ_IOMUXC_SD1_DATA5_USDHC1_DATA5 0xc5
238
-
MX8MQ_IOMUXC_SD1_DATA6_USDHC1_DATA6 0xc5
239
-
MX8MQ_IOMUXC_SD1_DATA7_USDHC1_DATA7 0xc5
240
-
MX8MQ_IOMUXC_SD1_STROBE_USDHC1_STROBE 0x85
230
+
MX8MQ_IOMUXC_SD1_CLK_USDHC1_CLK 0x8d
231
+
MX8MQ_IOMUXC_SD1_CMD_USDHC1_CMD 0xcd
232
+
MX8MQ_IOMUXC_SD1_DATA0_USDHC1_DATA0 0xcd
233
+
MX8MQ_IOMUXC_SD1_DATA1_USDHC1_DATA1 0xcd
234
+
MX8MQ_IOMUXC_SD1_DATA2_USDHC1_DATA2 0xcd
235
+
MX8MQ_IOMUXC_SD1_DATA3_USDHC1_DATA3 0xcd
236
+
MX8MQ_IOMUXC_SD1_DATA4_USDHC1_DATA4 0xcd
237
+
MX8MQ_IOMUXC_SD1_DATA5_USDHC1_DATA5 0xcd
238
+
MX8MQ_IOMUXC_SD1_DATA6_USDHC1_DATA6 0xcd
239
+
MX8MQ_IOMUXC_SD1_DATA7_USDHC1_DATA7 0xcd
240
+
MX8MQ_IOMUXC_SD1_STROBE_USDHC1_STROBE 0x8d
241
241
MX8MQ_IOMUXC_SD1_RESET_B_USDHC1_RESET_B 0xc1
242
242
>;
243
243
};
244
244
245
245
pinctrl_usdhc1_200mhz: usdhc1-200grp {
246
246
fsl,pins = <
247
-
MX8MQ_IOMUXC_SD1_CLK_USDHC1_CLK 0x87
248
-
MX8MQ_IOMUXC_SD1_CMD_USDHC1_CMD 0xc7
249
-
MX8MQ_IOMUXC_SD1_DATA0_USDHC1_DATA0 0xc7
250
-
MX8MQ_IOMUXC_SD1_DATA1_USDHC1_DATA1 0xc7
251
-
MX8MQ_IOMUXC_SD1_DATA2_USDHC1_DATA2 0xc7
252
-
MX8MQ_IOMUXC_SD1_DATA3_USDHC1_DATA3 0xc7
253
-
MX8MQ_IOMUXC_SD1_DATA4_USDHC1_DATA4 0xc7
254
-
MX8MQ_IOMUXC_SD1_DATA5_USDHC1_DATA5 0xc7
255
-
MX8MQ_IOMUXC_SD1_DATA6_USDHC1_DATA6 0xc7
256
-
MX8MQ_IOMUXC_SD1_DATA7_USDHC1_DATA7 0xc7
257
-
MX8MQ_IOMUXC_SD1_STROBE_USDHC1_STROBE 0x87
247
+
MX8MQ_IOMUXC_SD1_CLK_USDHC1_CLK 0x9f
248
+
MX8MQ_IOMUXC_SD1_CMD_USDHC1_CMD 0xdf
249
+
MX8MQ_IOMUXC_SD1_DATA0_USDHC1_DATA0 0xdf
250
+
MX8MQ_IOMUXC_SD1_DATA1_USDHC1_DATA1 0xdf
251
+
MX8MQ_IOMUXC_SD1_DATA2_USDHC1_DATA2 0xdf
252
+
MX8MQ_IOMUXC_SD1_DATA3_USDHC1_DATA3 0xdf
253
+
MX8MQ_IOMUXC_SD1_DATA4_USDHC1_DATA4 0xdf
254
+
MX8MQ_IOMUXC_SD1_DATA5_USDHC1_DATA5 0xdf
255
+
MX8MQ_IOMUXC_SD1_DATA6_USDHC1_DATA6 0xdf
256
+
MX8MQ_IOMUXC_SD1_DATA7_USDHC1_DATA7 0xdf
257
+
MX8MQ_IOMUXC_SD1_STROBE_USDHC1_STROBE 0x9f
258
258
MX8MQ_IOMUXC_SD1_RESET_B_USDHC1_RESET_B 0xc1
259
259
>;
260
260
};
+2
arch/arm64/boot/dts/freescale/imx8mq.dtsi
+2
arch/arm64/boot/dts/freescale/imx8mq.dtsi
···
360
360
<&clk IMX8MQ_CLK_NAND_USDHC_BUS>,
361
361
<&clk IMX8MQ_CLK_USDHC1_ROOT>;
362
362
clock-names = "ipg", "ahb", "per";
363
+
assigned-clocks = <&clk IMX8MQ_CLK_USDHC1>;
364
+
assigned-clock-rates = <400000000>;
363
365
fsl,tuning-start-tap = <20>;
364
366
fsl,tuning-step = <2>;
365
367
bus-width = <4>;
+2
arch/arm64/boot/dts/rockchip/rk3328-rock64.dts
+2
arch/arm64/boot/dts/rockchip/rk3328-rock64.dts
···
40
40
pinctrl-0 = <&usb30_host_drv>;
41
41
regulator-name = "vcc_host_5v";
42
42
regulator-always-on;
43
+
regulator-boot-on;
43
44
vin-supply = <&vcc_sys>;
44
45
};
45
46
···
52
51
pinctrl-0 = <&usb20_host_drv>;
53
52
regulator-name = "vcc_host1_5v";
54
53
regulator-always-on;
54
+
regulator-boot-on;
55
55
vin-supply = <&vcc_sys>;
56
56
};
57
57
+1
-1
arch/arm64/boot/dts/rockchip/rk3399-gru-bob.dts
+1
-1
arch/arm64/boot/dts/rockchip/rk3399-gru-bob.dts
+1
-1
arch/arm64/boot/dts/rockchip/rk3399-gru-kevin.dts
+1
-1
arch/arm64/boot/dts/rockchip/rk3399-gru-kevin.dts
+1
-1
arch/arm64/boot/dts/rockchip/rk3399-sapphire-excavator.dts
+1
-1
arch/arm64/boot/dts/rockchip/rk3399-sapphire-excavator.dts
+3
-3
drivers/bus/ti-sysc.c
+3
-3
drivers/bus/ti-sysc.c
···
781
781
SYSC_QUIRK("smartreflex", 0, -1, 0x38, -1, 0x00000000, 0xffffffff,
782
782
SYSC_QUIRK_LEGACY_IDLE),
783
783
SYSC_QUIRK("timer", 0, 0, 0x10, 0x14, 0x00000015, 0xffffffff,
784
-
SYSC_QUIRK_LEGACY_IDLE),
784
+
0),
785
785
/* Some timers on omap4 and later */
786
786
SYSC_QUIRK("timer", 0, 0, 0x10, -1, 0x50002100, 0xffffffff,
787
-
SYSC_QUIRK_LEGACY_IDLE),
787
+
0),
788
788
SYSC_QUIRK("timer", 0, 0, 0x10, -1, 0x4fff1301, 0xffff00ff,
789
-
SYSC_QUIRK_LEGACY_IDLE),
789
+
0),
790
790
SYSC_QUIRK("uart", 0, 0x50, 0x54, 0x58, 0x00000052, 0xffffffff,
791
791
SYSC_QUIRK_LEGACY_IDLE),
792
792
/* Uarts on omap4 and later */
+4
-1
drivers/clocksource/timer-ti-dm.c
+4
-1
drivers/clocksource/timer-ti-dm.c
···
154
154
if (IS_ERR(parent))
155
155
return -ENODEV;
156
156
157
+
/* Bail out if both clocks point to fck */
158
+
if (clk_is_match(parent, timer->fclk))
159
+
return 0;
160
+
157
161
ret = clk_set_parent(timer->fclk, parent);
158
162
if (ret < 0)
159
163
pr_err("%s: failed to set parent\n", __func__);
···
868
864
timer->pdev = pdev;
869
865
870
866
pm_runtime_enable(dev);
871
-
pm_runtime_irq_safe(dev);
872
867
873
868
if (!timer->reserved) {
874
869
ret = pm_runtime_get_sync(dev);