Linux kernel mirror (for testing)
git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git
kernel
os
linux
Merge branch 'drm-fixes' of git://people.freedesktop.org/~airlied/linux
Pull drm fixes from Dave Airlie:
"Radeon, nouveau, exynos, intel, mgag200..
Not all strictly regressions but there was probably only one patch I'd
have really left out and it didn't seem worth respinning exynos to
avoid it, the line change count is quite low.
radeon: regressions + more dynamic powermanagement fixes, since DPM
is a new feature, and off by default I'd prefer to keep merging
fixes since it has a large userbase already and I'd like to keep
them on mainline
nouveau: is mostly regression fixes
i915: is a regression fix since Daniel is on holidays I've merged it.
mgag200: I've picked a bunch of targetted fixes from a big bunch of
distro patches,
exynos: build fixes mostly, one regression fix
I expect things will slow right down now, I may send on the intel
early quirk from Jesse separatly, since I think the x86 maintainers
acked it"
* 'drm-fixes' of git://people.freedesktop.org/~airlied/linux: (37 commits)
drm/i915: fix missed hunk after GT access breakage
drm/radeon/dpm: re-enable cac control on SI
drm/radeon/dpm: fix calculations in si_calculate_leakage_for_v_and_t_formula
drm: fix 64 bit drm fixed point helpers
drm/radeon/atom: initialize more atom interpretor elements to 0
drm/nouveau: fix semaphore dmabuf obj
drm/nouveau/vm: make vm refcount into a kref
drm/nv31/mpeg: don't recognize nv3x cards as having nv44 graph class
drm/nv40/mpeg: write magic value to channel object to make it work
drm/nouveau: fix size check for cards without vm
drm/nv50-/disp: remove dcb_outp_match call, and related variables
drm/nva3-/disp: fix hda eld writing, needs to be padded
drm/nv31/mpeg: fix mpeg engine initialization
drm/nv50/mc: include vp in the fb error reporting mask
drm/nouveau: fix null pointer dereference in poll_changed
drm/nv50/gpio: post-nv92 cards have 32 interrupt lines
drm/nvc0/fb: take lock in nvc0_ram_put()
drm/nouveau/core: xtensa firmware size needs to be 0x40000 no matter what
drm/mgag200: Fix LUT programming for 16bpp
drm/mgag200: Fix framebuffer pitch calculation
...
+193
-126
-1
drivers/gpu/drm/exynos/exynos_ddc.c
-1
drivers/gpu/drm/exynos/exynos_ddc.c
-1
drivers/gpu/drm/exynos/exynos_drm_fimc.c
-1
drivers/gpu/drm/exynos/exynos_drm_fimc.c
-3
drivers/gpu/drm/exynos/exynos_drm_fimd.c
-3
drivers/gpu/drm/exynos/exynos_drm_fimd.c
···
14
14
#include <drm/drmP.h>
15
15
16
16
#include <linux/kernel.h>
17
-
#include <linux/module.h>
18
17
#include <linux/platform_device.h>
19
18
#include <linux/clk.h>
20
19
#include <linux/of_device.h>
···
129
130
.data = &exynos5_fimd_driver_data },
130
131
{},
131
132
};
132
-
MODULE_DEVICE_TABLE(of, fimd_driver_dt_match);
133
133
#endif
134
134
135
135
static inline struct fimd_driver_data *drm_fimd_get_driver_data(
···
1080
1082
},
1081
1083
{},
1082
1084
};
1083
-
MODULE_DEVICE_TABLE(platform, fimd_driver_ids);
1084
1085
1085
1086
static const struct dev_pm_ops fimd_pm_ops = {
1086
1087
SET_SYSTEM_SLEEP_PM_OPS(fimd_suspend, fimd_resume)
+14
-5
drivers/gpu/drm/exynos/exynos_drm_g2d.c
+14
-5
drivers/gpu/drm/exynos/exynos_drm_g2d.c
···
8
8
*/
9
9
10
10
#include <linux/kernel.h>
11
-
#include <linux/module.h>
12
11
#include <linux/clk.h>
13
12
#include <linux/err.h>
14
13
#include <linux/interrupt.h>
···
805
806
struct g2d_cmdlist_node *node =
806
807
list_first_entry(&runqueue_node->run_cmdlist,
807
808
struct g2d_cmdlist_node, list);
809
+
int ret;
808
810
809
-
pm_runtime_get_sync(g2d->dev);
810
-
clk_enable(g2d->gate_clk);
811
+
ret = pm_runtime_get_sync(g2d->dev);
812
+
if (ret < 0) {
813
+
dev_warn(g2d->dev, "failed pm power on.\n");
814
+
return;
815
+
}
816
+
817
+
ret = clk_prepare_enable(g2d->gate_clk);
818
+
if (ret < 0) {
819
+
dev_warn(g2d->dev, "failed to enable clock.\n");
820
+
pm_runtime_put_sync(g2d->dev);
821
+
return;
822
+
}
811
823
812
824
writel_relaxed(node->dma_addr, g2d->regs + G2D_DMA_SFR_BASE_ADDR);
813
825
writel_relaxed(G2D_DMA_START, g2d->regs + G2D_DMA_COMMAND);
···
871
861
runqueue_work);
872
862
873
863
mutex_lock(&g2d->runqueue_mutex);
874
-
clk_disable(g2d->gate_clk);
864
+
clk_disable_unprepare(g2d->gate_clk);
875
865
pm_runtime_put_sync(g2d->dev);
876
866
877
867
complete(&g2d->runqueue_node->complete);
···
1531
1521
{ .compatible = "samsung,exynos5250-g2d" },
1532
1522
{},
1533
1523
};
1534
-
MODULE_DEVICE_TABLE(of, exynos_g2d_match);
1535
1524
#endif
1536
1525
1537
1526
struct platform_driver g2d_driver = {
-1
drivers/gpu/drm/exynos/exynos_drm_gsc.c
-1
drivers/gpu/drm/exynos/exynos_drm_gsc.c
-1
drivers/gpu/drm/exynos/exynos_drm_hdmi.c
-1
drivers/gpu/drm/exynos/exynos_drm_hdmi.c
+6
-7
drivers/gpu/drm/exynos/exynos_drm_ipp.c
+6
-7
drivers/gpu/drm/exynos/exynos_drm_ipp.c
···
12
12
*
13
13
*/
14
14
#include <linux/kernel.h>
15
-
#include <linux/module.h>
16
15
#include <linux/platform_device.h>
17
16
#include <linux/types.h>
18
17
#include <linux/clk.h>
···
341
342
*/
342
343
ippdrv = ipp_find_obj(&ctx->ipp_idr, &ctx->ipp_lock,
343
344
prop_list->ipp_id);
344
-
if (!ippdrv) {
345
+
if (IS_ERR(ippdrv)) {
345
346
DRM_ERROR("not found ipp%d driver.\n",
346
347
prop_list->ipp_id);
347
-
return -EINVAL;
348
+
return PTR_ERR(ippdrv);
348
349
}
349
350
350
351
prop_list = ippdrv->prop_list;
···
969
970
/* find command node */
970
971
c_node = ipp_find_obj(&ctx->prop_idr, &ctx->prop_lock,
971
972
qbuf->prop_id);
972
-
if (!c_node) {
973
+
if (IS_ERR(c_node)) {
973
974
DRM_ERROR("failed to get command node.\n");
974
-
return -EFAULT;
975
+
return PTR_ERR(c_node);
975
976
}
976
977
977
978
/* buffer control */
···
1105
1106
1106
1107
c_node = ipp_find_obj(&ctx->prop_idr, &ctx->prop_lock,
1107
1108
cmd_ctrl->prop_id);
1108
-
if (!c_node) {
1109
+
if (IS_ERR(c_node)) {
1109
1110
DRM_ERROR("invalid command node list.\n");
1110
-
return -EINVAL;
1111
+
return PTR_ERR(c_node);
1111
1112
}
1112
1113
1113
1114
if (!exynos_drm_ipp_check_valid(ippdrv->dev, cmd_ctrl->ctrl,
-1
drivers/gpu/drm/exynos/exynos_drm_rotator.c
-1
drivers/gpu/drm/exynos/exynos_drm_rotator.c
-1
drivers/gpu/drm/exynos/exynos_drm_vidi.c
-1
drivers/gpu/drm/exynos/exynos_drm_vidi.c
-1
drivers/gpu/drm/exynos/exynos_hdmi.c
-1
drivers/gpu/drm/exynos/exynos_hdmi.c
-1
drivers/gpu/drm/exynos/exynos_hdmiphy.c
-1
drivers/gpu/drm/exynos/exynos_hdmiphy.c
-1
drivers/gpu/drm/exynos/exynos_mixer.c
-1
drivers/gpu/drm/exynos/exynos_mixer.c
+1
drivers/gpu/drm/i915/i915_dma.c
+1
drivers/gpu/drm/i915/i915_dma.c
+1
drivers/gpu/drm/i915/i915_drv.h
+1
drivers/gpu/drm/i915/i915_drv.h
···
1582
1582
void i915_handle_error(struct drm_device *dev, bool wedged);
1583
1583
1584
1584
extern void intel_irq_init(struct drm_device *dev);
1585
+
extern void intel_pm_init(struct drm_device *dev);
1585
1586
extern void intel_hpd_init(struct drm_device *dev);
1586
1587
extern void intel_gt_init(struct drm_device *dev);
1587
1588
extern void intel_gt_sanitize(struct drm_device *dev);
+6
drivers/gpu/drm/i915/intel_pm.c
+6
drivers/gpu/drm/i915/intel_pm.c
···
5536
5536
dev_priv->gt.force_wake_get = __gen6_gt_force_wake_get;
5537
5537
dev_priv->gt.force_wake_put = __gen6_gt_force_wake_put;
5538
5538
}
5539
+
}
5540
+
5541
+
void intel_pm_init(struct drm_device *dev)
5542
+
{
5543
+
struct drm_i915_private *dev_priv = dev->dev_private;
5544
+
5539
5545
INIT_DELAYED_WORK(&dev_priv->rps.delayed_resume_work,
5540
5546
intel_gen6_powersave_work);
5541
5547
}
+45
-1
drivers/gpu/drm/mgag200/mgag200_mode.c
+45
-1
drivers/gpu/drm/mgag200/mgag200_mode.c
···
29
29
struct mga_crtc *mga_crtc = to_mga_crtc(crtc);
30
30
struct drm_device *dev = crtc->dev;
31
31
struct mga_device *mdev = dev->dev_private;
32
+
struct drm_framebuffer *fb = crtc->fb;
32
33
int i;
33
34
34
35
if (!crtc->enabled)
···
37
36
38
37
WREG8(DAC_INDEX + MGA1064_INDEX, 0);
39
38
39
+
if (fb && fb->bits_per_pixel == 16) {
40
+
int inc = (fb->depth == 15) ? 8 : 4;
41
+
u8 r, b;
42
+
for (i = 0; i < MGAG200_LUT_SIZE; i += inc) {
43
+
if (fb->depth == 16) {
44
+
if (i > (MGAG200_LUT_SIZE >> 1)) {
45
+
r = b = 0;
46
+
} else {
47
+
r = mga_crtc->lut_r[i << 1];
48
+
b = mga_crtc->lut_b[i << 1];
49
+
}
50
+
} else {
51
+
r = mga_crtc->lut_r[i];
52
+
b = mga_crtc->lut_b[i];
53
+
}
54
+
/* VGA registers */
55
+
WREG8(DAC_INDEX + MGA1064_COL_PAL, r);
56
+
WREG8(DAC_INDEX + MGA1064_COL_PAL, mga_crtc->lut_g[i]);
57
+
WREG8(DAC_INDEX + MGA1064_COL_PAL, b);
58
+
}
59
+
return;
60
+
}
40
61
for (i = 0; i < MGAG200_LUT_SIZE; i++) {
41
62
/* VGA registers */
42
63
WREG8(DAC_INDEX + MGA1064_COL_PAL, mga_crtc->lut_r[i]);
···
900
877
901
878
pitch = crtc->fb->pitches[0] / (crtc->fb->bits_per_pixel / 8);
902
879
if (crtc->fb->bits_per_pixel == 24)
903
-
pitch = pitch >> (4 - bppshift);
880
+
pitch = (pitch * 3) >> (4 - bppshift);
904
881
else
905
882
pitch = pitch >> (4 - bppshift);
906
883
···
1274
1251
kfree(mga_crtc);
1275
1252
}
1276
1253
1254
+
static void mga_crtc_disable(struct drm_crtc *crtc)
1255
+
{
1256
+
int ret;
1257
+
DRM_DEBUG_KMS("\n");
1258
+
mga_crtc_dpms(crtc, DRM_MODE_DPMS_OFF);
1259
+
if (crtc->fb) {
1260
+
struct mga_framebuffer *mga_fb = to_mga_framebuffer(crtc->fb);
1261
+
struct drm_gem_object *obj = mga_fb->obj;
1262
+
struct mgag200_bo *bo = gem_to_mga_bo(obj);
1263
+
ret = mgag200_bo_reserve(bo, false);
1264
+
if (ret)
1265
+
return;
1266
+
mgag200_bo_push_sysram(bo);
1267
+
mgag200_bo_unreserve(bo);
1268
+
}
1269
+
crtc->fb = NULL;
1270
+
}
1271
+
1277
1272
/* These provide the minimum set of functions required to handle a CRTC */
1278
1273
static const struct drm_crtc_funcs mga_crtc_funcs = {
1279
1274
.cursor_set = mga_crtc_cursor_set,
···
1302
1261
};
1303
1262
1304
1263
static const struct drm_crtc_helper_funcs mga_helper_funcs = {
1264
+
.disable = mga_crtc_disable,
1305
1265
.dpms = mga_crtc_dpms,
1306
1266
.mode_fixup = mga_crtc_mode_fixup,
1307
1267
.mode_set = mga_crtc_mode_set,
···
1622
1580
&mga_vga_connector_funcs, DRM_MODE_CONNECTOR_VGA);
1623
1581
1624
1582
drm_connector_helper_add(connector, &mga_vga_connector_helper_funcs);
1583
+
1584
+
drm_sysfs_connector_add(connector);
1625
1585
1626
1586
mga_connector->i2c = mgag200_i2c_create(dev);
1627
1587
if (!mga_connector->i2c)
+1
drivers/gpu/drm/mgag200/mgag200_ttm.c
+1
drivers/gpu/drm/mgag200/mgag200_ttm.c
+2
drivers/gpu/drm/nouveau/core/engine/disp/hdanva3.c
+2
drivers/gpu/drm/nouveau/core/engine/disp/hdanva3.c
+2
drivers/gpu/drm/nouveau/core/engine/disp/hdanvd0.c
+2
drivers/gpu/drm/nouveau/core/engine/disp/hdanvd0.c
-8
drivers/gpu/drm/nouveau/core/engine/disp/sornv50.c
-8
drivers/gpu/drm/nouveau/core/engine/disp/sornv50.c
···
47
47
nv50_sor_mthd(struct nouveau_object *object, u32 mthd, void *args, u32 size)
48
48
{
49
49
struct nv50_disp_priv *priv = (void *)object->engine;
50
-
struct nouveau_bios *bios = nouveau_bios(priv);
51
-
const u16 type = (mthd & NV50_DISP_SOR_MTHD_TYPE) >> 12;
52
50
const u8 head = (mthd & NV50_DISP_SOR_MTHD_HEAD) >> 3;
53
-
const u8 link = (mthd & NV50_DISP_SOR_MTHD_LINK) >> 2;
54
51
const u8 or = (mthd & NV50_DISP_SOR_MTHD_OR);
55
-
const u16 mask = (0x0100 << head) | (0x0040 << link) | (0x0001 << or);
56
-
struct dcb_output outp;
57
-
u8 ver, hdr;
58
52
u32 data;
59
53
int ret = -EINVAL;
60
54
···
56
62
return -EINVAL;
57
63
data = *(u32 *)args;
58
64
59
-
if (type && !dcb_outp_match(bios, type, mask, &ver, &hdr, &outp))
60
-
return -ENODEV;
61
65
62
66
switch (mthd & ~0x3f) {
63
67
case NV50_DISP_SOR_PWR:
+6
-3
drivers/gpu/drm/nouveau/core/engine/mpeg/nv31.c
+6
-3
drivers/gpu/drm/nouveau/core/engine/mpeg/nv31.c
···
265
265
int
266
266
nv31_mpeg_init(struct nouveau_object *object)
267
267
{
268
-
struct nouveau_engine *engine = nv_engine(object->engine);
269
-
struct nv31_mpeg_priv *priv = (void *)engine;
268
+
struct nouveau_engine *engine = nv_engine(object);
269
+
struct nv31_mpeg_priv *priv = (void *)object;
270
270
struct nouveau_fb *pfb = nouveau_fb(object);
271
271
int ret, i;
272
272
···
284
284
/* PMPEG init */
285
285
nv_wr32(priv, 0x00b32c, 0x00000000);
286
286
nv_wr32(priv, 0x00b314, 0x00000100);
287
-
nv_wr32(priv, 0x00b220, nv44_graph_class(priv) ? 0x00000044 : 0x00000031);
287
+
if (nv_device(priv)->chipset >= 0x40 && nv44_graph_class(priv))
288
+
nv_wr32(priv, 0x00b220, 0x00000044);
289
+
else
290
+
nv_wr32(priv, 0x00b220, 0x00000031);
288
291
nv_wr32(priv, 0x00b300, 0x02001ec1);
289
292
nv_mask(priv, 0x00b32c, 0x00000001, 0x00000001);
290
293
+1
drivers/gpu/drm/nouveau/core/engine/mpeg/nv40.c
+1
drivers/gpu/drm/nouveau/core/engine/mpeg/nv40.c
+7
-1
drivers/gpu/drm/nouveau/core/engine/xtensa.c
+7
-1
drivers/gpu/drm/nouveau/core/engine/xtensa.c
···
118
118
return ret;
119
119
}
120
120
121
-
ret = nouveau_gpuobj_new(object, NULL, fw->size, 0x1000, 0,
121
+
if (fw->size > 0x40000) {
122
+
nv_warn(xtensa, "firmware %s too large\n", name);
123
+
release_firmware(fw);
124
+
return -EINVAL;
125
+
}
126
+
127
+
ret = nouveau_gpuobj_new(object, NULL, 0x40000, 0x1000, 0,
122
128
&xtensa->gpu_fw);
123
129
if (ret) {
124
130
release_firmware(fw);
+1
-1
drivers/gpu/drm/nouveau/core/include/subdev/vm.h
+1
-1
drivers/gpu/drm/nouveau/core/include/subdev/vm.h
+1
-1
drivers/gpu/drm/nouveau/core/subdev/fb/priv.h
+1
-1
drivers/gpu/drm/nouveau/core/subdev/fb/priv.h
···
81
81
void nv46_fb_tile_init(struct nouveau_fb *, int i, u32 addr, u32 size,
82
82
u32 pitch, u32 flags, struct nouveau_fb_tile *);
83
83
84
-
void nv50_ram_put(struct nouveau_fb *, struct nouveau_mem **);
84
+
void __nv50_ram_put(struct nouveau_fb *, struct nouveau_mem *);
85
85
extern int nv50_fb_memtype[0x80];
86
86
87
87
#endif
+14
-8
drivers/gpu/drm/nouveau/core/subdev/fb/ramnv50.c
+14
-8
drivers/gpu/drm/nouveau/core/subdev/fb/ramnv50.c
···
27
27
#include "priv.h"
28
28
29
29
void
30
-
nv50_ram_put(struct nouveau_fb *pfb, struct nouveau_mem **pmem)
30
+
__nv50_ram_put(struct nouveau_fb *pfb, struct nouveau_mem *mem)
31
31
{
32
32
struct nouveau_mm_node *this;
33
-
struct nouveau_mem *mem;
34
33
35
-
mem = *pmem;
36
-
*pmem = NULL;
37
-
if (unlikely(mem == NULL))
38
-
return;
39
-
40
-
mutex_lock(&pfb->base.mutex);
41
34
while (!list_empty(&mem->regions)) {
42
35
this = list_first_entry(&mem->regions, typeof(*this), rl_entry);
43
36
···
39
46
}
40
47
41
48
nouveau_mm_free(&pfb->tags, &mem->tag);
49
+
}
50
+
51
+
void
52
+
nv50_ram_put(struct nouveau_fb *pfb, struct nouveau_mem **pmem)
53
+
{
54
+
struct nouveau_mem *mem = *pmem;
55
+
56
+
*pmem = NULL;
57
+
if (unlikely(mem == NULL))
58
+
return;
59
+
60
+
mutex_lock(&pfb->base.mutex);
61
+
__nv50_ram_put(pfb, mem);
42
62
mutex_unlock(&pfb->base.mutex);
43
63
44
64
kfree(mem);
+11
-3
drivers/gpu/drm/nouveau/core/subdev/fb/ramnvc0.c
+11
-3
drivers/gpu/drm/nouveau/core/subdev/fb/ramnvc0.c
···
33
33
nvc0_ram_put(struct nouveau_fb *pfb, struct nouveau_mem **pmem)
34
34
{
35
35
struct nouveau_ltcg *ltcg = nouveau_ltcg(pfb);
36
+
struct nouveau_mem *mem = *pmem;
36
37
37
-
if ((*pmem)->tag)
38
-
ltcg->tags_free(ltcg, &(*pmem)->tag);
38
+
*pmem = NULL;
39
+
if (unlikely(mem == NULL))
40
+
return;
39
41
40
-
nv50_ram_put(pfb, pmem);
42
+
mutex_lock(&pfb->base.mutex);
43
+
if (mem->tag)
44
+
ltcg->tags_free(ltcg, &mem->tag);
45
+
__nv50_ram_put(pfb, mem);
46
+
mutex_unlock(&pfb->base.mutex);
47
+
48
+
kfree(mem);
41
49
}
42
50
43
51
int
+5
-5
drivers/gpu/drm/nouveau/core/subdev/gpio/nv50.c
+5
-5
drivers/gpu/drm/nouveau/core/subdev/gpio/nv50.c
···
103
103
int i;
104
104
105
105
intr0 = nv_rd32(priv, 0xe054) & nv_rd32(priv, 0xe050);
106
-
if (nv_device(priv)->chipset >= 0x90)
106
+
if (nv_device(priv)->chipset > 0x92)
107
107
intr1 = nv_rd32(priv, 0xe074) & nv_rd32(priv, 0xe070);
108
108
109
109
hi = (intr0 & 0x0000ffff) | (intr1 << 16);
···
115
115
}
116
116
117
117
nv_wr32(priv, 0xe054, intr0);
118
-
if (nv_device(priv)->chipset >= 0x90)
118
+
if (nv_device(priv)->chipset > 0x92)
119
119
nv_wr32(priv, 0xe074, intr1);
120
120
}
121
121
···
146
146
int ret;
147
147
148
148
ret = nouveau_gpio_create(parent, engine, oclass,
149
-
nv_device(parent)->chipset >= 0x90 ? 32 : 16,
149
+
nv_device(parent)->chipset > 0x92 ? 32 : 16,
150
150
&priv);
151
151
*pobject = nv_object(priv);
152
152
if (ret)
···
182
182
/* disable, and ack any pending gpio interrupts */
183
183
nv_wr32(priv, 0xe050, 0x00000000);
184
184
nv_wr32(priv, 0xe054, 0xffffffff);
185
-
if (nv_device(priv)->chipset >= 0x90) {
185
+
if (nv_device(priv)->chipset > 0x92) {
186
186
nv_wr32(priv, 0xe070, 0x00000000);
187
187
nv_wr32(priv, 0xe074, 0xffffffff);
188
188
}
···
195
195
{
196
196
struct nv50_gpio_priv *priv = (void *)object;
197
197
nv_wr32(priv, 0xe050, 0x00000000);
198
-
if (nv_device(priv)->chipset >= 0x90)
198
+
if (nv_device(priv)->chipset > 0x92)
199
199
nv_wr32(priv, 0xe070, 0x00000000);
200
200
return nouveau_gpio_fini(&priv->base, suspend);
201
201
}
+1
-1
drivers/gpu/drm/nouveau/core/subdev/mc/nv50.c
+1
-1
drivers/gpu/drm/nouveau/core/subdev/mc/nv50.c
+11
-18
drivers/gpu/drm/nouveau/core/subdev/vm/base.c
+11
-18
drivers/gpu/drm/nouveau/core/subdev/vm/base.c
···
361
361
362
362
INIT_LIST_HEAD(&vm->pgd_list);
363
363
vm->vmm = vmm;
364
-
vm->refcount = 1;
364
+
kref_init(&vm->refcount);
365
365
vm->fpde = offset >> (vmm->pgt_bits + 12);
366
366
vm->lpde = (offset + length - 1) >> (vmm->pgt_bits + 12);
367
367
···
441
441
}
442
442
443
443
static void
444
-
nouveau_vm_del(struct nouveau_vm *vm)
444
+
nouveau_vm_del(struct kref *kref)
445
445
{
446
+
struct nouveau_vm *vm = container_of(kref, typeof(*vm), refcount);
446
447
struct nouveau_vm_pgd *vpgd, *tmp;
447
448
448
449
list_for_each_entry_safe(vpgd, tmp, &vm->pgd_list, head) {
···
459
458
nouveau_vm_ref(struct nouveau_vm *ref, struct nouveau_vm **ptr,
460
459
struct nouveau_gpuobj *pgd)
461
460
{
462
-
struct nouveau_vm *vm;
463
-
int ret;
464
-
465
-
vm = ref;
466
-
if (vm) {
467
-
ret = nouveau_vm_link(vm, pgd);
461
+
if (ref) {
462
+
int ret = nouveau_vm_link(ref, pgd);
468
463
if (ret)
469
464
return ret;
470
465
471
-
vm->refcount++;
466
+
kref_get(&ref->refcount);
472
467
}
473
468
474
-
vm = *ptr;
469
+
if (*ptr) {
470
+
nouveau_vm_unlink(*ptr, pgd);
471
+
kref_put(&(*ptr)->refcount, nouveau_vm_del);
472
+
}
473
+
475
474
*ptr = ref;
476
-
477
-
if (vm) {
478
-
nouveau_vm_unlink(vm, pgd);
479
-
480
-
if (--vm->refcount == 0)
481
-
nouveau_vm_del(vm);
482
-
}
483
-
484
475
return 0;
485
476
}
+6
-1
drivers/gpu/drm/nouveau/nouveau_bo.c
+6
-1
drivers/gpu/drm/nouveau/nouveau_bo.c
···
198
198
size_t acc_size;
199
199
int ret;
200
200
int type = ttm_bo_type_device;
201
-
int max_size = INT_MAX & ~((1 << drm->client.base.vm->vmm->lpg_shift) - 1);
201
+
int lpg_shift = 12;
202
+
int max_size;
203
+
204
+
if (drm->client.base.vm)
205
+
lpg_shift = drm->client.base.vm->vmm->lpg_shift;
206
+
max_size = INT_MAX & ~((1 << lpg_shift) - 1);
202
207
203
208
if (size <= 0 || size > max_size) {
204
209
nv_warn(drm, "skipped size %x\n", (u32)size);
+2
-1
drivers/gpu/drm/nouveau/nouveau_fbcon.c
+2
-1
drivers/gpu/drm/nouveau/nouveau_fbcon.c
···
398
398
nouveau_fbcon_output_poll_changed(struct drm_device *dev)
399
399
{
400
400
struct nouveau_drm *drm = nouveau_drm(dev);
401
-
drm_fb_helper_hotplug_event(&drm->fbcon->helper);
401
+
if (drm->fbcon)
402
+
drm_fb_helper_hotplug_event(&drm->fbcon->helper);
402
403
}
403
404
404
405
static int
+1
-1
drivers/gpu/drm/nouveau/nv17_fence.c
+1
-1
drivers/gpu/drm/nouveau/nv17_fence.c
···
76
76
struct ttm_mem_reg *mem = &priv->bo->bo.mem;
77
77
struct nouveau_object *object;
78
78
u32 start = mem->start * PAGE_SIZE;
79
-
u32 limit = mem->start + mem->size - 1;
79
+
u32 limit = start + mem->size - 1;
80
80
int ret = 0;
81
81
82
82
fctx = chan->fence = kzalloc(sizeof(*fctx), GFP_KERNEL);
+9
-5
drivers/gpu/drm/nouveau/nv50_fence.c
+9
-5
drivers/gpu/drm/nouveau/nv50_fence.c
···
39
39
struct nv10_fence_chan *fctx;
40
40
struct ttm_mem_reg *mem = &priv->bo->bo.mem;
41
41
struct nouveau_object *object;
42
+
u32 start = mem->start * PAGE_SIZE;
43
+
u32 limit = start + mem->size - 1;
42
44
int ret, i;
43
45
44
46
fctx = chan->fence = kzalloc(sizeof(*fctx), GFP_KERNEL);
···
53
51
fctx->base.sync = nv17_fence_sync;
54
52
55
53
ret = nouveau_object_new(nv_object(chan->cli), chan->handle,
56
-
NvSema, 0x0002,
54
+
NvSema, 0x003d,
57
55
&(struct nv_dma_class) {
58
56
.flags = NV_DMA_TARGET_VRAM |
59
57
NV_DMA_ACCESS_RDWR,
60
-
.start = mem->start * PAGE_SIZE,
61
-
.limit = mem->size - 1,
58
+
.start = start,
59
+
.limit = limit,
62
60
}, sizeof(struct nv_dma_class),
63
61
&object);
64
62
65
63
/* dma objects for display sync channel semaphore blocks */
66
64
for (i = 0; !ret && i < dev->mode_config.num_crtc; i++) {
67
65
struct nouveau_bo *bo = nv50_display_crtc_sema(dev, i);
66
+
u32 start = bo->bo.mem.start * PAGE_SIZE;
67
+
u32 limit = start + bo->bo.mem.size - 1;
68
68
69
69
ret = nouveau_object_new(nv_object(chan->cli), chan->handle,
70
70
NvEvoSema0 + i, 0x003d,
71
71
&(struct nv_dma_class) {
72
72
.flags = NV_DMA_TARGET_VRAM |
73
73
NV_DMA_ACCESS_RDWR,
74
-
.start = bo->bo.offset,
75
-
.limit = bo->bo.offset + 0xfff,
74
+
.start = start,
75
+
.limit = limit,
76
76
}, sizeof(struct nv_dma_class),
77
77
&object);
78
78
}
+5
drivers/gpu/drm/radeon/atom.c
+5
drivers/gpu/drm/radeon/atom.c
···
1222
1222
int r;
1223
1223
1224
1224
mutex_lock(&ctx->mutex);
1225
+
/* reset data block */
1226
+
ctx->data_block = 0;
1225
1227
/* reset reg block */
1226
1228
ctx->reg_block = 0;
1227
1229
/* reset fb window */
1228
1230
ctx->fb_base = 0;
1229
1231
/* reset io mode */
1230
1232
ctx->io_mode = ATOM_IO_MM;
1233
+
/* reset divmul */
1234
+
ctx->divmul[0] = 0;
1235
+
ctx->divmul[1] = 0;
1231
1236
r = atom_execute_table_locked(ctx, index, params);
1232
1237
mutex_unlock(&ctx->mutex);
1233
1238
return r;
+1
-1
drivers/gpu/drm/radeon/evergreen_hdmi.c
+1
-1
drivers/gpu/drm/radeon/evergreen_hdmi.c
···
157
157
* number (coefficient of two integer numbers. DCCG_AUDIO_DTOx_PHASE
158
158
* is the numerator, DCCG_AUDIO_DTOx_MODULE is the denominator
159
159
*/
160
+
WREG32(DCCG_AUDIO_DTO_SOURCE, DCCG_AUDIO_DTO0_SOURCE_SEL(radeon_crtc->crtc_id));
160
161
WREG32(DCCG_AUDIO_DTO0_PHASE, base_rate * 100);
161
162
WREG32(DCCG_AUDIO_DTO0_MODULE, clock * 100);
162
-
WREG32(DCCG_AUDIO_DTO_SOURCE, DCCG_AUDIO_DTO0_SOURCE_SEL(radeon_crtc->crtc_id));
163
163
}
164
164
165
165
+1
-6
drivers/gpu/drm/radeon/ni_dpm.c
+1
-6
drivers/gpu/drm/radeon/ni_dpm.c
···
1054
1054
int ni_dpm_force_performance_level(struct radeon_device *rdev,
1055
1055
enum radeon_dpm_forced_level level)
1056
1056
{
1057
-
struct radeon_ps *rps = rdev->pm.dpm.current_ps;
1058
-
struct ni_ps *ps = ni_get_ps(rps);
1059
-
u32 levels;
1060
-
1061
1057
if (level == RADEON_DPM_FORCED_LEVEL_HIGH) {
1062
1058
if (ni_send_msg_to_smc_with_parameter(rdev, PPSMC_MSG_SetEnabledLevels, 0) != PPSMC_Result_OK)
1063
1059
return -EINVAL;
···
1064
1068
if (ni_send_msg_to_smc_with_parameter(rdev, PPSMC_MSG_SetForcedLevels, 0) != PPSMC_Result_OK)
1065
1069
return -EINVAL;
1066
1070
1067
-
levels = ps->performance_level_count - 1;
1068
-
if (ni_send_msg_to_smc_with_parameter(rdev, PPSMC_MSG_SetEnabledLevels, levels) != PPSMC_Result_OK)
1071
+
if (ni_send_msg_to_smc_with_parameter(rdev, PPSMC_MSG_SetEnabledLevels, 1) != PPSMC_Result_OK)
1069
1072
return -EINVAL;
1070
1073
} else if (level == RADEON_DPM_FORCED_LEVEL_AUTO) {
1071
1074
if (ni_send_msg_to_smc_with_parameter(rdev, PPSMC_MSG_SetForcedLevels, 0) != PPSMC_Result_OK)
+1
-1
drivers/gpu/drm/radeon/radeon_atombios.c
+1
-1
drivers/gpu/drm/radeon/radeon_atombios.c
···
2782
2782
ATOM_PLL_CNTL_FLAG_PLL_POST_DIV_EN) ? true : false;
2783
2783
dividers->enable_dithen = (args.v3.ucCntlFlag &
2784
2784
ATOM_PLL_CNTL_FLAG_FRACTION_DISABLE) ? false : true;
2785
-
dividers->fb_div = le16_to_cpu(args.v3.ulFbDiv.usFbDiv);
2785
+
dividers->whole_fb_div = le16_to_cpu(args.v3.ulFbDiv.usFbDiv);
2786
2786
dividers->frac_fb_div = le16_to_cpu(args.v3.ulFbDiv.usFbDivFrac);
2787
2787
dividers->ref_div = args.v3.ucRefDiv;
2788
2788
dividers->vco_mode = (args.v3.ucCntlFlag &
+5
-9
drivers/gpu/drm/radeon/si.c
+5
-9
drivers/gpu/drm/radeon/si.c
···
5215
5215
5216
5216
static void si_init_cg(struct radeon_device *rdev)
5217
5217
{
5218
-
bool has_uvd = true;
5219
-
5220
5218
si_enable_mgcg(rdev, true);
5221
-
si_enable_cgcg(rdev, true);
5219
+
si_enable_cgcg(rdev, false);
5222
5220
/* disable MC LS on Tahiti */
5223
5221
if (rdev->family == CHIP_TAHITI)
5224
5222
si_enable_mc_ls(rdev, false);
5225
-
if (has_uvd) {
5223
+
if (rdev->has_uvd) {
5226
5224
si_enable_uvd_mgcg(rdev, true);
5227
5225
si_init_uvd_internal_cg(rdev);
5228
5226
}
···
5228
5230
5229
5231
static void si_fini_cg(struct radeon_device *rdev)
5230
5232
{
5231
-
bool has_uvd = true;
5232
-
5233
-
if (has_uvd)
5233
+
if (rdev->has_uvd)
5234
5234
si_enable_uvd_mgcg(rdev, false);
5235
5235
si_enable_cgcg(rdev, false);
5236
5236
si_enable_mgcg(rdev, false);
···
5237
5241
static void si_init_pg(struct radeon_device *rdev)
5238
5242
{
5239
5243
bool has_pg = false;
5240
-
5244
+
#if 0
5241
5245
/* only cape verde supports PG */
5242
5246
if (rdev->family == CHIP_VERDE)
5243
5247
has_pg = true;
5244
-
5248
+
#endif
5245
5249
if (has_pg) {
5246
5250
si_init_ao_cu_mask(rdev);
5247
5251
si_init_dma_pg(rdev);
+19
-20
drivers/gpu/drm/radeon/si_dpm.c
+19
-20
drivers/gpu/drm/radeon/si_dpm.c
···
37
37
38
38
#define SMC_RAM_END 0x20000
39
39
40
-
#define DDR3_DRAM_ROWS 0x2000
41
-
42
40
#define SCLK_MIN_DEEPSLEEP_FREQ 1350
43
41
44
42
static const struct si_cac_config_reg cac_weights_tahiti[] =
···
1765
1767
{
1766
1768
s64 kt, kv, leakage_w, i_leakage, vddc;
1767
1769
s64 temperature, t_slope, t_intercept, av, bv, t_ref;
1770
+
s64 tmp;
1768
1771
1769
-
i_leakage = drm_int2fixp(ileakage / 100);
1772
+
i_leakage = drm_int2fixp(ileakage) / 100;
1770
1773
vddc = div64_s64(drm_int2fixp(v), 1000);
1771
1774
temperature = div64_s64(drm_int2fixp(t), 1000);
1772
1775
···
1777
1778
bv = div64_s64(drm_int2fixp(coeff->bv), 100000000);
1778
1779
t_ref = drm_int2fixp(coeff->t_ref);
1779
1780
1780
-
kt = drm_fixp_div(drm_fixp_exp(drm_fixp_mul(drm_fixp_mul(t_slope, vddc) + t_intercept, temperature)),
1781
-
drm_fixp_exp(drm_fixp_mul(drm_fixp_mul(t_slope, vddc) + t_intercept, t_ref)));
1781
+
tmp = drm_fixp_mul(t_slope, vddc) + t_intercept;
1782
+
kt = drm_fixp_exp(drm_fixp_mul(tmp, temperature));
1783
+
kt = drm_fixp_div(kt, drm_fixp_exp(drm_fixp_mul(tmp, t_ref)));
1782
1784
kv = drm_fixp_mul(av, drm_fixp_exp(drm_fixp_mul(bv, vddc)));
1783
1785
1784
1786
leakage_w = drm_fixp_mul(drm_fixp_mul(drm_fixp_mul(i_leakage, kt), kv), vddc);
···
1931
1931
si_pi->cac_override = cac_override_pitcairn;
1932
1932
si_pi->powertune_data = &powertune_data_pitcairn;
1933
1933
si_pi->dte_data = dte_data_pitcairn;
1934
+
break;
1934
1935
}
1935
1936
} else if (rdev->family == CHIP_VERDE) {
1936
1937
si_pi->lcac_config = lcac_cape_verde;
···
1942
1941
case 0x683B:
1943
1942
case 0x683F:
1944
1943
case 0x6829:
1944
+
case 0x6835:
1945
1945
si_pi->cac_weights = cac_weights_cape_verde_pro;
1946
1946
si_pi->dte_data = dte_data_cape_verde;
1947
1947
break;
···
3239
3237
{
3240
3238
struct radeon_ps *rps = rdev->pm.dpm.current_ps;
3241
3239
struct ni_ps *ps = ni_get_ps(rps);
3242
-
u32 levels;
3240
+
u32 levels = ps->performance_level_count;
3243
3241
3244
3242
if (level == RADEON_DPM_FORCED_LEVEL_HIGH) {
3245
-
if (si_send_msg_to_smc_with_parameter(rdev, PPSMC_MSG_SetEnabledLevels, 0) != PPSMC_Result_OK)
3243
+
if (si_send_msg_to_smc_with_parameter(rdev, PPSMC_MSG_SetEnabledLevels, levels) != PPSMC_Result_OK)
3246
3244
return -EINVAL;
3247
3245
3248
3246
if (si_send_msg_to_smc_with_parameter(rdev, PPSMC_MSG_SetForcedLevels, 1) != PPSMC_Result_OK)
···
3251
3249
if (si_send_msg_to_smc_with_parameter(rdev, PPSMC_MSG_SetForcedLevels, 0) != PPSMC_Result_OK)
3252
3250
return -EINVAL;
3253
3251
3254
-
levels = ps->performance_level_count - 1;
3255
-
if (si_send_msg_to_smc_with_parameter(rdev, PPSMC_MSG_SetEnabledLevels, levels) != PPSMC_Result_OK)
3252
+
if (si_send_msg_to_smc_with_parameter(rdev, PPSMC_MSG_SetEnabledLevels, 1) != PPSMC_Result_OK)
3256
3253
return -EINVAL;
3257
3254
} else if (level == RADEON_DPM_FORCED_LEVEL_AUTO) {
3258
3255
if (si_send_msg_to_smc_with_parameter(rdev, PPSMC_MSG_SetForcedLevels, 0) != PPSMC_Result_OK)
3259
3256
return -EINVAL;
3260
3257
3261
-
if (si_send_msg_to_smc_with_parameter(rdev, PPSMC_MSG_SetEnabledLevels, 0) != PPSMC_Result_OK)
3258
+
if (si_send_msg_to_smc_with_parameter(rdev, PPSMC_MSG_SetEnabledLevels, levels) != PPSMC_Result_OK)
3262
3259
return -EINVAL;
3263
3260
}
3264
3261
···
3621
3620
{
3622
3621
u32 tmp = RREG32(CG_DISPLAY_GAP_CNTL);
3623
3622
3623
+
tmp &= ~(DISP1_GAP_MASK | DISP2_GAP_MASK);
3624
+
tmp |= (DISP1_GAP(R600_PM_DISPLAY_GAP_IGNORE) |
3625
+
DISP2_GAP(R600_PM_DISPLAY_GAP_IGNORE));
3626
+
3624
3627
tmp &= ~(DISP1_GAP_MCHG_MASK | DISP2_GAP_MCHG_MASK);
3625
-
tmp |= (DISP1_GAP_MCHG(R600_PM_DISPLAY_GAP_IGNORE) |
3628
+
tmp |= (DISP1_GAP_MCHG(R600_PM_DISPLAY_GAP_VBLANK) |
3626
3629
DISP2_GAP_MCHG(R600_PM_DISPLAY_GAP_IGNORE));
3627
3630
WREG32(CG_DISPLAY_GAP_CNTL, tmp);
3628
3631
}
···
4041
4036
static u32 si_calculate_memory_refresh_rate(struct radeon_device *rdev,
4042
4037
u32 engine_clock)
4043
4038
{
4044
-
struct rv7xx_power_info *pi = rv770_get_pi(rdev);
4045
4039
u32 dram_rows;
4046
4040
u32 dram_refresh_rate;
4047
4041
u32 mc_arb_rfsh_rate;
4048
4042
u32 tmp = (RREG32(MC_ARB_RAMCFG) & NOOFROWS_MASK) >> NOOFROWS_SHIFT;
4049
4043
4050
-
if (pi->mem_gddr5)
4051
-
dram_rows = 1 << (tmp + 10);
4044
+
if (tmp >= 4)
4045
+
dram_rows = 16384;
4052
4046
else
4053
-
dram_rows = DDR3_DRAM_ROWS;
4047
+
dram_rows = 1 << (tmp + 10);
4054
4048
4055
4049
dram_refresh_rate = 1 << ((RREG32(MC_SEQ_MISC0) & 0x3) + 3);
4056
4050
mc_arb_rfsh_rate = ((engine_clock * 10) * dram_refresh_rate / dram_rows - 32) / 64;
···
6017
6013
return ret;
6018
6014
}
6019
6015
6020
-
#if 0
6021
-
/* XXX */
6022
6016
ret = si_dpm_force_performance_level(rdev, RADEON_DPM_FORCED_LEVEL_AUTO);
6023
6017
if (ret) {
6024
6018
DRM_ERROR("si_dpm_force_performance_level failed\n");
6025
6019
return ret;
6026
6020
}
6027
-
#else
6028
-
rdev->pm.dpm.forced_level = RADEON_DPM_FORCED_LEVEL_AUTO;
6029
-
#endif
6030
6021
6031
6022
return 0;
6032
6023
}
+7
-7
include/drm/drm_fixed.h
+7
-7
include/drm/drm_fixed.h
···
84
84
return ((s64)a) >> DRM_FIXED_POINT;
85
85
}
86
86
87
-
static inline s64 drm_fixp_msbset(int64_t a)
87
+
static inline unsigned drm_fixp_msbset(int64_t a)
88
88
{
89
89
unsigned shift, sign = (a >> 63) & 1;
90
90
91
91
for (shift = 62; shift > 0; --shift)
92
-
if ((a >> shift) != sign)
92
+
if (((a >> shift) & 1) != sign)
93
93
return shift;
94
94
95
95
return 0;
···
100
100
unsigned shift = drm_fixp_msbset(a) + drm_fixp_msbset(b);
101
101
s64 result;
102
102
103
-
if (shift > 63) {
104
-
shift = shift - 63;
105
-
a >>= shift >> 1;
103
+
if (shift > 61) {
104
+
shift = shift - 61;
105
+
a >>= (shift >> 1) + (shift & 1);
106
106
b >>= shift >> 1;
107
107
} else
108
108
shift = 0;
···
120
120
121
121
static inline s64 drm_fixp_div(s64 a, s64 b)
122
122
{
123
-
unsigned shift = 63 - drm_fixp_msbset(a);
123
+
unsigned shift = 62 - drm_fixp_msbset(a);
124
124
s64 result;
125
125
126
126
a <<= shift;
···
154
154
}
155
155
156
156
if (x < 0)
157
-
sum = drm_fixp_div(1, sum);
157
+
sum = drm_fixp_div(DRM_FIXED_ONE, sum);
158
158
159
159
return sum;
160
160
}