tjh.dev / kernel
Linux kernel mirror (for testing) git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git
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drm/amdgpu: Enable devcoredump for JPEG5_0_0

Add register list and enable devcoredump for JPEG5_0_0

V2: (Lijo)
- remove version specific callbacks and use simplified helper functions

V3: (Lijo)
- move amdgpu_jpeg_reg_dump_fini() to sw_fini() and avoid the call here

Signed-off-by: Sathishkumar S <sathishkumar.sundararaju@amd.com>
Reviewed-by: Leo Liu <leo.liu@amd.com>
Acked-by: Lijo Lazar <lijo.lazar@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>

authored by

Sathishkumar S and committed by
Alex Deucher 64dc2f00 8ecd4ec6

+22
+22
drivers/gpu/drm/amd/amdgpu/jpeg_v5_0_0.c
··· 34 34 #include "ivsrcid/vcn/irqsrcs_vcn_5_0.h" 35 35 #include "jpeg_v5_0_0.h" 36 36 37 + static const struct amdgpu_hwip_reg_entry jpeg_reg_list_5_0[] = { 38 + SOC15_REG_ENTRY_STR(JPEG, 0, regUVD_JPEG_POWER_STATUS), 39 + SOC15_REG_ENTRY_STR(JPEG, 0, regUVD_JPEG_INT_STAT), 40 + SOC15_REG_ENTRY_STR(JPEG, 0, regUVD_JRBC_RB_RPTR), 41 + SOC15_REG_ENTRY_STR(JPEG, 0, regUVD_JRBC_RB_WPTR), 42 + SOC15_REG_ENTRY_STR(JPEG, 0, regUVD_JRBC_RB_CNTL), 43 + SOC15_REG_ENTRY_STR(JPEG, 0, regUVD_JRBC_RB_SIZE), 44 + SOC15_REG_ENTRY_STR(JPEG, 0, regUVD_JRBC_STATUS), 45 + SOC15_REG_ENTRY_STR(JPEG, 0, regJPEG_DEC_ADDR_MODE), 46 + SOC15_REG_ENTRY_STR(JPEG, 0, regJPEG_DEC_GFX10_ADDR_CONFIG), 47 + SOC15_REG_ENTRY_STR(JPEG, 0, regJPEG_DEC_Y_GFX10_TILING_SURFACE), 48 + SOC15_REG_ENTRY_STR(JPEG, 0, regJPEG_DEC_UV_GFX10_TILING_SURFACE), 49 + SOC15_REG_ENTRY_STR(JPEG, 0, regUVD_JPEG_PITCH), 50 + SOC15_REG_ENTRY_STR(JPEG, 0, regUVD_JPEG_UV_PITCH), 51 + }; 52 + 37 53 static void jpeg_v5_0_0_set_dec_ring_funcs(struct amdgpu_device *adev); 38 54 static void jpeg_v5_0_0_set_irq_funcs(struct amdgpu_device *adev); 39 55 static int jpeg_v5_0_0_set_powergating_state(struct amdgpu_ip_block *ip_block, ··· 115 99 116 100 adev->jpeg.internal.jpeg_pitch[0] = regUVD_JPEG_PITCH_INTERNAL_OFFSET; 117 101 adev->jpeg.inst->external.jpeg_pitch[0] = SOC15_REG_OFFSET(JPEG, 0, regUVD_JPEG_PITCH); 102 + 103 + r = amdgpu_jpeg_reg_dump_init(adev, jpeg_reg_list_5_0, ARRAY_SIZE(jpeg_reg_list_5_0)); 104 + if (r) 105 + return r; 118 106 119 107 /* TODO: Add queue reset mask when FW fully supports it */ 120 108 adev->jpeg.supported_reset = ··· 657 637 .wait_for_idle = jpeg_v5_0_0_wait_for_idle, 658 638 .set_clockgating_state = jpeg_v5_0_0_set_clockgating_state, 659 639 .set_powergating_state = jpeg_v5_0_0_set_powergating_state, 640 + .dump_ip_state = amdgpu_jpeg_dump_ip_state, 641 + .print_ip_state = amdgpu_jpeg_print_ip_state, 660 642 }; 661 643 662 644 static const struct amdgpu_ring_funcs jpeg_v5_0_0_dec_ring_vm_funcs = {