tjh.dev / kernel
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drm/amd/display: Hardcode dtbclk value in bw_params

[why&how]

dtbclk should always be 600MHz. Previous logic was to get the real value
from SMU, but this returns 0 when dtbclk is off. Not a problem during
boot when pre-OS enables dtbclk, but PnP was broken due to this.

Reviewed-by: Charlene Liu <charlene.liu@amd.com>
Reviewed-by: Nicholas Kazlauskas <nicholas.kazlauskas@amd.com>
Signed-off-by: Matthew Stewart <Matthew.Stewart2@amd.com>
Signed-off-by: Chuanyu Tseng <chuanyu.tseng@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>

authored by

Matthew Stewart and committed by
Alex Deucher 64fd3f93 05112f1f

+2 -5
+2 -5
drivers/gpu/drm/amd/display/dc/clk_mgr/dcn42/dcn42_clk_mgr.c
··· 594 594 dcn42_dump_clk_registers(&clk_mgr_base->boot_snapshot, clk_mgr); 595 595 596 596 clk_mgr_base->clks.ref_dtbclk_khz = clk_mgr_base->boot_snapshot.dtbclk * 10; 597 - if (clk_mgr_base->boot_snapshot.dtbclk > 59000) { 598 - /*dtbclk enabled based on*/ 599 - clk_mgr_base->clks.dtbclk_en = true; 600 - } 597 + clk_mgr_base->clks.dtbclk_en = clk_mgr_base->boot_snapshot.dtbclk > 59000; 601 598 } 602 599 603 600 static struct clk_bw_params dcn42_bw_params = { ··· 1066 1069 clk_mgr_base->bw_params->clk_table.num_entries_per_clk.num_memclk_levels = dpm_clks->NumMemPstatesEnabled; 1067 1070 1068 1071 /* DTBCLK*/ 1069 - clk_mgr_base->bw_params->clk_table.entries[0].dtbclk_mhz = clk_mgr_base->clks.ref_dtbclk_khz / 1000; 1072 + clk_mgr_base->bw_params->clk_table.entries[0].dtbclk_mhz = 600; /* Fixed on platform */ 1070 1073 clk_mgr_base->bw_params->clk_table.num_entries_per_clk.num_dtbclk_levels = 1; 1071 1074 } 1072 1075 }