Linux kernel mirror (for testing)
git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git
kernel
os
linux
drm/amdgpu: Remove volatile references from VCN
Reviewed-by: Christian König <christian.koenig@amd.com>
Signed-off-by: Rodrigo Siqueira <siqueira@igalia.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
authored by
Rodrigo Siqueira
and committed by
Alex Deucher
65307484
89702530
+51
-51
+5
-5
drivers/gpu/drm/amd/amdgpu/amdgpu_vcn.c
+5
-5
drivers/gpu/drm/amd/amdgpu/amdgpu_vcn.c
···
1157
1157
{
1158
1158
struct amdgpu_vcn_inst *vcn;
1159
1159
void *log_buf;
1160
-
volatile struct amdgpu_vcn_fwlog *plog;
1160
+
struct amdgpu_vcn_fwlog *plog;
1161
1161
unsigned int read_pos, write_pos, available, i, read_bytes = 0;
1162
1162
unsigned int read_num[2] = {0};
1163
1163
···
1170
1170
1171
1171
log_buf = vcn->fw_shared.cpu_addr + vcn->fw_shared.mem_size;
1172
1172
1173
-
plog = (volatile struct amdgpu_vcn_fwlog *)log_buf;
1173
+
plog = (struct amdgpu_vcn_fwlog *)log_buf;
1174
1174
read_pos = plog->rptr;
1175
1175
write_pos = plog->wptr;
1176
1176
···
1237
1237
void amdgpu_vcn_fwlog_init(struct amdgpu_vcn_inst *vcn)
1238
1238
{
1239
1239
#if defined(CONFIG_DEBUG_FS)
1240
-
volatile uint32_t *flag = vcn->fw_shared.cpu_addr;
1240
+
uint32_t *flag = vcn->fw_shared.cpu_addr;
1241
1241
void *fw_log_cpu_addr = vcn->fw_shared.cpu_addr + vcn->fw_shared.mem_size;
1242
1242
uint64_t fw_log_gpu_addr = vcn->fw_shared.gpu_addr + vcn->fw_shared.mem_size;
1243
-
volatile struct amdgpu_vcn_fwlog *log_buf = fw_log_cpu_addr;
1244
-
volatile struct amdgpu_fw_shared_fw_logging *fw_log = vcn->fw_shared.cpu_addr
1243
+
struct amdgpu_vcn_fwlog *log_buf = fw_log_cpu_addr;
1244
+
struct amdgpu_fw_shared_fw_logging *fw_log = vcn->fw_shared.cpu_addr
1245
1245
+ vcn->fw_shared.log_offset;
1246
1246
*flag |= cpu_to_le32(AMDGPU_VCN_FW_LOGGING_FLAG);
1247
1247
fw_log->is_enabled = 1;
+1
-1
drivers/gpu/drm/amd/amdgpu/vcn_v1_0.c
+1
-1
drivers/gpu/drm/amd/amdgpu/vcn_v1_0.c
···
193
193
adev->vcn.inst[0].pause_dpg_mode = vcn_v1_0_pause_dpg_mode;
194
194
195
195
if (amdgpu_vcnfw_log) {
196
-
volatile struct amdgpu_fw_shared *fw_shared = adev->vcn.inst->fw_shared.cpu_addr;
196
+
struct amdgpu_fw_shared *fw_shared = adev->vcn.inst->fw_shared.cpu_addr;
197
197
198
198
fw_shared->present_flag_0 = 0;
199
199
amdgpu_vcn_fwlog_init(adev->vcn.inst);
+5
-5
drivers/gpu/drm/amd/amdgpu/vcn_v2_0.c
+5
-5
drivers/gpu/drm/amd/amdgpu/vcn_v2_0.c
···
137
137
struct amdgpu_ring *ring;
138
138
int i, r;
139
139
struct amdgpu_device *adev = ip_block->adev;
140
-
volatile struct amdgpu_fw_shared *fw_shared;
140
+
struct amdgpu_fw_shared *fw_shared;
141
141
142
142
/* VCN DEC TRAP */
143
143
r = amdgpu_irq_add_id(adev, SOC15_IH_CLIENTID_VCN,
···
252
252
{
253
253
int r, idx;
254
254
struct amdgpu_device *adev = ip_block->adev;
255
-
volatile struct amdgpu_fw_shared *fw_shared = adev->vcn.inst->fw_shared.cpu_addr;
255
+
struct amdgpu_fw_shared *fw_shared = adev->vcn.inst->fw_shared.cpu_addr;
256
256
257
257
if (drm_dev_enter(adev_to_drm(adev), &idx)) {
258
258
fw_shared->present_flag_0 = 0;
···
853
853
static int vcn_v2_0_start_dpg_mode(struct amdgpu_vcn_inst *vinst, bool indirect)
854
854
{
855
855
struct amdgpu_device *adev = vinst->adev;
856
-
volatile struct amdgpu_fw_shared *fw_shared = adev->vcn.inst->fw_shared.cpu_addr;
856
+
struct amdgpu_fw_shared *fw_shared = adev->vcn.inst->fw_shared.cpu_addr;
857
857
struct amdgpu_ring *ring = &adev->vcn.inst->ring_dec;
858
858
uint32_t rb_bufsz, tmp;
859
859
int ret;
···
1001
1001
static int vcn_v2_0_start(struct amdgpu_vcn_inst *vinst)
1002
1002
{
1003
1003
struct amdgpu_device *adev = vinst->adev;
1004
-
volatile struct amdgpu_fw_shared *fw_shared = adev->vcn.inst->fw_shared.cpu_addr;
1004
+
struct amdgpu_fw_shared *fw_shared = adev->vcn.inst->fw_shared.cpu_addr;
1005
1005
struct amdgpu_ring *ring = &adev->vcn.inst->ring_dec;
1006
1006
uint32_t rb_bufsz, tmp;
1007
1007
uint32_t lmi_swap_cntl;
···
1308
1308
UVD_POWER_STATUS__UVD_POWER_STATUS_MASK);
1309
1309
1310
1310
if (!ret_code) {
1311
-
volatile struct amdgpu_fw_shared *fw_shared = adev->vcn.inst->fw_shared.cpu_addr;
1311
+
struct amdgpu_fw_shared *fw_shared = adev->vcn.inst->fw_shared.cpu_addr;
1312
1312
/* pause DPG */
1313
1313
reg_data |= UVD_DPG_PAUSE__NJ_PAUSE_DPG_REQ_MASK;
1314
1314
WREG32_SOC15(UVD, 0, mmUVD_DPG_PAUSE, reg_data);
+5
-5
drivers/gpu/drm/amd/amdgpu/vcn_v2_5.c
+5
-5
drivers/gpu/drm/amd/amdgpu/vcn_v2_5.c
···
277
277
struct amdgpu_device *adev = ip_block->adev;
278
278
279
279
for (j = 0; j < adev->vcn.num_vcn_inst; j++) {
280
-
volatile struct amdgpu_fw_shared *fw_shared;
280
+
struct amdgpu_fw_shared *fw_shared;
281
281
282
282
if (adev->vcn.harvest_config & (1 << j))
283
283
continue;
···
420
420
{
421
421
int i, r, idx;
422
422
struct amdgpu_device *adev = ip_block->adev;
423
-
volatile struct amdgpu_fw_shared *fw_shared;
423
+
struct amdgpu_fw_shared *fw_shared;
424
424
425
425
if (drm_dev_enter(adev_to_drm(adev), &idx)) {
426
426
for (i = 0; i < adev->vcn.num_vcn_inst; i++) {
···
998
998
{
999
999
struct amdgpu_device *adev = vinst->adev;
1000
1000
int inst_idx = vinst->inst;
1001
-
volatile struct amdgpu_fw_shared *fw_shared = adev->vcn.inst[inst_idx].fw_shared.cpu_addr;
1001
+
struct amdgpu_fw_shared *fw_shared = adev->vcn.inst[inst_idx].fw_shared.cpu_addr;
1002
1002
struct amdgpu_ring *ring;
1003
1003
uint32_t rb_bufsz, tmp;
1004
1004
int ret;
···
1155
1155
{
1156
1156
struct amdgpu_device *adev = vinst->adev;
1157
1157
int i = vinst->inst;
1158
-
volatile struct amdgpu_fw_shared *fw_shared =
1158
+
struct amdgpu_fw_shared *fw_shared =
1159
1159
adev->vcn.inst[i].fw_shared.cpu_addr;
1160
1160
struct amdgpu_ring *ring;
1161
1161
uint32_t rb_bufsz, tmp;
···
1667
1667
UVD_POWER_STATUS__UVD_POWER_STATUS_MASK);
1668
1668
1669
1669
if (!ret_code) {
1670
-
volatile struct amdgpu_fw_shared *fw_shared = adev->vcn.inst[inst_idx].fw_shared.cpu_addr;
1670
+
struct amdgpu_fw_shared *fw_shared = adev->vcn.inst[inst_idx].fw_shared.cpu_addr;
1671
1671
1672
1672
/* pause DPG */
1673
1673
reg_data |= UVD_DPG_PAUSE__NJ_PAUSE_DPG_REQ_MASK;
+6
-6
drivers/gpu/drm/amd/amdgpu/vcn_v3_0.c
+6
-6
drivers/gpu/drm/amd/amdgpu/vcn_v3_0.c
···
191
191
}
192
192
193
193
for (i = 0; i < adev->vcn.num_vcn_inst; i++) {
194
-
volatile struct amdgpu_fw_shared *fw_shared;
194
+
struct amdgpu_fw_shared *fw_shared;
195
195
196
196
if (adev->vcn.harvest_config & (1 << i))
197
197
continue;
···
327
327
328
328
if (drm_dev_enter(adev_to_drm(adev), &idx)) {
329
329
for (i = 0; i < adev->vcn.num_vcn_inst; i++) {
330
-
volatile struct amdgpu_fw_shared *fw_shared;
330
+
struct amdgpu_fw_shared *fw_shared;
331
331
332
332
if (adev->vcn.harvest_config & (1 << i))
333
333
continue;
···
1029
1029
{
1030
1030
struct amdgpu_device *adev = vinst->adev;
1031
1031
int inst_idx = vinst->inst;
1032
-
volatile struct amdgpu_fw_shared *fw_shared = adev->vcn.inst[inst_idx].fw_shared.cpu_addr;
1032
+
struct amdgpu_fw_shared *fw_shared = adev->vcn.inst[inst_idx].fw_shared.cpu_addr;
1033
1033
struct amdgpu_ring *ring;
1034
1034
uint32_t rb_bufsz, tmp;
1035
1035
int ret;
···
1194
1194
{
1195
1195
struct amdgpu_device *adev = vinst->adev;
1196
1196
int i = vinst->inst;
1197
-
volatile struct amdgpu_fw_shared *fw_shared;
1197
+
struct amdgpu_fw_shared *fw_shared;
1198
1198
struct amdgpu_ring *ring;
1199
1199
uint32_t rb_bufsz, tmp;
1200
1200
int j, k, r;
···
1715
1715
{
1716
1716
struct amdgpu_device *adev = vinst->adev;
1717
1717
int inst_idx = vinst->inst;
1718
-
volatile struct amdgpu_fw_shared *fw_shared;
1718
+
struct amdgpu_fw_shared *fw_shared;
1719
1719
struct amdgpu_ring *ring;
1720
1720
uint32_t reg_data = 0;
1721
1721
int ret_code;
···
1834
1834
static void vcn_v3_0_dec_ring_set_wptr(struct amdgpu_ring *ring)
1835
1835
{
1836
1836
struct amdgpu_device *adev = ring->adev;
1837
-
volatile struct amdgpu_fw_shared *fw_shared;
1837
+
struct amdgpu_fw_shared *fw_shared;
1838
1838
1839
1839
if (adev->pg_flags & AMD_PG_SUPPORT_VCN_DPG) {
1840
1840
/*whenever update RBC_RB_WPTR, we save the wptr in shared rb.wptr and scratch2 */
+7
-7
drivers/gpu/drm/amd/amdgpu/vcn_v4_0.c
+7
-7
drivers/gpu/drm/amd/amdgpu/vcn_v4_0.c
···
148
148
149
149
static int vcn_v4_0_fw_shared_init(struct amdgpu_device *adev, int inst_idx)
150
150
{
151
-
volatile struct amdgpu_vcn4_fw_shared *fw_shared;
151
+
struct amdgpu_vcn4_fw_shared *fw_shared;
152
152
153
153
fw_shared = adev->vcn.inst[inst_idx].fw_shared.cpu_addr;
154
154
fw_shared->present_flag_0 = cpu_to_le32(AMDGPU_FW_SHARED_FLAG_0_UNIFIED_QUEUE);
···
278
278
279
279
if (drm_dev_enter(adev_to_drm(adev), &idx)) {
280
280
for (i = 0; i < adev->vcn.num_vcn_inst; i++) {
281
-
volatile struct amdgpu_vcn4_fw_shared *fw_shared;
281
+
struct amdgpu_vcn4_fw_shared *fw_shared;
282
282
283
283
if (adev->vcn.harvest_config & (1 << i))
284
284
continue;
···
997
997
{
998
998
struct amdgpu_device *adev = vinst->adev;
999
999
int inst_idx = vinst->inst;
1000
-
volatile struct amdgpu_vcn4_fw_shared *fw_shared = adev->vcn.inst[inst_idx].fw_shared.cpu_addr;
1000
+
struct amdgpu_vcn4_fw_shared *fw_shared = adev->vcn.inst[inst_idx].fw_shared.cpu_addr;
1001
1001
struct amdgpu_ring *ring;
1002
1002
uint32_t tmp;
1003
1003
int ret;
···
1137
1137
{
1138
1138
struct amdgpu_device *adev = vinst->adev;
1139
1139
int i = vinst->inst;
1140
-
volatile struct amdgpu_vcn4_fw_shared *fw_shared;
1140
+
struct amdgpu_vcn4_fw_shared *fw_shared;
1141
1141
struct amdgpu_ring *ring;
1142
1142
uint32_t tmp;
1143
1143
int j, k, r;
···
1354
1354
struct mmsch_v4_0_cmd_end end = { {0} };
1355
1355
struct mmsch_v4_0_init_header header;
1356
1356
1357
-
volatile struct amdgpu_vcn4_fw_shared *fw_shared;
1358
-
volatile struct amdgpu_fw_shared_rb_setup *rb_setup;
1357
+
struct amdgpu_vcn4_fw_shared *fw_shared;
1358
+
struct amdgpu_fw_shared_rb_setup *rb_setup;
1359
1359
1360
1360
direct_wt.cmd_header.command_type =
1361
1361
MMSCH_COMMAND__DIRECT_REG_WRITE;
···
1606
1606
{
1607
1607
struct amdgpu_device *adev = vinst->adev;
1608
1608
int i = vinst->inst;
1609
-
volatile struct amdgpu_vcn4_fw_shared *fw_shared;
1609
+
struct amdgpu_vcn4_fw_shared *fw_shared;
1610
1610
uint32_t tmp;
1611
1611
int r = 0;
1612
1612
+6
-6
drivers/gpu/drm/amd/amdgpu/vcn_v4_0_3.c
+6
-6
drivers/gpu/drm/amd/amdgpu/vcn_v4_0_3.c
···
263
263
264
264
if (drm_dev_enter(&adev->ddev, &idx)) {
265
265
for (i = 0; i < adev->vcn.num_vcn_inst; i++) {
266
-
volatile struct amdgpu_vcn4_fw_shared *fw_shared;
266
+
struct amdgpu_vcn4_fw_shared *fw_shared;
267
267
268
268
fw_shared = adev->vcn.inst[i].fw_shared.cpu_addr;
269
269
fw_shared->present_flag_0 = 0;
···
845
845
{
846
846
struct amdgpu_device *adev = vinst->adev;
847
847
int inst_idx = vinst->inst;
848
-
volatile struct amdgpu_vcn4_fw_shared *fw_shared =
848
+
struct amdgpu_vcn4_fw_shared *fw_shared =
849
849
adev->vcn.inst[inst_idx].fw_shared.cpu_addr;
850
850
struct amdgpu_ring *ring;
851
851
int vcn_inst, ret;
···
1012
1012
struct mmsch_v4_0_cmd_end end = { {0} };
1013
1013
struct mmsch_v4_0_3_init_header header;
1014
1014
1015
-
volatile struct amdgpu_vcn4_fw_shared *fw_shared;
1016
-
volatile struct amdgpu_fw_shared_rb_setup *rb_setup;
1015
+
struct amdgpu_vcn4_fw_shared *fw_shared;
1016
+
struct amdgpu_fw_shared_rb_setup *rb_setup;
1017
1017
1018
1018
direct_wt.cmd_header.command_type =
1019
1019
MMSCH_COMMAND__DIRECT_REG_WRITE;
···
1187
1187
{
1188
1188
struct amdgpu_device *adev = vinst->adev;
1189
1189
int i = vinst->inst;
1190
-
volatile struct amdgpu_vcn4_fw_shared *fw_shared;
1190
+
struct amdgpu_vcn4_fw_shared *fw_shared;
1191
1191
struct amdgpu_ring *ring;
1192
1192
int j, k, r, vcn_inst;
1193
1193
uint32_t tmp;
···
1397
1397
{
1398
1398
struct amdgpu_device *adev = vinst->adev;
1399
1399
int i = vinst->inst;
1400
-
volatile struct amdgpu_vcn4_fw_shared *fw_shared;
1400
+
struct amdgpu_vcn4_fw_shared *fw_shared;
1401
1401
int r = 0, vcn_inst;
1402
1402
uint32_t tmp;
1403
1403
+5
-5
drivers/gpu/drm/amd/amdgpu/vcn_v4_0_5.c
+5
-5
drivers/gpu/drm/amd/amdgpu/vcn_v4_0_5.c
···
149
149
int i, r;
150
150
151
151
for (i = 0; i < adev->vcn.num_vcn_inst; i++) {
152
-
volatile struct amdgpu_vcn4_fw_shared *fw_shared;
152
+
struct amdgpu_vcn4_fw_shared *fw_shared;
153
153
154
154
if (adev->vcn.harvest_config & (1 << i))
155
155
continue;
···
249
249
250
250
if (drm_dev_enter(adev_to_drm(adev), &idx)) {
251
251
for (i = 0; i < adev->vcn.num_vcn_inst; i++) {
252
-
volatile struct amdgpu_vcn4_fw_shared *fw_shared;
252
+
struct amdgpu_vcn4_fw_shared *fw_shared;
253
253
254
254
if (adev->vcn.harvest_config & (1 << i))
255
255
continue;
···
910
910
{
911
911
struct amdgpu_device *adev = vinst->adev;
912
912
int inst_idx = vinst->inst;
913
-
volatile struct amdgpu_vcn4_fw_shared *fw_shared = adev->vcn.inst[inst_idx].fw_shared.cpu_addr;
913
+
struct amdgpu_vcn4_fw_shared *fw_shared = adev->vcn.inst[inst_idx].fw_shared.cpu_addr;
914
914
struct amdgpu_ring *ring;
915
915
uint32_t tmp;
916
916
int ret;
···
1047
1047
{
1048
1048
struct amdgpu_device *adev = vinst->adev;
1049
1049
int i = vinst->inst;
1050
-
volatile struct amdgpu_vcn4_fw_shared *fw_shared;
1050
+
struct amdgpu_vcn4_fw_shared *fw_shared;
1051
1051
struct amdgpu_ring *ring;
1052
1052
uint32_t tmp;
1053
1053
int j, k, r;
···
1266
1266
{
1267
1267
struct amdgpu_device *adev = vinst->adev;
1268
1268
int i = vinst->inst;
1269
-
volatile struct amdgpu_vcn4_fw_shared *fw_shared;
1269
+
struct amdgpu_vcn4_fw_shared *fw_shared;
1270
1270
uint32_t tmp;
1271
1271
int r = 0;
1272
1272
+5
-5
drivers/gpu/drm/amd/amdgpu/vcn_v5_0_0.c
+5
-5
drivers/gpu/drm/amd/amdgpu/vcn_v5_0_0.c
···
129
129
int i, r;
130
130
131
131
for (i = 0; i < adev->vcn.num_vcn_inst; i++) {
132
-
volatile struct amdgpu_vcn5_fw_shared *fw_shared;
132
+
struct amdgpu_vcn5_fw_shared *fw_shared;
133
133
134
134
if (adev->vcn.harvest_config & (1 << i))
135
135
continue;
···
211
211
212
212
if (drm_dev_enter(adev_to_drm(adev), &idx)) {
213
213
for (i = 0; i < adev->vcn.num_vcn_inst; i++) {
214
-
volatile struct amdgpu_vcn5_fw_shared *fw_shared;
214
+
struct amdgpu_vcn5_fw_shared *fw_shared;
215
215
216
216
if (adev->vcn.harvest_config & (1 << i))
217
217
continue;
···
692
692
{
693
693
struct amdgpu_device *adev = vinst->adev;
694
694
int inst_idx = vinst->inst;
695
-
volatile struct amdgpu_vcn5_fw_shared *fw_shared = adev->vcn.inst[inst_idx].fw_shared.cpu_addr;
695
+
struct amdgpu_vcn5_fw_shared *fw_shared = adev->vcn.inst[inst_idx].fw_shared.cpu_addr;
696
696
struct amdgpu_ring *ring;
697
697
uint32_t tmp;
698
698
int ret;
···
802
802
{
803
803
struct amdgpu_device *adev = vinst->adev;
804
804
int i = vinst->inst;
805
-
volatile struct amdgpu_vcn5_fw_shared *fw_shared;
805
+
struct amdgpu_vcn5_fw_shared *fw_shared;
806
806
struct amdgpu_ring *ring;
807
807
uint32_t tmp;
808
808
int j, k, r;
···
995
995
{
996
996
struct amdgpu_device *adev = vinst->adev;
997
997
int i = vinst->inst;
998
-
volatile struct amdgpu_vcn5_fw_shared *fw_shared;
998
+
struct amdgpu_vcn5_fw_shared *fw_shared;
999
999
uint32_t tmp;
1000
1000
int r = 0;
1001
1001
+6
-6
drivers/gpu/drm/amd/amdgpu/vcn_v5_0_1.c
+6
-6
drivers/gpu/drm/amd/amdgpu/vcn_v5_0_1.c
···
226
226
227
227
if (drm_dev_enter(adev_to_drm(adev), &idx)) {
228
228
for (i = 0; i < adev->vcn.num_vcn_inst; i++) {
229
-
volatile struct amdgpu_vcn5_fw_shared *fw_shared;
229
+
struct amdgpu_vcn5_fw_shared *fw_shared;
230
230
231
231
fw_shared = adev->vcn.inst[i].fw_shared.cpu_addr;
232
232
fw_shared->present_flag_0 = 0;
···
640
640
{
641
641
struct amdgpu_device *adev = vinst->adev;
642
642
int inst_idx = vinst->inst;
643
-
volatile struct amdgpu_vcn5_fw_shared *fw_shared =
643
+
struct amdgpu_vcn5_fw_shared *fw_shared =
644
644
adev->vcn.inst[inst_idx].fw_shared.cpu_addr;
645
645
struct amdgpu_ring *ring;
646
646
struct dpg_pause_state state = {.fw_based = VCN_DPG_STATE__PAUSE};
···
776
776
struct mmsch_v5_0_cmd_end end = { {0} };
777
777
struct mmsch_v5_0_init_header header;
778
778
779
-
volatile struct amdgpu_vcn5_fw_shared *fw_shared;
780
-
volatile struct amdgpu_fw_shared_rb_setup *rb_setup;
779
+
struct amdgpu_vcn5_fw_shared *fw_shared;
780
+
struct amdgpu_fw_shared_rb_setup *rb_setup;
781
781
782
782
direct_wt.cmd_header.command_type =
783
783
MMSCH_COMMAND__DIRECT_REG_WRITE;
···
951
951
{
952
952
struct amdgpu_device *adev = vinst->adev;
953
953
int i = vinst->inst;
954
-
volatile struct amdgpu_vcn5_fw_shared *fw_shared;
954
+
struct amdgpu_vcn5_fw_shared *fw_shared;
955
955
struct amdgpu_ring *ring;
956
956
uint32_t tmp;
957
957
int j, k, r, vcn_inst;
···
1143
1143
{
1144
1144
struct amdgpu_device *adev = vinst->adev;
1145
1145
int i = vinst->inst;
1146
-
volatile struct amdgpu_vcn5_fw_shared *fw_shared;
1146
+
struct amdgpu_vcn5_fw_shared *fw_shared;
1147
1147
uint32_t tmp;
1148
1148
int r = 0, vcn_inst;
1149
1149