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drivers/perf: riscv: Add raw event v2 support

SBI v3.0 introduced a new raw event type that allows wider
mhpmeventX width to be programmed via CFG_MATCH.

Use the raw event v2 if SBI v3.0 is available.

Reviewed-by: Anup Patel <anup@brainfault.org>
Signed-off-by: Atish Patra <atishp@rivosinc.com>
Acked-by: Paul Walmsley <pjw@kernel.org>
Link: https://lore.kernel.org/r/20250909-pmu_event_info-v6-2-d8f80cacb884@rivosinc.com
Signed-off-by: Anup Patel <anup@brainfault.org>

authored by

Atish Patra and committed by
Anup Patel 656ef2ea 8c8d0f00

+15 -5
+4
arch/riscv/include/asm/sbi.h
··· 161 161 162 162 #define RISCV_PMU_RAW_EVENT_MASK GENMASK_ULL(47, 0) 163 163 #define RISCV_PMU_PLAT_FW_EVENT_MASK GENMASK_ULL(61, 0) 164 + /* SBI v3.0 allows extended hpmeventX width value */ 165 + #define RISCV_PMU_RAW_EVENT_V2_MASK GENMASK_ULL(55, 0) 164 166 #define RISCV_PMU_RAW_EVENT_IDX 0x20000 167 + #define RISCV_PMU_RAW_EVENT_V2_IDX 0x30000 165 168 #define RISCV_PLAT_FW_EVENT 0xFFFF 166 169 167 170 /** General pmu event codes specified in SBI PMU extension */ ··· 222 219 SBI_PMU_EVENT_TYPE_HW = 0x0, 223 220 SBI_PMU_EVENT_TYPE_CACHE = 0x1, 224 221 SBI_PMU_EVENT_TYPE_RAW = 0x2, 222 + SBI_PMU_EVENT_TYPE_RAW_V2 = 0x3, 225 223 SBI_PMU_EVENT_TYPE_FW = 0xf, 226 224 }; 227 225
+11 -5
drivers/perf/riscv_pmu_sbi.c
··· 59 59 #define PERF_EVENT_FLAG_USER_ACCESS BIT(SYSCTL_USER_ACCESS) 60 60 #define PERF_EVENT_FLAG_LEGACY BIT(SYSCTL_LEGACY) 61 61 62 - PMU_FORMAT_ATTR(event, "config:0-47"); 62 + PMU_FORMAT_ATTR(event, "config:0-55"); 63 63 PMU_FORMAT_ATTR(firmware, "config:62-63"); 64 64 65 65 static bool sbi_v2_available; ··· 527 527 break; 528 528 case PERF_TYPE_RAW: 529 529 /* 530 - * As per SBI specification, the upper 16 bits must be unused 531 - * for a hardware raw event. 530 + * As per SBI v0.3 specification, 531 + * -- the upper 16 bits must be unused for a hardware raw event. 532 + * As per SBI v2.0 specification, 533 + * -- the upper 8 bits must be unused for a hardware raw event. 532 534 * Bits 63:62 are used to distinguish between raw events 533 535 * 00 - Hardware raw event 534 536 * 10 - SBI firmware events ··· 539 537 540 538 switch (config >> 62) { 541 539 case 0: 542 - /* Return error any bits [48-63] is set as it is not allowed by the spec */ 543 - if (!(config & ~RISCV_PMU_RAW_EVENT_MASK)) { 540 + if (sbi_v3_available) { 541 + if (!(config & ~RISCV_PMU_RAW_EVENT_V2_MASK)) { 542 + *econfig = config & RISCV_PMU_RAW_EVENT_V2_MASK; 543 + ret = RISCV_PMU_RAW_EVENT_V2_IDX; 544 + } 545 + } else if (!(config & ~RISCV_PMU_RAW_EVENT_MASK)) { 544 546 *econfig = config & RISCV_PMU_RAW_EVENT_MASK; 545 547 ret = RISCV_PMU_RAW_EVENT_IDX; 546 548 }