Merge tag 'drm-next-2026-04-22' of https://gitlab.freedesktop.org/drm/kernel

+1

drivers/dma-buf/dma-buf.c

··· 1353 1353 * Upon return importers may continue to access the DMA-buf memory. The caller 1354 1354 * must do two additional waits to ensure that the memory is no longer being 1355 1355 * accessed: 1356 + * 1356 1357 * 1) Until dma_resv_wait_timeout() retires fences the importer is allowed to 1357 1358 * fully access the memory. 1358 1359 * 2) Until the importer calls unmap it is allowed to speculatively

+17

drivers/gpu/drm/amd/amdgpu/Kconfig

··· 103 103 Add -Werror to the build flags for amdgpu.ko. 104 104 Only enable this if you are warning code for amdgpu.ko. 105 105 106 + 107 + config GCOV_PROFILE_AMDGPU 108 + bool "Enable GCOV profiling on amdgpu" 109 + depends on DRM_AMDGPU 110 + depends on GCOV_KERNEL 111 + default n 112 + help 113 + Enable GCOV profiling on the amdgpu driver for checking which 114 + functions/lines are executed during testing. This adds compiler 115 + instrumentation flags to all amdgpu source files, producing 116 + .gcda/.gcno coverage data accessible via debugfs. 117 + 118 + This increases the amdgpu module size by ~50% and adds ~2-5% 119 + runtime overhead on GPU submission paths. 120 + 121 + If unsure, say N. 122 + 106 123 source "drivers/gpu/drm/amd/acp/Kconfig" 107 124 source "drivers/gpu/drm/amd/display/Kconfig" 108 125 source "drivers/gpu/drm/amd/amdkfd/Kconfig"

+4

drivers/gpu/drm/amd/amdgpu/Makefile

··· 27 27 DISPLAY_FOLDER_NAME=display 28 28 FULL_AMD_DISPLAY_PATH = $(FULL_AMD_PATH)/$(DISPLAY_FOLDER_NAME) 29 29 30 + ifdef CONFIG_GCOV_PROFILE_AMDGPU 31 + GCOV_PROFILE := y 32 + endif 33 + 30 34 ccflags-y := -I$(FULL_AMD_PATH)/include/asic_reg \ 31 35 -I$(FULL_AMD_PATH)/include \ 32 36 -I$(FULL_AMD_PATH)/amdgpu \

+1 -1

drivers/gpu/drm/amd/amdgpu/aldebaran.c

··· 179 179 list_for_each_entry(tmp_adev, reset_device_list, reset_list) { 180 180 /* For XGMI run all resets in parallel to speed up the process */ 181 181 if (tmp_adev->gmc.xgmi.num_physical_nodes > 1) { 182 - if (!queue_work(system_unbound_wq, 182 + if (!queue_work(system_dfl_wq, 183 183 &tmp_adev->reset_cntl->reset_work)) 184 184 r = -EALREADY; 185 185 } else

-5

drivers/gpu/drm/amd/amdgpu/amdgpu.h

··· 1045 1045 struct amdgpu_mqd mqds[AMDGPU_HW_IP_NUM]; 1046 1046 const struct amdgpu_userq_funcs *userq_funcs[AMDGPU_HW_IP_NUM]; 1047 1047 1048 - /* xarray used to retrieve the user queue fence driver reference 1049 - * in the EOP interrupt handler to signal the particular user 1050 - * queue fence. 1051 - */ 1052 - struct xarray userq_xa; 1053 1048 /** 1054 1049 * @userq_doorbell_xa: Global user queue map (doorbell index → queue) 1055 1050 * Key: doorbell_index (unique global identifier for the queue)

+4 -1

drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd.c

··· 805 805 } else { 806 806 tmp = adev->gmc.mem_partitions[mem_id].size; 807 807 } 808 - do_div(tmp, adev->xcp_mgr->num_xcp_per_mem_partition); 808 + 809 + if (adev->xcp_mgr->mem_alloc_mode == AMDGPU_PARTITION_MEM_CAPPING_EVEN) 810 + do_div(tmp, adev->xcp_mgr->num_xcp_per_mem_partition); 811 + 809 812 return ALIGN_DOWN(tmp, PAGE_SIZE); 810 813 } else if (adev->apu_prefer_gtt) { 811 814 return (ttm_tt_pages_limit() << PAGE_SHIFT);

+3 -3

drivers/gpu/drm/amd/amdgpu/amdgpu_atombios.c

··· 1685 1685 (uint32_t)(ATOM_VRAM_BLOCK_SRIOV_MSG_SHARE_RESERVATION << 1686 1686 ATOM_VRAM_OPERATION_FLAGS_SHIFT)) { 1687 1687 /* Firmware request VRAM reservation for SR-IOV */ 1688 - adev->mman.fw_vram_usage_start_offset = (start_addr & 1689 - (~ATOM_VRAM_OPERATION_FLAGS_MASK)) << 10; 1690 - adev->mman.fw_vram_usage_size = size << 10; 1688 + amdgpu_ttm_init_vram_resv(adev, AMDGPU_RESV_FW_VRAM_USAGE, 1689 + (start_addr & (~ATOM_VRAM_OPERATION_FLAGS_MASK)) << 10, 1690 + size << 10, true); 1691 1691 /* Use the default scratch size */ 1692 1692 usage_bytes = 0; 1693 1693 } else {

+9 -9

drivers/gpu/drm/amd/amdgpu/amdgpu_atomfirmware.c

··· 120 120 (u32)(ATOM_VRAM_BLOCK_SRIOV_MSG_SHARE_RESERVATION << 121 121 ATOM_VRAM_OPERATION_FLAGS_SHIFT)) { 122 122 /* Firmware request VRAM reservation for SR-IOV */ 123 - adev->mman.fw_vram_usage_start_offset = (start_addr & 124 - (~ATOM_VRAM_OPERATION_FLAGS_MASK)) << 10; 125 - adev->mman.fw_vram_usage_size = fw_size << 10; 123 + amdgpu_ttm_init_vram_resv(adev, AMDGPU_RESV_FW_VRAM_USAGE, 124 + (start_addr & (~ATOM_VRAM_OPERATION_FLAGS_MASK)) << 10, 125 + fw_size << 10, true); 126 126 /* Use the default scratch size */ 127 127 *usage_bytes = 0; 128 128 } else { ··· 152 152 ((fw_start_addr & (ATOM_VRAM_BLOCK_NEEDS_NO_RESERVATION << 153 153 ATOM_VRAM_OPERATION_FLAGS_SHIFT)) == 0)) { 154 154 /* Firmware request VRAM reservation for SR-IOV */ 155 - adev->mman.fw_vram_usage_start_offset = (fw_start_addr & 156 - (~ATOM_VRAM_OPERATION_FLAGS_MASK)) << 10; 157 - adev->mman.fw_vram_usage_size = fw_size << 10; 155 + amdgpu_ttm_init_vram_resv(adev, AMDGPU_RESV_FW_VRAM_USAGE, 156 + (fw_start_addr & (~ATOM_VRAM_OPERATION_FLAGS_MASK)) << 10, 157 + fw_size << 10, true); 158 158 } 159 159 160 160 if (amdgpu_sriov_vf(adev) && 161 161 ((drv_start_addr & (ATOM_VRAM_BLOCK_NEEDS_NO_RESERVATION << 162 162 ATOM_VRAM_OPERATION_FLAGS_SHIFT)) == 0)) { 163 163 /* driver request VRAM reservation for SR-IOV */ 164 - adev->mman.drv_vram_usage_start_offset = (drv_start_addr & 165 - (~ATOM_VRAM_OPERATION_FLAGS_MASK)) << 10; 166 - adev->mman.drv_vram_usage_size = drv_size << 10; 164 + amdgpu_ttm_init_vram_resv(adev, AMDGPU_RESV_DRV_VRAM_USAGE, 165 + (drv_start_addr & (~ATOM_VRAM_OPERATION_FLAGS_MASK)) << 10, 166 + drv_size << 10, true); 167 167 } 168 168 169 169 *usage_bytes = 0;

+168 -17

drivers/gpu/drm/amd/amdgpu/amdgpu_dev_coredump.c

··· 210 210 static ssize_t 211 211 amdgpu_devcoredump_format(char *buffer, size_t count, struct amdgpu_coredump_info *coredump) 212 212 { 213 + struct amdgpu_device *adev = coredump->adev; 213 214 struct drm_printer p; 214 215 struct drm_print_iterator iter; 215 216 struct amdgpu_vm_fault_info *fault_info; 217 + struct amdgpu_bo_va_mapping *mapping; 216 218 struct amdgpu_ip_block *ip_block; 217 - int ver; 219 + struct amdgpu_res_cursor cursor; 220 + struct amdgpu_bo *abo, *root; 221 + uint64_t va_start, offset; 222 + struct amdgpu_ring *ring; 223 + struct amdgpu_vm *vm; 224 + u32 *ib_content; 225 + uint8_t *kptr; 226 + int ver, i, j, r; 227 + u32 ring_idx, off; 228 + bool sizing_pass; 218 229 230 + sizing_pass = buffer == NULL; 219 231 iter.data = buffer; 220 232 iter.offset = 0; 221 233 iter.remain = count; ··· 315 303 316 304 /* Add ring buffer information */ 317 305 drm_printf(&p, "Ring buffer information\n"); 318 - for (int i = 0; i < coredump->adev->num_rings; i++) { 319 - int j = 0; 320 - struct amdgpu_ring *ring = coredump->adev->rings[i]; 306 + if (coredump->num_rings) { 307 + for (i = 0; i < coredump->num_rings; i++) { 308 + ring_idx = coredump->rings[i].ring_index; 309 + ring = coredump->adev->rings[ring_idx]; 310 + off = coredump->rings[i].offset; 321 311 322 - drm_printf(&p, "ring name: %s\n", ring->name); 323 - drm_printf(&p, "Rptr: 0x%llx Wptr: 0x%llx RB mask: %x\n", 324 - amdgpu_ring_get_rptr(ring), 325 - amdgpu_ring_get_wptr(ring), 326 - ring->buf_mask); 327 - drm_printf(&p, "Ring size in dwords: %d\n", 328 - ring->ring_size / 4); 329 - drm_printf(&p, "Ring contents\n"); 330 - drm_printf(&p, "Offset \t Value\n"); 312 + drm_printf(&p, "ring name: %s\n", ring->name); 313 + drm_printf(&p, "Rptr: 0x%llx Wptr: 0x%llx RB mask: %x\n", 314 + coredump->rings[i].rptr, 315 + coredump->rings[i].wptr, 316 + ring->buf_mask); 317 + drm_printf(&p, "Ring size in dwords: %d\n", 318 + ring->ring_size / 4); 319 + drm_printf(&p, "Ring contents\n"); 320 + drm_printf(&p, "Offset \t Value\n"); 331 321 332 - while (j < ring->ring_size) { 333 - drm_printf(&p, "0x%x \t 0x%x\n", j, ring->ring[j / 4]); 334 - j += 4; 322 + for (j = 0; j < ring->ring_size; j += 4) 323 + drm_printf(&p, "0x%x \t 0x%x\n", j, 324 + coredump->rings_dw[off + j / 4]); 335 325 } 336 326 } 337 327 ··· 341 327 drm_printf(&p, "VRAM lost check is skipped!\n"); 342 328 else if (coredump->reset_vram_lost) 343 329 drm_printf(&p, "VRAM is lost due to GPU reset!\n"); 330 + 331 + if (coredump->num_ibs) { 332 + /* Don't try to lookup the VM or map the BOs when calculating the 333 + * size required to store the devcoredump. 334 + */ 335 + if (sizing_pass) 336 + vm = NULL; 337 + else 338 + vm = amdgpu_vm_lock_by_pasid(adev, &root, coredump->pasid); 339 + 340 + for (int i = 0; i < coredump->num_ibs && (sizing_pass || vm); i++) { 341 + ib_content = kvmalloc_array(coredump->ibs[i].ib_size_dw, 4, 342 + GFP_KERNEL); 343 + if (!ib_content) 344 + continue; 345 + 346 + /* vm=NULL can only happen when 'sizing_pass' is true. Skip to the 347 + * drm_printf() calls (ib_content doesn't need to be initialized 348 + * as its content won't be written anywhere). 349 + */ 350 + if (!vm) 351 + goto output_ib_content; 352 + 353 + va_start = coredump->ibs[i].gpu_addr & AMDGPU_GMC_HOLE_MASK; 354 + mapping = amdgpu_vm_bo_lookup_mapping(vm, va_start / AMDGPU_GPU_PAGE_SIZE); 355 + if (!mapping) 356 + goto free_ib_content; 357 + 358 + offset = va_start - (mapping->start * AMDGPU_GPU_PAGE_SIZE); 359 + abo = amdgpu_bo_ref(mapping->bo_va->base.bo); 360 + r = amdgpu_bo_reserve(abo, false); 361 + if (r) 362 + goto free_ib_content; 363 + 364 + if (abo->flags & AMDGPU_GEM_CREATE_NO_CPU_ACCESS) { 365 + off = 0; 366 + 367 + if (abo->tbo.resource->mem_type != TTM_PL_VRAM) 368 + goto unreserve_abo; 369 + 370 + amdgpu_res_first(abo->tbo.resource, offset, 371 + coredump->ibs[i].ib_size_dw * 4, 372 + &cursor); 373 + while (cursor.remaining) { 374 + amdgpu_device_mm_access(adev, cursor.start / 4, 375 + &ib_content[off], cursor.size / 4, 376 + false); 377 + off += cursor.size; 378 + amdgpu_res_next(&cursor, cursor.size); 379 + } 380 + } else { 381 + r = ttm_bo_kmap(&abo->tbo, 0, 382 + PFN_UP(abo->tbo.base.size), 383 + &abo->kmap); 384 + if (r) 385 + goto unreserve_abo; 386 + 387 + kptr = amdgpu_bo_kptr(abo); 388 + kptr += offset; 389 + memcpy(ib_content, kptr, 390 + coredump->ibs[i].ib_size_dw * 4); 391 + 392 + amdgpu_bo_kunmap(abo); 393 + } 394 + 395 + output_ib_content: 396 + drm_printf(&p, "\nIB #%d 0x%llx %d dw\n", 397 + i, coredump->ibs[i].gpu_addr, coredump->ibs[i].ib_size_dw); 398 + for (int j = 0; j < coredump->ibs[i].ib_size_dw; j++) 399 + drm_printf(&p, "0x%08x\n", ib_content[j]); 400 + unreserve_abo: 401 + if (vm) 402 + amdgpu_bo_unreserve(abo); 403 + free_ib_content: 404 + kvfree(ib_content); 405 + } 406 + if (vm) { 407 + amdgpu_bo_unreserve(root); 408 + amdgpu_bo_unref(&root); 409 + } 410 + } 344 411 345 412 return count - iter.remain; 346 413 } ··· 454 359 struct amdgpu_coredump_info *coredump = data; 455 360 456 361 kvfree(coredump->formatted); 362 + kvfree(coredump->rings); 363 + kvfree(coredump->rings_dw); 457 364 kvfree(data); 458 365 } 459 366 ··· 492 395 { 493 396 struct drm_device *dev = adev_to_drm(adev); 494 397 struct amdgpu_coredump_info *coredump; 398 + size_t size = sizeof(*coredump); 495 399 struct drm_sched_job *s_job; 400 + u64 total_ring_size, ring_count; 401 + struct amdgpu_ring *ring; 402 + int i, off, idx; 496 403 497 404 /* No need to generate a new coredump if there's one in progress already. */ 498 405 if (work_pending(&adev->coredump_work)) 499 406 return; 500 407 501 - coredump = kzalloc_obj(*coredump, GFP_NOWAIT); 408 + if (job && job->pasid) 409 + size += sizeof(struct amdgpu_coredump_ib_info) * job->num_ibs; 410 + 411 + coredump = kzalloc(size, GFP_NOWAIT); 502 412 if (!coredump) 503 413 return; 504 414 505 415 coredump->skip_vram_check = skip_vram_check; 506 416 coredump->reset_vram_lost = vram_lost; 417 + coredump->pasid = job->pasid; 507 418 508 419 if (job && job->pasid) { 509 420 struct amdgpu_task_info *ti; ··· 521 416 coredump->reset_task_info = *ti; 522 417 amdgpu_vm_put_task_info(ti); 523 418 } 419 + coredump->num_ibs = job->num_ibs; 420 + for (i = 0; i < job->num_ibs; ++i) { 421 + coredump->ibs[i].gpu_addr = job->ibs[i].gpu_addr; 422 + coredump->ibs[i].ib_size_dw = job->ibs[i].length_dw; 423 + } 524 424 } 525 425 526 426 if (job) { 527 427 s_job = &job->base; 528 428 coredump->ring = to_amdgpu_ring(s_job->sched); 429 + } 430 + 431 + /* Dump ring content if memory allocation succeeds. */ 432 + ring_count = 0; 433 + total_ring_size = 0; 434 + for (i = 0; i < adev->num_rings; i++) { 435 + ring = adev->rings[i]; 436 + 437 + /* Only dump rings with unsignalled fences. */ 438 + if (atomic_read(&ring->fence_drv.last_seq) == ring->fence_drv.sync_seq && 439 + coredump->ring != ring) 440 + continue; 441 + 442 + total_ring_size += ring->ring_size; 443 + ring_count++; 444 + } 445 + coredump->rings_dw = kzalloc(total_ring_size, GFP_NOWAIT); 446 + coredump->rings = kcalloc(ring_count, sizeof(struct amdgpu_coredump_ring), GFP_NOWAIT); 447 + if (coredump->rings && coredump->rings_dw) { 448 + for (i = 0, off = 0, idx = 0; i < adev->num_rings; i++) { 449 + ring = adev->rings[i]; 450 + 451 + if (atomic_read(&ring->fence_drv.last_seq) == ring->fence_drv.sync_seq && 452 + coredump->ring != ring) 453 + continue; 454 + 455 + coredump->rings[idx].ring_index = ring->idx; 456 + coredump->rings[idx].rptr = amdgpu_ring_get_rptr(ring); 457 + coredump->rings[idx].wptr = amdgpu_ring_get_wptr(ring); 458 + coredump->rings[idx].offset = off; 459 + 460 + memcpy(&coredump->rings_dw[off], ring->ring, ring->ring_size); 461 + off += ring->ring_size; 462 + idx++; 463 + } 464 + coredump->num_rings = idx; 465 + } else { 466 + kvfree(coredump->rings_dw); 467 + kvfree(coredump->rings); 468 + coredump->rings_dw = NULL; 469 + coredump->rings = NULL; 529 470 } 530 471 531 472 coredump->adev = adev;

+21

drivers/gpu/drm/amd/amdgpu/amdgpu_dev_coredump.h

··· 31 31 32 32 #define AMDGPU_COREDUMP_VERSION "1" 33 33 34 + struct amdgpu_coredump_ring { 35 + u64 rptr; 36 + u64 wptr; 37 + u32 ring_index; 38 + u32 offset; 39 + }; 40 + 41 + struct amdgpu_coredump_ib_info { 42 + uint64_t gpu_addr; 43 + u32 ib_size_dw; 44 + }; 45 + 34 46 struct amdgpu_coredump_info { 35 47 struct amdgpu_device *adev; 36 48 struct amdgpu_task_info reset_task_info; ··· 51 39 bool skip_vram_check; 52 40 bool reset_vram_lost; 53 41 struct amdgpu_ring *ring; 42 + 43 + struct amdgpu_coredump_ring *rings; 44 + u32 *rings_dw; 45 + u32 num_rings; 46 + 54 47 /* Readable form of coredevdump, generate once to speed up 55 48 * reading it (see drm_coredump_printer's documentation). 56 49 */ 57 50 ssize_t formatted_size; 58 51 char *formatted; 52 + 53 + unsigned int pasid; 54 + int num_ibs; 55 + struct amdgpu_coredump_ib_info ibs[] __counted_by(num_ibs); 59 56 }; 60 57 #endif 61 58

+4 -6

drivers/gpu/drm/amd/amdgpu/amdgpu_device.c

··· 3757 3757 spin_lock_init(&adev->virt.rlcg_reg_lock); 3758 3758 spin_lock_init(&adev->wb.lock); 3759 3759 3760 - xa_init_flags(&adev->userq_xa, XA_FLAGS_LOCK_IRQ); 3761 - 3762 3760 INIT_LIST_HEAD(&adev->reset_list); 3763 3761 3764 3762 INIT_LIST_HEAD(&adev->ras_list); 3765 3763 3766 3764 INIT_LIST_HEAD(&adev->pm.od_kobj_list); 3767 3765 3768 - xa_init(&adev->userq_doorbell_xa); 3766 + xa_init_flags(&adev->userq_doorbell_xa, XA_FLAGS_LOCK_IRQ); 3769 3767 3770 3768 INIT_DELAYED_WORK(&adev->delayed_init_work, 3771 3769 amdgpu_device_delayed_init_work_handler); ··· 4063 4065 } 4064 4066 /* must succeed. */ 4065 4067 amdgpu_ras_resume(adev); 4066 - queue_delayed_work(system_wq, &adev->delayed_init_work, 4068 + queue_delayed_work(system_dfl_wq, &adev->delayed_init_work, 4067 4069 msecs_to_jiffies(AMDGPU_RESUME_MS)); 4068 4070 } 4069 4071 ··· 4628 4630 if (r) 4629 4631 goto exit; 4630 4632 4631 - queue_delayed_work(system_wq, &adev->delayed_init_work, 4633 + queue_delayed_work(system_dfl_wq, &adev->delayed_init_work, 4632 4634 msecs_to_jiffies(AMDGPU_RESUME_MS)); 4633 4635 exit: 4634 4636 if (amdgpu_sriov_vf(adev)) { ··· 5337 5339 list_for_each_entry(tmp_adev, device_list_handle, reset_list) { 5338 5340 /* For XGMI run all resets in parallel to speed up the process */ 5339 5341 if (tmp_adev->gmc.xgmi.num_physical_nodes > 1) { 5340 - if (!queue_work(system_unbound_wq, 5342 + if (!queue_work(system_dfl_wq, 5341 5343 &tmp_adev->xgmi_reset_work)) 5342 5344 r = -EALREADY; 5343 5345 } else

+2 -5

drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c

··· 641 641 * CIK (Sea Islands) are second generation GCN GPUs, supported by both 642 642 * drivers: radeon (old) and amdgpu (new). This parameter controls whether 643 643 * amdgpu should support CIK. 644 - * By default: 645 - * - CIK dedicated GPUs are supported by amdgpu. 646 - * - CIK APUs are supported by radeon (except when radeon is not built). 644 + * By default, CIK dedicated GPUs and APUs are supported by amdgpu. 647 645 * Only relevant when CONFIG_DRM_AMDGPU_CIK is enabled to build CIK support in amdgpu. 648 646 * See also radeon.cik_support which should be disabled when amdgpu.cik_support is 649 647 * enabled, and vice versa. ··· 2321 2323 2322 2324 case CHIP_BONAIRE: 2323 2325 case CHIP_HAWAII: 2324 - support_by_default = true; 2325 - fallthrough; 2326 2326 case CHIP_KAVERI: 2327 2327 case CHIP_KABINI: 2328 2328 case CHIP_MULLINS: ··· 2328 2332 param = "cik_support"; 2329 2333 module_param = amdgpu_cik_support; 2330 2334 amdgpu_support_built = IS_ENABLED(CONFIG_DRM_AMDGPU_CIK); 2335 + support_by_default = true; 2331 2336 break; 2332 2337 2333 2338 default:

+39

drivers/gpu/drm/amd/amdgpu/amdgpu_gfx.c

··· 1580 1580 return count; 1581 1581 } 1582 1582 1583 + static ssize_t compute_partition_mem_alloc_mode_show(struct device *dev, 1584 + struct device_attribute *addr, 1585 + char *buf) 1586 + { 1587 + struct drm_device *ddev = dev_get_drvdata(dev); 1588 + struct amdgpu_device *adev = drm_to_adev(ddev); 1589 + int mode = adev->xcp_mgr->mem_alloc_mode; 1590 + 1591 + return sysfs_emit(buf, "%s\n", 1592 + amdgpu_gfx_compute_mem_alloc_mode_desc(mode)); 1593 + } 1594 + 1595 + 1596 + static ssize_t compute_partition_mem_alloc_mode_store(struct device *dev, 1597 + struct device_attribute *addr, 1598 + const char *buf, size_t count) 1599 + { 1600 + struct drm_device *ddev = dev_get_drvdata(dev); 1601 + struct amdgpu_device *adev = drm_to_adev(ddev); 1602 + 1603 + if (!strncasecmp("CAPPING", buf, strlen("CAPPING"))) 1604 + adev->xcp_mgr->mem_alloc_mode = AMDGPU_PARTITION_MEM_CAPPING_EVEN; 1605 + else if (!strncasecmp("ALL", buf, strlen("ALL"))) 1606 + adev->xcp_mgr->mem_alloc_mode = AMDGPU_PARTITION_MEM_ALLOC_ALL; 1607 + else 1608 + return -EINVAL; 1609 + 1610 + return count; 1611 + } 1612 + 1583 1613 static const char *xcp_desc[] = { 1584 1614 [AMDGPU_SPX_PARTITION_MODE] = "SPX", 1585 1615 [AMDGPU_DPX_PARTITION_MODE] = "DPX", ··· 1965 1935 static DEVICE_ATTR(compute_reset_mask, 0444, 1966 1936 amdgpu_gfx_get_compute_reset_mask, NULL); 1967 1937 1938 + static DEVICE_ATTR(compute_partition_mem_alloc_mode, 0644, 1939 + compute_partition_mem_alloc_mode_show, 1940 + compute_partition_mem_alloc_mode_store); 1941 + 1968 1942 static int amdgpu_gfx_sysfs_xcp_init(struct amdgpu_device *adev) 1969 1943 { 1970 1944 struct amdgpu_xcp_mgr *xcp_mgr = adev->xcp_mgr; ··· 1986 1952 ~(S_IWUSR | S_IWGRP | S_IWOTH); 1987 1953 1988 1954 r = device_create_file(adev->dev, &dev_attr_current_compute_partition); 1955 + if (r) 1956 + return r; 1957 + 1958 + r = device_create_file(adev->dev, 1959 + &dev_attr_compute_partition_mem_alloc_mode); 1989 1960 if (r) 1990 1961 return r; 1991 1962

+17

drivers/gpu/drm/amd/amdgpu/amdgpu_gfx.h

··· 71 71 AMDGPU_AUTO_COMPUTE_PARTITION_MODE = -2, 72 72 }; 73 73 74 + enum amdgpu_gfx_partition_mem_alloc_mode { 75 + AMDGPU_PARTITION_MEM_CAPPING_EVEN = 0, 76 + AMDGPU_PARTITION_MEM_ALLOC_ALL = 1, 77 + }; 78 + 74 79 #define NUM_XCC(x) hweight16(x) 75 80 76 81 enum amdgpu_gfx_ras_mem_id_type { ··· 677 672 return "QPX"; 678 673 case AMDGPU_CPX_PARTITION_MODE: 679 674 return "CPX"; 675 + default: 676 + return "UNKNOWN"; 677 + } 678 + } 679 + 680 + static inline const char *amdgpu_gfx_compute_mem_alloc_mode_desc(int mode) 681 + { 682 + switch (mode) { 683 + case AMDGPU_PARTITION_MEM_CAPPING_EVEN: 684 + return "CAPPING"; 685 + case AMDGPU_PARTITION_MEM_ALLOC_ALL: 686 + return "ALL"; 680 687 default: 681 688 return "UNKNOWN"; 682 689 }

+13 -10

drivers/gpu/drm/amd/amdgpu/amdgpu_gmc.c

··· 1033 1033 } 1034 1034 } 1035 1035 1036 - void amdgpu_gmc_get_vbios_allocations(struct amdgpu_device *adev) 1036 + void amdgpu_gmc_init_vga_resv_regions(struct amdgpu_device *adev) 1037 1037 { 1038 1038 unsigned size; 1039 + 1040 + if (adev->gmc.is_app_apu) 1041 + return; 1039 1042 1040 1043 /* 1041 1044 * Some ASICs need to reserve a region of video memory to avoid access 1042 1045 * from driver 1043 1046 */ 1044 - adev->mman.stolen_reserved_offset = 0; 1045 - adev->mman.stolen_reserved_size = 0; 1046 - 1047 1047 /* 1048 1048 * TODO: 1049 1049 * Currently there is a bug where some memory client outside ··· 1060 1060 */ 1061 1061 #ifdef CONFIG_X86 1062 1062 if (amdgpu_sriov_vf(adev) && hypervisor_is_type(X86_HYPER_MS_HYPERV)) { 1063 - adev->mman.stolen_reserved_offset = 0x500000; 1064 - adev->mman.stolen_reserved_size = 0x200000; 1063 + amdgpu_ttm_init_vram_resv(adev, AMDGPU_RESV_STOLEN_RESERVED, 1064 + 0x500000, 0x200000, false); 1065 1065 } 1066 1066 #endif 1067 1067 break; ··· 1099 1099 size = 0; 1100 1100 1101 1101 if (size > AMDGPU_VBIOS_VGA_ALLOCATION) { 1102 - adev->mman.stolen_vga_size = AMDGPU_VBIOS_VGA_ALLOCATION; 1103 - adev->mman.stolen_extended_size = size - adev->mman.stolen_vga_size; 1102 + amdgpu_ttm_init_vram_resv(adev, AMDGPU_RESV_STOLEN_VGA, 1103 + 0, AMDGPU_VBIOS_VGA_ALLOCATION, false); 1104 + amdgpu_ttm_init_vram_resv(adev, AMDGPU_RESV_STOLEN_EXTENDED, 1105 + AMDGPU_VBIOS_VGA_ALLOCATION, 1106 + size - AMDGPU_VBIOS_VGA_ALLOCATION, false); 1104 1107 } else { 1105 - adev->mman.stolen_vga_size = size; 1106 - adev->mman.stolen_extended_size = 0; 1108 + amdgpu_ttm_init_vram_resv(adev, AMDGPU_RESV_STOLEN_VGA, 1109 + 0, size, false); 1107 1110 } 1108 1111 } 1109 1112

+1 -1

drivers/gpu/drm/amd/amdgpu/amdgpu_gmc.h

··· 456 456 amdgpu_gmc_set_vm_fault_masks(struct amdgpu_device *adev, int hub_type, 457 457 bool enable); 458 458 459 - void amdgpu_gmc_get_vbios_allocations(struct amdgpu_device *adev); 459 + void amdgpu_gmc_init_vga_resv_regions(struct amdgpu_device *adev); 460 460 461 461 void amdgpu_gmc_init_pdb0(struct amdgpu_device *adev); 462 462 uint64_t amdgpu_gmc_vram_mc2pa(struct amdgpu_device *adev, uint64_t mc_addr);

+19 -20

drivers/gpu/drm/amd/amdgpu/amdgpu_ids.c

··· 22 22 */ 23 23 #include "amdgpu_ids.h" 24 24 25 - #include <linux/idr.h> 25 + #include <linux/xarray.h> 26 26 #include <linux/dma-fence-array.h> 27 27 28 28 ··· 40 40 * VMs are looked up from the PASID per amdgpu_device. 41 41 */ 42 42 43 - static DEFINE_IDR(amdgpu_pasid_idr); 44 - static DEFINE_SPINLOCK(amdgpu_pasid_idr_lock); 43 + static DEFINE_XARRAY_FLAGS(amdgpu_pasid_xa, XA_FLAGS_LOCK_IRQ | XA_FLAGS_ALLOC1); 44 + static u32 amdgpu_pasid_xa_next; 45 45 46 46 /* Helper to free pasid from a fence callback */ 47 47 struct amdgpu_pasid_cb { ··· 62 62 */ 63 63 int amdgpu_pasid_alloc(unsigned int bits) 64 64 { 65 - int pasid; 65 + u32 pasid; 66 + int r; 66 67 67 68 if (bits == 0) 68 69 return -EINVAL; 69 70 70 - spin_lock(&amdgpu_pasid_idr_lock); 71 - /* TODO: Need to replace the idr with an xarry, and then 72 - * handle the internal locking with ATOMIC safe paths. 73 - */ 74 - pasid = idr_alloc_cyclic(&amdgpu_pasid_idr, NULL, 1, 75 - 1U << bits, GFP_ATOMIC); 76 - spin_unlock(&amdgpu_pasid_idr_lock); 71 + r = xa_alloc_cyclic_irq(&amdgpu_pasid_xa, &pasid, xa_mk_value(0), 72 + XA_LIMIT(1, (1U << bits) - 1), 73 + &amdgpu_pasid_xa_next, GFP_KERNEL); 74 + if (r < 0) 75 + return r; 77 76 78 - if (pasid >= 0) 79 - trace_amdgpu_pasid_allocated(pasid); 80 - 77 + trace_amdgpu_pasid_allocated(pasid); 81 78 return pasid; 82 79 } 83 80 84 81 /** 85 82 * amdgpu_pasid_free - Free a PASID 86 83 * @pasid: PASID to free 84 + * 85 + * Called in IRQ context. 87 86 */ 88 87 void amdgpu_pasid_free(u32 pasid) 89 88 { 89 + unsigned long flags; 90 + 90 91 trace_amdgpu_pasid_freed(pasid); 91 92 92 - spin_lock(&amdgpu_pasid_idr_lock); 93 - idr_remove(&amdgpu_pasid_idr, pasid); 94 - spin_unlock(&amdgpu_pasid_idr_lock); 93 + xa_lock_irqsave(&amdgpu_pasid_xa, flags); 94 + __xa_erase(&amdgpu_pasid_xa, pasid); 95 + xa_unlock_irqrestore(&amdgpu_pasid_xa, flags); 95 96 } 96 97 97 98 static void amdgpu_pasid_free_cb(struct dma_fence *fence, ··· 635 634 */ 636 635 void amdgpu_pasid_mgr_cleanup(void) 637 636 { 638 - spin_lock(&amdgpu_pasid_idr_lock); 639 - idr_destroy(&amdgpu_pasid_idr); 640 - spin_unlock(&amdgpu_pasid_idr_lock); 637 + xa_destroy(&amdgpu_pasid_xa); 641 638 }

+7 -6

drivers/gpu/drm/amd/amdgpu/amdgpu_psp.c

··· 1076 1076 return 0; 1077 1077 } 1078 1078 1079 - amdgpu_bo_free_kernel(&adev->mman.fw_reserved_memory, NULL, NULL); 1079 + amdgpu_ttm_unmark_vram_reserved(adev, AMDGPU_RESV_FW); 1080 1080 1081 1081 reserv_size = roundup(reserv_size, SZ_1M); 1082 1082 1083 - ret = amdgpu_bo_create_kernel_at(adev, reserv_addr, reserv_size, &adev->mman.fw_reserved_memory, NULL); 1083 + amdgpu_ttm_init_vram_resv(adev, AMDGPU_RESV_FW, 1084 + reserv_addr, reserv_size, false); 1085 + ret = amdgpu_ttm_mark_vram_reserved(adev, AMDGPU_RESV_FW); 1084 1086 if (ret) { 1085 1087 dev_err(adev->dev, "reserve fw region failed(%d)!\n", ret); 1086 - amdgpu_bo_free_kernel(&adev->mman.fw_reserved_memory, NULL, NULL); 1087 1088 return ret; 1088 1089 } 1089 1090 1090 1091 reserv_size_ext = roundup(reserv_size_ext, SZ_1M); 1091 1092 1092 - ret = amdgpu_bo_create_kernel_at(adev, reserv_addr_ext, reserv_size_ext, 1093 - &adev->mman.fw_reserved_memory_extend, NULL); 1093 + amdgpu_ttm_init_vram_resv(adev, AMDGPU_RESV_FW_EXTEND, 1094 + reserv_addr_ext, reserv_size_ext, false); 1095 + ret = amdgpu_ttm_mark_vram_reserved(adev, AMDGPU_RESV_FW_EXTEND); 1094 1096 if (ret) { 1095 1097 dev_err(adev->dev, "reserve extend fw region failed(%d)!\n", ret); 1096 - amdgpu_bo_free_kernel(&adev->mman.fw_reserved_memory_extend, NULL, NULL); 1097 1098 return ret; 1098 1099 } 1099 1100

-1

drivers/gpu/drm/amd/amdgpu/amdgpu_psp.h

··· 277 277 278 278 /*vram offset of the c2p training data*/ 279 279 u64 c2p_train_data_offset; 280 - struct amdgpu_bo *c2p_bo; 281 280 282 281 enum psp_memory_training_init_flag init; 283 282 u32 training_cnt;

+1 -1

drivers/gpu/drm/amd/amdgpu/amdgpu_ras.c

··· 5726 5726 5727 5727 static void amdgpu_ras_critical_region_init(struct amdgpu_device *adev) 5728 5728 { 5729 - amdgpu_ras_add_critical_region(adev, adev->mman.fw_reserved_memory); 5729 + amdgpu_ras_add_critical_region(adev, adev->mman.resv_region[AMDGPU_RESV_FW].bo); 5730 5730 } 5731 5731 5732 5732 static void amdgpu_ras_critical_region_fini(struct amdgpu_device *adev)

+1 -1

drivers/gpu/drm/amd/amdgpu/amdgpu_reset.c

··· 116 116 /* Mode1 reset needs to be triggered on all devices together */ 117 117 list_for_each_entry(tmp_adev, reset_device_list, reset_list) { 118 118 /* For XGMI run all resets in parallel to speed up the process */ 119 - if (!queue_work(system_unbound_wq, &tmp_adev->xgmi_reset_work)) 119 + if (!queue_work(system_dfl_wq, &tmp_adev->xgmi_reset_work)) 120 120 r = -EALREADY; 121 121 if (r) { 122 122 dev_err(tmp_adev->dev,

+7 -4

drivers/gpu/drm/amd/amdgpu/amdgpu_ring.h

··· 559 559 560 560 int amdgpu_ring_init_mqd(struct amdgpu_ring *ring); 561 561 562 - static inline u32 amdgpu_ib_get_value(struct amdgpu_ib *ib, int idx) 562 + static inline u32 amdgpu_ib_get_value(struct amdgpu_ib *ib, uint32_t idx) 563 563 { 564 - return ib->ptr[idx]; 564 + if (idx < ib->length_dw) 565 + return ib->ptr[idx]; 566 + return 0; 565 567 } 566 568 567 - static inline void amdgpu_ib_set_value(struct amdgpu_ib *ib, int idx, 569 + static inline void amdgpu_ib_set_value(struct amdgpu_ib *ib, uint32_t idx, 568 570 uint32_t value) 569 571 { 570 - ib->ptr[idx] = value; 572 + if (idx < ib->length_dw) 573 + ib->ptr[idx] = value; 571 574 } 572 575 573 576 int amdgpu_ib_get(struct amdgpu_device *adev, struct amdgpu_vm *vm,

+157 -207

drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.c

··· 1671 1671 .access_memory = &amdgpu_ttm_access_memory, 1672 1672 }; 1673 1673 1674 - /* 1675 - * Firmware Reservation functions 1676 - */ 1677 - /** 1678 - * amdgpu_ttm_fw_reserve_vram_fini - free fw reserved vram 1679 - * 1680 - * @adev: amdgpu_device pointer 1681 - * 1682 - * free fw reserved vram if it has been reserved. 1683 - */ 1684 - static void amdgpu_ttm_fw_reserve_vram_fini(struct amdgpu_device *adev) 1674 + void amdgpu_ttm_init_vram_resv(struct amdgpu_device *adev, 1675 + enum amdgpu_resv_region_id id, 1676 + uint64_t offset, uint64_t size, 1677 + bool needs_cpu_map) 1685 1678 { 1686 - amdgpu_bo_free_kernel(&adev->mman.fw_vram_usage_reserved_bo, 1687 - NULL, &adev->mman.fw_vram_usage_va); 1679 + struct amdgpu_vram_resv *resv; 1680 + 1681 + if (id >= AMDGPU_RESV_MAX) 1682 + return; 1683 + 1684 + resv = &adev->mman.resv_region[id]; 1685 + resv->offset = offset; 1686 + resv->size = size; 1687 + resv->needs_cpu_map = needs_cpu_map; 1688 1688 } 1689 1689 1690 - /* 1691 - * Driver Reservation functions 1692 - */ 1693 - /** 1694 - * amdgpu_ttm_drv_reserve_vram_fini - free drv reserved vram 1695 - * 1696 - * @adev: amdgpu_device pointer 1697 - * 1698 - * free drv reserved vram if it has been reserved. 1699 - */ 1700 - static void amdgpu_ttm_drv_reserve_vram_fini(struct amdgpu_device *adev) 1690 + static void amdgpu_ttm_init_fw_resv_region(struct amdgpu_device *adev) 1701 1691 { 1702 - amdgpu_bo_free_kernel(&adev->mman.drv_vram_usage_reserved_bo, 1703 - NULL, 1704 - &adev->mman.drv_vram_usage_va); 1692 + uint32_t reserve_size = 0; 1693 + 1694 + if (!adev->discovery.reserve_tmr) 1695 + return; 1696 + 1697 + /* 1698 + * Query reserved tmr size through atom firmwareinfo for Sienna_Cichlid and onwards for all 1699 + * the use cases (IP discovery/G6 memory training/profiling/diagnostic data.etc) 1700 + * 1701 + * Otherwise, fallback to legacy approach to check and reserve tmr block for ip 1702 + * discovery data and G6 memory training data respectively 1703 + */ 1704 + if (adev->bios) 1705 + reserve_size = 1706 + amdgpu_atomfirmware_get_fw_reserved_fb_size(adev); 1707 + 1708 + if (!adev->bios && 1709 + (amdgpu_ip_version(adev, GC_HWIP, 0) == IP_VERSION(9, 4, 3) || 1710 + amdgpu_ip_version(adev, GC_HWIP, 0) == IP_VERSION(9, 4, 4) || 1711 + amdgpu_ip_version(adev, GC_HWIP, 0) == IP_VERSION(9, 5, 0))) 1712 + reserve_size = max(reserve_size, (uint32_t)280 << 20); 1713 + else if (!adev->bios && 1714 + amdgpu_ip_version(adev, GC_HWIP, 0) == IP_VERSION(12, 1, 0)) { 1715 + if (hweight32(adev->aid_mask) == 1) 1716 + reserve_size = max(reserve_size, (uint32_t)128 << 20); 1717 + else 1718 + reserve_size = max(reserve_size, (uint32_t)144 << 20); 1719 + } else if (!reserve_size) 1720 + reserve_size = DISCOVERY_TMR_OFFSET; 1721 + 1722 + amdgpu_ttm_init_vram_resv(adev, AMDGPU_RESV_FW, 1723 + adev->gmc.real_vram_size - reserve_size, 1724 + reserve_size, false); 1705 1725 } 1706 1726 1707 - /** 1708 - * amdgpu_ttm_fw_reserve_vram_init - create bo vram reservation from fw 1709 - * 1710 - * @adev: amdgpu_device pointer 1711 - * 1712 - * create bo vram reservation from fw. 1713 - */ 1714 - static int amdgpu_ttm_fw_reserve_vram_init(struct amdgpu_device *adev) 1727 + static void amdgpu_ttm_init_mem_train_resv_region(struct amdgpu_device *adev) 1728 + { 1729 + uint64_t reserve_size; 1730 + uint64_t offset; 1731 + 1732 + if (!adev->discovery.reserve_tmr) 1733 + return; 1734 + 1735 + if (!adev->bios || amdgpu_sriov_vf(adev)) 1736 + return; 1737 + 1738 + if (!amdgpu_atomfirmware_mem_training_supported(adev)) 1739 + return; 1740 + 1741 + reserve_size = adev->mman.resv_region[AMDGPU_RESV_FW].size; 1742 + offset = ALIGN((adev->gmc.mc_vram_size - reserve_size - SZ_1M), SZ_1M); 1743 + amdgpu_ttm_init_vram_resv(adev, AMDGPU_RESV_MEM_TRAIN, 1744 + offset, 1745 + GDDR6_MEM_TRAINING_DATA_SIZE_IN_BYTES, 1746 + false); 1747 + } 1748 + 1749 + static void amdgpu_ttm_init_vram_resv_regions(struct amdgpu_device *adev) 1715 1750 { 1716 1751 uint64_t vram_size = adev->gmc.visible_vram_size; 1717 1752 1718 - adev->mman.fw_vram_usage_va = NULL; 1719 - adev->mman.fw_vram_usage_reserved_bo = NULL; 1753 + /* Initialize memory reservations as required for VGA. 1754 + * This is used for VGA emulation and pre-OS scanout buffers to 1755 + * avoid display artifacts while transitioning between pre-OS 1756 + * and driver. 1757 + */ 1758 + amdgpu_gmc_init_vga_resv_regions(adev); 1759 + amdgpu_ttm_init_fw_resv_region(adev); 1760 + amdgpu_ttm_init_mem_train_resv_region(adev); 1720 1761 1721 - if (adev->mman.fw_vram_usage_size == 0 || 1722 - adev->mman.fw_vram_usage_size > vram_size) 1723 - return 0; 1762 + if (adev->mman.resv_region[AMDGPU_RESV_FW_VRAM_USAGE].size > vram_size) 1763 + adev->mman.resv_region[AMDGPU_RESV_FW_VRAM_USAGE].size = 0; 1724 1764 1725 - return amdgpu_bo_create_kernel_at(adev, 1726 - adev->mman.fw_vram_usage_start_offset, 1727 - adev->mman.fw_vram_usage_size, 1728 - &adev->mman.fw_vram_usage_reserved_bo, 1729 - &adev->mman.fw_vram_usage_va); 1765 + if (adev->mman.resv_region[AMDGPU_RESV_DRV_VRAM_USAGE].size > vram_size) 1766 + adev->mman.resv_region[AMDGPU_RESV_DRV_VRAM_USAGE].size = 0; 1730 1767 } 1731 1768 1732 - /** 1733 - * amdgpu_ttm_drv_reserve_vram_init - create bo vram reservation from driver 1734 - * 1735 - * @adev: amdgpu_device pointer 1736 - * 1737 - * create bo vram reservation from drv. 1738 - */ 1739 - static int amdgpu_ttm_drv_reserve_vram_init(struct amdgpu_device *adev) 1769 + int amdgpu_ttm_mark_vram_reserved(struct amdgpu_device *adev, 1770 + enum amdgpu_resv_region_id id) 1740 1771 { 1741 - u64 vram_size = adev->gmc.visible_vram_size; 1772 + struct amdgpu_vram_resv *resv; 1773 + int ret; 1742 1774 1743 - adev->mman.drv_vram_usage_va = NULL; 1744 - adev->mman.drv_vram_usage_reserved_bo = NULL; 1775 + if (id >= AMDGPU_RESV_MAX) 1776 + return -EINVAL; 1745 1777 1746 - if (adev->mman.drv_vram_usage_size == 0 || 1747 - adev->mman.drv_vram_usage_size > vram_size) 1778 + resv = &adev->mman.resv_region[id]; 1779 + if (!resv->size) 1748 1780 return 0; 1749 1781 1750 - return amdgpu_bo_create_kernel_at(adev, 1751 - adev->mman.drv_vram_usage_start_offset, 1752 - adev->mman.drv_vram_usage_size, 1753 - &adev->mman.drv_vram_usage_reserved_bo, 1754 - &adev->mman.drv_vram_usage_va); 1782 + ret = amdgpu_bo_create_kernel_at(adev, resv->offset, resv->size, 1783 + &resv->bo, 1784 + resv->needs_cpu_map ? &resv->cpu_ptr : NULL); 1785 + if (ret) { 1786 + dev_err(adev->dev, 1787 + "reserve vram failed: id=%d offset=0x%llx size=0x%llx ret=%d\n", 1788 + id, resv->offset, resv->size, ret); 1789 + memset(resv, 0, sizeof(*resv)); 1790 + } 1791 + 1792 + return ret; 1793 + } 1794 + 1795 + void amdgpu_ttm_unmark_vram_reserved(struct amdgpu_device *adev, 1796 + enum amdgpu_resv_region_id id) 1797 + { 1798 + struct amdgpu_vram_resv *resv; 1799 + 1800 + if (id >= AMDGPU_RESV_MAX) 1801 + return; 1802 + 1803 + resv = &adev->mman.resv_region[id]; 1804 + if (!resv->bo) 1805 + return; 1806 + 1807 + amdgpu_bo_free_kernel(&resv->bo, NULL, 1808 + resv->needs_cpu_map ? &resv->cpu_ptr : NULL); 1809 + memset(resv, 0, sizeof(*resv)); 1810 + } 1811 + 1812 + /* 1813 + * Reserve all regions with non-zero size. Regions whose info is not 1814 + * yet available (e.g., fw extended region) may still be reserved 1815 + * during runtime. 1816 + */ 1817 + static int amdgpu_ttm_alloc_vram_resv_regions(struct amdgpu_device *adev) 1818 + { 1819 + int i, r; 1820 + 1821 + for (i = 0; i < AMDGPU_RESV_MAX; i++) { 1822 + r = amdgpu_ttm_mark_vram_reserved(adev, i); 1823 + if (r) 1824 + return r; 1825 + } 1826 + 1827 + return 0; 1755 1828 } 1756 1829 1757 1830 /* ··· 1843 1770 struct psp_memory_training_context *ctx = &adev->psp.mem_train_ctx; 1844 1771 1845 1772 ctx->init = PSP_MEM_TRAIN_NOT_SUPPORT; 1846 - amdgpu_bo_free_kernel(&ctx->c2p_bo, NULL, NULL); 1847 - ctx->c2p_bo = NULL; 1773 + amdgpu_ttm_unmark_vram_reserved(adev, AMDGPU_RESV_MEM_TRAIN); 1848 1774 1849 1775 return 0; 1850 1776 } 1851 1777 1852 - static void amdgpu_ttm_training_data_block_init(struct amdgpu_device *adev, 1853 - uint32_t reserve_size) 1778 + static void amdgpu_ttm_training_data_block_init(struct amdgpu_device *adev) 1854 1779 { 1855 1780 struct psp_memory_training_context *ctx = &adev->psp.mem_train_ctx; 1781 + struct amdgpu_vram_resv *resv = 1782 + &adev->mman.resv_region[AMDGPU_RESV_MEM_TRAIN]; 1856 1783 1857 1784 memset(ctx, 0, sizeof(*ctx)); 1858 1785 1859 - ctx->c2p_train_data_offset = 1860 - ALIGN((adev->gmc.mc_vram_size - reserve_size - SZ_1M), SZ_1M); 1786 + ctx->c2p_train_data_offset = resv->offset; 1861 1787 ctx->p2c_train_data_offset = 1862 1788 (adev->gmc.mc_vram_size - GDDR6_MEM_TRAINING_OFFSET); 1863 - ctx->train_data_size = 1864 - GDDR6_MEM_TRAINING_DATA_SIZE_IN_BYTES; 1789 + ctx->train_data_size = resv->size; 1865 1790 1866 1791 DRM_DEBUG("train_data_size:%llx,p2c_train_data_offset:%llx,c2p_train_data_offset:%llx.\n", 1867 1792 ctx->train_data_size, 1868 1793 ctx->p2c_train_data_offset, 1869 1794 ctx->c2p_train_data_offset); 1870 - } 1871 - 1872 - /* 1873 - * reserve TMR memory at the top of VRAM which holds 1874 - * IP Discovery data and is protected by PSP. 1875 - */ 1876 - static int amdgpu_ttm_reserve_tmr(struct amdgpu_device *adev) 1877 - { 1878 - struct psp_memory_training_context *ctx = &adev->psp.mem_train_ctx; 1879 - bool mem_train_support = false; 1880 - uint32_t reserve_size = 0; 1881 - int ret; 1882 - 1883 - if (adev->bios && !amdgpu_sriov_vf(adev)) { 1884 - if (amdgpu_atomfirmware_mem_training_supported(adev)) 1885 - mem_train_support = true; 1886 - else 1887 - DRM_DEBUG("memory training does not support!\n"); 1888 - } 1889 - 1890 - /* 1891 - * Query reserved tmr size through atom firmwareinfo for Sienna_Cichlid and onwards for all 1892 - * the use cases (IP discovery/G6 memory training/profiling/diagnostic data.etc) 1893 - * 1894 - * Otherwise, fallback to legacy approach to check and reserve tmr block for ip 1895 - * discovery data and G6 memory training data respectively 1896 - */ 1897 - if (adev->bios) 1898 - reserve_size = 1899 - amdgpu_atomfirmware_get_fw_reserved_fb_size(adev); 1900 - 1901 - if (!adev->bios && 1902 - (amdgpu_ip_version(adev, GC_HWIP, 0) == IP_VERSION(9, 4, 3) || 1903 - amdgpu_ip_version(adev, GC_HWIP, 0) == IP_VERSION(9, 4, 4) || 1904 - amdgpu_ip_version(adev, GC_HWIP, 0) == IP_VERSION(9, 5, 0))) 1905 - reserve_size = max(reserve_size, (uint32_t)280 << 20); 1906 - else if (!adev->bios && 1907 - amdgpu_ip_version(adev, GC_HWIP, 0) == IP_VERSION(12, 1, 0)) { 1908 - if (hweight32(adev->aid_mask) == 1) 1909 - reserve_size = max(reserve_size, (uint32_t)128 << 20); 1910 - else 1911 - reserve_size = max(reserve_size, (uint32_t)144 << 20); 1912 - } else if (!reserve_size) 1913 - reserve_size = DISCOVERY_TMR_OFFSET; 1914 - 1915 - if (mem_train_support) { 1916 - /* reserve vram for mem train according to TMR location */ 1917 - amdgpu_ttm_training_data_block_init(adev, reserve_size); 1918 - ret = amdgpu_bo_create_kernel_at(adev, 1919 - ctx->c2p_train_data_offset, 1920 - ctx->train_data_size, 1921 - &ctx->c2p_bo, 1922 - NULL); 1923 - if (ret) { 1924 - dev_err(adev->dev, "alloc c2p_bo failed(%d)!\n", ret); 1925 - amdgpu_ttm_training_reserve_vram_fini(adev); 1926 - return ret; 1927 - } 1928 - ctx->init = PSP_MEM_TRAIN_RESERVE_SUCCESS; 1929 - } 1930 - 1931 - ret = amdgpu_bo_create_kernel_at( 1932 - adev, adev->gmc.real_vram_size - reserve_size, reserve_size, 1933 - &adev->mman.fw_reserved_memory, NULL); 1934 - if (ret) { 1935 - dev_err(adev->dev, "alloc tmr failed(%d)!\n", ret); 1936 - amdgpu_bo_free_kernel(&adev->mman.fw_reserved_memory, NULL, 1937 - NULL); 1938 - return ret; 1939 - } 1940 - 1941 - return 0; 1942 1795 } 1943 1796 1944 1797 static int amdgpu_ttm_pools_init(struct amdgpu_device *adev) ··· 2114 2115 adev->gmc.visible_vram_size); 2115 2116 #endif 2116 2117 2117 - /* 2118 - *The reserved vram for firmware must be pinned to the specified 2119 - *place on the VRAM, so reserve it early. 2120 - */ 2121 - r = amdgpu_ttm_fw_reserve_vram_init(adev); 2118 + amdgpu_ttm_init_vram_resv_regions(adev); 2119 + 2120 + r = amdgpu_ttm_alloc_vram_resv_regions(adev); 2122 2121 if (r) 2123 2122 return r; 2124 2123 2125 - /* 2126 - * The reserved VRAM for the driver must be pinned to a specific 2127 - * location in VRAM, so reserve it early. 2128 - */ 2129 - r = amdgpu_ttm_drv_reserve_vram_init(adev); 2130 - if (r) 2131 - return r; 2124 + if (adev->mman.resv_region[AMDGPU_RESV_MEM_TRAIN].size) { 2125 + struct psp_memory_training_context *ctx = 2126 + &adev->psp.mem_train_ctx; 2132 2127 2133 - /* 2134 - * only NAVI10 and later ASICs support IP discovery. 2135 - * If IP discovery is enabled, a block of memory should be 2136 - * reserved for it. 2137 - */ 2138 - if (adev->discovery.reserve_tmr) { 2139 - r = amdgpu_ttm_reserve_tmr(adev); 2140 - if (r) 2141 - return r; 2142 - } 2143 - 2144 - /* allocate memory as required for VGA 2145 - * This is used for VGA emulation and pre-OS scanout buffers to 2146 - * avoid display artifacts while transitioning between pre-OS 2147 - * and driver. 2148 - */ 2149 - if (!adev->gmc.is_app_apu) { 2150 - r = amdgpu_bo_create_kernel_at(adev, 0, 2151 - adev->mman.stolen_vga_size, 2152 - &adev->mman.stolen_vga_memory, 2153 - NULL); 2154 - if (r) 2155 - return r; 2156 - 2157 - r = amdgpu_bo_create_kernel_at(adev, adev->mman.stolen_vga_size, 2158 - adev->mman.stolen_extended_size, 2159 - &adev->mman.stolen_extended_memory, 2160 - NULL); 2161 - 2162 - if (r) 2163 - return r; 2164 - 2165 - r = amdgpu_bo_create_kernel_at(adev, 2166 - adev->mman.stolen_reserved_offset, 2167 - adev->mman.stolen_reserved_size, 2168 - &adev->mman.stolen_reserved_memory, 2169 - NULL); 2170 - if (r) 2171 - return r; 2172 - } else { 2173 - DRM_DEBUG_DRIVER("Skipped stolen memory reservation\n"); 2128 + amdgpu_ttm_training_data_block_init(adev); 2129 + ctx->init = PSP_MEM_TRAIN_RESERVE_SUCCESS; 2174 2130 } 2175 2131 2176 2132 dev_info(adev->dev, " %uM of VRAM memory ready\n", ··· 2238 2284 amdgpu_ttm_training_reserve_vram_fini(adev); 2239 2285 /* return the stolen vga memory back to VRAM */ 2240 2286 if (!adev->gmc.is_app_apu) { 2241 - amdgpu_bo_free_kernel(&adev->mman.stolen_vga_memory, NULL, NULL); 2242 - amdgpu_bo_free_kernel(&adev->mman.stolen_extended_memory, NULL, NULL); 2287 + amdgpu_ttm_unmark_vram_reserved(adev, AMDGPU_RESV_STOLEN_VGA); 2288 + amdgpu_ttm_unmark_vram_reserved(adev, AMDGPU_RESV_STOLEN_EXTENDED); 2243 2289 /* return the FW reserved memory back to VRAM */ 2244 - amdgpu_bo_free_kernel(&adev->mman.fw_reserved_memory, NULL, 2245 - NULL); 2246 - amdgpu_bo_free_kernel(&adev->mman.fw_reserved_memory_extend, NULL, 2247 - NULL); 2248 - if (adev->mman.stolen_reserved_size) 2249 - amdgpu_bo_free_kernel(&adev->mman.stolen_reserved_memory, 2250 - NULL, NULL); 2290 + amdgpu_ttm_unmark_vram_reserved(adev, AMDGPU_RESV_FW); 2291 + amdgpu_ttm_unmark_vram_reserved(adev, AMDGPU_RESV_FW_EXTEND); 2292 + amdgpu_ttm_unmark_vram_reserved(adev, AMDGPU_RESV_STOLEN_RESERVED); 2251 2293 } 2252 2294 amdgpu_bo_free_kernel(&adev->mman.sdma_access_bo, NULL, 2253 2295 &adev->mman.sdma_access_ptr); 2254 2296 2255 2297 amdgpu_ttm_free_mmio_remap_bo(adev); 2256 - amdgpu_ttm_fw_reserve_vram_fini(adev); 2257 - amdgpu_ttm_drv_reserve_vram_fini(adev); 2298 + amdgpu_ttm_unmark_vram_reserved(adev, AMDGPU_RESV_FW_VRAM_USAGE); 2299 + amdgpu_ttm_unmark_vram_reserved(adev, AMDGPU_RESV_DRV_VRAM_USAGE); 2258 2300 2259 2301 if (drm_dev_enter(adev_to_drm(adev), &idx)) { 2260 2302

+30 -23

drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.h

··· 59 59 u64 gart_window_offs[2]; 60 60 }; 61 61 62 + enum amdgpu_resv_region_id { 63 + AMDGPU_RESV_STOLEN_VGA, 64 + AMDGPU_RESV_STOLEN_EXTENDED, 65 + AMDGPU_RESV_STOLEN_RESERVED, 66 + AMDGPU_RESV_FW, 67 + AMDGPU_RESV_FW_EXTEND, 68 + AMDGPU_RESV_FW_VRAM_USAGE, 69 + AMDGPU_RESV_DRV_VRAM_USAGE, 70 + AMDGPU_RESV_MEM_TRAIN, 71 + AMDGPU_RESV_MAX 72 + }; 73 + 74 + struct amdgpu_vram_resv { 75 + uint64_t offset; 76 + uint64_t size; 77 + struct amdgpu_bo *bo; 78 + void *cpu_ptr; 79 + bool needs_cpu_map; 80 + }; 81 + 62 82 struct amdgpu_mman { 63 83 struct ttm_device bdev; 64 84 struct ttm_pool *ttm_pools; ··· 103 83 struct amdgpu_gtt_mgr gtt_mgr; 104 84 struct ttm_resource_manager preempt_mgr; 105 85 106 - uint64_t stolen_vga_size; 107 - struct amdgpu_bo *stolen_vga_memory; 108 - uint64_t stolen_extended_size; 109 - struct amdgpu_bo *stolen_extended_memory; 110 86 bool keep_stolen_vga_memory; 111 87 112 - struct amdgpu_bo *stolen_reserved_memory; 113 - uint64_t stolen_reserved_offset; 114 - uint64_t stolen_reserved_size; 115 - 116 - /* fw reserved memory */ 117 - struct amdgpu_bo *fw_reserved_memory; 118 - struct amdgpu_bo *fw_reserved_memory_extend; 119 - 120 - /* firmware VRAM reservation */ 121 - u64 fw_vram_usage_start_offset; 122 - u64 fw_vram_usage_size; 123 - struct amdgpu_bo *fw_vram_usage_reserved_bo; 124 - void *fw_vram_usage_va; 125 - 126 - /* driver VRAM reservation */ 127 - u64 drv_vram_usage_start_offset; 128 - u64 drv_vram_usage_size; 129 - struct amdgpu_bo *drv_vram_usage_reserved_bo; 130 - void *drv_vram_usage_va; 88 + struct amdgpu_vram_resv resv_region[AMDGPU_RESV_MAX]; 131 89 132 90 /* PAGE_SIZE'd BO for process memory r/w over SDMA. */ 133 91 struct amdgpu_bo *sdma_access_bo; ··· 172 174 173 175 bool amdgpu_res_cpu_visible(struct amdgpu_device *adev, 174 176 struct ttm_resource *res); 177 + 178 + void amdgpu_ttm_init_vram_resv(struct amdgpu_device *adev, 179 + enum amdgpu_resv_region_id id, 180 + uint64_t offset, uint64_t size, 181 + bool needs_cpu_map); 182 + int amdgpu_ttm_mark_vram_reserved(struct amdgpu_device *adev, 183 + enum amdgpu_resv_region_id id); 184 + void amdgpu_ttm_unmark_vram_reserved(struct amdgpu_device *adev, 185 + enum amdgpu_resv_region_id id); 175 186 176 187 int amdgpu_ttm_init(struct amdgpu_device *adev); 177 188 void amdgpu_ttm_fini(struct amdgpu_device *adev);

+24 -57

drivers/gpu/drm/amd/amdgpu/amdgpu_userq.c

··· 427 427 return r; 428 428 } 429 429 430 - static int amdgpu_userq_wait_for_last_fence(struct amdgpu_usermode_queue *queue) 430 + static void amdgpu_userq_wait_for_last_fence(struct amdgpu_usermode_queue *queue) 431 431 { 432 - struct amdgpu_userq_mgr *uq_mgr = queue->userq_mgr; 433 432 struct dma_fence *f = queue->last_fence; 434 - int ret = 0; 435 433 436 - if (f && !dma_fence_is_signaled(f)) { 437 - ret = dma_fence_wait_timeout(f, true, MAX_SCHEDULE_TIMEOUT); 438 - if (ret <= 0) { 439 - drm_file_err(uq_mgr->file, "Timed out waiting for fence=%llu:%llu\n", 440 - f->context, f->seqno); 441 - queue->state = AMDGPU_USERQ_STATE_HUNG; 442 - return -ETIME; 443 - } 444 - } 434 + if (!f) 435 + return; 445 436 446 - return ret; 437 + dma_fence_wait(f, false); 447 438 } 448 439 449 440 static void amdgpu_userq_cleanup(struct amdgpu_usermode_queue *queue) ··· 449 458 /* Drop the userq reference. */ 450 459 amdgpu_userq_buffer_vas_list_cleanup(adev, queue); 451 460 uq_funcs->mqd_destroy(queue); 452 - amdgpu_userq_fence_driver_free(queue); 453 461 /* Use interrupt-safe locking since IRQ handlers may access these XArrays */ 454 462 xa_erase_irq(&adev->userq_doorbell_xa, queue->doorbell_index); 463 + amdgpu_userq_fence_driver_free(queue); 464 + queue->fence_drv = NULL; 455 465 queue->userq_mgr = NULL; 456 466 list_del(&queue->userq_va_list); 457 467 kfree(queue); ··· 791 799 792 800 queue->doorbell_index = index; 793 801 xa_init_flags(&queue->fence_drv_xa, XA_FLAGS_ALLOC); 794 - r = amdgpu_userq_fence_driver_alloc(adev, queue); 802 + r = amdgpu_userq_fence_driver_alloc(adev, &queue->fence_drv); 795 803 if (r) { 796 804 drm_file_err(uq_mgr->file, "Failed to alloc fence driver\n"); 797 805 goto free_queue; ··· 1015 1023 mutex_unlock(&uq_mgr->userq_mutex); 1016 1024 1017 1025 if (ret) 1018 - drm_file_err(uq_mgr->file, "Failed to map all the queues\n"); 1026 + drm_file_err(uq_mgr->file, 1027 + "Failed to map all the queues, restore failed ret=%d\n", ret); 1019 1028 return ret; 1020 1029 } 1021 1030 ··· 1223 1230 1224 1231 ret = amdgpu_userq_vm_validate(uq_mgr); 1225 1232 if (ret) { 1226 - drm_file_err(uq_mgr->file, "Failed to validate BOs to restore\n"); 1233 + drm_file_err(uq_mgr->file, "Failed to validate BOs to restore ret=%d\n", ret); 1227 1234 goto put_fence; 1228 1235 } 1229 1236 1230 - ret = amdgpu_userq_restore_all(uq_mgr); 1231 - if (ret) 1232 - drm_file_err(uq_mgr->file, "Failed to restore all queues\n"); 1237 + amdgpu_userq_restore_all(uq_mgr); 1233 1238 1234 1239 put_fence: 1235 1240 dma_fence_put(ev_fence); ··· 1249 1258 } 1250 1259 1251 1260 if (ret) 1252 - drm_file_err(uq_mgr->file, "Couldn't unmap all the queues\n"); 1261 + drm_file_err(uq_mgr->file, 1262 + "Couldn't unmap all the queues, eviction failed ret=%d\n", ret); 1253 1263 return ret; 1254 1264 } 1255 1265 ··· 1271 1279 amdgpu_device_gpu_recover(adev, NULL, &reset_context); 1272 1280 } 1273 1281 1274 - static int 1282 + static void 1275 1283 amdgpu_userq_wait_for_signal(struct amdgpu_userq_mgr *uq_mgr) 1276 1284 { 1277 1285 struct amdgpu_usermode_queue *queue; 1278 1286 unsigned long queue_id; 1279 - int ret; 1280 1287 1281 1288 xa_for_each(&uq_mgr->userq_xa, queue_id, queue) { 1282 1289 struct dma_fence *f = queue->last_fence; 1283 1290 1284 - if (!f || dma_fence_is_signaled(f)) 1291 + if (!f) 1285 1292 continue; 1286 1293 1287 - ret = dma_fence_wait_timeout(f, true, msecs_to_jiffies(100)); 1288 - if (ret <= 0) { 1289 - drm_file_err(uq_mgr->file, "Timed out waiting for fence=%llu:%llu\n", 1290 - f->context, f->seqno); 1291 - 1292 - return -ETIMEDOUT; 1293 - } 1294 + dma_fence_wait(f, false); 1294 1295 } 1295 - 1296 - return 0; 1297 1296 } 1298 1297 1299 1298 void 1300 1299 amdgpu_userq_evict(struct amdgpu_userq_mgr *uq_mgr) 1301 1300 { 1302 - struct amdgpu_device *adev = uq_mgr->adev; 1303 - int ret; 1304 - 1305 1301 /* Wait for any pending userqueue fence work to finish */ 1306 - ret = amdgpu_userq_wait_for_signal(uq_mgr); 1307 - if (ret) 1308 - dev_err(adev->dev, "Not evicting userqueue, timeout waiting for work\n"); 1309 - 1310 - ret = amdgpu_userq_evict_all(uq_mgr); 1311 - if (ret) 1312 - dev_err(adev->dev, "Failed to evict userqueue\n"); 1313 - 1302 + amdgpu_userq_wait_for_signal(uq_mgr); 1303 + amdgpu_userq_evict_all(uq_mgr); 1314 1304 } 1315 1305 1316 1306 int amdgpu_userq_mgr_init(struct amdgpu_userq_mgr *userq_mgr, struct drm_file *file_priv, ··· 1454 1480 return ret; 1455 1481 } 1456 1482 1457 - int amdgpu_userq_gem_va_unmap_validate(struct amdgpu_device *adev, 1458 - struct amdgpu_bo_va_mapping *mapping, 1459 - uint64_t saddr) 1483 + void amdgpu_userq_gem_va_unmap_validate(struct amdgpu_device *adev, 1484 + struct amdgpu_bo_va_mapping *mapping, 1485 + uint64_t saddr) 1460 1486 { 1461 1487 u32 ip_mask = amdgpu_userq_get_supported_ip_mask(adev); 1462 1488 struct amdgpu_bo_va *bo_va = mapping->bo_va; 1463 1489 struct dma_resv *resv = bo_va->base.bo->tbo.base.resv; 1464 - int ret = 0; 1465 1490 1466 1491 if (!ip_mask) 1467 - return 0; 1492 + return; 1468 1493 1469 1494 dev_warn_once(adev->dev, "now unmapping a vital queue va:%llx\n", saddr); 1470 1495 /** ··· 1474 1501 * unmap is only for one kind of userq VAs, so at this point suppose 1475 1502 * the eviction fence is always unsignaled. 1476 1503 */ 1477 - if (!dma_resv_test_signaled(resv, DMA_RESV_USAGE_BOOKKEEP)) { 1478 - ret = dma_resv_wait_timeout(resv, DMA_RESV_USAGE_BOOKKEEP, true, 1479 - MAX_SCHEDULE_TIMEOUT); 1480 - if (ret <= 0) 1481 - return -EBUSY; 1482 - } 1483 - 1484 - return 0; 1504 + dma_resv_wait_timeout(resv, DMA_RESV_USAGE_BOOKKEEP, 1505 + false, MAX_SCHEDULE_TIMEOUT); 1485 1506 } 1486 1507 1487 1508 void amdgpu_userq_pre_reset(struct amdgpu_device *adev)

+3 -3

drivers/gpu/drm/amd/amdgpu/amdgpu_userq.h

··· 160 160 int amdgpu_userq_input_va_validate(struct amdgpu_device *adev, 161 161 struct amdgpu_usermode_queue *queue, 162 162 u64 addr, u64 expected_size); 163 - int amdgpu_userq_gem_va_unmap_validate(struct amdgpu_device *adev, 164 - struct amdgpu_bo_va_mapping *mapping, 165 - uint64_t saddr); 163 + void amdgpu_userq_gem_va_unmap_validate(struct amdgpu_device *adev, 164 + struct amdgpu_bo_va_mapping *mapping, 165 + uint64_t saddr); 166 166 #endif

+9 -23

drivers/gpu/drm/amd/amdgpu/amdgpu_userq_fence.c

··· 78 78 } 79 79 80 80 int amdgpu_userq_fence_driver_alloc(struct amdgpu_device *adev, 81 - struct amdgpu_usermode_queue *userq) 81 + struct amdgpu_userq_fence_driver **fence_drv_req) 82 82 { 83 83 struct amdgpu_userq_fence_driver *fence_drv; 84 - unsigned long flags; 85 84 int r; 85 + 86 + if (!fence_drv_req) 87 + return -EINVAL; 88 + *fence_drv_req = NULL; 86 89 87 90 fence_drv = kzalloc_obj(*fence_drv); 88 91 if (!fence_drv) ··· 107 104 fence_drv->context = dma_fence_context_alloc(1); 108 105 get_task_comm(fence_drv->timeline_name, current); 109 106 110 - xa_lock_irqsave(&adev->userq_xa, flags); 111 - r = xa_err(__xa_store(&adev->userq_xa, userq->doorbell_index, 112 - fence_drv, GFP_KERNEL)); 113 - xa_unlock_irqrestore(&adev->userq_xa, flags); 114 - if (r) 115 - goto free_seq64; 116 - 117 - userq->fence_drv = fence_drv; 107 + *fence_drv_req = fence_drv; 118 108 119 109 return 0; 120 110 121 - free_seq64: 122 - amdgpu_seq64_free(adev, fence_drv->va); 123 111 free_fence_drv: 124 112 kfree(fence_drv); 125 113 ··· 138 144 amdgpu_userq_fence_driver_free(struct amdgpu_usermode_queue *userq) 139 145 { 140 146 dma_fence_put(userq->last_fence); 141 - 147 + userq->last_fence = NULL; 142 148 amdgpu_userq_walk_and_drop_fence_drv(&userq->fence_drv_xa); 143 149 xa_destroy(&userq->fence_drv_xa); 144 - /* Drop the fence_drv reference held by user queue */ 150 + /* Drop the queue's ownership reference to fence_drv explicitly */ 145 151 amdgpu_userq_fence_driver_put(userq->fence_drv); 146 152 } 147 153 ··· 181 187 struct amdgpu_userq_fence_driver *fence_drv = container_of(ref, 182 188 struct amdgpu_userq_fence_driver, 183 189 refcount); 184 - struct amdgpu_userq_fence_driver *xa_fence_drv; 185 190 struct amdgpu_device *adev = fence_drv->adev; 186 191 struct amdgpu_userq_fence *fence, *tmp; 187 - struct xarray *xa = &adev->userq_xa; 188 - unsigned long index, flags; 192 + unsigned long flags; 189 193 struct dma_fence *f; 190 194 191 195 spin_lock_irqsave(&fence_drv->fence_list_lock, flags); ··· 199 207 dma_fence_put(f); 200 208 } 201 209 spin_unlock_irqrestore(&fence_drv->fence_list_lock, flags); 202 - 203 - xa_lock_irqsave(xa, flags); 204 - xa_for_each(xa, index, xa_fence_drv) 205 - if (xa_fence_drv == fence_drv) 206 - __xa_erase(xa, index); 207 - xa_unlock_irqrestore(xa, flags); 208 210 209 211 /* Free seq64 memory */ 210 212 amdgpu_seq64_free(adev, fence_drv->va);

+1 -1

drivers/gpu/drm/amd/amdgpu/amdgpu_userq_fence.h

··· 64 64 void amdgpu_userq_fence_driver_get(struct amdgpu_userq_fence_driver *fence_drv); 65 65 void amdgpu_userq_fence_driver_put(struct amdgpu_userq_fence_driver *fence_drv); 66 66 int amdgpu_userq_fence_driver_alloc(struct amdgpu_device *adev, 67 - struct amdgpu_usermode_queue *userq); 67 + struct amdgpu_userq_fence_driver **fence_drv_req); 68 68 void amdgpu_userq_fence_driver_free(struct amdgpu_usermode_queue *userq); 69 69 void amdgpu_userq_fence_driver_process(struct amdgpu_userq_fence_driver *fence_drv); 70 70 void amdgpu_userq_fence_driver_force_completion(struct amdgpu_usermode_queue *userq);

+3

drivers/gpu/drm/amd/amdgpu/amdgpu_vce.c

··· 680 680 uint64_t addr; 681 681 int r; 682 682 683 + if (lo >= ib->length_dw || hi >= ib->length_dw) 684 + return -EINVAL; 685 + 683 686 if (index == 0xffffffff) 684 687 index = 0; 685 688

+26 -24

drivers/gpu/drm/amd/amdgpu/amdgpu_virt.c

··· 437 437 struct eeprom_table_record bp; 438 438 uint64_t retired_page; 439 439 uint32_t bp_idx, bp_cnt; 440 - void *vram_usage_va = NULL; 441 - 442 - if (adev->mman.fw_vram_usage_va) 443 - vram_usage_va = adev->mman.fw_vram_usage_va; 444 - else 445 - vram_usage_va = adev->mman.drv_vram_usage_va; 440 + void *fw_va = adev->mman.resv_region[AMDGPU_RESV_FW_VRAM_USAGE].cpu_ptr; 441 + void *drv_va = adev->mman.resv_region[AMDGPU_RESV_DRV_VRAM_USAGE].cpu_ptr; 442 + void *vram_usage_va = fw_va ? fw_va : drv_va; 446 443 447 444 memset(&bp, 0, sizeof(bp)); 448 445 ··· 707 710 void amdgpu_virt_init_data_exchange(struct amdgpu_device *adev) 708 711 { 709 712 uint32_t *pfvf_data = NULL; 713 + void *fw_va = adev->mman.resv_region[AMDGPU_RESV_FW_VRAM_USAGE].cpu_ptr; 714 + void *drv_va = adev->mman.resv_region[AMDGPU_RESV_DRV_VRAM_USAGE].cpu_ptr; 710 715 711 716 adev->virt.fw_reserve.p_pf2vf = NULL; 712 717 adev->virt.fw_reserve.p_vf2pf = NULL; 713 718 adev->virt.vf2pf_update_interval_ms = 0; 714 719 adev->virt.vf2pf_update_retry_cnt = 0; 715 720 716 - if (adev->mman.fw_vram_usage_va && adev->mman.drv_vram_usage_va) { 721 + if (fw_va && drv_va) { 717 722 dev_warn(adev->dev, "Currently fw_vram and drv_vram should not have values at the same time!"); 718 - } else if (adev->mman.fw_vram_usage_va || adev->mman.drv_vram_usage_va) { 723 + } else if (fw_va || drv_va) { 719 724 /* go through this logic in ip_init and reset to init workqueue*/ 720 725 amdgpu_virt_exchange_data(adev); 721 726 ··· 762 763 uint64_t bp_block_offset = 0; 763 764 uint32_t bp_block_size = 0; 764 765 struct amd_sriov_msg_pf2vf_info *pf2vf_v2 = NULL; 766 + void *fw_va = adev->mman.resv_region[AMDGPU_RESV_FW_VRAM_USAGE].cpu_ptr; 767 + void *drv_va = adev->mman.resv_region[AMDGPU_RESV_DRV_VRAM_USAGE].cpu_ptr; 765 768 766 - if (adev->mman.fw_vram_usage_va || adev->mman.drv_vram_usage_va) { 767 - if (adev->mman.fw_vram_usage_va) { 769 + if (fw_va || drv_va) { 770 + if (fw_va) { 768 771 if (adev->virt.req_init_data_ver == GPU_CRIT_REGION_V2) { 769 772 adev->virt.fw_reserve.p_pf2vf = 770 773 (struct amd_sriov_msg_pf2vf_info_header *) 771 - (adev->mman.fw_vram_usage_va + 774 + (fw_va + 772 775 adev->virt.crit_regn_tbl[AMD_SRIOV_MSG_DATAEXCHANGE_TABLE_ID].offset); 773 776 adev->virt.fw_reserve.p_vf2pf = 774 777 (struct amd_sriov_msg_vf2pf_info_header *) 775 - (adev->mman.fw_vram_usage_va + 778 + (fw_va + 776 779 adev->virt.crit_regn_tbl[AMD_SRIOV_MSG_DATAEXCHANGE_TABLE_ID].offset + 777 780 (AMD_SRIOV_MSG_SIZE_KB << 10)); 778 781 adev->virt.fw_reserve.ras_telemetry = 779 - (adev->mman.fw_vram_usage_va + 782 + (fw_va + 780 783 adev->virt.crit_regn_tbl[AMD_SRIOV_MSG_RAS_TELEMETRY_TABLE_ID].offset); 781 784 } else { 782 785 adev->virt.fw_reserve.p_pf2vf = 783 786 (struct amd_sriov_msg_pf2vf_info_header *) 784 - (adev->mman.fw_vram_usage_va + (AMD_SRIOV_MSG_PF2VF_OFFSET_KB_V1 << 10)); 787 + (fw_va + (AMD_SRIOV_MSG_PF2VF_OFFSET_KB_V1 << 10)); 785 788 adev->virt.fw_reserve.p_vf2pf = 786 789 (struct amd_sriov_msg_vf2pf_info_header *) 787 - (adev->mman.fw_vram_usage_va + (AMD_SRIOV_MSG_VF2PF_OFFSET_KB_V1 << 10)); 790 + (fw_va + (AMD_SRIOV_MSG_VF2PF_OFFSET_KB_V1 << 10)); 788 791 adev->virt.fw_reserve.ras_telemetry = 789 - (adev->mman.fw_vram_usage_va + (AMD_SRIOV_MSG_RAS_TELEMETRY_OFFSET_KB_V1 << 10)); 792 + (fw_va + (AMD_SRIOV_MSG_RAS_TELEMETRY_OFFSET_KB_V1 << 10)); 790 793 } 791 - } else if (adev->mman.drv_vram_usage_va) { 794 + } else if (drv_va) { 792 795 adev->virt.fw_reserve.p_pf2vf = 793 796 (struct amd_sriov_msg_pf2vf_info_header *) 794 - (adev->mman.drv_vram_usage_va + (AMD_SRIOV_MSG_PF2VF_OFFSET_KB_V1 << 10)); 797 + (drv_va + (AMD_SRIOV_MSG_PF2VF_OFFSET_KB_V1 << 10)); 795 798 adev->virt.fw_reserve.p_vf2pf = 796 799 (struct amd_sriov_msg_vf2pf_info_header *) 797 - (adev->mman.drv_vram_usage_va + (AMD_SRIOV_MSG_VF2PF_OFFSET_KB_V1 << 10)); 800 + (drv_va + (AMD_SRIOV_MSG_VF2PF_OFFSET_KB_V1 << 10)); 798 801 adev->virt.fw_reserve.ras_telemetry = 799 - (adev->mman.drv_vram_usage_va + (AMD_SRIOV_MSG_RAS_TELEMETRY_OFFSET_KB_V1 << 10)); 802 + (drv_va + (AMD_SRIOV_MSG_RAS_TELEMETRY_OFFSET_KB_V1 << 10)); 800 803 } 801 804 802 805 amdgpu_virt_read_pf2vf_data(adev); ··· 1082 1081 } 1083 1082 1084 1083 /* reserved memory starts from crit region base offset with the size of 5MB */ 1085 - adev->mman.fw_vram_usage_start_offset = adev->virt.crit_regn.offset; 1086 - adev->mman.fw_vram_usage_size = adev->virt.crit_regn.size_kb << 10; 1084 + amdgpu_ttm_init_vram_resv(adev, AMDGPU_RESV_FW_VRAM_USAGE, 1085 + adev->virt.crit_regn.offset, 1086 + adev->virt.crit_regn.size_kb << 10, true); 1087 1087 dev_info(adev->dev, 1088 1088 "critical region v%d requested to reserve memory start at %08llx with %llu KB.\n", 1089 1089 init_data_hdr->version, 1090 - adev->mman.fw_vram_usage_start_offset, 1091 - adev->mman.fw_vram_usage_size >> 10); 1090 + adev->mman.resv_region[AMDGPU_RESV_FW_VRAM_USAGE].offset, 1091 + adev->mman.resv_region[AMDGPU_RESV_FW_VRAM_USAGE].size >> 10); 1092 1092 1093 1093 adev->virt.is_dynamic_crit_regn_enabled = true; 1094 1094

+53 -36

drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c

··· 1978 1978 struct amdgpu_bo_va_mapping *mapping; 1979 1979 struct amdgpu_vm *vm = bo_va->base.vm; 1980 1980 bool valid = true; 1981 - int r; 1982 1981 1983 1982 saddr /= AMDGPU_GPU_PAGE_SIZE; 1984 1983 ··· 2002 2003 * during user requests GEM unmap IOCTL except for forcing the unmap 2003 2004 * from user space. 2004 2005 */ 2005 - if (unlikely(atomic_read(&bo_va->userq_va_mapped) > 0)) { 2006 - r = amdgpu_userq_gem_va_unmap_validate(adev, mapping, saddr); 2007 - if (unlikely(r == -EBUSY)) 2008 - dev_warn_once(adev->dev, 2009 - "Attempt to unmap an active userq buffer\n"); 2010 - } 2006 + if (unlikely(atomic_read(&bo_va->userq_va_mapped) > 0)) 2007 + amdgpu_userq_gem_va_unmap_validate(adev, mapping, saddr); 2011 2008 2012 2009 list_del(&mapping->list); 2013 2010 amdgpu_vm_it_remove(mapping, &vm->va); ··· 2950 2955 } 2951 2956 2952 2957 /** 2958 + * amdgpu_vm_lock_by_pasid - return an amdgpu_vm and its root bo from a pasid, if possible. 2959 + * @adev: amdgpu device pointer 2960 + * @root: root BO of the VM 2961 + * @pasid: PASID of the VM 2962 + * The caller needs to unreserve and unref the root bo on success. 2963 + */ 2964 + struct amdgpu_vm *amdgpu_vm_lock_by_pasid(struct amdgpu_device *adev, 2965 + struct amdgpu_bo **root, u32 pasid) 2966 + { 2967 + unsigned long irqflags; 2968 + struct amdgpu_vm *vm; 2969 + int r; 2970 + 2971 + xa_lock_irqsave(&adev->vm_manager.pasids, irqflags); 2972 + vm = xa_load(&adev->vm_manager.pasids, pasid); 2973 + *root = vm ? amdgpu_bo_ref(vm->root.bo) : NULL; 2974 + xa_unlock_irqrestore(&adev->vm_manager.pasids, irqflags); 2975 + 2976 + if (!*root) 2977 + return NULL; 2978 + 2979 + r = amdgpu_bo_reserve(*root, true); 2980 + if (r) 2981 + goto error_unref; 2982 + 2983 + /* Double check that the VM still exists */ 2984 + xa_lock_irqsave(&adev->vm_manager.pasids, irqflags); 2985 + vm = xa_load(&adev->vm_manager.pasids, pasid); 2986 + if (vm && vm->root.bo != *root) 2987 + vm = NULL; 2988 + xa_unlock_irqrestore(&adev->vm_manager.pasids, irqflags); 2989 + if (!vm) 2990 + goto error_unlock; 2991 + 2992 + return vm; 2993 + error_unlock: 2994 + amdgpu_bo_unreserve(*root); 2995 + 2996 + error_unref: 2997 + amdgpu_bo_unref(root); 2998 + return NULL; 2999 + } 3000 + 3001 + /** 2953 3002 * amdgpu_vm_handle_fault - graceful handling of VM faults. 2954 3003 * @adev: amdgpu device pointer 2955 3004 * @pasid: PASID of the VM ··· 3008 2969 * shouldn't be reported any more. 3009 2970 */ 3010 2971 bool amdgpu_vm_handle_fault(struct amdgpu_device *adev, u32 pasid, 3011 - u32 vmid, u32 node_id, uint64_t addr, uint64_t ts, 3012 - bool write_fault) 2972 + u32 vmid, u32 node_id, uint64_t addr, 2973 + uint64_t ts, bool write_fault) 3013 2974 { 3014 2975 bool is_compute_context = false; 3015 2976 struct amdgpu_bo *root; 3016 - unsigned long irqflags; 3017 2977 uint64_t value, flags; 3018 2978 struct amdgpu_vm *vm; 3019 2979 int r; 3020 2980 3021 - xa_lock_irqsave(&adev->vm_manager.pasids, irqflags); 3022 - vm = xa_load(&adev->vm_manager.pasids, pasid); 3023 - if (vm) { 3024 - root = amdgpu_bo_ref(vm->root.bo); 3025 - is_compute_context = vm->is_compute_context; 3026 - } else { 3027 - root = NULL; 3028 - } 3029 - xa_unlock_irqrestore(&adev->vm_manager.pasids, irqflags); 3030 - 3031 - if (!root) 2981 + vm = amdgpu_vm_lock_by_pasid(adev, &root, pasid); 2982 + if (!vm) 3032 2983 return false; 2984 + 2985 + is_compute_context = vm->is_compute_context; 3033 2986 3034 2987 if (is_compute_context && !svm_range_restore_pages(adev, pasid, vmid, 3035 2988 node_id, addr >> PAGE_SHIFT, ts, write_fault)) { 2989 + amdgpu_bo_unreserve(root); 3036 2990 amdgpu_bo_unref(&root); 3037 2991 return true; 3038 2992 } 3039 2993 3040 2994 addr /= AMDGPU_GPU_PAGE_SIZE; 3041 - 3042 - r = amdgpu_bo_reserve(root, true); 3043 - if (r) 3044 - goto error_unref; 3045 - 3046 - /* Double check that the VM still exists */ 3047 - xa_lock_irqsave(&adev->vm_manager.pasids, irqflags); 3048 - vm = xa_load(&adev->vm_manager.pasids, pasid); 3049 - if (vm && vm->root.bo != root) 3050 - vm = NULL; 3051 - xa_unlock_irqrestore(&adev->vm_manager.pasids, irqflags); 3052 - if (!vm) 3053 - goto error_unlock; 3054 - 3055 2995 flags = AMDGPU_PTE_VALID | AMDGPU_PTE_SNOOPED | 3056 2996 AMDGPU_PTE_SYSTEM; 3057 2997 ··· 3069 3051 if (r < 0) 3070 3052 dev_err(adev->dev, "Can't handle page fault (%d)\n", r); 3071 3053 3072 - error_unref: 3073 3054 amdgpu_bo_unref(&root); 3074 3055 3075 3056 return false;

+3

drivers/gpu/drm/amd/amdgpu/amdgpu_vm.h

··· 592 592 u32 vmid, u32 node_id, uint64_t addr, uint64_t ts, 593 593 bool write_fault); 594 594 595 + struct amdgpu_vm *amdgpu_vm_lock_by_pasid(struct amdgpu_device *adev, 596 + struct amdgpu_bo **root, u32 pasid); 597 + 595 598 void amdgpu_vm_set_task_info(struct amdgpu_vm *vm); 596 599 597 600 void amdgpu_vm_move_to_lru_tail(struct amdgpu_device *adev,

+1

drivers/gpu/drm/amd/amdgpu/amdgpu_xcp.c

··· 181 181 } 182 182 183 183 xcp_mgr->num_xcps = num_xcps; 184 + xcp_mgr->mem_alloc_mode = AMDGPU_PARTITION_MEM_CAPPING_EVEN; 184 185 amdgpu_xcp_update_partition_sched_list(adev); 185 186 186 187 return 0;

+2

drivers/gpu/drm/amd/amdgpu/amdgpu_xcp.h

··· 132 132 struct amdgpu_xcp_cfg *xcp_cfg; 133 133 uint32_t supp_xcp_modes; 134 134 uint32_t avail_xcp_modes; 135 + /* used to determin KFD memory alloc mode for each partition */ 136 + uint32_t mem_alloc_mode; 135 137 }; 136 138 137 139 struct amdgpu_xcp_mgr_funcs {

+5 -5

drivers/gpu/drm/amd/amdgpu/gfx_v11_0.c

··· 6502 6502 DRM_DEBUG("IH: CP EOP\n"); 6503 6503 6504 6504 if (adev->enable_mes && doorbell_offset) { 6505 - struct amdgpu_userq_fence_driver *fence_drv = NULL; 6506 - struct xarray *xa = &adev->userq_xa; 6505 + struct amdgpu_usermode_queue *queue; 6506 + struct xarray *xa = &adev->userq_doorbell_xa; 6507 6507 unsigned long flags; 6508 6508 6509 6509 xa_lock_irqsave(xa, flags); 6510 - fence_drv = xa_load(xa, doorbell_offset); 6511 - if (fence_drv) 6512 - amdgpu_userq_fence_driver_process(fence_drv); 6510 + queue = xa_load(xa, doorbell_offset); 6511 + if (queue) 6512 + amdgpu_userq_fence_driver_process(queue->fence_drv); 6513 6513 xa_unlock_irqrestore(xa, flags); 6514 6514 } else { 6515 6515 me_id = (entry->ring_id & 0x0c) >> 2;

+5 -5

drivers/gpu/drm/amd/amdgpu/gfx_v12_0.c

··· 4854 4854 DRM_DEBUG("IH: CP EOP\n"); 4855 4855 4856 4856 if (adev->enable_mes && doorbell_offset) { 4857 - struct amdgpu_userq_fence_driver *fence_drv = NULL; 4858 - struct xarray *xa = &adev->userq_xa; 4857 + struct xarray *xa = &adev->userq_doorbell_xa; 4858 + struct amdgpu_usermode_queue *queue; 4859 4859 unsigned long flags; 4860 4860 4861 4861 xa_lock_irqsave(xa, flags); 4862 - fence_drv = xa_load(xa, doorbell_offset); 4863 - if (fence_drv) 4864 - amdgpu_userq_fence_driver_process(fence_drv); 4862 + queue = xa_load(xa, doorbell_offset); 4863 + if (queue) 4864 + amdgpu_userq_fence_driver_process(queue->fence_drv); 4865 4865 xa_unlock_irqrestore(xa, flags); 4866 4866 } else { 4867 4867 me_id = (entry->ring_id & 0x0c) >> 2;

+6 -5

drivers/gpu/drm/amd/amdgpu/gfx_v12_1.c

··· 3643 3643 DRM_DEBUG("IH: CP EOP\n"); 3644 3644 3645 3645 if (adev->enable_mes && doorbell_offset) { 3646 - struct amdgpu_userq_fence_driver *fence_drv = NULL; 3647 - struct xarray *xa = &adev->userq_xa; 3646 + struct xarray *xa = &adev->userq_doorbell_xa; 3647 + struct amdgpu_usermode_queue *queue; 3648 3648 unsigned long flags; 3649 3649 3650 3650 xa_lock_irqsave(xa, flags); 3651 - fence_drv = xa_load(xa, doorbell_offset); 3652 - if (fence_drv) 3653 - amdgpu_userq_fence_driver_process(fence_drv); 3651 + queue = xa_load(xa, doorbell_offset); 3652 + if (queue) 3653 + amdgpu_userq_fence_driver_process(queue->fence_drv); 3654 + 3654 3655 xa_unlock_irqrestore(xa, flags); 3655 3656 } else { 3656 3657 me_id = (entry->ring_id & 0x0c) >> 2;

-2

drivers/gpu/drm/amd/amdgpu/gmc_v10_0.c

··· 860 860 if (r) 861 861 return r; 862 862 863 - amdgpu_gmc_get_vbios_allocations(adev); 864 - 865 863 /* Memory manager */ 866 864 r = amdgpu_bo_init(adev); 867 865 if (r)

-2

drivers/gpu/drm/amd/amdgpu/gmc_v11_0.c

··· 834 834 if (r) 835 835 return r; 836 836 837 - amdgpu_gmc_get_vbios_allocations(adev); 838 - 839 837 /* Memory manager */ 840 838 r = amdgpu_bo_init(adev); 841 839 if (r)

-2

drivers/gpu/drm/amd/amdgpu/gmc_v12_0.c

··· 924 924 if (r) 925 925 return r; 926 926 927 - amdgpu_gmc_get_vbios_allocations(adev); 928 - 929 927 #ifdef HAVE_ACPI_DEV_GET_FIRST_MATCH_DEV 930 928 if (amdgpu_ip_version(adev, GC_HWIP, 0) == IP_VERSION(12, 1, 0)) { 931 929 r = amdgpu_gmc_init_mem_ranges(adev);

-2

drivers/gpu/drm/amd/amdgpu/gmc_v6_0.c

··· 854 854 if (r) 855 855 return r; 856 856 857 - amdgpu_gmc_get_vbios_allocations(adev); 858 - 859 857 r = amdgpu_bo_init(adev); 860 858 if (r) 861 859 return r;

-2

drivers/gpu/drm/amd/amdgpu/gmc_v7_0.c

··· 1034 1034 if (r) 1035 1035 return r; 1036 1036 1037 - amdgpu_gmc_get_vbios_allocations(adev); 1038 - 1039 1037 /* Memory manager */ 1040 1038 r = amdgpu_bo_init(adev); 1041 1039 if (r)

-2

drivers/gpu/drm/amd/amdgpu/gmc_v8_0.c

··· 1149 1149 if (r) 1150 1150 return r; 1151 1151 1152 - amdgpu_gmc_get_vbios_allocations(adev); 1153 - 1154 1152 /* Memory manager */ 1155 1153 r = amdgpu_bo_init(adev); 1156 1154 if (r)

-2

drivers/gpu/drm/amd/amdgpu/gmc_v9_0.c

··· 2010 2010 if (r) 2011 2011 return r; 2012 2012 2013 - amdgpu_gmc_get_vbios_allocations(adev); 2014 - 2015 2013 if (amdgpu_is_multi_aid(adev)) { 2016 2014 r = amdgpu_gmc_init_mem_ranges(adev); 2017 2015 if (r)

+5 -5

drivers/gpu/drm/amd/amdgpu/sdma_v6_0.c

··· 1662 1662 u32 doorbell_offset = entry->src_data[0]; 1663 1663 1664 1664 if (adev->enable_mes && doorbell_offset) { 1665 - struct amdgpu_userq_fence_driver *fence_drv = NULL; 1666 - struct xarray *xa = &adev->userq_xa; 1665 + struct amdgpu_usermode_queue *queue; 1666 + struct xarray *xa = &adev->userq_doorbell_xa; 1667 1667 unsigned long flags; 1668 1668 1669 1669 doorbell_offset >>= SDMA0_QUEUE0_DOORBELL_OFFSET__OFFSET__SHIFT; 1670 1670 1671 1671 xa_lock_irqsave(xa, flags); 1672 - fence_drv = xa_load(xa, doorbell_offset); 1673 - if (fence_drv) 1674 - amdgpu_userq_fence_driver_process(fence_drv); 1672 + queue = xa_load(xa, doorbell_offset); 1673 + if (queue) 1674 + amdgpu_userq_fence_driver_process(queue->fence_drv); 1675 1675 xa_unlock_irqrestore(xa, flags); 1676 1676 } 1677 1677

+5 -5

drivers/gpu/drm/amd/amdgpu/sdma_v7_0.c

··· 1594 1594 u32 doorbell_offset = entry->src_data[0]; 1595 1595 1596 1596 if (adev->enable_mes && doorbell_offset) { 1597 - struct amdgpu_userq_fence_driver *fence_drv = NULL; 1598 - struct xarray *xa = &adev->userq_xa; 1597 + struct xarray *xa = &adev->userq_doorbell_xa; 1598 + struct amdgpu_usermode_queue *queue; 1599 1599 unsigned long flags; 1600 1600 1601 1601 doorbell_offset >>= SDMA0_QUEUE0_DOORBELL_OFFSET__OFFSET__SHIFT; 1602 1602 1603 1603 xa_lock_irqsave(xa, flags); 1604 - fence_drv = xa_load(xa, doorbell_offset); 1605 - if (fence_drv) 1606 - amdgpu_userq_fence_driver_process(fence_drv); 1604 + queue = xa_load(xa, doorbell_offset); 1605 + if (queue) 1606 + amdgpu_userq_fence_driver_process(queue->fence_drv); 1607 1607 xa_unlock_irqrestore(xa, flags); 1608 1608 } 1609 1609

+19 -4

drivers/gpu/drm/amd/amdgpu/vcn_v3_0.c

··· 1909 1909 struct ttm_operation_ctx ctx = { false, false }; 1910 1910 struct amdgpu_device *adev = p->adev; 1911 1911 struct amdgpu_bo_va_mapping *map; 1912 - uint32_t *msg, num_buffers; 1912 + uint32_t *msg, num_buffers, len_dw; 1913 1913 struct amdgpu_bo *bo; 1914 1914 uint64_t start, end; 1915 1915 unsigned int i; ··· 1930 1930 return -EINVAL; 1931 1931 } 1932 1932 1933 + if (end - addr < 16) { 1934 + DRM_ERROR("VCN messages must be at least 4 DWORDs!\n"); 1935 + return -EINVAL; 1936 + } 1937 + 1933 1938 bo->flags |= AMDGPU_GEM_CREATE_CPU_ACCESS_REQUIRED; 1934 1939 amdgpu_bo_placement_from_domain(bo, bo->allowed_domains); 1935 1940 r = ttm_bo_validate(&bo->tbo, &bo->placement, &ctx); ··· 1951 1946 1952 1947 msg = ptr + addr - start; 1953 1948 1954 - /* Check length */ 1955 1949 if (msg[1] > end - addr) { 1950 + DRM_ERROR("VCN message header does not fit in BO!\n"); 1956 1951 r = -EINVAL; 1957 1952 goto out; 1958 1953 } ··· 1960 1955 if (msg[3] != RDECODE_MSG_CREATE) 1961 1956 goto out; 1962 1957 1958 + len_dw = msg[1] / 4; 1963 1959 num_buffers = msg[2]; 1960 + 1961 + /* Verify that all indices fit within the claimed length. Each index is 4 DWORDs */ 1962 + if (num_buffers > len_dw || 6 + num_buffers * 4 > len_dw) { 1963 + DRM_ERROR("VCN message has too many buffers!\n"); 1964 + r = -EINVAL; 1965 + goto out; 1966 + } 1967 + 1964 1968 for (i = 0, msg = &msg[6]; i < num_buffers; ++i, msg += 4) { 1965 1969 uint32_t offset, size, *create; 1966 1970 ··· 1979 1965 offset = msg[1]; 1980 1966 size = msg[2]; 1981 1967 1982 - if (offset + size > end) { 1968 + if (size < 4 || offset + size > end - addr) { 1969 + DRM_ERROR("VCN message buffer exceeds BO bounds!\n"); 1983 1970 r = -EINVAL; 1984 1971 goto out; 1985 1972 } 1986 1973 1987 1974 create = ptr + addr + offset - start; 1988 1975 1989 - /* H246, HEVC and VP9 can run on any instance */ 1976 + /* H264, HEVC and VP9 can run on any instance */ 1990 1977 if (create[0] == 0x7 || create[0] == 0x10 || create[0] == 0x11) 1991 1978 continue; 1992 1979

+30 -14

drivers/gpu/drm/amd/amdgpu/vcn_v4_0.c

··· 1826 1826 struct ttm_operation_ctx ctx = { false, false }; 1827 1827 struct amdgpu_device *adev = p->adev; 1828 1828 struct amdgpu_bo_va_mapping *map; 1829 - uint32_t *msg, num_buffers; 1829 + uint32_t *msg, num_buffers, len_dw; 1830 1830 struct amdgpu_bo *bo; 1831 1831 uint64_t start, end; 1832 1832 unsigned int i; ··· 1847 1847 return -EINVAL; 1848 1848 } 1849 1849 1850 + if (end - addr < 16) { 1851 + DRM_ERROR("VCN messages must be at least 4 DWORDs!\n"); 1852 + return -EINVAL; 1853 + } 1854 + 1850 1855 bo->flags |= AMDGPU_GEM_CREATE_CPU_ACCESS_REQUIRED; 1851 1856 amdgpu_bo_placement_from_domain(bo, bo->allowed_domains); 1852 1857 r = ttm_bo_validate(&bo->tbo, &bo->placement, &ctx); ··· 1868 1863 1869 1864 msg = ptr + addr - start; 1870 1865 1871 - /* Check length */ 1872 1866 if (msg[1] > end - addr) { 1867 + DRM_ERROR("VCN message header does not fit in BO!\n"); 1873 1868 r = -EINVAL; 1874 1869 goto out; 1875 1870 } ··· 1877 1872 if (msg[3] != RDECODE_MSG_CREATE) 1878 1873 goto out; 1879 1874 1875 + len_dw = msg[1] / 4; 1880 1876 num_buffers = msg[2]; 1877 + 1878 + /* Verify that all indices fit within the claimed length. Each index is 4 DWORDs */ 1879 + if (num_buffers > len_dw || 6 + num_buffers * 4 > len_dw) { 1880 + DRM_ERROR("VCN message has too many buffers!\n"); 1881 + r = -EINVAL; 1882 + goto out; 1883 + } 1884 + 1881 1885 for (i = 0, msg = &msg[6]; i < num_buffers; ++i, msg += 4) { 1882 1886 uint32_t offset, size, *create; 1883 1887 ··· 1896 1882 offset = msg[1]; 1897 1883 size = msg[2]; 1898 1884 1899 - if (offset + size > end) { 1885 + if (size < 4 || offset + size > end - addr) { 1886 + DRM_ERROR("VCN message buffer exceeds BO bounds!\n"); 1900 1887 r = -EINVAL; 1901 1888 goto out; 1902 1889 } ··· 1928 1913 static int vcn_v4_0_enc_find_ib_param(struct amdgpu_ib *ib, uint32_t id, int start) 1929 1914 { 1930 1915 int i; 1916 + uint32_t len; 1931 1917 1932 - for (i = start; i < ib->length_dw && ib->ptr[i] >= 8; i += ib->ptr[i] / 4) { 1933 - if (ib->ptr[i + 1] == id) 1918 + for (i = start; (len = amdgpu_ib_get_value(ib, i)) >= 8; i += len / 4) { 1919 + if (amdgpu_ib_get_value(ib, i + 1) == id) 1934 1920 return i; 1935 1921 } 1936 1922 return -1; ··· 1942 1926 struct amdgpu_ib *ib) 1943 1927 { 1944 1928 struct amdgpu_ring *ring = amdgpu_job_ring(job); 1945 - struct amdgpu_vcn_decode_buffer *decode_buffer; 1946 - uint64_t addr; 1947 1929 uint32_t val; 1948 1930 int idx = 0, sidx; 1949 1931 ··· 1952 1938 while ((idx = vcn_v4_0_enc_find_ib_param(ib, RADEON_VCN_ENGINE_INFO, idx)) >= 0) { 1953 1939 val = amdgpu_ib_get_value(ib, idx + 2); /* RADEON_VCN_ENGINE_TYPE */ 1954 1940 if (val == RADEON_VCN_ENGINE_TYPE_DECODE) { 1955 - decode_buffer = (struct amdgpu_vcn_decode_buffer *)&ib->ptr[idx + 6]; 1941 + uint32_t valid_buf_flag = amdgpu_ib_get_value(ib, idx + 6); 1942 + uint64_t msg_buffer_addr; 1956 1943 1957 - if (!(decode_buffer->valid_buf_flag & 0x1)) 1944 + if (!(valid_buf_flag & 0x1)) 1958 1945 return 0; 1959 1946 1960 - addr = ((u64)decode_buffer->msg_buffer_address_hi) << 32 | 1961 - decode_buffer->msg_buffer_address_lo; 1962 - return vcn_v4_0_dec_msg(p, job, addr); 1947 + msg_buffer_addr = ((u64)amdgpu_ib_get_value(ib, idx + 7)) << 32 | 1948 + amdgpu_ib_get_value(ib, idx + 8); 1949 + return vcn_v4_0_dec_msg(p, job, msg_buffer_addr); 1963 1950 } else if (val == RADEON_VCN_ENGINE_TYPE_ENCODE) { 1964 1951 sidx = vcn_v4_0_enc_find_ib_param(ib, RENCODE_IB_PARAM_SESSION_INIT, idx); 1965 - if (sidx >= 0 && ib->ptr[sidx + 2] == RENCODE_ENCODE_STANDARD_AV1) 1952 + if (sidx >= 0 && 1953 + amdgpu_ib_get_value(ib, sidx + 2) == RENCODE_ENCODE_STANDARD_AV1) 1966 1954 return vcn_v4_0_limit_sched(p, job); 1967 1955 } 1968 - idx += ib->ptr[idx] / 4; 1956 + idx += amdgpu_ib_get_value(ib, idx) / 4; 1969 1957 } 1970 1958 return 0; 1971 1959 }

+2 -1

drivers/gpu/drm/amd/amdkfd/kfd_process.c

··· 689 689 int kfd_process_create_wq(void) 690 690 { 691 691 if (!kfd_process_wq) 692 - kfd_process_wq = alloc_workqueue("kfd_process_wq", 0, 0); 692 + kfd_process_wq = alloc_workqueue("kfd_process_wq", WQ_UNBOUND, 693 + 0); 693 694 if (!kfd_restore_wq) 694 695 kfd_restore_wq = alloc_ordered_workqueue("kfd_restore_wq", 695 696 WQ_FREEZABLE);

+72 -56

drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c

··· 572 572 offload_work->stream = stream; 573 573 offload_work->adjust = adjust_copy; 574 574 575 - queue_work(system_wq, &offload_work->work); 575 + queue_work(system_percpu_wq, &offload_work->work); 576 576 } 577 577 578 578 static void dm_vupdate_high_irq(void *interrupt_params) ··· 3833 3833 .atomic_commit_setup = amdgpu_dm_atomic_setup_commit, 3834 3834 }; 3835 3835 3836 + #define DDC_MANUFACTURERNAME_SAMSUNG 0x2D4C 3837 + 3838 + static void dm_set_panel_type(struct amdgpu_dm_connector *aconnector) 3839 + { 3840 + struct drm_connector *connector = &aconnector->base; 3841 + struct drm_display_info *display_info = &connector->display_info; 3842 + struct dc_link *link = aconnector->dc_link; 3843 + struct amdgpu_device *adev; 3844 + 3845 + adev = drm_to_adev(connector->dev); 3846 + 3847 + link->panel_type = PANEL_TYPE_NONE; 3848 + 3849 + switch (display_info->amd_vsdb.panel_type) { 3850 + case AMD_VSDB_PANEL_TYPE_OLED: 3851 + link->panel_type = PANEL_TYPE_OLED; 3852 + break; 3853 + case AMD_VSDB_PANEL_TYPE_MINILED: 3854 + link->panel_type = PANEL_TYPE_MINILED; 3855 + break; 3856 + } 3857 + 3858 + /* If VSDB didn't determine panel type, check DPCD ext caps */ 3859 + if (link->panel_type == PANEL_TYPE_NONE) { 3860 + if (link->dpcd_sink_ext_caps.bits.miniled == 1) 3861 + link->panel_type = PANEL_TYPE_MINILED; 3862 + if (link->dpcd_sink_ext_caps.bits.oled == 1) 3863 + link->panel_type = PANEL_TYPE_OLED; 3864 + } 3865 + 3866 + /* 3867 + * TODO: get panel type from DID2 that has device technology field 3868 + * to specify if it's OLED or not. But we need to wait for DID2 3869 + * support in DC and EDID parser to be able to use it here. 3870 + */ 3871 + 3872 + if (link->panel_type == PANEL_TYPE_NONE) { 3873 + struct drm_amd_vsdb_info *vsdb = &display_info->amd_vsdb; 3874 + u32 lum1_max = vsdb->luminance_range1.max_luminance; 3875 + u32 lum2_max = vsdb->luminance_range2.max_luminance; 3876 + 3877 + if (vsdb->version && link->local_sink && 3878 + link->local_sink->edid_caps.manufacturer_id == 3879 + DDC_MANUFACTURERNAME_SAMSUNG && 3880 + lum1_max >= ((lum2_max * 3) / 2)) 3881 + link->panel_type = PANEL_TYPE_MINILED; 3882 + } 3883 + 3884 + if (link->panel_type == PANEL_TYPE_OLED) 3885 + drm_object_property_set_value(&connector->base, 3886 + adev_to_drm(adev)->mode_config.panel_type_property, 3887 + DRM_MODE_PANEL_TYPE_OLED); 3888 + else 3889 + drm_object_property_set_value(&connector->base, 3890 + adev_to_drm(adev)->mode_config.panel_type_property, 3891 + DRM_MODE_PANEL_TYPE_UNKNOWN); 3892 + 3893 + drm_dbg_kms(aconnector->base.dev, "Panel type: %d\n", link->panel_type); 3894 + } 3895 + 3836 3896 static void update_connector_ext_caps(struct amdgpu_dm_connector *aconnector) 3837 3897 { 3838 3898 const struct drm_panel_backlight_quirk *panel_backlight_quirk; ··· 3913 3853 caps = &adev->dm.backlight_caps[aconnector->bl_idx]; 3914 3854 caps->ext_caps = &aconnector->dc_link->dpcd_sink_ext_caps; 3915 3855 caps->aux_support = false; 3916 - 3917 - drm_object_property_set_value(&conn_base->base, 3918 - adev_to_drm(adev)->mode_config.panel_type_property, 3919 - caps->ext_caps->bits.oled ? DRM_MODE_PANEL_TYPE_OLED : DRM_MODE_PANEL_TYPE_UNKNOWN); 3920 3856 3921 3857 if (caps->ext_caps->bits.oled == 1 3922 3858 /* ··· 4087 4031 4088 4032 amdgpu_dm_update_freesync_caps(connector, aconnector->drm_edid); 4089 4033 update_connector_ext_caps(aconnector); 4034 + dm_set_panel_type(aconnector); 4090 4035 } else { 4091 4036 hdmi_cec_unset_edid(aconnector); 4092 4037 drm_dp_cec_unset_edid(&aconnector->dm_dp_aux.aux); ··· 4268 4211 dc_sink_retain(aconnector->hdmi_prev_sink); 4269 4212 4270 4213 /* Schedule delayed detection. */ 4271 - if (mod_delayed_work(system_wq, 4214 + if (mod_delayed_work(system_percpu_wq, 4272 4215 &aconnector->hdmi_hpd_debounce_work, 4273 4216 msecs_to_jiffies(aconnector->hdmi_hpd_debounce_delay_ms))) 4274 4217 drm_dbg_kms(dev, "HDMI HPD: Re-scheduled debounce work\n"); ··· 11199 11142 if (!adev->in_suspend) { 11200 11143 /* return the stolen vga memory back to VRAM */ 11201 11144 if (!adev->mman.keep_stolen_vga_memory) 11202 - amdgpu_bo_free_kernel(&adev->mman.stolen_vga_memory, NULL, NULL); 11203 - amdgpu_bo_free_kernel(&adev->mman.stolen_extended_memory, NULL, NULL); 11145 + amdgpu_ttm_unmark_vram_reserved(adev, AMDGPU_RESV_STOLEN_VGA); 11146 + amdgpu_ttm_unmark_vram_reserved(adev, AMDGPU_RESV_STOLEN_EXTENDED); 11204 11147 } 11205 11148 11206 11149 /* ··· 13212 13155 } 13213 13156 } 13214 13157 13215 - static int parse_amd_vsdb(struct amdgpu_dm_connector *aconnector, 13216 - const struct edid *edid, struct amdgpu_hdmi_vsdb_info *vsdb_info) 13158 + static int get_amd_vsdb(struct amdgpu_dm_connector *aconnector, 13159 + struct amdgpu_hdmi_vsdb_info *vsdb_info) 13217 13160 { 13218 - u8 *edid_ext = NULL; 13219 - int i; 13220 - int j = 0; 13221 - int total_ext_block_len; 13161 + struct drm_connector *connector = &aconnector->base; 13222 13162 13223 - if (edid == NULL || edid->extensions == 0) 13224 - return -ENODEV; 13163 + vsdb_info->replay_mode = connector->display_info.amd_vsdb.replay_mode; 13164 + vsdb_info->amd_vsdb_version = connector->display_info.amd_vsdb.version; 13225 13165 13226 - /* Find DisplayID extension */ 13227 - for (i = 0; i < edid->extensions; i++) { 13228 - edid_ext = (void *)(edid + (i + 1)); 13229 - if (edid_ext[0] == DISPLAYID_EXT) 13230 - break; 13231 - } 13232 - 13233 - total_ext_block_len = EDID_LENGTH * edid->extensions; 13234 - while (j < total_ext_block_len - sizeof(struct amd_vsdb_block)) { 13235 - struct amd_vsdb_block *amd_vsdb = (struct amd_vsdb_block *)&edid_ext[j]; 13236 - unsigned int ieeeId = (amd_vsdb->ieee_id[2] << 16) | (amd_vsdb->ieee_id[1] << 8) | (amd_vsdb->ieee_id[0]); 13237 - 13238 - if (ieeeId == HDMI_AMD_VENDOR_SPECIFIC_DATA_BLOCK_IEEE_REGISTRATION_ID && 13239 - amd_vsdb->version == HDMI_AMD_VENDOR_SPECIFIC_DATA_BLOCK_VERSION_3) { 13240 - u8 panel_type; 13241 - vsdb_info->replay_mode = (amd_vsdb->feature_caps & AMD_VSDB_VERSION_3_FEATURECAP_REPLAYMODE) ? true : false; 13242 - vsdb_info->amd_vsdb_version = HDMI_AMD_VENDOR_SPECIFIC_DATA_BLOCK_VERSION_3; 13243 - drm_dbg_kms(aconnector->base.dev, "Panel supports Replay Mode: %d\n", vsdb_info->replay_mode); 13244 - panel_type = (amd_vsdb->color_space_eotf_support & AMD_VDSB_VERSION_3_PANEL_TYPE_MASK) >> AMD_VDSB_VERSION_3_PANEL_TYPE_SHIFT; 13245 - switch (panel_type) { 13246 - case AMD_VSDB_PANEL_TYPE_OLED: 13247 - aconnector->dc_link->panel_type = PANEL_TYPE_OLED; 13248 - break; 13249 - case AMD_VSDB_PANEL_TYPE_MINILED: 13250 - aconnector->dc_link->panel_type = PANEL_TYPE_MINILED; 13251 - break; 13252 - default: 13253 - aconnector->dc_link->panel_type = PANEL_TYPE_NONE; 13254 - break; 13255 - } 13256 - drm_dbg_kms(aconnector->base.dev, "Panel type: %d\n", 13257 - aconnector->dc_link->panel_type); 13258 - 13259 - return true; 13260 - } 13261 - j++; 13262 - } 13263 - 13264 - return false; 13166 + return connector->display_info.amd_vsdb.version != 0; 13265 13167 } 13266 13168 13267 13169 static int parse_hdmi_amd_vsdb(struct amdgpu_dm_connector *aconnector, ··· 13323 13307 freesync_capable = true; 13324 13308 } 13325 13309 13326 - parse_amd_vsdb(amdgpu_dm_connector, edid, &vsdb_info); 13310 + get_amd_vsdb(amdgpu_dm_connector, &vsdb_info); 13327 13311 13328 13312 if (vsdb_info.replay_mode) { 13329 13313 amdgpu_dm_connector->vsdb_info.replay_mode = vsdb_info.replay_mode;

-14

drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.h

··· 53 53 54 54 #define AMDGPU_DMUB_NOTIFICATION_MAX 8 55 55 56 - #define HDMI_AMD_VENDOR_SPECIFIC_DATA_BLOCK_IEEE_REGISTRATION_ID 0x00001A 57 - #define AMD_VSDB_VERSION_3_FEATURECAP_REPLAYMODE 0x40 58 - #define AMD_VDSB_VERSION_3_PANEL_TYPE_MASK 0xC0 59 - #define AMD_VDSB_VERSION_3_PANEL_TYPE_SHIFT 6 60 - #define HDMI_AMD_VENDOR_SPECIFIC_DATA_BLOCK_VERSION_3 0x3 61 - 62 56 enum amd_vsdb_panel_type { 63 57 AMD_VSDB_PANEL_TYPE_DEFAULT = 0, 64 58 AMD_VSDB_PANEL_TYPE_MINILED, ··· 90 96 struct dc_plane_state; 91 97 struct dmub_notification; 92 98 struct dmub_cmd_fused_request; 93 - 94 - struct amd_vsdb_block { 95 - unsigned char ieee_id[3]; 96 - unsigned char version; 97 - unsigned char feature_caps; 98 - unsigned char reserved[3]; 99 - unsigned char color_space_eotf_support; 100 - }; 101 99 102 100 struct common_irq_params { 103 101 struct amdgpu_device *adev;

+10 -11

drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_crtc.c

··· 101 101 102 102 /** 103 103 * amdgpu_dm_crtc_set_panel_sr_feature() - Manage panel self-refresh features. 104 - * 105 - * @vblank_work: is a pointer to a struct vblank_control_work object. 106 - * @vblank_enabled: indicates whether the DRM vblank counter is currently 107 - * enabled (true) or disabled (false). 108 - * @allow_sr_entry: represents whether entry into the self-refresh mode is 109 - * allowed (true) or not allowed (false). 104 + * @dm: amdgpu display manager instance. 105 + * @acrtc: CRTC whose panel self-refresh state is being updated. 106 + * @stream: DC stream associated with @acrtc. 107 + * @vblank_enabled: Whether the DRM vblank counter is currently enabled. 108 + * @allow_sr_entry: Whether entry into self-refresh mode is allowed. 110 109 * 111 110 * The DRM vblank counter enable/disable action is used as the trigger to enable 112 111 * or disable various panel self-refresh features: 113 112 * 114 113 * Panel Replay and PSR SU 115 114 * - Enable when: 116 - * - VRR is disabled 117 - * - vblank counter is disabled 118 - * - entry is allowed: usermode demonstrates an adequate number of fast 119 - * commits) 120 - * - CRC capture window isn't active 115 + * - VRR is disabled 116 + * - vblank counter is disabled 117 + * - entry is allowed: usermode demonstrates an adequate number of fast 118 + * commits 119 + * - CRC capture window isn't active 121 120 * - Keep enabled even when vblank counter gets enabled 122 121 * 123 122 * PSR1

+9

drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_ism.c

··· 35 35 36 36 /** 37 37 * dm_ism_next_state - Get next state based on current state and event 38 + * @current_state: current ISM state 39 + * @event: event being processed 40 + * @next_state: place to store the next state 38 41 * 39 42 * This function defines the idle state management FSM. Invalid transitions 40 43 * are ignored and will not progress the FSM. ··· 151 148 152 149 /** 153 150 * dm_ism_get_idle_allow_delay - Calculate hysteresis-based idle allow delay 151 + * @ism: ISM instance containing configuration, history, and current state 152 + * @stream: display stream used to derive frame timing values for delay 153 + * 154 + * Calculates the delay before allowing idle optimizations based on recent 155 + * idle history and the current stream timing. 154 156 */ 155 157 static uint64_t dm_ism_get_idle_allow_delay(const struct amdgpu_dm_ism *ism, 156 158 const struct dc_stream_state *stream) ··· 220 212 221 213 /** 222 214 * dm_ism_insert_record - Insert a record into the circular history buffer 215 + * @ism: ISM instance 223 216 */ 224 217 static void dm_ism_insert_record(struct amdgpu_dm_ism *ism) 225 218 {

+1 -1

drivers/gpu/drm/amd/display/amdgpu_dm/dc_fpu.c

··· 59 59 } 60 60 61 61 /** 62 - * dc_assert_fp_enabled - Check if FPU protection is enabled 62 + * dc_is_fp_enabled - Check if FPU protection is enabled 63 63 * 64 64 * This function tells if the code is already under FPU protection or not. A 65 65 * function that works as an API for a set of FPU operations can use this

+3 -2

drivers/gpu/drm/amd/display/dc/core/dc_hw_sequencer.c

··· 23 23 * 24 24 */ 25 25 26 + #include <linux/array_size.h> 27 + 26 28 #include "dm_services.h" 27 29 #include "core_types.h" 28 30 #include "timing_generator.h" ··· 42 40 #include "dcn10/dcn10_hubbub.h" 43 41 #include "dce/dmub_hw_lock_mgr.h" 44 42 45 - #define NUM_ELEMENTS(a) (sizeof(a) / sizeof((a)[0])) 46 43 #define MAX_NUM_MCACHE 8 47 44 48 45 /* used as index in array of black_color_format */ ··· 231 230 int i; 232 231 enum dc_color_space_type type; 233 232 const uint16_t *val = NULL; 234 - int arr_size = NUM_ELEMENTS(output_csc_matrix); 233 + int arr_size = ARRAY_SIZE(output_csc_matrix); 235 234 236 235 type = get_color_space_type(color_space); 237 236 for (i = 0; i < arr_size; i++)

+1 -1

drivers/gpu/drm/amd/display/dc/core/dc_resource.c

··· 5062 5062 option = DITHER_OPTION_SPATIAL8; 5063 5063 break; 5064 5064 case COLOR_DEPTH_101010: 5065 - option = DITHER_OPTION_TRUN10; 5065 + option = DITHER_OPTION_SPATIAL10; 5066 5066 break; 5067 5067 default: 5068 5068 option = DITHER_OPTION_DISABLE;

+3 -3

drivers/gpu/drm/amd/display/dc/dce/dce_clock_source.c

··· 23 23 * 24 24 */ 25 25 26 + #include <linux/array_size.h> 27 + 26 28 #include "dm_services.h" 27 29 28 30 ··· 58 56 #define FRACT_FB_DIVIDER_DEC_POINTS_MAX_NUM 6 59 57 #define CALC_PLL_CLK_SRC_ERR_TOLERANCE 1 60 58 #define MAX_PLL_CALC_ERROR 0xFFFFFFFF 61 - 62 - #define NUM_ELEMENTS(a) (sizeof(a) / sizeof((a)[0])) 63 59 64 60 static const struct spread_spectrum_data *get_ss_data_entry( 65 61 struct dce110_clk_src *clk_src, ··· 1271 1271 { 1272 1272 int i; 1273 1273 1274 - for (i = 0; i < NUM_ELEMENTS(video_optimized_pixel_rates); i++) { 1274 + for (i = 0; i < ARRAY_SIZE(video_optimized_pixel_rates); i++) { 1275 1275 const struct pixel_rate_range_table_entry *e = &video_optimized_pixel_rates[i]; 1276 1276 1277 1277 if (e->range_min_khz <= pixel_rate_khz && pixel_rate_khz <= e->range_max_khz) {

-3

drivers/gpu/drm/amd/display/dc/dpp/dcn10/dcn10_dpp_cm.c

··· 49 49 #define FN(reg_name, field_name) \ 50 50 dpp->tf_shift->field_name, dpp->tf_mask->field_name 51 51 52 - #define NUM_ELEMENTS(a) (sizeof(a) / sizeof((a)[0])) 53 - 54 - 55 52 enum dcn10_coef_filter_type_sel { 56 53 SCL_COEF_LUMA_VERT_FILTER = 0, 57 54 SCL_COEF_LUMA_HORZ_FILTER = 1,

-3

drivers/gpu/drm/amd/display/dc/dpp/dcn401/dcn401_dpp_cm.c

··· 49 49 #define FN(reg_name, field_name) \ 50 50 dpp->tf_shift->field_name, dpp->tf_mask->field_name 51 51 52 - #define NUM_ELEMENTS(a) (sizeof(a) / sizeof((a)[0])) 53 - 54 - 55 52 enum dcn401_coef_filter_type_sel { 56 53 SCL_COEF_LUMA_VERT_FILTER = 0, 57 54 SCL_COEF_LUMA_HORZ_FILTER = 1,

-2

drivers/gpu/drm/amd/display/dc/mpc/dcn20/dcn20_mpc.c

··· 43 43 #define FN(reg_name, field_name) \ 44 44 mpc20->mpc_shift->field_name, mpc20->mpc_mask->field_name 45 45 46 - #define NUM_ELEMENTS(a) (sizeof(a) / sizeof((a)[0])) 47 - 48 46 void mpc2_update_blending( 49 47 struct mpc *mpc, 50 48 struct mpcc_blnd_cfg *blnd_cfg,

-4

drivers/gpu/drm/amd/display/dc/mpc/dcn30/dcn30_mpc.c

··· 40 40 #define FN(reg_name, field_name) \ 41 41 mpc30->mpc_shift->field_name, mpc30->mpc_mask->field_name 42 42 43 - 44 - #define NUM_ELEMENTS(a) (sizeof(a) / sizeof((a)[0])) 45 - 46 - 47 43 void mpc3_mpc_init(struct mpc *mpc) 48 44 { 49 45 struct dcn30_mpc *mpc30 = TO_DCN30_MPC(mpc);

+17

drivers/gpu/drm/amd/pm/swsmu/inc/amdgpu_smu.h

··· 2164 2164 smu_feature_list_clear_all(smu, SMU_FEATURE_LIST_ALLOWED); 2165 2165 } 2166 2166 2167 + /* 2168 + * smu_safe_u16_nn - Make u16 safe by filtering negative overflow errors 2169 + * @val: Input u16 value, may contain invalid negative overflows 2170 + * 2171 + * Convert u16 to non-negative value. Cast to s16 to detect negative values 2172 + * caused by calculation errors. Return 0 for negative errors, return 2173 + * original value if valid. 2174 + * 2175 + * Return: Valid u16 value or 0 2176 + */ 2177 + static inline u16 smu_safe_u16_nn(u16 val) 2178 + { 2179 + s16 tmp = (s16)val; 2180 + 2181 + return tmp < 0 ? 0 : val; 2182 + } 2183 + 2167 2184 #endif

+5 -5

drivers/gpu/drm/amd/pm/swsmu/smu13/smu_v13_0_0_ppt.c

··· 773 773 *value = metrics->AverageGfxclkFrequencyPreDs; 774 774 break; 775 775 case METRICS_AVERAGE_FCLK: 776 - if (metrics->AverageUclkActivity <= SMU_13_0_0_BUSY_THRESHOLD) 776 + if (smu_safe_u16_nn(metrics->AverageUclkActivity) <= SMU_13_0_0_BUSY_THRESHOLD) 777 777 *value = metrics->AverageFclkFrequencyPostDs; 778 778 else 779 779 *value = metrics->AverageFclkFrequencyPreDs; 780 780 break; 781 781 case METRICS_AVERAGE_UCLK: 782 - if (metrics->AverageUclkActivity <= SMU_13_0_0_BUSY_THRESHOLD) 782 + if (smu_safe_u16_nn(metrics->AverageUclkActivity) <= SMU_13_0_0_BUSY_THRESHOLD) 783 783 *value = metrics->AverageMemclkFrequencyPostDs; 784 784 else 785 785 *value = metrics->AverageMemclkFrequencyPreDs; ··· 800 800 *value = metrics->AverageGfxActivity; 801 801 break; 802 802 case METRICS_AVERAGE_MEMACTIVITY: 803 - *value = metrics->AverageUclkActivity; 803 + *value = smu_safe_u16_nn(metrics->AverageUclkActivity); 804 804 break; 805 805 case METRICS_AVERAGE_VCNACTIVITY: 806 806 *value = max(metrics->Vcn0ActivityPercentage, ··· 2085 2085 metrics->AvgTemperature[TEMP_VR_MEM1]); 2086 2086 2087 2087 gpu_metrics->average_gfx_activity = metrics->AverageGfxActivity; 2088 - gpu_metrics->average_umc_activity = metrics->AverageUclkActivity; 2088 + gpu_metrics->average_umc_activity = smu_safe_u16_nn(metrics->AverageUclkActivity); 2089 2089 gpu_metrics->average_mm_activity = max(metrics->Vcn0ActivityPercentage, 2090 2090 metrics->Vcn1ActivityPercentage); 2091 2091 ··· 2102 2102 else 2103 2103 gpu_metrics->average_gfxclk_frequency = metrics->AverageGfxclkFrequencyPreDs; 2104 2104 2105 - if (metrics->AverageUclkActivity <= SMU_13_0_0_BUSY_THRESHOLD) 2105 + if (smu_safe_u16_nn(metrics->AverageUclkActivity) <= SMU_13_0_0_BUSY_THRESHOLD) 2106 2106 gpu_metrics->average_uclk_frequency = metrics->AverageMemclkFrequencyPostDs; 2107 2107 else 2108 2108 gpu_metrics->average_uclk_frequency = metrics->AverageMemclkFrequencyPreDs;

+7 -2

drivers/gpu/drm/amd/pm/swsmu/smu13/smu_v13_0_12_ppt.c

··· 479 479 } 480 480 481 481 amdgpu_hdp_invalidate(smu->adev, NULL); 482 + 483 + ret = smu_cmn_vram_cpy(smu, sys_table->cache.buffer, 484 + table->cpu_addr, 485 + smu_v13_0_12_get_system_metrics_size()); 486 + if (ret) 487 + return ret; 488 + 482 489 smu_table_cache_update_time(sys_table, jiffies); 483 - memcpy(sys_table->cache.buffer, table->cpu_addr, 484 - smu_v13_0_12_get_system_metrics_size()); 485 490 486 491 return 0; 487 492 }

+12 -7

drivers/gpu/drm/amd/pm/swsmu/smu13/smu_v13_0_6_ppt.c

··· 778 778 } 779 779 780 780 amdgpu_hdp_invalidate(smu->adev, NULL); 781 - memcpy(smu_table->metrics_table, table->cpu_addr, table_size); 781 + ret = smu_cmn_vram_cpy(smu, smu_table->metrics_table, 782 + table->cpu_addr, table_size); 783 + if (ret) 784 + return ret; 782 785 783 786 smu_table->metrics_time = jiffies; 784 787 } ··· 860 857 } 861 858 862 859 amdgpu_hdp_invalidate(smu->adev, NULL); 863 - memcpy(smu_table->metrics_table, table->cpu_addr, table_size); 864 860 865 - return 0; 861 + return smu_cmn_vram_cpy(smu, smu_table->metrics_table, 862 + table->cpu_addr, table_size); 866 863 } 867 864 868 865 static void smu_v13_0_6_update_caps(struct smu_context *smu) ··· 2407 2404 2408 2405 table_size = smu_table->tables[SMU_TABLE_I2C_COMMANDS].size; 2409 2406 2410 - memcpy(table->cpu_addr, table_data, table_size); 2407 + ret = smu_cmn_vram_cpy(smu, table->cpu_addr, table_data, table_size); 2408 + if (ret) 2409 + return ret; 2410 + 2411 2411 /* Flush hdp cache */ 2412 2412 amdgpu_hdp_flush(adev, NULL); 2413 - ret = smu_cmn_send_smc_msg(smu, SMU_MSG_RequestI2cTransaction, 2414 - NULL); 2415 2413 2416 - return ret; 2414 + return smu_cmn_send_smc_msg(smu, SMU_MSG_RequestI2cTransaction, 2415 + NULL); 2417 2416 } 2418 2417 2419 2418 static int smu_v13_0_6_i2c_xfer(struct i2c_adapter *i2c_adap,

+5 -5

drivers/gpu/drm/amd/pm/swsmu/smu13/smu_v13_0_7_ppt.c

··· 783 783 *value = metrics->AverageGfxclkFrequencyPreDs; 784 784 break; 785 785 case METRICS_AVERAGE_FCLK: 786 - if (metrics->AverageUclkActivity <= SMU_13_0_7_BUSY_THRESHOLD) 786 + if (smu_safe_u16_nn(metrics->AverageUclkActivity) <= SMU_13_0_7_BUSY_THRESHOLD) 787 787 *value = metrics->AverageFclkFrequencyPostDs; 788 788 else 789 789 *value = metrics->AverageFclkFrequencyPreDs; 790 790 break; 791 791 case METRICS_AVERAGE_UCLK: 792 - if (metrics->AverageUclkActivity <= SMU_13_0_7_BUSY_THRESHOLD) 792 + if (smu_safe_u16_nn(metrics->AverageUclkActivity) <= SMU_13_0_7_BUSY_THRESHOLD) 793 793 *value = metrics->AverageMemclkFrequencyPostDs; 794 794 else 795 795 *value = metrics->AverageMemclkFrequencyPreDs; ··· 814 814 *value = metrics->AverageGfxActivity; 815 815 break; 816 816 case METRICS_AVERAGE_MEMACTIVITY: 817 - *value = metrics->AverageUclkActivity; 817 + *value = smu_safe_u16_nn(metrics->AverageUclkActivity); 818 818 break; 819 819 case METRICS_AVERAGE_SOCKETPOWER: 820 820 *value = metrics->AverageSocketPower << 8; ··· 2091 2091 metrics->AvgTemperature[TEMP_VR_MEM1]); 2092 2092 2093 2093 gpu_metrics->average_gfx_activity = metrics->AverageGfxActivity; 2094 - gpu_metrics->average_umc_activity = metrics->AverageUclkActivity; 2094 + gpu_metrics->average_umc_activity = smu_safe_u16_nn(metrics->AverageUclkActivity); 2095 2095 gpu_metrics->average_mm_activity = max(metrics->Vcn0ActivityPercentage, 2096 2096 metrics->Vcn1ActivityPercentage); 2097 2097 ··· 2104 2104 else 2105 2105 gpu_metrics->average_gfxclk_frequency = metrics->AverageGfxclkFrequencyPreDs; 2106 2106 2107 - if (metrics->AverageUclkActivity <= SMU_13_0_7_BUSY_THRESHOLD) 2107 + if (smu_safe_u16_nn(metrics->AverageUclkActivity) <= SMU_13_0_7_BUSY_THRESHOLD) 2108 2108 gpu_metrics->average_uclk_frequency = metrics->AverageMemclkFrequencyPostDs; 2109 2109 else 2110 2110 gpu_metrics->average_uclk_frequency = metrics->AverageMemclkFrequencyPreDs;

+5 -5

drivers/gpu/drm/amd/pm/swsmu/smu14/smu_v14_0_2_ppt.c

··· 661 661 *value = metrics->AverageGfxclkFrequencyPreDs; 662 662 break; 663 663 case METRICS_AVERAGE_FCLK: 664 - if (metrics->AverageUclkActivity <= SMU_14_0_2_BUSY_THRESHOLD) 664 + if (smu_safe_u16_nn(metrics->AverageUclkActivity) <= SMU_14_0_2_BUSY_THRESHOLD) 665 665 *value = metrics->AverageFclkFrequencyPostDs; 666 666 else 667 667 *value = metrics->AverageFclkFrequencyPreDs; 668 668 break; 669 669 case METRICS_AVERAGE_UCLK: 670 - if (metrics->AverageUclkActivity <= SMU_14_0_2_BUSY_THRESHOLD) 670 + if (smu_safe_u16_nn(metrics->AverageUclkActivity) <= SMU_14_0_2_BUSY_THRESHOLD) 671 671 *value = metrics->AverageMemclkFrequencyPostDs; 672 672 else 673 673 *value = metrics->AverageMemclkFrequencyPreDs; ··· 688 688 *value = metrics->AverageGfxActivity; 689 689 break; 690 690 case METRICS_AVERAGE_MEMACTIVITY: 691 - *value = metrics->AverageUclkActivity; 691 + *value = smu_safe_u16_nn(metrics->AverageUclkActivity); 692 692 break; 693 693 case METRICS_AVERAGE_VCNACTIVITY: 694 694 *value = max(metrics->AverageVcn0ActivityPercentage, ··· 2147 2147 metrics->AvgTemperature[TEMP_VR_MEM1]); 2148 2148 2149 2149 gpu_metrics->average_gfx_activity = metrics->AverageGfxActivity; 2150 - gpu_metrics->average_umc_activity = metrics->AverageUclkActivity; 2150 + gpu_metrics->average_umc_activity = smu_safe_u16_nn(metrics->AverageUclkActivity); 2151 2151 gpu_metrics->average_mm_activity = max(metrics->AverageVcn0ActivityPercentage, 2152 2152 metrics->Vcn1ActivityPercentage); 2153 2153 ··· 2159 2159 else 2160 2160 gpu_metrics->average_gfxclk_frequency = metrics->AverageGfxclkFrequencyPreDs; 2161 2161 2162 - if (metrics->AverageUclkActivity <= SMU_14_0_2_BUSY_THRESHOLD) 2162 + if (smu_safe_u16_nn(metrics->AverageUclkActivity) <= SMU_14_0_2_BUSY_THRESHOLD) 2163 2163 gpu_metrics->average_uclk_frequency = metrics->AverageMemclkFrequencyPostDs; 2164 2164 else 2165 2165 gpu_metrics->average_uclk_frequency = metrics->AverageMemclkFrequencyPreDs;

+44 -42

drivers/gpu/drm/amd/pm/swsmu/smu15/smu_v15_0_8_ppt.c

··· 344 344 } 345 345 346 346 amdgpu_device_invalidate_hdp(smu->adev, NULL); 347 - memcpy(smu_table->metrics_table, table->cpu_addr, table_size); 347 + ret = smu_cmn_vram_cpy(smu, smu_table->metrics_table, 348 + table->cpu_addr, table_size); 349 + if (ret) { 350 + mutex_unlock(&smu_table->metrics_lock); 351 + return ret; 352 + } 348 353 349 354 smu_table->metrics_time = jiffies; 350 355 } ··· 556 551 } 557 552 558 553 amdgpu_hdp_invalidate(smu->adev, NULL); 554 + 555 + ret = smu_cmn_vram_cpy(smu, sys_table->cache.buffer, 556 + table->cpu_addr, 557 + sizeof(SystemMetricsTable_t)); 558 + if (ret) 559 + return ret; 560 + 559 561 smu_table_cache_update_time(sys_table, jiffies); 560 - memcpy(sys_table->cache.buffer, table->cpu_addr, 561 - sizeof(SystemMetricsTable_t)); 562 562 563 563 return 0; 564 564 } ··· 998 988 } 999 989 1000 990 amdgpu_hdp_invalidate(smu->adev, NULL); 1001 - memcpy(smu_table->metrics_table, table->cpu_addr, table_size); 1002 991 1003 - return 0; 992 + return smu_cmn_vram_cpy(smu, smu_table->metrics_table, 993 + table->cpu_addr, table_size); 1004 994 } 1005 995 1006 996 static int smu_v15_0_8_fru_get_product_info(struct smu_context *smu, ··· 1611 1601 uint32_t mid_mask = adev->aid_mask; 1612 1602 MetricsTable_t *metrics; 1613 1603 1614 - metrics = kzalloc(sizeof(MetricsTable_t), GFP_KERNEL); 1615 - 1616 1604 ret = smu_v15_0_8_get_metrics_table_internal(smu, 1, NULL); 1617 1605 if (ret) 1618 1606 return ret; ··· 1783 1775 *current_power_limit = power_limit; 1784 1776 1785 1777 if (default_power_limit) 1786 - *max_power_limit = pptable->MaxSocketPowerLimit; 1778 + *default_power_limit = pptable->MaxSocketPowerLimit; 1787 1779 1788 1780 if (max_power_limit) 1789 1781 *max_power_limit = pptable->MaxSocketPowerLimit; ··· 1909 1901 if (smu_dpm->dpm_level != AMD_DPM_FORCED_LEVEL_MANUAL) 1910 1902 return -EINVAL; 1911 1903 1912 - if (smu_dpm->dpm_level == AMD_DPM_FORCED_LEVEL_MANUAL) { 1913 - if (min >= max) { 1914 - dev_err(smu->adev->dev, 1915 - "Minimum clk should be less than the maximum allowed clock\n"); 1916 - return -EINVAL; 1917 - } 1918 - 1919 - if (clk_type == SMU_GFXCLK || clk_type == SMU_SCLK) { 1920 - if ((min == pstate_table->gfxclk_pstate.curr.min) && 1921 - (max == pstate_table->gfxclk_pstate.curr.max)) 1922 - return 0; 1923 - 1924 - ret = smu_v15_0_8_set_gfx_soft_freq_limited_range(smu, 1925 - min, max); 1926 - if (!ret) { 1927 - pstate_table->gfxclk_pstate.curr.min = min; 1928 - pstate_table->gfxclk_pstate.curr.max = max; 1929 - } 1930 - } 1931 - 1932 - if (clk_type == SMU_UCLK) { 1933 - if (max == pstate_table->uclk_pstate.curr.max) 1934 - return 0; 1935 - 1936 - ret = smu_v15_0_set_soft_freq_limited_range(smu, 1937 - SMU_UCLK, 1938 - 0, max, 1939 - false); 1940 - if (!ret) 1941 - pstate_table->uclk_pstate.curr.max = max; 1942 - } 1943 - 1944 - return ret; 1904 + if (min >= max) { 1905 + dev_err(smu->adev->dev, 1906 + "Minimum clk should be less than the maximum allowed clock\n"); 1907 + return -EINVAL; 1945 1908 } 1946 1909 1947 - return 0; 1910 + if (clk_type == SMU_GFXCLK || clk_type == SMU_SCLK) { 1911 + if ((min == pstate_table->gfxclk_pstate.curr.min) && 1912 + (max == pstate_table->gfxclk_pstate.curr.max)) 1913 + return 0; 1914 + 1915 + ret = smu_v15_0_8_set_gfx_soft_freq_limited_range(smu, min, 1916 + max); 1917 + if (!ret) { 1918 + pstate_table->gfxclk_pstate.curr.min = min; 1919 + pstate_table->gfxclk_pstate.curr.max = max; 1920 + } 1921 + } 1922 + 1923 + if (clk_type == SMU_UCLK) { 1924 + if (max == pstate_table->uclk_pstate.curr.max) 1925 + return 0; 1926 + 1927 + ret = smu_v15_0_set_soft_freq_limited_range(smu, SMU_UCLK, 0, 1928 + max, false); 1929 + if (!ret) 1930 + pstate_table->uclk_pstate.curr.max = max; 1931 + } 1932 + 1933 + return ret; 1948 1934 } 1949 1935 1950 1936 static int smu_v15_0_8_od_edit_dpm_table(struct smu_context *smu,

+12

drivers/gpu/drm/amd/pm/swsmu/smu_cmn.c

··· 1104 1104 return 0; 1105 1105 } 1106 1106 1107 + int smu_cmn_vram_cpy(struct smu_context *smu, void *dst, const void *src, 1108 + size_t len) 1109 + { 1110 + memcpy(dst, src, len); 1111 + 1112 + /* Don't trust the copy operation if RAS fatal error happened. */ 1113 + if (amdgpu_ras_get_fed_status(smu->adev)) 1114 + return -EHWPOISON; 1115 + 1116 + return 0; 1117 + } 1118 + 1107 1119 int smu_cmn_write_watermarks_table(struct smu_context *smu) 1108 1120 { 1109 1121 void *watermarks_table = smu->smu_table.watermarks_table;

+3

drivers/gpu/drm/amd/pm/swsmu/smu_cmn.h

··· 174 174 void *table_data, 175 175 bool drv2smu); 176 176 177 + int smu_cmn_vram_cpy(struct smu_context *smu, void *dst, 178 + const void *src, size_t len); 179 + 177 180 int smu_cmn_write_watermarks_table(struct smu_context *smu); 178 181 179 182 int smu_cmn_write_pptable(struct smu_context *smu);

+3 -6

drivers/gpu/drm/amd/ras/ras_mgr/amdgpu_ras_mgr.c

··· 290 290 /* Disabled by default */ 291 291 con->uniras_enabled = false; 292 292 293 - /* Enabled only in debug mode */ 294 - if (adev->debug_enable_ras_aca) { 293 + if (amdgpu_ip_version(adev, MP0_HWIP, 0) == IP_VERSION(13, 0, 14) || 294 + adev->debug_enable_ras_aca) 295 295 con->uniras_enabled = true; 296 - RAS_DEV_INFO(adev, "Debug amdgpu uniras!"); 297 - } 298 - 299 - if (!con->uniras_enabled) 296 + else 300 297 return 0; 301 298 302 299 ras_mgr = kzalloc_obj(*ras_mgr);

+8 -8

drivers/gpu/drm/amd/ras/ras_mgr/amdgpu_virt_ras_cmd.c

··· 36 36 struct amdgpu_device *adev = ras_core->dev; 37 37 struct amdsriov_ras_telemetry *ras_telemetry_cpu; 38 38 struct amdsriov_ras_telemetry *ras_telemetry_gpu; 39 + void *fw_va = adev->mman.resv_region[AMDGPU_RESV_FW_VRAM_USAGE].cpu_ptr; 40 + void *drv_va = adev->mman.resv_region[AMDGPU_RESV_DRV_VRAM_USAGE].cpu_ptr; 39 41 uint64_t fw_vram_usage_start_offset = 0; 40 42 uint64_t ras_telemetry_offset = 0; 41 43 42 44 if (!adev->virt.fw_reserve.ras_telemetry) 43 45 return -EINVAL; 44 46 45 - if (adev->mman.fw_vram_usage_va && 46 - adev->mman.fw_vram_usage_va <= adev->virt.fw_reserve.ras_telemetry) { 47 - fw_vram_usage_start_offset = adev->mman.fw_vram_usage_start_offset; 47 + if (fw_va && fw_va <= adev->virt.fw_reserve.ras_telemetry) { 48 + fw_vram_usage_start_offset = adev->mman.resv_region[AMDGPU_RESV_FW_VRAM_USAGE].offset; 48 49 ras_telemetry_offset = (uintptr_t)adev->virt.fw_reserve.ras_telemetry - 49 - (uintptr_t)adev->mman.fw_vram_usage_va; 50 - } else if (adev->mman.drv_vram_usage_va && 51 - adev->mman.drv_vram_usage_va <= adev->virt.fw_reserve.ras_telemetry) { 52 - fw_vram_usage_start_offset = adev->mman.drv_vram_usage_start_offset; 50 + (uintptr_t)fw_va; 51 + } else if (drv_va && drv_va <= adev->virt.fw_reserve.ras_telemetry) { 52 + fw_vram_usage_start_offset = adev->mman.resv_region[AMDGPU_RESV_DRV_VRAM_USAGE].offset; 53 53 ras_telemetry_offset = (uintptr_t)adev->virt.fw_reserve.ras_telemetry - 54 - (uintptr_t)adev->mman.drv_vram_usage_va; 54 + (uintptr_t)drv_va; 55 55 } else { 56 56 return -EINVAL; 57 57 }

+72

drivers/gpu/drm/drm_edid.c

··· 99 99 }; 100 100 101 101 #define MICROSOFT_IEEE_OUI 0xca125c 102 + #define AMD_IEEE_OUI 0x00001A 103 + 104 + #define AMD_VSDB_V3_PAYLOAD_MIN_LEN 15 105 + #define AMD_VSDB_V3_PAYLOAD_MAX_LEN 20 106 + 107 + struct amd_vsdb_v3_payload { 108 + u8 oui[3]; 109 + u8 version; 110 + u8 feature_caps; 111 + u8 rsvd0[3]; 112 + u8 cs_eotf_support; 113 + u8 lum1_max; 114 + u8 lum1_min; 115 + u8 lum2_max; 116 + u8 lum2_min; 117 + u8 rsvd1[2]; 118 + /* 119 + * Bytes beyond AMD_VSDB_V3_PAYLOAD_MIN_LEN are optional; a 120 + * monitor may provide a payload as short as 15 bytes. Always 121 + * check cea_db_payload_len() before accessing extra[]. 122 + */ 123 + u8 extra[AMD_VSDB_V3_PAYLOAD_MAX_LEN - AMD_VSDB_V3_PAYLOAD_MIN_LEN]; 124 + } __packed; 102 125 103 126 struct detailed_mode_closure { 104 127 struct drm_connector *connector; ··· 5228 5205 cea_db_payload_len(db) == 21; 5229 5206 } 5230 5207 5208 + static bool cea_db_is_amd_vsdb(const struct cea_db *db) 5209 + { 5210 + return cea_db_is_vendor(db, AMD_IEEE_OUI) && 5211 + cea_db_payload_len(db) >= AMD_VSDB_V3_PAYLOAD_MIN_LEN && 5212 + cea_db_payload_len(db) <= AMD_VSDB_V3_PAYLOAD_MAX_LEN; 5213 + } 5214 + 5231 5215 static bool cea_db_is_vcdb(const struct cea_db *db) 5232 5216 { 5233 5217 return cea_db_is_extended_tag(db, CTA_EXT_DB_VIDEO_CAP) && ··· 6431 6401 connector->base.id, connector->name, version, db[5]); 6432 6402 } 6433 6403 6404 + static void drm_parse_amd_vsdb(struct drm_connector *connector, 6405 + const struct cea_db *db) 6406 + { 6407 + struct drm_display_info *info = &connector->display_info; 6408 + const u8 *data = cea_db_data(db); 6409 + const struct amd_vsdb_v3_payload *p; 6410 + 6411 + p = (const struct amd_vsdb_v3_payload *)data; 6412 + 6413 + if (p->version != 0x03) { 6414 + drm_dbg_kms(connector->dev, 6415 + "[CONNECTOR:%d:%s] Unsupported AMD VSDB version %u\n", 6416 + connector->base.id, connector->name, p->version); 6417 + return; 6418 + } 6419 + 6420 + info->amd_vsdb.version = p->version; 6421 + info->amd_vsdb.replay_mode = p->feature_caps & 0x40; 6422 + info->amd_vsdb.panel_type = (p->cs_eotf_support & 0xC0) >> 6; 6423 + info->amd_vsdb.luminance_range1.max_luminance = p->lum1_max; 6424 + info->amd_vsdb.luminance_range1.min_luminance = p->lum1_min; 6425 + info->amd_vsdb.luminance_range2.max_luminance = p->lum2_max; 6426 + info->amd_vsdb.luminance_range2.min_luminance = p->lum2_min; 6427 + 6428 + /* 6429 + * The AMD VSDB v3 payload length is variable (15..20 bytes). 6430 + * All fields through p->rsvd1 (byte 14) are always present, 6431 + * but p->extra[] (bytes 15+) may not be. Any future access to 6432 + * extra[] must be guarded with a runtime length check to avoid 6433 + * out-of-bounds reads on shorter (but spec-valid) payloads. 6434 + * For example: 6435 + * 6436 + * int len = cea_db_payload_len(db); 6437 + * 6438 + * if (len > AMD_VSDB_V3_PAYLOAD_MIN_LEN) 6439 + * info->amd_vsdb.foo = p->extra[0]; 6440 + */ 6441 + } 6442 + 6434 6443 static void drm_parse_cea_ext(struct drm_connector *connector, 6435 6444 const struct drm_edid *drm_edid) 6436 6445 { ··· 6518 6449 drm_parse_hdmi_forum_scds(connector, data); 6519 6450 else if (cea_db_is_microsoft_vsdb(db)) 6520 6451 drm_parse_microsoft_vsdb(connector, data); 6452 + else if (cea_db_is_amd_vsdb(db)) 6453 + drm_parse_amd_vsdb(connector, db); 6521 6454 else if (cea_db_is_y420cmdb(db)) 6522 6455 parse_cta_y420cmdb(connector, db, &y420cmdb_map); 6523 6456 else if (cea_db_is_y420vdb(db)) ··· 6712 6641 info->quirks = 0; 6713 6642 6714 6643 info->source_physical_address = CEC_PHYS_ADDR_INVALID; 6644 + memset(&info->amd_vsdb, 0, sizeof(info->amd_vsdb)); 6715 6645 } 6716 6646 6717 6647 static void update_displayid_info(struct drm_connector *connector,

+46 -3

drivers/gpu/drm/i915/display/intel_crtc.c

··· 209 209 crtc->base.state = &crtc_state->uapi; 210 210 crtc->config = crtc_state; 211 211 212 + INIT_LIST_HEAD(&crtc->pipe_head); 213 + 212 214 return crtc; 213 215 } 214 216 ··· 223 221 static void intel_crtc_destroy(struct drm_crtc *_crtc) 224 222 { 225 223 struct intel_crtc *crtc = to_intel_crtc(_crtc); 224 + 225 + list_del(&crtc->pipe_head); 226 226 227 227 cpu_latency_qos_remove_request(&crtc->vblank_pm_qos); 228 228 ··· 312 308 .get_vblank_timestamp = intel_crtc_get_vblank_timestamp, 313 309 }; 314 310 311 + static void add_crtc_to_pipe_list(struct intel_display *display, struct intel_crtc *crtc) 312 + { 313 + struct intel_crtc *iter; 314 + 315 + list_for_each_entry(iter, &display->pipe_list, pipe_head) { 316 + if (crtc->pipe < iter->pipe) { 317 + list_add_tail(&crtc->pipe_head, &iter->pipe_head); 318 + return; 319 + } 320 + } 321 + 322 + list_add_tail(&crtc->pipe_head, &display->pipe_list); 323 + } 324 + 315 325 static int __intel_crtc_init(struct intel_display *display, enum pipe pipe) 316 326 { 317 327 struct intel_plane *primary, *cursor; ··· 411 393 412 394 cpu_latency_qos_add_request(&crtc->vblank_pm_qos, PM_QOS_DEFAULT_VALUE); 413 395 414 - drm_WARN_ON(display->drm, drm_crtc_index(&crtc->base) != crtc->pipe); 415 - 416 396 if (HAS_CASF(display) && crtc->num_scalers >= 2) 417 397 drm_crtc_create_sharpness_strength_property(&crtc->base); 398 + 399 + add_crtc_to_pipe_list(display, crtc); 418 400 419 401 return 0; 420 402 ··· 422 404 intel_crtc_free(crtc); 423 405 424 406 return ret; 407 + } 408 + 409 + #define HAS_PIPE(display, pipe) (DISPLAY_RUNTIME_INFO(display)->pipe_mask & BIT(pipe)) 410 + 411 + /* 412 + * Expose the pipes in order A, C, B, D on discrete platforms to trick user 413 + * space into using pipes that are more likely to be available for both a) user 414 + * space if pipe B has been reserved for the joiner, and b) the joiner if pipe A 415 + * doesn't need the joiner. 416 + * 417 + * Swap pipes B and C only if both are available i.e. not fused off. 418 + */ 419 + static enum pipe reorder_pipe(struct intel_display *display, enum pipe pipe) 420 + { 421 + if (!display->platform.dgfx || !HAS_PIPE(display, PIPE_B) || !HAS_PIPE(display, PIPE_C)) 422 + return pipe; 423 + 424 + switch (pipe) { 425 + case PIPE_B: 426 + return PIPE_C; 427 + case PIPE_C: 428 + return PIPE_B; 429 + default: 430 + return pipe; 431 + } 425 432 } 426 433 427 434 int intel_crtc_init(struct intel_display *display) ··· 458 415 INTEL_NUM_PIPES(display), str_plural(INTEL_NUM_PIPES(display))); 459 416 460 417 for_each_pipe(display, pipe) { 461 - ret = __intel_crtc_init(display, pipe); 418 + ret = __intel_crtc_init(display, reorder_pipe(display, pipe)); 462 419 if (ret) 463 420 return ret; 464 421 }

+5 -15

drivers/gpu/drm/i915/display/intel_display.c

··· 5939 5939 return -EINVAL; 5940 5940 } 5941 5941 5942 - /* 5943 - * The state copy logic assumes the primary crtc gets processed 5944 - * before the secondary crtc during the main compute_config loop. 5945 - * This works because the crtcs are created in pipe order, 5946 - * and the hardware requires primary pipe < secondary pipe as well. 5947 - * Should that change we need to rethink the logic. 5948 - */ 5949 - if (WARN_ON(drm_crtc_index(&primary_crtc->base) > 5950 - drm_crtc_index(&secondary_crtc->base))) 5951 - return -EINVAL; 5952 - 5953 5942 drm_dbg_kms(display->drm, 5954 5943 "[CRTC:%d:%s] Used as secondary for joiner primary [CRTC:%d:%s]\n", 5955 5944 secondary_crtc->base.base.id, secondary_crtc->base.name, ··· 6316 6327 6317 6328 for_each_new_intel_crtc_in_state(state, crtc, new_crtc_state, i) { 6318 6329 if (!intel_crtc_needs_modeset(new_crtc_state)) { 6319 - if (intel_crtc_is_joiner_secondary(new_crtc_state)) 6320 - copy_joiner_crtc_state_nomodeset(state, crtc); 6321 - else 6330 + if (!intel_crtc_is_joiner_secondary(new_crtc_state)) 6322 6331 intel_crtc_copy_uapi_to_hw_state_nomodeset(state, crtc); 6323 6332 continue; 6324 6333 } ··· 6447 6460 goto fail; 6448 6461 6449 6462 for_each_new_intel_crtc_in_state(state, crtc, new_crtc_state, i) { 6450 - if (!intel_crtc_needs_modeset(new_crtc_state)) 6463 + if (!intel_crtc_needs_modeset(new_crtc_state)) { 6464 + if (intel_crtc_is_joiner_secondary(new_crtc_state)) 6465 + copy_joiner_crtc_state_nomodeset(state, crtc); 6451 6466 continue; 6467 + } 6452 6468 6453 6469 if (intel_crtc_is_joiner_secondary(new_crtc_state)) { 6454 6470 drm_WARN_ON(display->drm, new_crtc_state->uapi.enable);

+38 -52

drivers/gpu/drm/i915/display/intel_display.h

··· 212 212 base.head) \ 213 213 for_each_if((intel_plane)->pipe == (intel_crtc)->pipe) 214 214 215 - #define for_each_intel_crtc(dev, intel_crtc) \ 216 - list_for_each_entry(intel_crtc, \ 217 - &(dev)->mode_config.crtc_list, \ 218 - base.head) 215 + #define for_each_intel_crtc(dev, crtc) \ 216 + list_for_each_entry((crtc), \ 217 + &to_intel_display(dev)->pipe_list, \ 218 + pipe_head) 219 219 220 - #define for_each_intel_crtc_in_pipe_mask(dev, intel_crtc, pipe_mask) \ 221 - list_for_each_entry(intel_crtc, \ 222 - &(dev)->mode_config.crtc_list, \ 223 - base.head) \ 224 - for_each_if((pipe_mask) & BIT(intel_crtc->pipe)) 220 + #define for_each_intel_crtc_reverse(dev, crtc) \ 221 + list_for_each_entry_reverse((crtc), \ 222 + &to_intel_display(dev)->pipe_list, \ 223 + pipe_head) 225 224 226 - #define for_each_intel_crtc_in_pipe_mask_reverse(dev, intel_crtc, pipe_mask) \ 227 - list_for_each_entry_reverse((intel_crtc), \ 228 - &(dev)->mode_config.crtc_list, \ 229 - base.head) \ 230 - for_each_if((pipe_mask) & BIT((intel_crtc)->pipe)) 225 + #define for_each_intel_crtc_in_pipe_mask(dev, crtc, pipe_mask) \ 226 + for_each_intel_crtc((dev), (crtc)) \ 227 + for_each_if((pipe_mask) & BIT((crtc)->pipe)) 228 + 229 + #define for_each_intel_crtc_in_pipe_mask_reverse(dev, crtc, pipe_mask) \ 230 + for_each_intel_crtc_reverse((dev), (crtc)) \ 231 + for_each_if((pipe_mask) & BIT((crtc)->pipe)) 231 232 232 233 #define for_each_intel_encoder(dev, intel_encoder) \ 233 234 list_for_each_entry(intel_encoder, \ ··· 270 269 (__i)++) \ 271 270 for_each_if(plane) 272 271 273 - #define for_each_old_intel_crtc_in_state(__state, crtc, old_crtc_state, __i) \ 274 - for ((__i) = 0; \ 275 - (__i) < (__state)->base.dev->mode_config.num_crtc && \ 276 - ((crtc) = to_intel_crtc((__state)->base.crtcs[__i].ptr), \ 277 - (old_crtc_state) = to_intel_crtc_state((__state)->base.crtcs[__i].old_state), 1); \ 278 - (__i)++) \ 279 - for_each_if(crtc) 280 - 281 272 #define for_each_new_intel_plane_in_state(__state, plane, new_plane_state, __i) \ 282 273 for ((__i) = 0; \ 283 274 (__i) < (__state)->base.dev->mode_config.num_total_plane && \ ··· 277 284 (new_plane_state) = to_intel_plane_state((__state)->base.planes[__i].new_state), 1); \ 278 285 (__i)++) \ 279 286 for_each_if(plane) 280 - 281 - #define for_each_new_intel_crtc_in_state(__state, crtc, new_crtc_state, __i) \ 282 - for ((__i) = 0; \ 283 - (__i) < (__state)->base.dev->mode_config.num_crtc && \ 284 - ((crtc) = to_intel_crtc((__state)->base.crtcs[__i].ptr), \ 285 - (new_crtc_state) = to_intel_crtc_state((__state)->base.crtcs[__i].new_state), 1); \ 286 - (__i)++) \ 287 - for_each_if(crtc) 288 - 289 - #define for_each_new_intel_crtc_in_state_reverse(__state, crtc, new_crtc_state, __i) \ 290 - for ((__i) = (__state)->base.dev->mode_config.num_crtc - 1; \ 291 - (__i) >= 0 && \ 292 - ((crtc) = to_intel_crtc((__state)->base.crtcs[__i].ptr), \ 293 - (new_crtc_state) = to_intel_crtc_state((__state)->base.crtcs[__i].new_state), 1); \ 294 - (__i)--) \ 295 - for_each_if(crtc) 296 287 297 288 #define for_each_oldnew_intel_plane_in_state(__state, plane, old_plane_state, new_plane_state, __i) \ 298 289 for ((__i) = 0; \ ··· 287 310 (__i)++) \ 288 311 for_each_if(plane) 289 312 313 + #define for_each_old_intel_crtc_in_state(__state, crtc, old_crtc_state, __i) \ 314 + for_each_intel_crtc((__state)->base.dev, (crtc)) \ 315 + for_each_if(((__i) = drm_crtc_index(&(crtc)->base), (void)(__i), \ 316 + (old_crtc_state) = intel_atomic_get_old_crtc_state((__state), (crtc)))) 317 + 318 + #define for_each_new_intel_crtc_in_state(__state, crtc, new_crtc_state, __i) \ 319 + for_each_intel_crtc((__state)->base.dev, (crtc)) \ 320 + for_each_if(((__i) = drm_crtc_index(&(crtc)->base), (void)(__i), \ 321 + (new_crtc_state) = intel_atomic_get_new_crtc_state((__state), (crtc)))) 322 + 323 + #define for_each_new_intel_crtc_in_state_reverse(__state, crtc, new_crtc_state, __i) \ 324 + for_each_intel_crtc_reverse((__state)->base.dev, (crtc)) \ 325 + for_each_if(((__i) = drm_crtc_index(&(crtc)->base), (void)(__i), \ 326 + (new_crtc_state) = intel_atomic_get_new_crtc_state((__state), (crtc)))) 327 + 290 328 #define for_each_oldnew_intel_crtc_in_state(__state, crtc, old_crtc_state, new_crtc_state, __i) \ 291 - for ((__i) = 0; \ 292 - (__i) < (__state)->base.dev->mode_config.num_crtc && \ 293 - ((crtc) = to_intel_crtc((__state)->base.crtcs[__i].ptr), \ 294 - (old_crtc_state) = to_intel_crtc_state((__state)->base.crtcs[__i].old_state), \ 295 - (new_crtc_state) = to_intel_crtc_state((__state)->base.crtcs[__i].new_state), 1); \ 296 - (__i)++) \ 297 - for_each_if(crtc) 329 + for_each_intel_crtc((__state)->base.dev, (crtc)) \ 330 + for_each_if(((__i) = drm_crtc_index(&(crtc)->base), (void)(__i), \ 331 + (old_crtc_state) = intel_atomic_get_old_crtc_state((__state), (crtc)), \ 332 + (new_crtc_state) = intel_atomic_get_new_crtc_state((__state), (crtc)))) 298 333 299 334 #define for_each_oldnew_intel_crtc_in_state_reverse(__state, crtc, old_crtc_state, new_crtc_state, __i) \ 300 - for ((__i) = (__state)->base.dev->mode_config.num_crtc - 1; \ 301 - (__i) >= 0 && \ 302 - ((crtc) = to_intel_crtc((__state)->base.crtcs[__i].ptr), \ 303 - (old_crtc_state) = to_intel_crtc_state((__state)->base.crtcs[__i].old_state), \ 304 - (new_crtc_state) = to_intel_crtc_state((__state)->base.crtcs[__i].new_state), 1); \ 305 - (__i)--) \ 306 - for_each_if(crtc) 335 + for_each_intel_crtc_reverse((__state)->base.dev, (crtc)) \ 336 + for_each_if(((__i) = drm_crtc_index(&(crtc)->base), (void)(__i), \ 337 + (old_crtc_state) = intel_atomic_get_old_crtc_state((__state), (crtc)), \ 338 + (new_crtc_state) = intel_atomic_get_new_crtc_state((__state), (crtc)))) 307 339 308 340 #define intel_atomic_crtc_state_for_each_plane_state( \ 309 341 plane, plane_state, \

+3

drivers/gpu/drm/i915/display/intel_display_core.h

··· 294 294 /* Parent, or core, driver functions exposed to display */ 295 295 const struct intel_display_parent_interface *parent; 296 296 297 + /* list of all intel_crtcs sorted by pipe */ 298 + struct list_head pipe_list; 299 + 297 300 /* Display functions */ 298 301 struct { 299 302 /* Top level crtc-ish functions */

+1

drivers/gpu/drm/i915/display/intel_display_driver.c

··· 117 117 118 118 drm_mode_config_init(display->drm); 119 119 INIT_LIST_HEAD(&display->global.obj_list); 120 + INIT_LIST_HEAD(&display->pipe_list); 120 121 121 122 mode_config->min_width = 0; 122 123 mode_config->min_height = 0;

+1

drivers/gpu/drm/i915/display/intel_display_types.h

··· 1484 1484 1485 1485 struct intel_crtc { 1486 1486 struct drm_crtc base; 1487 + struct list_head pipe_head; 1487 1488 enum pipe pipe; 1488 1489 /* 1489 1490 * Whether the crtc and the connected output pipeline is active. Implies

+7 -2

drivers/gpu/drm/i915/display/intel_dp_aux_backlight.c

··· 615 615 int ret; 616 616 u8 bit_min, bit_max; 617 617 618 - if (!(intel_dp->edp_dpcd[2] & DP_EDP_BACKLIGHT_BRIGHTNESS_AUX_SET_CAP)) 619 - return true; 618 + /* 619 + * Since we only support Fully AUX Based VESA Backlight interface make sure 620 + * backlight enable is possible via AUX along with backlight adjustment 621 + */ 622 + if (!(intel_dp->edp_dpcd[1] & DP_EDP_BACKLIGHT_AUX_ENABLE_CAP && 623 + intel_dp->edp_dpcd[2] & DP_EDP_BACKLIGHT_BRIGHTNESS_AUX_SET_CAP)) 624 + return false; 620 625 621 626 ret = drm_dp_dpcd_read_byte(&intel_dp->aux, DP_EDP_PWMGEN_BIT_COUNT_CAP_MIN, &bit_min); 622 627 if (ret < 0)

+2 -2

drivers/gpu/drm/i915/display/skl_watermark.c

··· 4028 4028 } 4029 4029 4030 4030 /* DDB */ 4031 - hw_ddb_entry = &hw->ddb[PLANE_CURSOR]; 4032 - sw_ddb_entry = &new_crtc_state->wm.skl.plane_ddb[PLANE_CURSOR]; 4031 + hw_ddb_entry = &hw->ddb[plane->id]; 4032 + sw_ddb_entry = &new_crtc_state->wm.skl.plane_ddb[plane->id]; 4033 4033 4034 4034 if (!skl_ddb_entry_equal(hw_ddb_entry, sw_ddb_entry)) { 4035 4035 drm_err(display->drm,

+2 -1

drivers/gpu/drm/radeon/radeon_display.c

··· 686 686 if (radeon_crtc == NULL) 687 687 return; 688 688 689 - radeon_crtc->flip_queue = alloc_workqueue("radeon-crtc", WQ_HIGHPRI, 0); 689 + radeon_crtc->flip_queue = alloc_workqueue("radeon-crtc", 690 + WQ_HIGHPRI | WQ_PERCPU, 0); 690 691 if (!radeon_crtc->flip_queue) { 691 692 kfree(radeon_crtc); 692 693 return;

+1 -2

drivers/gpu/drm/radeon/radeon_drv.c

··· 278 278 279 279 case CHIP_BONAIRE: 280 280 case CHIP_HAWAII: 281 - support_by_default = false; 282 - fallthrough; 283 281 case CHIP_KAVERI: 284 282 case CHIP_KABINI: 285 283 case CHIP_MULLINS: 286 284 gen = "CIK"; 287 285 module_param = radeon_cik_support; 288 286 amdgpu_support_built &= IS_ENABLED(CONFIG_DRM_AMDGPU_CIK); 287 + support_by_default = false; 289 288 break; 290 289 291 290 default:

+1

drivers/gpu/drm/xe/display/xe_display.c

··· 21 21 #include "intel_audio.h" 22 22 #include "intel_bw.h" 23 23 #include "intel_display.h" 24 + #include "intel_display_core.h" 24 25 #include "intel_display_device.h" 25 26 #include "intel_display_driver.h" 26 27 #include "intel_display_irq.h"

+38

include/drm/drm_connector.h

··· 694 694 }; 695 695 696 696 /** 697 + * struct drm_amd_vsdb_info - AMD-specific VSDB information 698 + * 699 + * This structure holds information parsed from the AMD Vendor-Specific Data 700 + * Block (VSDB) version 3. 701 + */ 702 + struct drm_amd_vsdb_info { 703 + /** 704 + * @version: Version of the Vendor-Specific Data Block (VSDB) 705 + */ 706 + u8 version; 707 + 708 + /** 709 + * @replay_mode: Panel Replay supported 710 + */ 711 + bool replay_mode; 712 + 713 + /** 714 + * @panel_type: Panel technology type 715 + */ 716 + u8 panel_type; 717 + 718 + /** 719 + * @luminance_range1: Luminance for max back light 720 + */ 721 + struct drm_luminance_range_info luminance_range1; 722 + 723 + /** 724 + * @luminance_range2: Luminance for min back light 725 + */ 726 + struct drm_luminance_range_info luminance_range2; 727 + }; 728 + 729 + /** 697 730 * struct drm_display_info - runtime data about the connected sink 698 731 * 699 732 * Describes a given display (e.g. CRT or flat panel) and its limitations. For ··· 916 883 * Defaults to CEC_PHYS_ADDR_INVALID (0xffff). 917 884 */ 918 885 u16 source_physical_address; 886 + 887 + /** 888 + * @amd_vsdb: AMD-specific VSDB information. 889 + */ 890 + struct drm_amd_vsdb_info amd_vsdb; 919 891 }; 920 892 921 893 int drm_display_info_set_bus_formats(struct drm_display_info *info,

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