Linux kernel mirror (for testing)
git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git
kernel
os
linux
Merge branch 'drm-fixes' of git://people.freedesktop.org/~airlied/linux
Pull drm fixes from Dave Airlie:
"Fixes for i915, amdgpu/radeon and imx.
The IMX fix is for an autoloading regression found in Fedora. The
radeon fixes, are the same fix to amdgpu/radeon to avoid a hardware
lockup in some circumstances with a bad mode, and a double free bug I
took a few hours chasing down the other morning.
The i915 fixes are across the board, all stable material, and fixing
some hangs and suspend/resume issues, along with a live status
regressions"
* 'drm-fixes' of git://people.freedesktop.org/~airlied/linux:
gpu: ipu-v3: Fix imx-ipuv3-crtc module autoloading
drm/amdgpu: make sure vertical front porch is at least 1
drm/radeon: make sure vertical front porch is at least 1
drm/amdgpu: set metadata pointer to NULL after freeing.
drm/i915: Make RPS EI/thresholds multiple of 25 on SNB-BDW
drm/i915: Fake HDMI live status
drm/i915: Fix eDP low vswing for Broadwell
drm/i915/ddi: Fix eDP VDD handling during booting and suspend/resume
drm/i915: Fix system resume if PCI device remained enabled
drm/i915: Avoid stalling on pending flips for legacy cursor updates
+84
-16
+1
drivers/gpu/drm/amd/amdgpu/amdgpu_object.c
+1
drivers/gpu/drm/amd/amdgpu/amdgpu_object.c
+4
drivers/gpu/drm/amd/amdgpu/atombios_encoders.c
+4
drivers/gpu/drm/amd/amdgpu/atombios_encoders.c
···
298
298
&& (mode->crtc_vsync_start < (mode->crtc_vdisplay + 2)))
299
299
adjusted_mode->crtc_vsync_start = adjusted_mode->crtc_vdisplay + 2;
300
300
301
+
/* vertical FP must be at least 1 */
302
+
if (mode->crtc_vsync_start == mode->crtc_vdisplay)
303
+
adjusted_mode->crtc_vsync_start++;
304
+
301
305
/* get the native mode for scaling */
302
306
if (amdgpu_encoder->active_device & (ATOM_DEVICE_LCD_SUPPORT))
303
307
amdgpu_panel_mode_fixup(encoder, adjusted_mode);
+31
-1
drivers/gpu/drm/i915/i915_drv.c
+31
-1
drivers/gpu/drm/i915/i915_drv.c
···
792
792
static int i915_drm_resume_early(struct drm_device *dev)
793
793
{
794
794
struct drm_i915_private *dev_priv = dev->dev_private;
795
-
int ret = 0;
795
+
int ret;
796
796
797
797
/*
798
798
* We have a resume ordering issue with the snd-hda driver also
···
802
802
*
803
803
* FIXME: This should be solved with a special hdmi sink device or
804
804
* similar so that power domains can be employed.
805
+
*/
806
+
807
+
/*
808
+
* Note that we need to set the power state explicitly, since we
809
+
* powered off the device during freeze and the PCI core won't power
810
+
* it back up for us during thaw. Powering off the device during
811
+
* freeze is not a hard requirement though, and during the
812
+
* suspend/resume phases the PCI core makes sure we get here with the
813
+
* device powered on. So in case we change our freeze logic and keep
814
+
* the device powered we can also remove the following set power state
815
+
* call.
816
+
*/
817
+
ret = pci_set_power_state(dev->pdev, PCI_D0);
818
+
if (ret) {
819
+
DRM_ERROR("failed to set PCI D0 power state (%d)\n", ret);
820
+
goto out;
821
+
}
822
+
823
+
/*
824
+
* Note that pci_enable_device() first enables any parent bridge
825
+
* device and only then sets the power state for this device. The
826
+
* bridge enabling is a nop though, since bridge devices are resumed
827
+
* first. The order of enabling power and enabling the device is
828
+
* imposed by the PCI core as described above, so here we preserve the
829
+
* same order for the freeze/thaw phases.
830
+
*
831
+
* TODO: eventually we should remove pci_disable_device() /
832
+
* pci_enable_enable_device() from suspend/resume. Due to how they
833
+
* depend on the device enable refcount we can't anyway depend on them
834
+
* disabling/enabling the device.
805
835
*/
806
836
if (pci_enable_device(dev->pdev)) {
807
837
ret = -EIO;
+8
-1
drivers/gpu/drm/i915/i915_reg.h
+8
-1
drivers/gpu/drm/i915/i915_reg.h
···
2907
2907
#define GEN6_RP_STATE_CAP _MMIO(MCHBAR_MIRROR_BASE_SNB + 0x5998)
2908
2908
#define BXT_RP_STATE_CAP _MMIO(0x138170)
2909
2909
2910
-
#define INTERVAL_1_28_US(us) (((us) * 100) >> 7)
2910
+
/*
2911
+
* Make these a multiple of magic 25 to avoid SNB (eg. Dell XPS
2912
+
* 8300) freezing up around GPU hangs. Looks as if even
2913
+
* scheduling/timer interrupts start misbehaving if the RPS
2914
+
* EI/thresholds are "bad", leading to a very sluggish or even
2915
+
* frozen machine.
2916
+
*/
2917
+
#define INTERVAL_1_28_US(us) roundup(((us) * 100) >> 7, 25)
2911
2918
#define INTERVAL_1_33_US(us) (((us) * 3) >> 2)
2912
2919
#define INTERVAL_0_833_US(us) (((us) * 6) / 5)
2913
2920
#define GT_INTERVAL_FROM_US(dev_priv, us) (IS_GEN9(dev_priv) ? \
+13
-9
drivers/gpu/drm/i915/intel_ddi.c
+13
-9
drivers/gpu/drm/i915/intel_ddi.c
···
443
443
} else if (IS_BROADWELL(dev_priv)) {
444
444
ddi_translations_fdi = bdw_ddi_translations_fdi;
445
445
ddi_translations_dp = bdw_ddi_translations_dp;
446
-
ddi_translations_edp = bdw_ddi_translations_edp;
446
+
447
+
if (dev_priv->edp_low_vswing) {
448
+
ddi_translations_edp = bdw_ddi_translations_edp;
449
+
n_edp_entries = ARRAY_SIZE(bdw_ddi_translations_edp);
450
+
} else {
451
+
ddi_translations_edp = bdw_ddi_translations_dp;
452
+
n_edp_entries = ARRAY_SIZE(bdw_ddi_translations_dp);
453
+
}
454
+
447
455
ddi_translations_hdmi = bdw_ddi_translations_hdmi;
448
-
n_edp_entries = ARRAY_SIZE(bdw_ddi_translations_edp);
456
+
449
457
n_dp_entries = ARRAY_SIZE(bdw_ddi_translations_dp);
450
458
n_hdmi_entries = ARRAY_SIZE(bdw_ddi_translations_hdmi);
451
459
hdmi_default_entry = 7;
···
3209
3201
intel_ddi_clock_get(encoder, pipe_config);
3210
3202
}
3211
3203
3212
-
static void intel_ddi_destroy(struct drm_encoder *encoder)
3213
-
{
3214
-
/* HDMI has nothing special to destroy, so we can go with this. */
3215
-
intel_dp_encoder_destroy(encoder);
3216
-
}
3217
-
3218
3204
static bool intel_ddi_compute_config(struct intel_encoder *encoder,
3219
3205
struct intel_crtc_state *pipe_config)
3220
3206
{
···
3227
3225
}
3228
3226
3229
3227
static const struct drm_encoder_funcs intel_ddi_funcs = {
3230
-
.destroy = intel_ddi_destroy,
3228
+
.reset = intel_dp_encoder_reset,
3229
+
.destroy = intel_dp_encoder_destroy,
3231
3230
};
3232
3231
3233
3232
static struct intel_connector *
···
3327
3324
intel_encoder->post_disable = intel_ddi_post_disable;
3328
3325
intel_encoder->get_hw_state = intel_ddi_get_hw_state;
3329
3326
intel_encoder->get_config = intel_ddi_get_config;
3327
+
intel_encoder->suspend = intel_dp_encoder_suspend;
3330
3328
3331
3329
intel_dig_port->port = port;
3332
3330
intel_dig_port->saved_port_bits = I915_READ(DDI_BUF_CTL(port)) &
+3
drivers/gpu/drm/i915/intel_display.c
+3
drivers/gpu/drm/i915/intel_display.c
+2
-2
drivers/gpu/drm/i915/intel_dp.c
+2
-2
drivers/gpu/drm/i915/intel_dp.c
···
4898
4898
kfree(intel_dig_port);
4899
4899
}
4900
4900
4901
-
static void intel_dp_encoder_suspend(struct intel_encoder *intel_encoder)
4901
+
void intel_dp_encoder_suspend(struct intel_encoder *intel_encoder)
4902
4902
{
4903
4903
struct intel_dp *intel_dp = enc_to_intel_dp(&intel_encoder->base);
4904
4904
···
4940
4940
edp_panel_vdd_schedule_off(intel_dp);
4941
4941
}
4942
4942
4943
-
static void intel_dp_encoder_reset(struct drm_encoder *encoder)
4943
+
void intel_dp_encoder_reset(struct drm_encoder *encoder)
4944
4944
{
4945
4945
struct intel_dp *intel_dp;
4946
4946
+2
drivers/gpu/drm/i915/intel_drv.h
+2
drivers/gpu/drm/i915/intel_drv.h
···
1238
1238
void intel_dp_start_link_train(struct intel_dp *intel_dp);
1239
1239
void intel_dp_stop_link_train(struct intel_dp *intel_dp);
1240
1240
void intel_dp_sink_dpms(struct intel_dp *intel_dp, int mode);
1241
+
void intel_dp_encoder_reset(struct drm_encoder *encoder);
1242
+
void intel_dp_encoder_suspend(struct intel_encoder *intel_encoder);
1241
1243
void intel_dp_encoder_destroy(struct drm_encoder *encoder);
1242
1244
int intel_dp_sink_crc(struct intel_dp *intel_dp, u8 *crc);
1243
1245
bool intel_dp_compute_config(struct intel_encoder *encoder,
+10
-2
drivers/gpu/drm/i915/intel_hdmi.c
+10
-2
drivers/gpu/drm/i915/intel_hdmi.c
···
1415
1415
hdmi_to_dig_port(intel_hdmi));
1416
1416
}
1417
1417
1418
-
if (!live_status)
1419
-
DRM_DEBUG_KMS("Live status not up!");
1418
+
if (!live_status) {
1419
+
DRM_DEBUG_KMS("HDMI live status down\n");
1420
+
/*
1421
+
* Live status register is not reliable on all intel platforms.
1422
+
* So consider live_status only for certain platforms, for
1423
+
* others, read EDID to determine presence of sink.
1424
+
*/
1425
+
if (INTEL_INFO(dev_priv)->gen < 7 || IS_IVYBRIDGE(dev_priv))
1426
+
live_status = true;
1427
+
}
1420
1428
1421
1429
intel_hdmi_unset_edid(connector);
1422
1430
+4
drivers/gpu/drm/radeon/atombios_encoders.c
+4
drivers/gpu/drm/radeon/atombios_encoders.c
···
310
310
&& (mode->crtc_vsync_start < (mode->crtc_vdisplay + 2)))
311
311
adjusted_mode->crtc_vsync_start = adjusted_mode->crtc_vdisplay + 2;
312
312
313
+
/* vertical FP must be at least 1 */
314
+
if (mode->crtc_vsync_start == mode->crtc_vdisplay)
315
+
adjusted_mode->crtc_vsync_start++;
316
+
313
317
/* get the native mode for scaling */
314
318
if (radeon_encoder->active_device & (ATOM_DEVICE_LCD_SUPPORT)) {
315
319
radeon_panel_mode_fixup(encoder, adjusted_mode);
+6
-1
drivers/gpu/ipu-v3/ipu-common.c
+6
-1
drivers/gpu/ipu-v3/ipu-common.c
···
1068
1068
goto err_register;
1069
1069
}
1070
1070
1071
-
pdev->dev.of_node = of_node;
1072
1071
pdev->dev.parent = dev;
1073
1072
1074
1073
ret = platform_device_add_data(pdev, ®->pdata,
···
1078
1079
platform_device_put(pdev);
1079
1080
goto err_register;
1080
1081
}
1082
+
1083
+
/*
1084
+
* Set of_node only after calling platform_device_add. Otherwise
1085
+
* the platform:imx-ipuv3-crtc modalias won't be used.
1086
+
*/
1087
+
pdev->dev.of_node = of_node;
1081
1088
}
1082
1089
1083
1090
return 0;