Linux kernel mirror (for testing)
git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git
kernel
os
linux
Merge tag 'iommu-fixes-v4.10-rc2' of git://git.kernel.org/pub/scm/linux/kernel/git/joro/iommu
Pull IOMMU fixes from Joerg Roedel:
"Three fixes queued up:
- fix an issue with command buffer overflow handling in the AMD IOMMU
driver
- add an additional context entry flush to the Intel VT-d driver to
make sure any old context entry from kdump copying is flushed out
of the cache
- correct the encoding of the PASID table size in the Intel VT-d
driver"
* tag 'iommu-fixes-v4.10-rc2' of git://git.kernel.org/pub/scm/linux/kernel/git/joro/iommu:
iommu/amd: Fix the left value check of cmd buffer
iommu/vt-d: Fix pasid table size encoding
iommu/vt-d: Flush old iommu caches for kdump when the device gets context mapped
+42
-2
+1
-1
drivers/iommu/amd_iommu.c
+1
-1
drivers/iommu/amd_iommu.c
+41
-1
drivers/iommu/intel-iommu.c
+41
-1
drivers/iommu/intel-iommu.c
···
2037
2037
if (context_present(context))
2038
2038
goto out_unlock;
2039
2039
2040
+
/*
2041
+
* For kdump cases, old valid entries may be cached due to the
2042
+
* in-flight DMA and copied pgtable, but there is no unmapping
2043
+
* behaviour for them, thus we need an explicit cache flush for
2044
+
* the newly-mapped device. For kdump, at this point, the device
2045
+
* is supposed to finish reset at its driver probe stage, so no
2046
+
* in-flight DMA will exist, and we don't need to worry anymore
2047
+
* hereafter.
2048
+
*/
2049
+
if (context_copied(context)) {
2050
+
u16 did_old = context_domain_id(context);
2051
+
2052
+
if (did_old >= 0 && did_old < cap_ndoms(iommu->cap))
2053
+
iommu->flush.flush_context(iommu, did_old,
2054
+
(((u16)bus) << 8) | devfn,
2055
+
DMA_CCMD_MASK_NOBIT,
2056
+
DMA_CCMD_DEVICE_INVL);
2057
+
}
2058
+
2040
2059
pgd = domain->pgd;
2041
2060
2042
2061
context_clear_entry(context);
···
5204
5185
}
5205
5186
5206
5187
#ifdef CONFIG_INTEL_IOMMU_SVM
5188
+
#define MAX_NR_PASID_BITS (20)
5189
+
static inline unsigned long intel_iommu_get_pts(struct intel_iommu *iommu)
5190
+
{
5191
+
/*
5192
+
* Convert ecap_pss to extend context entry pts encoding, also
5193
+
* respect the soft pasid_max value set by the iommu.
5194
+
* - number of PASID bits = ecap_pss + 1
5195
+
* - number of PASID table entries = 2^(pts + 5)
5196
+
* Therefore, pts = ecap_pss - 4
5197
+
* e.g. KBL ecap_pss = 0x13, PASID has 20 bits, pts = 15
5198
+
*/
5199
+
if (ecap_pss(iommu->ecap) < 5)
5200
+
return 0;
5201
+
5202
+
/* pasid_max is encoded as actual number of entries not the bits */
5203
+
return find_first_bit((unsigned long *)&iommu->pasid_max,
5204
+
MAX_NR_PASID_BITS) - 5;
5205
+
}
5206
+
5207
5207
int intel_iommu_enable_pasid(struct intel_iommu *iommu, struct intel_svm_dev *sdev)
5208
5208
{
5209
5209
struct device_domain_info *info;
···
5255
5217
5256
5218
if (!(ctx_lo & CONTEXT_PASIDE)) {
5257
5219
context[1].hi = (u64)virt_to_phys(iommu->pasid_state_table);
5258
-
context[1].lo = (u64)virt_to_phys(iommu->pasid_table) | ecap_pss(iommu->ecap);
5220
+
context[1].lo = (u64)virt_to_phys(iommu->pasid_table) |
5221
+
intel_iommu_get_pts(iommu);
5222
+
5259
5223
wmb();
5260
5224
/* CONTEXT_TT_MULTI_LEVEL and CONTEXT_TT_DEV_IOTLB are both
5261
5225
* extended to permit requests-with-PASID if the PASIDE bit