Linux kernel mirror (for testing)
git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git
kernel
os
linux
spi: cadence-qspi: Add Renesas RZ/N1 support
Merge series from "Miquel Raynal (Schneider Electric)" <miquel.raynal@bootlin.com>:
This series adds support for the QSPI controller available on Renesas
RZ/N1S and RZ/N1D SoC. It has been tested with a custom board (see last
SPI patch for details), but has been tested by Wolfram (thank you!) on
the DB board.
Link: https://lore.kernel.org/linux-devicetree/20260116114852.52948-2-wsa+renesas@sang-engineering.com/
Adding support for this SoC required a few adaptations in the Cadence
QSPI driver. The bulk of the work is in the few last patches. Everything
else is just misc style fixes and improvements which bothered me while I
was wandering.
In order to support all constraints, I sometimes used a new quirk (for
the write protection feature and the "no indirect mode"), and sometimes
used the compatible directly. The ones I thought might not be RZ/N1
specific have been implemented under the form of a quirk, in order to
ease their reuse. The other adaptations, which I believe are more
Renesas specific, have been handled using the compatible. This is all
very arbitrary, and can be discussed.
+72
-59
+1
-1
Documentation/devicetree/bindings/spi/cdns,qspi-nor.yaml
+1
-1
Documentation/devicetree/bindings/spi/cdns,qspi-nor.yaml
+71
-58
drivers/spi/spi-cadence-quadspi.c
+71
-58
drivers/spi/spi-cadence-quadspi.c
···
40
40
#define CQSPI_DISABLE_DAC_MODE BIT(1)
41
41
#define CQSPI_SUPPORT_EXTERNAL_DMA BIT(2)
42
42
#define CQSPI_NO_SUPPORT_WR_COMPLETION BIT(3)
43
-
#define CQSPI_SLOW_SRAM BIT(4)
43
+
#define CQSPI_SLOW_SRAM BIT(4)
44
44
#define CQSPI_NEEDS_APB_AHB_HAZARD_WAR BIT(5)
45
45
#define CQSPI_RD_NO_IRQ BIT(6)
46
46
#define CQSPI_DMA_SET_MASK BIT(7)
47
47
#define CQSPI_SUPPORT_DEVICE_RESET BIT(8)
48
48
#define CQSPI_DISABLE_STIG_MODE BIT(9)
49
49
#define CQSPI_DISABLE_RUNTIME_PM BIT(10)
50
+
#define CQSPI_NO_INDIRECT_MODE BIT(11)
51
+
#define CQSPI_HAS_WR_PROTECT BIT(12)
50
52
51
53
/* Capabilities */
52
54
#define CQSPI_SUPPORTS_OCTAL BIT(0)
···
221
219
#define CQSPI_REG_IRQSTATUS 0x40
222
220
#define CQSPI_REG_IRQMASK 0x44
223
221
222
+
#define CQSPI_REG_WR_PROT_CTRL 0x58
223
+
224
224
#define CQSPI_REG_INDIRECTRD 0x60
225
225
#define CQSPI_REG_INDIRECTRD_START_MASK BIT(0)
226
226
#define CQSPI_REG_INDIRECTRD_CANCEL_MASK BIT(1)
···
378
374
/* Clear interrupt */
379
375
writel(irq_status, cqspi->iobase + CQSPI_REG_IRQSTATUS);
380
376
381
-
if (cqspi->use_dma_read && ddata && ddata->get_dma_status) {
382
-
if (ddata->get_dma_status(cqspi)) {
383
-
complete(&cqspi->transfer_complete);
384
-
return IRQ_HANDLED;
385
-
}
386
-
}
387
-
388
-
else if (!cqspi->slow_sram)
389
-
irq_status &= CQSPI_IRQ_MASK_RD | CQSPI_IRQ_MASK_WR;
390
-
else
377
+
if (cqspi->use_dma_read && ddata && ddata->get_dma_status)
378
+
irq_status = ddata->get_dma_status(cqspi);
379
+
else if (cqspi->slow_sram)
391
380
irq_status &= CQSPI_IRQ_MASK_RD_SLOW_SRAM | CQSPI_IRQ_MASK_WR;
381
+
else
382
+
irq_status &= CQSPI_IRQ_MASK_RD | CQSPI_IRQ_MASK_WR;
392
383
393
384
if (irq_status)
394
385
complete(&cqspi->transfer_complete);
···
1262
1263
1263
1264
reg = readl(reg_base + CQSPI_REG_CONFIG);
1264
1265
reg &= ~(CQSPI_REG_CONFIG_BAUD_MASK << CQSPI_REG_CONFIG_BAUD_LSB);
1265
-
reg |= (div & CQSPI_REG_CONFIG_BAUD_MASK) << CQSPI_REG_CONFIG_BAUD_LSB;
1266
+
reg |= div << CQSPI_REG_CONFIG_BAUD_LSB;
1266
1267
writel(reg, reg_base + CQSPI_REG_CONFIG);
1267
1268
}
1268
1269
···
1429
1430
if (ret)
1430
1431
return ret;
1431
1432
1432
-
if (cqspi->use_direct_mode && ((from + len) <= cqspi->ahb_size))
1433
+
if ((cqspi->use_direct_mode && ((from + len) <= cqspi->ahb_size)) ||
1434
+
(cqspi->ddata && cqspi->ddata->quirks & CQSPI_NO_INDIRECT_MODE))
1433
1435
return cqspi_direct_read_execute(f_pdata, buf, from, len);
1434
1436
1435
1437
if (cqspi->use_dma_read && ddata && ddata->indirect_read_dma &&
···
1536
1536
return false;
1537
1537
if (op->data.nbytes && op->data.buswidth != 8)
1538
1538
return false;
1539
+
1540
+
/* A single opcode is supported, it will be repeated */
1541
+
if ((op->cmd.opcode >> 8) != (op->cmd.opcode & 0xFF))
1542
+
return false;
1539
1543
} else if (!all_false) {
1540
1544
/* Mixed DTR modes are not supported. */
1541
1545
return false;
···
1598
1594
cqspi->fifo_depth = 0;
1599
1595
}
1600
1596
1601
-
if (of_property_read_u32(np, "cdns,fifo-width", &cqspi->fifo_width)) {
1602
-
dev_err(dev, "couldn't determine fifo-width\n");
1603
-
return -ENXIO;
1604
-
}
1597
+
if (of_property_read_u32(np, "cdns,fifo-width", &cqspi->fifo_width))
1598
+
cqspi->fifo_width = 4;
1605
1599
1606
1600
if (of_property_read_u32(np, "cdns,trigger-address",
1607
1601
&cqspi->trigger_address)) {
···
1629
1627
/* Disable all interrupts. */
1630
1628
writel(0, cqspi->iobase + CQSPI_REG_IRQMASK);
1631
1629
1632
-
/* Configure the SRAM split to 1:1 . */
1633
-
writel(cqspi->fifo_depth / 2, cqspi->iobase + CQSPI_REG_SRAMPARTITION);
1630
+
if (!(cqspi->ddata && cqspi->ddata->quirks & CQSPI_NO_INDIRECT_MODE)) {
1631
+
/* Configure the SRAM split to 1:1 . */
1632
+
writel(cqspi->fifo_depth / 2, cqspi->iobase + CQSPI_REG_SRAMPARTITION);
1633
+
/* Load indirect trigger address. */
1634
+
writel(cqspi->trigger_address,
1635
+
cqspi->iobase + CQSPI_REG_INDIRECTTRIGGER);
1634
1636
1635
-
/* Load indirect trigger address. */
1636
-
writel(cqspi->trigger_address,
1637
-
cqspi->iobase + CQSPI_REG_INDIRECTTRIGGER);
1637
+
/* Program read watermark -- 1/2 of the FIFO. */
1638
+
writel(cqspi->fifo_depth * cqspi->fifo_width / 2,
1639
+
cqspi->iobase + CQSPI_REG_INDIRECTRDWATERMARK);
1640
+
/* Program write watermark -- 1/8 of the FIFO. */
1641
+
writel(cqspi->fifo_depth * cqspi->fifo_width / 8,
1642
+
cqspi->iobase + CQSPI_REG_INDIRECTWRWATERMARK);
1643
+
}
1638
1644
1639
-
/* Program read watermark -- 1/2 of the FIFO. */
1640
-
writel(cqspi->fifo_depth * cqspi->fifo_width / 2,
1641
-
cqspi->iobase + CQSPI_REG_INDIRECTRDWATERMARK);
1642
-
/* Program write watermark -- 1/8 of the FIFO. */
1643
-
writel(cqspi->fifo_depth * cqspi->fifo_width / 8,
1644
-
cqspi->iobase + CQSPI_REG_INDIRECTWRWATERMARK);
1645
+
/* Disable write protection at controller level */
1646
+
if (cqspi->ddata && cqspi->ddata->quirks & CQSPI_HAS_WR_PROTECT)
1647
+
writel(0, cqspi->iobase + CQSPI_REG_WR_PROT_CTRL);
1645
1648
1646
1649
/* Disable direct access controller */
1647
1650
if (!cqspi->use_direct_mode) {
···
1897
1890
ret = clk_prepare_enable(cqspi->clk);
1898
1891
if (ret) {
1899
1892
dev_err(dev, "Cannot enable QSPI clock.\n");
1900
-
goto probe_clk_failed;
1893
+
goto disable_rpm;
1901
1894
}
1902
1895
1903
1896
/* Obtain QSPI reset control */
···
1905
1898
if (IS_ERR(rstc)) {
1906
1899
ret = PTR_ERR(rstc);
1907
1900
dev_err(dev, "Cannot get QSPI reset.\n");
1908
-
goto probe_reset_failed;
1901
+
goto disable_clk;
1909
1902
}
1910
1903
1911
1904
rstc_ocp = devm_reset_control_get_optional_exclusive(dev, "qspi-ocp");
1912
1905
if (IS_ERR(rstc_ocp)) {
1913
1906
ret = PTR_ERR(rstc_ocp);
1914
1907
dev_err(dev, "Cannot get QSPI OCP reset.\n");
1915
-
goto probe_reset_failed;
1908
+
goto disable_clk;
1916
1909
}
1917
1910
1918
1911
if (of_device_is_compatible(pdev->dev.of_node, "starfive,jh7110-qspi")) {
···
1920
1913
if (IS_ERR(rstc_ref)) {
1921
1914
ret = PTR_ERR(rstc_ref);
1922
1915
dev_err(dev, "Cannot get QSPI REF reset.\n");
1923
-
goto probe_reset_failed;
1916
+
goto disable_clk;
1924
1917
}
1925
1918
reset_control_assert(rstc_ref);
1926
1919
reset_control_deassert(rstc_ref);
···
1962
1955
if (ddata->jh7110_clk_init) {
1963
1956
ret = cqspi_jh7110_clk_init(pdev, cqspi);
1964
1957
if (ret)
1965
-
goto probe_reset_failed;
1958
+
goto disable_clk;
1966
1959
}
1967
1960
if (ddata->quirks & CQSPI_DISABLE_STIG_MODE)
1968
1961
cqspi->disable_stig_mode = true;
···
1970
1963
if (ddata->quirks & CQSPI_DMA_SET_MASK) {
1971
1964
ret = dma_set_mask(&pdev->dev, DMA_BIT_MASK(64));
1972
1965
if (ret)
1973
-
goto probe_reset_failed;
1966
+
goto disable_clks;
1974
1967
}
1975
1968
}
1976
1969
···
1981
1974
pdev->name, cqspi);
1982
1975
if (ret) {
1983
1976
dev_err(dev, "Cannot request IRQ.\n");
1984
-
goto probe_reset_failed;
1977
+
goto disable_clks;
1985
1978
}
1986
1979
1987
1980
cqspi_wait_idle(cqspi);
···
2008
2001
ret = cqspi_request_mmap_dma(cqspi);
2009
2002
if (ret == -EPROBE_DEFER) {
2010
2003
dev_err_probe(&pdev->dev, ret, "Failed to request mmap DMA\n");
2011
-
goto probe_setup_failed;
2004
+
goto disable_controller;
2012
2005
}
2013
2006
}
2014
2007
2015
2008
ret = spi_register_controller(host);
2016
2009
if (ret) {
2017
2010
dev_err(&pdev->dev, "failed to register SPI ctlr %d\n", ret);
2018
-
goto probe_setup_failed;
2011
+
goto release_dma_chan;
2019
2012
}
2020
2013
2021
2014
if (!(ddata && (ddata->quirks & CQSPI_DISABLE_RUNTIME_PM)))
2022
2015
pm_runtime_put_autosuspend(dev);
2023
2016
2024
2017
return 0;
2025
-
probe_setup_failed:
2026
-
if (!(ddata && (ddata->quirks & CQSPI_DISABLE_RUNTIME_PM)))
2027
-
pm_runtime_disable(dev);
2018
+
2019
+
release_dma_chan:
2020
+
if (cqspi->rx_chan)
2021
+
dma_release_channel(cqspi->rx_chan);
2022
+
disable_controller:
2028
2023
cqspi_controller_enable(cqspi, 0);
2029
-
probe_reset_failed:
2024
+
disable_clks:
2030
2025
if (cqspi->is_jh7110)
2031
2026
cqspi_jh7110_disable_clk(pdev, cqspi);
2032
-
2027
+
disable_clk:
2033
2028
if (pm_runtime_get_sync(&pdev->dev) >= 0)
2034
2029
clk_disable_unprepare(cqspi->clk);
2035
-
probe_clk_failed:
2030
+
disable_rpm:
2031
+
if (!(ddata && (ddata->quirks & CQSPI_DISABLE_RUNTIME_PM)))
2032
+
pm_runtime_disable(dev);
2033
+
2036
2034
return ret;
2037
2035
}
2038
2036
···
2046
2034
const struct cqspi_driver_platdata *ddata;
2047
2035
struct cqspi_st *cqspi = platform_get_drvdata(pdev);
2048
2036
struct device *dev = &pdev->dev;
2037
+
int ret = 0;
2049
2038
2050
2039
ddata = of_device_get_match_data(dev);
2051
2040
···
2056
2043
cqspi_wait_idle(cqspi);
2057
2044
2058
2045
spi_unregister_controller(cqspi->host);
2059
-
cqspi_controller_enable(cqspi, 0);
2060
2046
2061
2047
if (cqspi->rx_chan)
2062
2048
dma_release_channel(cqspi->rx_chan);
2063
2049
2064
-
if (!(ddata && (ddata->quirks & CQSPI_DISABLE_RUNTIME_PM)))
2065
-
if (pm_runtime_get_sync(&pdev->dev) >= 0)
2066
-
clk_disable(cqspi->clk);
2050
+
cqspi_controller_enable(cqspi, 0);
2067
2051
2068
2052
if (cqspi->is_jh7110)
2069
2053
cqspi_jh7110_disable_clk(pdev, cqspi);
2054
+
2055
+
if (!(ddata && (ddata->quirks & CQSPI_DISABLE_RUNTIME_PM)))
2056
+
ret = pm_runtime_get_sync(&pdev->dev);
2057
+
2058
+
if (ret >= 0)
2059
+
clk_disable(cqspi->clk);
2070
2060
2071
2061
if (!(ddata && (ddata->quirks & CQSPI_DISABLE_RUNTIME_PM))) {
2072
2062
pm_runtime_put_sync(&pdev->dev);
···
2150
2134
};
2151
2135
2152
2136
static const struct cqspi_driver_platdata socfpga_qspi = {
2153
-
.quirks = CQSPI_DISABLE_DAC_MODE
2154
-
| CQSPI_NO_SUPPORT_WR_COMPLETION
2155
-
| CQSPI_SLOW_SRAM
2156
-
| CQSPI_DISABLE_STIG_MODE
2157
-
| CQSPI_DISABLE_RUNTIME_PM,
2137
+
.quirks = CQSPI_DISABLE_DAC_MODE | CQSPI_NO_SUPPORT_WR_COMPLETION |
2138
+
CQSPI_SLOW_SRAM | CQSPI_DISABLE_STIG_MODE |
2139
+
CQSPI_DISABLE_RUNTIME_PM,
2158
2140
};
2159
2141
2160
2142
static const struct cqspi_driver_platdata versal_ospi = {
2161
2143
.hwcaps_mask = CQSPI_SUPPORTS_OCTAL,
2162
-
.quirks = CQSPI_DISABLE_DAC_MODE | CQSPI_SUPPORT_EXTERNAL_DMA
2163
-
| CQSPI_DMA_SET_MASK,
2144
+
.quirks = CQSPI_DISABLE_DAC_MODE | CQSPI_SUPPORT_EXTERNAL_DMA |
2145
+
CQSPI_DMA_SET_MASK,
2164
2146
.indirect_read_dma = cqspi_versal_indirect_read_dma,
2165
2147
.get_dma_status = cqspi_get_versal_dma_status,
2166
2148
};
2167
2149
2168
2150
static const struct cqspi_driver_platdata versal2_ospi = {
2169
2151
.hwcaps_mask = CQSPI_SUPPORTS_OCTAL,
2170
-
.quirks = CQSPI_DISABLE_DAC_MODE | CQSPI_SUPPORT_EXTERNAL_DMA
2171
-
| CQSPI_DMA_SET_MASK
2172
-
| CQSPI_SUPPORT_DEVICE_RESET,
2152
+
.quirks = CQSPI_DISABLE_DAC_MODE | CQSPI_SUPPORT_EXTERNAL_DMA |
2153
+
CQSPI_DMA_SET_MASK | CQSPI_SUPPORT_DEVICE_RESET,
2173
2154
.indirect_read_dma = cqspi_versal_indirect_read_dma,
2174
2155
.get_dma_status = cqspi_get_versal_dma_status,
2175
2156
};
···
2183
2170
static const struct cqspi_driver_platdata mobileye_eyeq5_ospi = {
2184
2171
.hwcaps_mask = CQSPI_SUPPORTS_OCTAL,
2185
2172
.quirks = CQSPI_DISABLE_DAC_MODE | CQSPI_NO_SUPPORT_WR_COMPLETION |
2186
-
CQSPI_RD_NO_IRQ,
2173
+
CQSPI_RD_NO_IRQ,
2187
2174
};
2188
2175
2189
2176
static const struct of_device_id cqspi_dt_ids[] = {