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perf/x86/amd: Support PERF_PMU_CAP_MEDIATED_VPMU for AMD host

Apply the PERF_PMU_CAP_MEDIATED_VPMU flag for version 2 and later
implementations of the core PMU. Aside from having Global Control and
Status registers, virtualizing the PMU using the mediated model requires
an interface to set or clear the overflow bits in the Global Status MSRs
while restoring or saving the PMU context of a vCPU.

PerfMonV2-capable hardware has additional MSRs for this purpose, namely
PerfCntrGlobalStatusSet and PerfCntrGlobalStatusClr, thereby making it
suitable for use with mediated vPMU.

Signed-off-by: Sandipan Das <sandipan.das@amd.com>
Signed-off-by: Mingwei Zhang <mizhang@google.com>
Signed-off-by: Sean Christopherson <seanjc@google.com>
Signed-off-by: Peter Zijlstra (Intel) <peterz@infradead.org>
Tested-by: Xudong Hao <xudong.hao@intel.com>
Link: https://patch.msgid.link/20251206001720.468579-14-seanjc@google.com

authored by

Sandipan Das and committed by
Peter Zijlstra 65eb3a9a 4280d795

+2
+2
arch/x86/events/amd/core.c
··· 1439 1439 1440 1440 amd_pmu_global_cntr_mask = x86_pmu.cntr_mask64; 1441 1441 1442 + x86_get_pmu(smp_processor_id())->capabilities |= PERF_PMU_CAP_MEDIATED_VPMU; 1443 + 1442 1444 /* Update PMC handling functions */ 1443 1445 x86_pmu.enable_all = amd_pmu_v2_enable_all; 1444 1446 x86_pmu.disable_all = amd_pmu_v2_disable_all;