Linux kernel mirror (for testing)
git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git
kernel
os
linux
Merge tag 'armsoc-fixes' of git://git.kernel.org/pub/scm/linux/kernel/git/arm/arm-soc
Pull ARM SoC fixes from Arnd Bergmann:
"This comes a bit later than I planned, and as a consequence is a
larger than it should be.
Most of the changes are devicetree fixes, across lots of platforms:
Renesas, Samsung Exynos, Marvell EBU, TI OMAP, Rockchips, Amlogic
Meson, Sigma Desings Tango, Allwinner SUNxi and TI Davinci.
Also across many platforms, I applied an older series of simple
randconfig build fixes. This includes making the CONFIG_MTD_XIP option
compile again, which had been broken for many years and probably has
not been missed, but it felt wrong to just remove it completely.
The only other changes are:
- We enable HWSPINLOCK in defconfig to get some Qualcomm boards to
work out of the box.
- A few regression fixes for Texas Instruments OMAP2+.
- A boot regression fix for the Renesas regulator quirk.
- A suspend/resume fix for Uniphier SoCs, fixing the resume of the
system bus"
* tag 'armsoc-fixes' of git://git.kernel.org/pub/scm/linux/kernel/git/arm/arm-soc: (43 commits)
ARM: dts: tango4: Request RGMII RX and TX clock delays
bus: uniphier-system-bus: set up registers when resuming
ARM64: dts: marvell: armada-37xx: Fix the number of GPIO on south bridge
ARM: shmobile: rcar-gen2: Fix deadlock in regulator quirk
arm64: defconfig: enable missing HWSPINLOCK
ARM: pxa: select both FB and FB_W100 for eseries
ARM: ixp4xx: fix ioport_unmap definition
ARM: ep93xx: use ARM_PATCH_PHYS_VIRT correctly
ARM: mmp: mark usb_dma_mask as __maybe_unused
ARM: omap2: mark unused functions as __maybe_unused
ARM: omap1: avoid unused variable warning
ARM: sirf: mark sirfsoc_init_late as __maybe_unused
ARM: ixp4xx: use normal prototype for {read,write}s{b,w,l}
ARM: omap1/ams-delta: warn about failed regulator enable
ARM: rpc: rename RAM_SIZE macro
ARM: w90x900: normalize clk API
ARM: ep93xx: normalize clk API
ARM: dts: sun8i: a83t: Switch to CCU device tree binding macros
arm64: allwinner: sun50i-a64: Correct emac register size
ARM: dts: sunxi: h3/h5: Correct emac register size
...
+372
-103
+1
-1
Documentation/devicetree/bindings/gpu/arm,mali-midgard.txt
+1
-1
Documentation/devicetree/bindings/gpu/arm,mali-midgard.txt
···
40
40
Example for a Mali-T760:
41
41
42
42
gpu@ffa30000 {
43
-
compatible = "rockchip,rk3288-mali", "arm,mali-t760", "arm,mali-midgard";
43
+
compatible = "rockchip,rk3288-mali", "arm,mali-t760";
44
44
reg = <0xffa30000 0x10000>;
45
45
interrupts = <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>,
46
46
<GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>,
+1
-1
arch/arm/Kconfig
+1
-1
arch/arm/Kconfig
+2
-2
arch/arm/boot/dts/armada-388-gp.dts
+2
-2
arch/arm/boot/dts/armada-388-gp.dts
···
75
75
pinctrl-names = "default";
76
76
pinctrl-0 = <&pca0_pins>;
77
77
interrupt-parent = <&gpio0>;
78
-
interrupts = <18 IRQ_TYPE_EDGE_FALLING>;
78
+
interrupts = <18 IRQ_TYPE_LEVEL_LOW>;
79
79
gpio-controller;
80
80
#gpio-cells = <2>;
81
81
interrupt-controller;
···
87
87
compatible = "nxp,pca9555";
88
88
pinctrl-names = "default";
89
89
interrupt-parent = <&gpio0>;
90
-
interrupts = <18 IRQ_TYPE_EDGE_FALLING>;
90
+
interrupts = <18 IRQ_TYPE_LEVEL_LOW>;
91
91
gpio-controller;
92
92
#gpio-cells = <2>;
93
93
interrupt-controller;
-21
arch/arm/boot/dts/da850-evm.dts
-21
arch/arm/boot/dts/da850-evm.dts
···
301
301
pinctrl-names = "default";
302
302
pinctrl-0 = <&vpif_capture_pins>, <&vpif_display_pins>;
303
303
status = "okay";
304
-
305
-
/* VPIF capture port */
306
-
port@0 {
307
-
vpif_input_ch0: endpoint@0 {
308
-
reg = <0>;
309
-
bus-width = <8>;
310
-
};
311
-
312
-
vpif_input_ch1: endpoint@1 {
313
-
reg = <1>;
314
-
bus-width = <8>;
315
-
data-shift = <8>;
316
-
};
317
-
};
318
-
319
-
/* VPIF display port */
320
-
port@1 {
321
-
vpif_output_ch0: endpoint {
322
-
bus-width = <8>;
323
-
};
324
-
};
325
304
};
-7
arch/arm/boot/dts/da850-lcdk.dts
-7
arch/arm/boot/dts/da850-lcdk.dts
+33
-1
arch/arm/boot/dts/dm8168-evm.dts
+33
-1
arch/arm/boot/dts/dm8168-evm.dts
···
68
68
DM816X_IOPAD(0x0d08, MUX_MODE0) /* USB1_DRVVBUS */
69
69
>;
70
70
};
71
+
72
+
nandflash_pins: nandflash_pins {
73
+
pinctrl-single,pins = <
74
+
DM816X_IOPAD(0x0b38, PULL_UP | MUX_MODE0) /* PINCTRL207 GPMC_CS0*/
75
+
DM816X_IOPAD(0x0b60, PULL_ENA | MUX_MODE0) /* PINCTRL217 GPMC_ADV_ALE */
76
+
DM816X_IOPAD(0x0b54, PULL_UP | PULL_ENA | MUX_MODE0) /* PINCTRL214 GPMC_OE_RE */
77
+
DM816X_IOPAD(0x0b58, PULL_ENA | MUX_MODE0) /* PINCTRL215 GPMC_BE0_CLE */
78
+
DM816X_IOPAD(0x0b50, PULL_UP | MUX_MODE0) /* PINCTRL213 GPMC_WE */
79
+
DM816X_IOPAD(0x0b6c, MUX_MODE0) /* PINCTRL220 GPMC_WAIT */
80
+
DM816X_IOPAD(0x0be4, PULL_ENA | MUX_MODE0) /* PINCTRL250 GPMC_CLK */
81
+
DM816X_IOPAD(0x0ba4, MUX_MODE0) /* PINCTRL234 GPMC_D0 */
82
+
DM816X_IOPAD(0x0ba8, MUX_MODE0) /* PINCTRL234 GPMC_D1 */
83
+
DM816X_IOPAD(0x0bac, MUX_MODE0) /* PINCTRL234 GPMC_D2 */
84
+
DM816X_IOPAD(0x0bb0, MUX_MODE0) /* PINCTRL234 GPMC_D3 */
85
+
DM816X_IOPAD(0x0bb4, MUX_MODE0) /* PINCTRL234 GPMC_D4 */
86
+
DM816X_IOPAD(0x0bb8, MUX_MODE0) /* PINCTRL234 GPMC_D5 */
87
+
DM816X_IOPAD(0x0bbc, MUX_MODE0) /* PINCTRL234 GPMC_D6 */
88
+
DM816X_IOPAD(0x0bc0, MUX_MODE0) /* PINCTRL234 GPMC_D7 */
89
+
DM816X_IOPAD(0x0bc4, MUX_MODE0) /* PINCTRL234 GPMC_D8 */
90
+
DM816X_IOPAD(0x0bc8, MUX_MODE0) /* PINCTRL234 GPMC_D9 */
91
+
DM816X_IOPAD(0x0bcc, MUX_MODE0) /* PINCTRL234 GPMC_D10 */
92
+
DM816X_IOPAD(0x0bd0, MUX_MODE0) /* PINCTRL234 GPMC_D11 */
93
+
DM816X_IOPAD(0x0bd4, MUX_MODE0) /* PINCTRL234 GPMC_D12 */
94
+
DM816X_IOPAD(0x0bd8, MUX_MODE0) /* PINCTRL234 GPMC_D13 */
95
+
DM816X_IOPAD(0x0bdc, MUX_MODE0) /* PINCTRL234 GPMC_D14 */
96
+
DM816X_IOPAD(0x0be0, MUX_MODE0) /* PINCTRL234 GPMC_D15 */
97
+
>;
98
+
};
71
99
};
72
100
73
101
&i2c1 {
···
118
90
119
91
&gpmc {
120
92
ranges = <0 0 0x04000000 0x01000000>; /* CS0: 16MB for NAND */
93
+
pinctrl-names = "default";
94
+
pinctrl-0 = <&nandflash_pins>;
121
95
122
96
nand@0,0 {
123
97
compatible = "ti,omap2-nand";
···
128
98
interrupt-parent = <&gpmc>;
129
99
interrupts = <0 IRQ_TYPE_NONE>, /* fifoevent */
130
100
<1 IRQ_TYPE_NONE>; /* termcount */
101
+
rb-gpios = <&gpmc 0 GPIO_ACTIVE_HIGH>; /* gpmc_wait0 */
131
102
#address-cells = <1>;
132
103
#size-cells = <1>;
133
104
ti,nand-ecc-opt = "bch8";
105
+
ti,elm-id = <&elm>;
134
106
nand-bus-width = <16>;
135
107
gpmc,device-width = <2>;
136
108
gpmc,sync-clk-ps = <0>;
···
196
164
vmmc-supply = <&vmmcsd_fixed>;
197
165
bus-width = <4>;
198
166
cd-gpios = <&gpio2 7 GPIO_ACTIVE_LOW>;
199
-
wp-gpios = <&gpio2 8 GPIO_ACTIVE_LOW>;
167
+
wp-gpios = <&gpio2 8 GPIO_ACTIVE_HIGH>;
200
168
};
201
169
202
170
/* At least dm8168-evm rev c won't support multipoint, later may */
+1
-1
arch/arm/boot/dts/dm816x.dtsi
+1
-1
arch/arm/boot/dts/dm816x.dtsi
+2
-2
arch/arm/boot/dts/dra71-evm.dts
+2
-2
arch/arm/boot/dts/dra71-evm.dts
···
190
190
ti,rx-internal-delay = <DP83867_RGMIIDCTL_2_25_NS>;
191
191
ti,tx-internal-delay = <DP83867_RGMIIDCTL_250_PS>;
192
192
ti,fifo-depth = <DP83867_PHYCR_FIFO_DEPTH_8_B_NIB>;
193
-
ti,impedance-control = <0x1f>;
193
+
ti,min-output-impedance;
194
194
};
195
195
196
196
dp83867_1: ethernet-phy@3 {
···
198
198
ti,rx-internal-delay = <DP83867_RGMIIDCTL_2_25_NS>;
199
199
ti,tx-internal-delay = <DP83867_RGMIIDCTL_250_PS>;
200
200
ti,fifo-depth = <DP83867_PHYCR_FIFO_DEPTH_8_B_NIB>;
201
-
ti,impedance-control = <0x1f>;
201
+
ti,min-output-impedance;
202
202
};
203
203
};
204
204
+3
arch/arm/boot/dts/exynos4.dtsi
+3
arch/arm/boot/dts/exynos4.dtsi
···
59
59
compatible = "samsung,exynos4210-audss-clock";
60
60
reg = <0x03810000 0x0C>;
61
61
#clock-cells = <1>;
62
+
clocks = <&clock CLK_FIN_PLL>, <&clock CLK_FOUT_EPLL>,
63
+
<&clock CLK_SCLK_AUDIO0>, <&clock CLK_SCLK_AUDIO0>;
64
+
clock-names = "pll_ref", "pll_in", "sclk_audio", "sclk_pcm_in";
62
65
};
63
66
64
67
i2s0: i2s@03830000 {
+2
-2
arch/arm/boot/dts/rk3288.dtsi
+2
-2
arch/arm/boot/dts/rk3288.dtsi
···
1126
1126
};
1127
1127
};
1128
1128
1129
-
gpu: mali@ffa30000 {
1130
-
compatible = "rockchip,rk3288-mali", "arm,mali-t760", "arm,mali-midgard";
1129
+
gpu: gpu@ffa30000 {
1130
+
compatible = "rockchip,rk3288-mali", "arm,mali-t760";
1131
1131
reg = <0xffa30000 0x10000>;
1132
1132
interrupts = <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>,
1133
1133
<GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>,
+9
-7
arch/arm/boot/dts/sun8i-a83t.dtsi
+9
-7
arch/arm/boot/dts/sun8i-a83t.dtsi
···
44
44
45
45
#include <dt-bindings/interrupt-controller/arm-gic.h>
46
46
47
+
#include <dt-bindings/clock/sun8i-a83t-ccu.h>
47
48
#include <dt-bindings/clock/sun8i-r-ccu.h>
49
+
#include <dt-bindings/reset/sun8i-a83t-ccu.h>
48
50
49
51
/ {
50
52
interrupt-parent = <&gic>;
···
177
175
compatible = "allwinner,sun8i-a83t-dma";
178
176
reg = <0x01c02000 0x1000>;
179
177
interrupts = <GIC_SPI 50 IRQ_TYPE_LEVEL_HIGH>;
180
-
clocks = <&ccu 21>;
181
-
resets = <&ccu 7>;
178
+
clocks = <&ccu CLK_BUS_DMA>;
179
+
resets = <&ccu RST_BUS_DMA>;
182
180
#dma-cells = <1>;
183
181
};
184
182
···
197
195
<GIC_SPI 17 IRQ_TYPE_LEVEL_HIGH>,
198
196
<GIC_SPI 100 IRQ_TYPE_LEVEL_HIGH>;
199
197
reg = <0x01c20800 0x400>;
200
-
clocks = <&ccu 45>, <&osc24M>, <&osc16Md512>;
198
+
clocks = <&ccu CLK_BUS_PIO>, <&osc24M>, <&osc16Md512>;
201
199
clock-names = "apb", "hosc", "losc";
202
200
gpio-controller;
203
201
interrupt-controller;
···
249
247
"allwinner,sun8i-h3-spdif";
250
248
reg = <0x01c21000 0x400>;
251
249
interrupts = <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>;
252
-
clocks = <&ccu 44>, <&ccu 76>;
253
-
resets = <&ccu 32>;
250
+
clocks = <&ccu CLK_BUS_SPDIF>, <&ccu CLK_SPDIF>;
251
+
resets = <&ccu RST_BUS_SPDIF>;
254
252
clock-names = "apb", "spdif";
255
253
dmas = <&dma 2>;
256
254
dma-names = "tx";
···
265
263
interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>;
266
264
reg-shift = <2>;
267
265
reg-io-width = <4>;
268
-
clocks = <&ccu 53>;
269
-
resets = <&ccu 40>;
266
+
clocks = <&ccu CLK_BUS_UART0>;
267
+
resets = <&ccu RST_BUS_UART0>;
270
268
status = "disabled";
271
269
};
272
270
+1
-1
arch/arm/boot/dts/sunxi-h3-h5.dtsi
+1
-1
arch/arm/boot/dts/sunxi-h3-h5.dtsi
···
394
394
emac: ethernet@1c30000 {
395
395
compatible = "allwinner,sun8i-h3-emac";
396
396
syscon = <&syscon>;
397
-
reg = <0x01c30000 0x104>;
397
+
reg = <0x01c30000 0x10000>;
398
398
interrupts = <GIC_SPI 82 IRQ_TYPE_LEVEL_HIGH>;
399
399
interrupt-names = "macirq";
400
400
resets = <&ccu RST_BUS_EMAC>;
+1
-1
arch/arm/boot/dts/tango4-vantage-1172.dts
+1
-1
arch/arm/boot/dts/tango4-vantage-1172.dts
+2
-2
arch/arm/mach-davinci/board-da850-evm.c
+2
-2
arch/arm/mach-davinci/board-da850-evm.c
···
1166
1166
1167
1167
#define TVP514X_STD_ALL (V4L2_STD_NTSC | V4L2_STD_PAL)
1168
1168
1169
-
static const struct vpif_input da850_ch0_inputs[] = {
1169
+
static struct vpif_input da850_ch0_inputs[] = {
1170
1170
{
1171
1171
.input = {
1172
1172
.index = 0,
···
1181
1181
},
1182
1182
};
1183
1183
1184
-
static const struct vpif_input da850_ch1_inputs[] = {
1184
+
static struct vpif_input da850_ch1_inputs[] = {
1185
1185
{
1186
1186
.input = {
1187
1187
.index = 0,
+9
arch/arm/mach-davinci/clock.c
+9
arch/arm/mach-davinci/clock.c
···
218
218
}
219
219
EXPORT_SYMBOL(clk_set_parent);
220
220
221
+
struct clk *clk_get_parent(struct clk *clk)
222
+
{
223
+
if (!clk)
224
+
return NULL;
225
+
226
+
return clk->parent;
227
+
}
228
+
EXPORT_SYMBOL(clk_get_parent);
229
+
221
230
int clk_register(struct clk *clk)
222
231
{
223
232
if (clk == NULL || IS_ERR(clk))
+20
arch/arm/mach-ep93xx/clock.c
+20
arch/arm/mach-ep93xx/clock.c
···
475
475
}
476
476
EXPORT_SYMBOL(clk_set_rate);
477
477
478
+
long clk_round_rate(struct clk *clk, unsigned long rate)
479
+
{
480
+
WARN_ON(clk);
481
+
return 0;
482
+
}
483
+
EXPORT_SYMBOL(clk_round_rate);
484
+
485
+
int clk_set_parent(struct clk *clk, struct clk *parent)
486
+
{
487
+
WARN_ON(clk);
488
+
return 0;
489
+
}
490
+
EXPORT_SYMBOL(clk_set_parent);
491
+
492
+
struct clk *clk_get_parent(struct clk *clk)
493
+
{
494
+
return clk->parent;
495
+
}
496
+
EXPORT_SYMBOL(clk_get_parent);
497
+
478
498
479
499
static char fclk_divisors[] = { 1, 2, 4, 8, 16, 1, 1, 1 };
480
500
static char hclk_divisors[] = { 1, 2, 4, 5, 6, 8, 16, 32 };
+26
-8
arch/arm/mach-ixp4xx/include/mach/io.h
+26
-8
arch/arm/mach-ixp4xx/include/mach/io.h
···
95
95
}
96
96
97
97
static inline void __indirect_writesb(volatile void __iomem *bus_addr,
98
-
const u8 *vaddr, int count)
98
+
const void *p, int count)
99
99
{
100
+
const u8 *vaddr = p;
101
+
100
102
while (count--)
101
103
writeb(*vaddr++, bus_addr);
102
104
}
···
120
118
}
121
119
122
120
static inline void __indirect_writesw(volatile void __iomem *bus_addr,
123
-
const u16 *vaddr, int count)
121
+
const void *p, int count)
124
122
{
123
+
const u16 *vaddr = p;
124
+
125
125
while (count--)
126
126
writew(*vaddr++, bus_addr);
127
127
}
···
141
137
}
142
138
143
139
static inline void __indirect_writesl(volatile void __iomem *bus_addr,
144
-
const u32 *vaddr, int count)
140
+
const void *p, int count)
145
141
{
142
+
const u32 *vaddr = p;
146
143
while (count--)
147
144
writel(*vaddr++, bus_addr);
148
145
}
···
165
160
}
166
161
167
162
static inline void __indirect_readsb(const volatile void __iomem *bus_addr,
168
-
u8 *vaddr, u32 count)
163
+
void *p, u32 count)
169
164
{
165
+
u8 *vaddr = p;
166
+
170
167
while (count--)
171
168
*vaddr++ = readb(bus_addr);
172
169
}
···
190
183
}
191
184
192
185
static inline void __indirect_readsw(const volatile void __iomem *bus_addr,
193
-
u16 *vaddr, u32 count)
186
+
void *p, u32 count)
194
187
{
188
+
u16 *vaddr = p;
189
+
195
190
while (count--)
196
191
*vaddr++ = readw(bus_addr);
197
192
}
···
213
204
}
214
205
215
206
static inline void __indirect_readsl(const volatile void __iomem *bus_addr,
216
-
u32 *vaddr, u32 count)
207
+
void *p, u32 count)
217
208
{
209
+
u32 *vaddr = p;
210
+
218
211
while (count--)
219
212
*vaddr++ = readl(bus_addr);
220
213
}
···
534
523
#endif
535
524
}
536
525
537
-
#define ioport_map(port, nr) ((void __iomem*)(port + PIO_OFFSET))
538
-
#define ioport_unmap(addr)
526
+
#define ioport_map(port, nr) ioport_map(port, nr)
527
+
static inline void __iomem *ioport_map(unsigned long port, unsigned int nr)
528
+
{
529
+
return ((void __iomem*)((port) + PIO_OFFSET));
530
+
}
531
+
#define ioport_unmap(addr) ioport_unmap(addr)
532
+
static inline void ioport_unmap(void __iomem *addr)
533
+
{
534
+
}
539
535
#endif /* CONFIG_PCI */
540
536
541
537
#endif /* __ASM_ARM_ARCH_IO_H */
+1
-1
arch/arm/mach-mmp/devices.c
+1
-1
arch/arm/mach-mmp/devices.c
+1
-1
arch/arm/mach-mvebu/platsmp.c
+1
-1
arch/arm/mach-mvebu/platsmp.c
+10
-2
arch/arm/mach-omap1/board-ams-delta.c
+10
-2
arch/arm/mach-omap1/board-ams-delta.c
···
510
510
static void modem_pm(struct uart_port *port, unsigned int state, unsigned old)
511
511
{
512
512
struct modem_private_data *priv = port->private_data;
513
+
int ret;
513
514
514
515
if (IS_ERR(priv->regulator))
515
516
return;
···
519
518
return;
520
519
521
520
if (state == 0)
522
-
regulator_enable(priv->regulator);
521
+
ret = regulator_enable(priv->regulator);
523
522
else if (old == 0)
524
-
regulator_disable(priv->regulator);
523
+
ret = regulator_disable(priv->regulator);
524
+
else
525
+
ret = 0;
526
+
527
+
if (ret)
528
+
dev_warn(port->dev,
529
+
"ams_delta modem_pm: failed to %sable regulator: %d\n",
530
+
state ? "dis" : "en", ret);
525
531
}
526
532
527
533
static struct plat_serial8250_port ams_delta_modem_ports[] = {
-4
arch/arm/mach-omap1/board-osk.c
-4
arch/arm/mach-omap1/board-osk.c
···
441
441
.chip_select = 0,
442
442
} };
443
443
444
-
#ifdef CONFIG_PM
445
444
static irqreturn_t
446
445
osk_mistral_wake_interrupt(int irq, void *ignored)
447
446
{
448
447
return IRQ_HANDLED;
449
448
}
450
-
#endif
451
449
452
450
static void __init osk_mistral_init(void)
453
451
{
···
513
515
514
516
gpio_direction_input(OMAP_MPUIO(2));
515
517
irq_set_irq_type(irq, IRQ_TYPE_EDGE_RISING);
516
-
#ifdef CONFIG_PM
517
518
/* share the IRQ in case someone wants to use the
518
519
* button for more than wakeup from system sleep.
519
520
*/
···
526
529
ret);
527
530
} else
528
531
enable_irq_wake(irq);
529
-
#endif
530
532
} else
531
533
printk(KERN_ERR "OSK+Mistral: wakeup button is awol\n");
532
534
+1
-1
arch/arm/mach-omap2/board-generic.c
+1
-1
arch/arm/mach-omap2/board-generic.c
+1
-1
arch/arm/mach-omap2/io.c
+1
-1
arch/arm/mach-omap2/io.c
-1
arch/arm/mach-omap2/pm34xx.c
-1
arch/arm/mach-omap2/pm34xx.c
+1
-6
arch/arm/mach-omap2/prm3xxx.c
+1
-6
arch/arm/mach-omap2/prm3xxx.c
···
692
692
{
693
693
struct device_node *np;
694
694
int irq_num;
695
-
int ret;
696
695
697
696
if (!(prm_features & PRM_HAS_IO_WAKEUP))
698
697
return 0;
···
711
712
}
712
713
713
714
omap3xxx_prm_enable_io_wakeup();
714
-
ret = omap_prcm_register_chain_handler(&omap3_prcm_irq_setup);
715
-
if (!ret)
716
-
irq_set_status_flags(omap_prcm_event_to_irq("io"),
717
-
IRQ_NOAUTOEN);
718
715
719
-
return ret;
716
+
return omap_prcm_register_chain_handler(&omap3_prcm_irq_setup);
720
717
}
721
718
722
719
static void __exit omap3xxx_prm_exit(void)
+55
arch/arm/mach-omap2/prm44xx.c
+55
arch/arm/mach-omap2/prm44xx.c
···
337
337
}
338
338
339
339
/**
340
+
* omap44xx_prm_enable_io_wakeup - enable wakeup events from I/O wakeup latches
341
+
*
342
+
* Activates the I/O wakeup event latches and allows events logged by
343
+
* those latches to signal a wakeup event to the PRCM. For I/O wakeups
344
+
* to occur, WAKEUPENABLE bits must be set in the pad mux registers, and
345
+
* omap44xx_prm_reconfigure_io_chain() must be called. No return value.
346
+
*/
347
+
static void __init omap44xx_prm_enable_io_wakeup(void)
348
+
{
349
+
s32 inst = omap4_prmst_get_prm_dev_inst();
350
+
351
+
if (inst == PRM_INSTANCE_UNKNOWN)
352
+
return;
353
+
354
+
omap4_prm_rmw_inst_reg_bits(OMAP4430_GLOBAL_WUEN_MASK,
355
+
OMAP4430_GLOBAL_WUEN_MASK,
356
+
inst,
357
+
omap4_prcm_irq_setup.pm_ctrl);
358
+
}
359
+
360
+
/**
340
361
* omap44xx_prm_read_reset_sources - return the last SoC reset source
341
362
*
342
363
* Return a u32 representing the last reset sources of the SoC. The
···
689
668
.pwrdm_has_voltdm = omap4_check_vcvp,
690
669
};
691
670
671
+
static int omap44xx_prm_late_init(void);
672
+
692
673
/*
693
674
* XXX document
694
675
*/
···
698
675
.read_reset_sources = &omap44xx_prm_read_reset_sources,
699
676
.was_any_context_lost_old = &omap44xx_prm_was_any_context_lost_old,
700
677
.clear_context_loss_flags_old = &omap44xx_prm_clear_context_loss_flags_old,
678
+
.late_init = &omap44xx_prm_late_init,
701
679
.assert_hardreset = omap4_prminst_assert_hardreset,
702
680
.deassert_hardreset = omap4_prminst_deassert_hardreset,
703
681
.is_hardreset_asserted = omap4_prminst_is_hardreset_asserted,
···
733
709
}
734
710
735
711
return prm_register(&omap44xx_prm_ll_data);
712
+
}
713
+
714
+
static int omap44xx_prm_late_init(void)
715
+
{
716
+
int irq_num;
717
+
718
+
if (!(prm_features & PRM_HAS_IO_WAKEUP))
719
+
return 0;
720
+
721
+
irq_num = of_irq_get(prm_init_data->np, 0);
722
+
/*
723
+
* Already have OMAP4 IRQ num. For all other platforms, we need
724
+
* IRQ numbers from DT
725
+
*/
726
+
if (irq_num < 0 && !(prm_init_data->flags & PRM_IRQ_DEFAULT)) {
727
+
if (irq_num == -EPROBE_DEFER)
728
+
return irq_num;
729
+
730
+
/* Have nothing to do */
731
+
return 0;
732
+
}
733
+
734
+
/* Once OMAP4 DT is filled as well */
735
+
if (irq_num >= 0) {
736
+
omap4_prcm_irq_setup.irq = irq_num;
737
+
omap4_prcm_irq_setup.xlate_irq = NULL;
738
+
}
739
+
740
+
omap44xx_prm_enable_io_wakeup();
741
+
742
+
return omap_prcm_register_chain_handler(&omap4_prcm_irq_setup);
736
743
}
737
744
738
745
static void __exit omap44xx_prm_exit(void)
+1
-1
arch/arm/mach-prima2/common.c
+1
-1
arch/arm/mach-prima2/common.c
+1
arch/arm/mach-pxa/Kconfig
+1
arch/arm/mach-pxa/Kconfig
+7
-3
arch/arm/mach-pxa/include/mach/mtd-xip.h
+7
-3
arch/arm/mach-pxa/include/mach/mtd-xip.h
···
17
17
18
18
#include <mach/regs-ost.h>
19
19
20
-
#define xip_irqpending() (ICIP & ICMR)
20
+
/* restored July 2017, this did not build since 2011! */
21
+
22
+
#define ICIP io_p2v(0x40d00000)
23
+
#define ICMR io_p2v(0x40d00004)
24
+
#define xip_irqpending() (readl(ICIP) & readl(ICMR))
21
25
22
26
/* we sample OSCR and convert desired delta to usec (1/4 ~= 1000000/3686400) */
23
-
#define xip_currtime() (OSCR)
24
-
#define xip_elapsed_since(x) (signed)((OSCR - (x)) / 4)
27
+
#define xip_currtime() readl(OSCR)
28
+
#define xip_elapsed_since(x) (signed)((readl(OSCR) - (x)) / 4)
25
29
26
30
/*
27
31
* xip_cpu_idle() is used when waiting for a delay equal or larger than
+2
-2
arch/arm/mach-rpc/include/mach/hardware.h
+2
-2
arch/arm/mach-rpc/include/mach/hardware.h
···
25
25
* *_SIZE is the size of the region
26
26
* *_BASE is the virtual address
27
27
*/
28
-
#define RAM_SIZE 0x10000000
29
-
#define RAM_START 0x10000000
28
+
#define RPC_RAM_SIZE 0x10000000
29
+
#define RPC_RAM_START 0x10000000
30
30
31
31
#define EASI_SIZE 0x08000000 /* EASI I/O */
32
32
#define EASI_START 0x08000000
+25
arch/arm/mach-sa1100/clock.c
+25
arch/arm/mach-sa1100/clock.c
···
35
35
36
36
static DEFINE_SPINLOCK(clocks_lock);
37
37
38
+
/* Dummy clk routine to build generic kernel parts that may be using them */
39
+
long clk_round_rate(struct clk *clk, unsigned long rate)
40
+
{
41
+
return clk_get_rate(clk);
42
+
}
43
+
EXPORT_SYMBOL(clk_round_rate);
44
+
45
+
int clk_set_rate(struct clk *clk, unsigned long rate)
46
+
{
47
+
return 0;
48
+
}
49
+
EXPORT_SYMBOL(clk_set_rate);
50
+
51
+
int clk_set_parent(struct clk *clk, struct clk *parent)
52
+
{
53
+
return 0;
54
+
}
55
+
EXPORT_SYMBOL(clk_set_parent);
56
+
57
+
struct clk *clk_get_parent(struct clk *clk)
58
+
{
59
+
return NULL;
60
+
}
61
+
EXPORT_SYMBOL(clk_get_parent);
62
+
38
63
static void clk_gpio27_enable(struct clk *clk)
39
64
{
40
65
/*
+2
-2
arch/arm/mach-sa1100/include/mach/mtd-xip.h
+2
-2
arch/arm/mach-sa1100/include/mach/mtd-xip.h
···
20
20
#define xip_irqpending() (ICIP & ICMR)
21
21
22
22
/* we sample OSCR and convert desired delta to usec (1/4 ~= 1000000/3686400) */
23
-
#define xip_currtime() (OSCR)
24
-
#define xip_elapsed_since(x) (signed)((OSCR - (x)) / 4)
23
+
#define xip_currtime() readl_relaxed(OSCR)
24
+
#define xip_elapsed_since(x) (signed)((readl_relaxed(OSCR) - (x)) / 4)
25
25
26
26
#endif /* __ARCH_SA1100_MTD_XIP_H__ */
+5
-1
arch/arm/mach-shmobile/regulator-quirk-rcar-gen2.c
+5
-1
arch/arm/mach-shmobile/regulator-quirk-rcar-gen2.c
···
67
67
{
68
68
struct device *dev = data;
69
69
struct i2c_client *client;
70
+
static bool done;
70
71
u32 mon;
72
+
73
+
if (done)
74
+
return 0;
71
75
72
76
mon = ioread32(irqc + IRQC_MONITOR);
73
77
dev_dbg(dev, "%s: %ld, IRQC_MONITOR = 0x%x\n", __func__, action, mon);
···
103
99
remove:
104
100
dev_info(dev, "IRQ2 is not asserted, removing quirk\n");
105
101
106
-
bus_unregister_notifier(&i2c_bus_type, nb);
102
+
done = true;
107
103
iounmap(irqc);
108
104
return 0;
109
105
}
+29
arch/arm/mach-w90x900/clock.c
+29
arch/arm/mach-w90x900/clock.c
···
93
93
94
94
__raw_writel(clken, W90X900_VA_CLKPWR + SUBCLK);
95
95
}
96
+
97
+
/* dummy functions, should not be called */
98
+
long clk_round_rate(struct clk *clk, unsigned long rate)
99
+
{
100
+
WARN_ON(clk);
101
+
return 0;
102
+
}
103
+
EXPORT_SYMBOL(clk_round_rate);
104
+
105
+
int clk_set_rate(struct clk *clk, unsigned long rate)
106
+
{
107
+
WARN_ON(clk);
108
+
return 0;
109
+
}
110
+
EXPORT_SYMBOL(clk_set_rate);
111
+
112
+
int clk_set_parent(struct clk *clk, struct clk *parent)
113
+
{
114
+
WARN_ON(clk);
115
+
return 0;
116
+
}
117
+
EXPORT_SYMBOL(clk_set_parent);
118
+
119
+
struct clk *clk_get_parent(struct clk *clk)
120
+
{
121
+
WARN_ON(clk);
122
+
return NULL;
123
+
}
124
+
EXPORT_SYMBOL(clk_get_parent);
+1
-1
arch/arm64/boot/dts/allwinner/sun50i-a64.dtsi
+1
-1
arch/arm64/boot/dts/allwinner/sun50i-a64.dtsi
···
452
452
emac: ethernet@1c30000 {
453
453
compatible = "allwinner,sun50i-a64-emac";
454
454
syscon = <&syscon>;
455
-
reg = <0x01c30000 0x100>;
455
+
reg = <0x01c30000 0x10000>;
456
456
interrupts = <GIC_SPI 82 IRQ_TYPE_LEVEL_HIGH>;
457
457
interrupt-names = "macirq";
458
458
resets = <&ccu RST_BUS_EMAC>;
+1
-1
arch/arm64/boot/dts/amlogic/meson-gx.dtsi
+1
-1
arch/arm64/boot/dts/amlogic/meson-gx.dtsi
+2
-2
arch/arm64/boot/dts/amlogic/meson-gxl-s905x-khadas-vim.dts
+2
-2
arch/arm64/boot/dts/amlogic/meson-gxl-s905x-khadas-vim.dts
···
109
109
status = "okay";
110
110
pinctrl-0 = <&pwm_ao_a_3_pins>, <&pwm_ao_b_pins>;
111
111
pinctrl-names = "default";
112
-
clocks = <&clkc CLKID_FCLK_DIV4>;
113
-
clock-names = "clkin0";
112
+
clocks = <&xtal> , <&xtal>;
113
+
clock-names = "clkin0", "clkin1" ;
114
114
};
115
115
116
116
&pwm_ef {
+91
-12
arch/arm64/boot/dts/amlogic/meson-gxl-s905x-libretech-cc.dts
+91
-12
arch/arm64/boot/dts/amlogic/meson-gxl-s905x-libretech-cc.dts
···
10
10
11
11
#include <dt-bindings/input/input.h>
12
12
13
-
#include "meson-gxl-s905x-p212.dtsi"
13
+
#include "meson-gxl-s905x.dtsi"
14
14
15
15
/ {
16
16
compatible = "libretech,cc", "amlogic,s905x", "amlogic,meson-gxl";
17
17
model = "Libre Technology CC";
18
+
19
+
aliases {
20
+
serial0 = &uart_AO;
21
+
};
22
+
23
+
chosen {
24
+
stdout-path = "serial0:115200n8";
25
+
};
18
26
19
27
cvbs-connector {
20
28
compatible = "composite-video-connector";
···
32
24
remote-endpoint = <&cvbs_vdac_out>;
33
25
};
34
26
};
27
+
};
28
+
29
+
emmc_pwrseq: emmc-pwrseq {
30
+
compatible = "mmc-pwrseq-emmc";
31
+
reset-gpios = <&gpio BOOT_9 GPIO_ACTIVE_LOW>;
35
32
};
36
33
37
34
hdmi-connector {
···
66
53
linux,default-trigger = "heartbeat";
67
54
};
68
55
};
56
+
57
+
memory@0 {
58
+
device_type = "memory";
59
+
reg = <0x0 0x0 0x0 0x80000000>;
60
+
};
61
+
62
+
vcc_3v3: regulator-vcc_3v3 {
63
+
compatible = "regulator-fixed";
64
+
regulator-name = "VCC_3V3";
65
+
regulator-min-microvolt = <3300000>;
66
+
regulator-max-microvolt = <3300000>;
67
+
};
68
+
69
+
vcc_card: regulator-vcc-card {
70
+
compatible = "regulator-gpio";
71
+
72
+
regulator-name = "VCC_CARD";
73
+
regulator-min-microvolt = <1800000>;
74
+
regulator-max-microvolt = <3300000>;
75
+
76
+
gpios = <&gpio_ao GPIOAO_3 GPIO_ACTIVE_HIGH>;
77
+
gpios-states = <0>;
78
+
79
+
states = <3300000 0>,
80
+
<1800000 1>;
81
+
};
82
+
83
+
vddio_boot: regulator-vddio_boot {
84
+
compatible = "regulator-fixed";
85
+
regulator-name = "VDDIO_BOOT";
86
+
regulator-min-microvolt = <3300000>;
87
+
regulator-max-microvolt = <3300000>;
88
+
};
69
89
};
70
90
71
91
&cvbs_vdac_port {
72
92
cvbs_vdac_out: endpoint {
73
93
remote-endpoint = <&cvbs_connector_in>;
74
94
};
95
+
};
96
+
97
+
ðmac {
98
+
status = "okay";
99
+
};
100
+
101
+
&ir {
102
+
status = "okay";
103
+
pinctrl-0 = <&remote_input_ao_pins>;
104
+
pinctrl-names = "default";
75
105
};
76
106
77
107
&hdmi_tx {
···
129
73
};
130
74
};
131
75
132
-
/*
133
-
* The following devices exists but are exposed on the general
134
-
* purpose GPIO header. End user may well decide to use those pins
135
-
* for another purpose
136
-
*/
76
+
/* SD card */
77
+
&sd_emmc_b {
78
+
status = "okay";
79
+
pinctrl-0 = <&sdcard_pins>;
80
+
pinctrl-names = "default";
137
81
138
-
&sd_emmc_a {
139
-
status = "disabled";
82
+
bus-width = <4>;
83
+
cap-sd-highspeed;
84
+
max-frequency = <100000000>;
85
+
disable-wp;
86
+
87
+
cd-gpios = <&gpio CARD_6 GPIO_ACTIVE_HIGH>;
88
+
cd-inverted;
89
+
90
+
vmmc-supply = <&vcc_3v3>;
91
+
vqmmc-supply = <&vcc_card>;
140
92
};
141
93
142
-
&uart_A {
143
-
status = "disabled";
94
+
/* eMMC */
95
+
&sd_emmc_c {
96
+
status = "okay";
97
+
pinctrl-0 = <&emmc_pins>;
98
+
pinctrl-names = "default";
99
+
100
+
bus-width = <8>;
101
+
cap-mmc-highspeed;
102
+
max-frequency = <50000000>;
103
+
non-removable;
104
+
disable-wp;
105
+
106
+
mmc-pwrseq = <&emmc_pwrseq>;
107
+
vmmc-supply = <&vcc_3v3>;
108
+
vqmmc-supply = <&vddio_boot>;
144
109
};
145
110
146
-
&wifi32k {
147
-
status = "disabled";
111
+
&uart_AO {
112
+
status = "okay";
113
+
pinctrl-0 = <&uart_ao_a_pins>;
114
+
pinctrl-names = "default";
148
115
};
+1
-1
arch/arm64/boot/dts/marvell/armada-37xx.dtsi
+1
-1
arch/arm64/boot/dts/marvell/armada-37xx.dtsi
+1
arch/arm64/boot/dts/marvell/armada-cp110-master.dtsi
+1
arch/arm64/boot/dts/marvell/armada-cp110-master.dtsi
+2
-1
arch/arm64/boot/dts/marvell/armada-cp110-slave.dtsi
+2
-1
arch/arm64/boot/dts/marvell/armada-cp110-slave.dtsi
···
64
64
compatible = "marvell,armada-8k-rtc";
65
65
reg = <0x284000 0x20>, <0x284080 0x24>;
66
66
reg-names = "rtc", "rtc-soc";
67
-
interrupts = <GIC_SPI 71 IRQ_TYPE_LEVEL_HIGH>;
67
+
interrupts = <ICU_GRP_NSR 77 IRQ_TYPE_LEVEL_HIGH>;
68
68
};
69
69
70
70
cps_ethernet: ethernet@0 {
···
261
261
interrupt-names = "mem", "ring0", "ring1",
262
262
"ring2", "ring3", "eip";
263
263
clocks = <&cps_clk 1 26>;
264
+
dma-coherent;
264
265
/*
265
266
* The cryptographic engine found on the cp110
266
267
* master is enabled by default at the SoC
+1
-1
arch/arm64/boot/dts/renesas/salvator-common.dtsi
+1
-1
arch/arm64/boot/dts/renesas/salvator-common.dtsi
+1
-1
arch/arm64/boot/dts/renesas/ulcb.dtsi
+1
-1
arch/arm64/boot/dts/renesas/ulcb.dtsi
+1
arch/arm64/configs/defconfig
+1
arch/arm64/configs/defconfig
+14
drivers/bus/uniphier-system-bus.c
+14
drivers/bus/uniphier-system-bus.c
···
256
256
257
257
uniphier_system_bus_set_reg(priv);
258
258
259
+
platform_set_drvdata(pdev, priv);
260
+
259
261
/* Now, the bus is configured. Populate platform_devices below it */
260
262
return of_platform_default_populate(dev->of_node, NULL, dev);
261
263
}
264
+
265
+
static int __maybe_unused uniphier_system_bus_resume(struct device *dev)
266
+
{
267
+
uniphier_system_bus_set_reg(dev_get_drvdata(dev));
268
+
269
+
return 0;
270
+
}
271
+
272
+
static const struct dev_pm_ops uniphier_system_bus_pm_ops = {
273
+
SET_SYSTEM_SLEEP_PM_OPS(NULL, uniphier_system_bus_resume)
274
+
};
262
275
263
276
static const struct of_device_id uniphier_system_bus_match[] = {
264
277
{ .compatible = "socionext,uniphier-system-bus" },
···
284
271
.driver = {
285
272
.name = "uniphier-system-bus",
286
273
.of_match_table = uniphier_system_bus_match,
274
+
.pm = &uniphier_system_bus_pm_ops,
287
275
},
288
276
};
289
277
module_platform_driver(uniphier_system_bus_driver);