Linux kernel mirror (for testing)
git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git
kernel
os
linux
PCI: Update CXL DVSEC definitions
CXL DVSEC definitions were recently moved into uapi/pci_regs.h, but the
newly added macros do not follow the file's existing naming conventions.
The current format uses CXL_DVSEC_XYZ, while the new CXL entries must
instead use the PCI_DVSEC_CXL_XYZ prefix to match the conventions already
established in pci_regs.h.
The new CXL DVSEC macros also introduce _MASK and _OFFSET suffixes, which
are not used anywhere else in the file. These suffixes lengthen the
identifiers and reduce readability. Remove _MASK and _OFFSET from the
recently added definitions.
Additionally, remove PCI_DVSEC_HEADER1_LENGTH, as it duplicates the existing
PCI_DVSEC_HEADER1_LEN() macro.
Update all existing references to use the new macro names.
Finally, update the inline documentation to reference the latest revision
of the CXL specification.
Signed-off-by: Terry Bowman <terry.bowman@amd.com>
Reviewed-by: Dan Williams <dan.j.williams@intel.com>
Acked-by: Bjorn Helgaas <bhelgaas@google.com>
Link: https://patch.msgid.link/20260114182055.46029-3-terry.bowman@amd.com
Signed-off-by: Dan Williams <dan.j.williams@intel.com>
Signed-off-by: Dave Jiang <dave.jiang@intel.com>
authored by
Terry Bowman
and committed by
Dave Jiang
6612bd9f
0f7afd80
+76
-82
+29
-29
drivers/cxl/core/pci.c
+29
-29
drivers/cxl/core/pci.c
···
86
86
i = 1;
87
87
do {
88
88
rc = pci_read_config_dword(pdev,
89
-
d + CXL_DVSEC_RANGE_SIZE_LOW(id),
89
+
d + PCI_DVSEC_CXL_RANGE_SIZE_LOW(id),
90
90
&temp);
91
91
if (rc)
92
92
return rc;
93
93
94
-
valid = FIELD_GET(CXL_DVSEC_MEM_INFO_VALID, temp);
94
+
valid = FIELD_GET(PCI_DVSEC_CXL_MEM_INFO_VALID, temp);
95
95
if (valid)
96
96
break;
97
97
msleep(1000);
···
121
121
/* Check MEM ACTIVE bit, up to 60s timeout by default */
122
122
for (i = media_ready_timeout; i; i--) {
123
123
rc = pci_read_config_dword(
124
-
pdev, d + CXL_DVSEC_RANGE_SIZE_LOW(id), &temp);
124
+
pdev, d + PCI_DVSEC_CXL_RANGE_SIZE_LOW(id), &temp);
125
125
if (rc)
126
126
return rc;
127
127
128
-
active = FIELD_GET(CXL_DVSEC_MEM_ACTIVE, temp);
128
+
active = FIELD_GET(PCI_DVSEC_CXL_MEM_ACTIVE, temp);
129
129
if (active)
130
130
break;
131
131
msleep(1000);
···
154
154
u16 cap;
155
155
156
156
rc = pci_read_config_word(pdev,
157
-
d + CXL_DVSEC_CAP_OFFSET, &cap);
157
+
d + PCI_DVSEC_CXL_CAP, &cap);
158
158
if (rc)
159
159
return rc;
160
160
161
-
hdm_count = FIELD_GET(CXL_DVSEC_HDM_COUNT_MASK, cap);
161
+
hdm_count = FIELD_GET(PCI_DVSEC_CXL_HDM_COUNT, cap);
162
162
for (i = 0; i < hdm_count; i++) {
163
163
rc = cxl_dvsec_mem_range_valid(cxlds, i);
164
164
if (rc)
···
186
186
u16 ctrl;
187
187
int rc;
188
188
189
-
rc = pci_read_config_word(pdev, d + CXL_DVSEC_CTRL_OFFSET, &ctrl);
189
+
rc = pci_read_config_word(pdev, d + PCI_DVSEC_CXL_CTRL, &ctrl);
190
190
if (rc < 0)
191
191
return rc;
192
192
193
-
if ((ctrl & CXL_DVSEC_MEM_ENABLE) == val)
193
+
if ((ctrl & PCI_DVSEC_CXL_MEM_ENABLE) == val)
194
194
return 1;
195
-
ctrl &= ~CXL_DVSEC_MEM_ENABLE;
195
+
ctrl &= ~PCI_DVSEC_CXL_MEM_ENABLE;
196
196
ctrl |= val;
197
197
198
-
rc = pci_write_config_word(pdev, d + CXL_DVSEC_CTRL_OFFSET, ctrl);
198
+
rc = pci_write_config_word(pdev, d + PCI_DVSEC_CXL_CTRL, ctrl);
199
199
if (rc < 0)
200
200
return rc;
201
201
···
211
211
{
212
212
int rc;
213
213
214
-
rc = cxl_set_mem_enable(cxlds, CXL_DVSEC_MEM_ENABLE);
214
+
rc = cxl_set_mem_enable(cxlds, PCI_DVSEC_CXL_MEM_ENABLE);
215
215
if (rc < 0)
216
216
return rc;
217
217
if (rc > 0)
···
273
273
return -ENXIO;
274
274
}
275
275
276
-
rc = pci_read_config_word(pdev, d + CXL_DVSEC_CAP_OFFSET, &cap);
276
+
rc = pci_read_config_word(pdev, d + PCI_DVSEC_CXL_CAP, &cap);
277
277
if (rc)
278
278
return rc;
279
279
280
-
if (!(cap & CXL_DVSEC_MEM_CAPABLE)) {
280
+
if (!(cap & PCI_DVSEC_CXL_MEM_CAPABLE)) {
281
281
dev_dbg(dev, "Not MEM Capable\n");
282
282
return -ENXIO;
283
283
}
···
288
288
* driver is for a spec defined class code which must be CXL.mem
289
289
* capable, there is no point in continuing to enable CXL.mem.
290
290
*/
291
-
hdm_count = FIELD_GET(CXL_DVSEC_HDM_COUNT_MASK, cap);
291
+
hdm_count = FIELD_GET(PCI_DVSEC_CXL_HDM_COUNT, cap);
292
292
if (!hdm_count || hdm_count > 2)
293
293
return -EINVAL;
294
294
···
297
297
* disabled, and they will remain moot after the HDM Decoder
298
298
* capability is enabled.
299
299
*/
300
-
rc = pci_read_config_word(pdev, d + CXL_DVSEC_CTRL_OFFSET, &ctrl);
300
+
rc = pci_read_config_word(pdev, d + PCI_DVSEC_CXL_CTRL, &ctrl);
301
301
if (rc)
302
302
return rc;
303
303
304
-
info->mem_enabled = FIELD_GET(CXL_DVSEC_MEM_ENABLE, ctrl);
304
+
info->mem_enabled = FIELD_GET(PCI_DVSEC_CXL_MEM_ENABLE, ctrl);
305
305
if (!info->mem_enabled)
306
306
return 0;
307
307
···
314
314
return rc;
315
315
316
316
rc = pci_read_config_dword(
317
-
pdev, d + CXL_DVSEC_RANGE_SIZE_HIGH(i), &temp);
317
+
pdev, d + PCI_DVSEC_CXL_RANGE_SIZE_HIGH(i), &temp);
318
318
if (rc)
319
319
return rc;
320
320
321
321
size = (u64)temp << 32;
322
322
323
323
rc = pci_read_config_dword(
324
-
pdev, d + CXL_DVSEC_RANGE_SIZE_LOW(i), &temp);
324
+
pdev, d + PCI_DVSEC_CXL_RANGE_SIZE_LOW(i), &temp);
325
325
if (rc)
326
326
return rc;
327
327
328
-
size |= temp & CXL_DVSEC_MEM_SIZE_LOW_MASK;
328
+
size |= temp & PCI_DVSEC_CXL_MEM_SIZE_LOW;
329
329
if (!size) {
330
330
continue;
331
331
}
332
332
333
333
rc = pci_read_config_dword(
334
-
pdev, d + CXL_DVSEC_RANGE_BASE_HIGH(i), &temp);
334
+
pdev, d + PCI_DVSEC_CXL_RANGE_BASE_HIGH(i), &temp);
335
335
if (rc)
336
336
return rc;
337
337
338
338
base = (u64)temp << 32;
339
339
340
340
rc = pci_read_config_dword(
341
-
pdev, d + CXL_DVSEC_RANGE_BASE_LOW(i), &temp);
341
+
pdev, d + PCI_DVSEC_CXL_RANGE_BASE_LOW(i), &temp);
342
342
if (rc)
343
343
return rc;
344
344
345
-
base |= temp & CXL_DVSEC_MEM_BASE_LOW_MASK;
345
+
base |= temp & PCI_DVSEC_CXL_MEM_BASE_LOW;
346
346
347
347
info->dvsec_range[ranges++] = (struct range) {
348
348
.start = base,
···
1068
1068
is_port = false;
1069
1069
1070
1070
dvsec = pci_find_dvsec_capability(pdev, PCI_VENDOR_ID_CXL,
1071
-
is_port ? CXL_DVSEC_PORT_GPF : CXL_DVSEC_DEVICE_GPF);
1071
+
is_port ? PCI_DVSEC_CXL_PORT_GPF : PCI_DVSEC_CXL_DEVICE_GPF);
1072
1072
if (!dvsec)
1073
1073
dev_warn(dev, "%s GPF DVSEC not present\n",
1074
1074
is_port ? "Port" : "Device");
···
1084
1084
1085
1085
switch (phase) {
1086
1086
case 1:
1087
-
offset = CXL_DVSEC_PORT_GPF_PHASE_1_CONTROL_OFFSET;
1088
-
base = CXL_DVSEC_PORT_GPF_PHASE_1_TMO_BASE_MASK;
1089
-
scale = CXL_DVSEC_PORT_GPF_PHASE_1_TMO_SCALE_MASK;
1087
+
offset = PCI_DVSEC_CXL_PORT_GPF_PHASE_1_CONTROL;
1088
+
base = PCI_DVSEC_CXL_PORT_GPF_PHASE_1_TMO_BASE;
1089
+
scale = PCI_DVSEC_CXL_PORT_GPF_PHASE_1_TMO_SCALE;
1090
1090
break;
1091
1091
case 2:
1092
-
offset = CXL_DVSEC_PORT_GPF_PHASE_2_CONTROL_OFFSET;
1093
-
base = CXL_DVSEC_PORT_GPF_PHASE_2_TMO_BASE_MASK;
1094
-
scale = CXL_DVSEC_PORT_GPF_PHASE_2_TMO_SCALE_MASK;
1092
+
offset = PCI_DVSEC_CXL_PORT_GPF_PHASE_2_CONTROL;
1093
+
base = PCI_DVSEC_CXL_PORT_GPF_PHASE_2_TMO_BASE;
1094
+
scale = PCI_DVSEC_CXL_PORT_GPF_PHASE_2_TMO_SCALE;
1095
1095
break;
1096
1096
default:
1097
1097
return -EINVAL;
+7
-7
drivers/cxl/core/regs.c
+7
-7
drivers/cxl/core/regs.c
···
271
271
static bool cxl_decode_regblock(struct pci_dev *pdev, u32 reg_lo, u32 reg_hi,
272
272
struct cxl_register_map *map)
273
273
{
274
-
u8 reg_type = FIELD_GET(CXL_DVSEC_REG_LOCATOR_BLOCK_ID_MASK, reg_lo);
275
-
int bar = FIELD_GET(CXL_DVSEC_REG_LOCATOR_BIR_MASK, reg_lo);
274
+
u8 reg_type = FIELD_GET(PCI_DVSEC_CXL_REG_LOCATOR_BLOCK_ID, reg_lo);
275
+
int bar = FIELD_GET(PCI_DVSEC_CXL_REG_LOCATOR_BIR, reg_lo);
276
276
u64 offset = ((u64)reg_hi << 32) |
277
-
(reg_lo & CXL_DVSEC_REG_LOCATOR_BLOCK_OFF_LOW_MASK);
277
+
(reg_lo & PCI_DVSEC_CXL_REG_LOCATOR_BLOCK_OFF_LOW);
278
278
279
279
if (offset > pci_resource_len(pdev, bar)) {
280
280
dev_warn(&pdev->dev,
···
311
311
};
312
312
313
313
regloc = pci_find_dvsec_capability(pdev, PCI_VENDOR_ID_CXL,
314
-
CXL_DVSEC_REG_LOCATOR);
314
+
PCI_DVSEC_CXL_REG_LOCATOR);
315
315
if (!regloc)
316
316
return -ENXIO;
317
317
318
318
pci_read_config_dword(pdev, regloc + PCI_DVSEC_HEADER1, ®loc_size);
319
-
regloc_size = FIELD_GET(PCI_DVSEC_HEADER1_LENGTH_MASK, regloc_size);
319
+
regloc_size = PCI_DVSEC_HEADER1_LEN(regloc_size);
320
320
321
-
regloc += CXL_DVSEC_REG_LOCATOR_BLOCK1_OFFSET;
322
-
regblocks = (regloc_size - CXL_DVSEC_REG_LOCATOR_BLOCK1_OFFSET) / 8;
321
+
regloc += PCI_DVSEC_CXL_REG_LOCATOR_BLOCK1;
322
+
regblocks = (regloc_size - PCI_DVSEC_CXL_REG_LOCATOR_BLOCK1) / 8;
323
323
324
324
for (i = 0; i < regblocks; i++, regloc += 8) {
325
325
u32 reg_lo, reg_hi;
+1
-1
drivers/cxl/pci.c
+1
-1
drivers/cxl/pci.c
···
933
933
cxlds->rcd = is_cxl_restricted(pdev);
934
934
cxlds->serial = pci_get_dsn(pdev);
935
935
cxlds->cxl_dvsec = pci_find_dvsec_capability(
936
-
pdev, PCI_VENDOR_ID_CXL, CXL_DVSEC_PCIE_DEVICE);
936
+
pdev, PCI_VENDOR_ID_CXL, PCI_DVSEC_CXL_DEVICE);
937
937
if (!cxlds->cxl_dvsec)
938
938
dev_warn(&pdev->dev,
939
939
"Device DVSEC not present, skip CXL.mem init\n");
+39
-45
include/uapi/linux/pci_regs.h
+39
-45
include/uapi/linux/pci_regs.h
···
1333
1333
#define PCI_IDE_SEL_ADDR_3(x) (28 + (x) * PCI_IDE_SEL_ADDR_BLOCK_SIZE)
1334
1334
#define PCI_IDE_SEL_BLOCK_SIZE(nr_assoc) (20 + PCI_IDE_SEL_ADDR_BLOCK_SIZE * (nr_assoc))
1335
1335
1336
-
/* Compute Express Link (CXL r3.1, sec 8.1.5) */
1337
-
#define PCI_DVSEC_CXL_PORT 3
1338
-
#define PCI_DVSEC_CXL_PORT_CTL 0x0c
1339
-
#define PCI_DVSEC_CXL_PORT_CTL_UNMASK_SBR 0x00000001
1340
-
1341
1336
/*
1342
-
* Compute Express Link (CXL r3.2, sec 8.1)
1337
+
* Compute Express Link (CXL r4.0, sec 8.1)
1343
1338
*
1344
1339
* Note that CXL DVSEC id 3 and 7 to be ignored when the CXL link state
1345
-
* is "disconnected" (CXL r3.2, sec 9.12.3). Re-enumerate these
1340
+
* is "disconnected" (CXL r4.0, sec 9.12.3). Re-enumerate these
1346
1341
* registers on downstream link-up events.
1347
1342
*/
1348
-
#define PCI_DVSEC_HEADER1_LENGTH_MASK __GENMASK(31, 20)
1349
1343
1350
-
/* CXL 3.2 8.1.3: PCIe DVSEC for CXL Device */
1351
-
#define CXL_DVSEC_PCIE_DEVICE 0
1352
-
#define CXL_DVSEC_CAP_OFFSET 0xA
1353
-
#define CXL_DVSEC_MEM_CAPABLE _BITUL(2)
1354
-
#define CXL_DVSEC_HDM_COUNT_MASK __GENMASK(5, 4)
1355
-
#define CXL_DVSEC_CTRL_OFFSET 0xC
1356
-
#define CXL_DVSEC_MEM_ENABLE _BITUL(2)
1357
-
#define CXL_DVSEC_RANGE_SIZE_HIGH(i) (0x18 + (i * 0x10))
1358
-
#define CXL_DVSEC_RANGE_SIZE_LOW(i) (0x1C + (i * 0x10))
1359
-
#define CXL_DVSEC_MEM_INFO_VALID _BITUL(0)
1360
-
#define CXL_DVSEC_MEM_ACTIVE _BITUL(1)
1361
-
#define CXL_DVSEC_MEM_SIZE_LOW_MASK __GENMASK(31, 28)
1362
-
#define CXL_DVSEC_RANGE_BASE_HIGH(i) (0x20 + (i * 0x10))
1363
-
#define CXL_DVSEC_RANGE_BASE_LOW(i) (0x24 + (i * 0x10))
1364
-
#define CXL_DVSEC_MEM_BASE_LOW_MASK __GENMASK(31, 28)
1344
+
/* CXL r4.0, 8.1.3: PCIe DVSEC for CXL Device */
1345
+
#define PCI_DVSEC_CXL_DEVICE 0
1346
+
#define PCI_DVSEC_CXL_CAP 0xA
1347
+
#define PCI_DVSEC_CXL_MEM_CAPABLE _BITUL(2)
1348
+
#define PCI_DVSEC_CXL_HDM_COUNT __GENMASK(5, 4)
1349
+
#define PCI_DVSEC_CXL_CTRL 0xC
1350
+
#define PCI_DVSEC_CXL_MEM_ENABLE _BITUL(2)
1351
+
#define PCI_DVSEC_CXL_RANGE_SIZE_HIGH(i) (0x18 + (i * 0x10))
1352
+
#define PCI_DVSEC_CXL_RANGE_SIZE_LOW(i) (0x1C + (i * 0x10))
1353
+
#define PCI_DVSEC_CXL_MEM_INFO_VALID _BITUL(0)
1354
+
#define PCI_DVSEC_CXL_MEM_ACTIVE _BITUL(1)
1355
+
#define PCI_DVSEC_CXL_MEM_SIZE_LOW __GENMASK(31, 28)
1356
+
#define PCI_DVSEC_CXL_RANGE_BASE_HIGH(i) (0x20 + (i * 0x10))
1357
+
#define PCI_DVSEC_CXL_RANGE_BASE_LOW(i) (0x24 + (i * 0x10))
1358
+
#define PCI_DVSEC_CXL_MEM_BASE_LOW __GENMASK(31, 28)
1365
1359
1366
1360
#define CXL_DVSEC_RANGE_MAX 2
1367
1361
1368
-
/* CXL 3.2 8.1.4: Non-CXL Function Map DVSEC */
1369
-
#define CXL_DVSEC_FUNCTION_MAP 2
1362
+
/* CXL r4.0, 8.1.4: Non-CXL Function Map DVSEC */
1363
+
#define PCI_DVSEC_CXL_FUNCTION_MAP 2
1370
1364
1371
-
/* CXL 3.2 8.1.5: Extensions DVSEC for Ports */
1372
-
#define CXL_DVSEC_PORT 3
1373
-
#define CXL_DVSEC_PORT_CTL 0x0c
1374
-
#define CXL_DVSEC_PORT_CTL_UNMASK_SBR 0x00000001
1365
+
/* CXL r4.0, 8.1.5: Extensions DVSEC for Ports */
1366
+
#define PCI_DVSEC_CXL_PORT 3
1367
+
#define PCI_DVSEC_CXL_PORT_CTL 0x0c
1368
+
#define PCI_DVSEC_CXL_PORT_CTL_UNMASK_SBR 0x00000001
1375
1369
1376
-
/* CXL 3.2 8.1.6: GPF DVSEC for CXL Port */
1377
-
#define CXL_DVSEC_PORT_GPF 4
1378
-
#define CXL_DVSEC_PORT_GPF_PHASE_1_CONTROL_OFFSET 0x0C
1379
-
#define CXL_DVSEC_PORT_GPF_PHASE_1_TMO_BASE_MASK __GENMASK(3, 0)
1380
-
#define CXL_DVSEC_PORT_GPF_PHASE_1_TMO_SCALE_MASK __GENMASK(11, 8)
1381
-
#define CXL_DVSEC_PORT_GPF_PHASE_2_CONTROL_OFFSET 0xE
1382
-
#define CXL_DVSEC_PORT_GPF_PHASE_2_TMO_BASE_MASK __GENMASK(3, 0)
1383
-
#define CXL_DVSEC_PORT_GPF_PHASE_2_TMO_SCALE_MASK __GENMASK(11, 8)
1370
+
/* CXL r4.0, 8.1.6: GPF DVSEC for CXL Port */
1371
+
#define PCI_DVSEC_CXL_PORT_GPF 4
1372
+
#define PCI_DVSEC_CXL_PORT_GPF_PHASE_1_CONTROL 0x0C
1373
+
#define PCI_DVSEC_CXL_PORT_GPF_PHASE_1_TMO_BASE __GENMASK(3, 0)
1374
+
#define PCI_DVSEC_CXL_PORT_GPF_PHASE_1_TMO_SCALE __GENMASK(11, 8)
1375
+
#define PCI_DVSEC_CXL_PORT_GPF_PHASE_2_CONTROL 0xE
1376
+
#define PCI_DVSEC_CXL_PORT_GPF_PHASE_2_TMO_BASE __GENMASK(3, 0)
1377
+
#define PCI_DVSEC_CXL_PORT_GPF_PHASE_2_TMO_SCALE __GENMASK(11, 8)
1384
1378
1385
-
/* CXL 3.2 8.1.7: GPF DVSEC for CXL Device */
1386
-
#define CXL_DVSEC_DEVICE_GPF 5
1379
+
/* CXL r4.0, 8.1.7: GPF DVSEC for CXL Device */
1380
+
#define PCI_DVSEC_CXL_DEVICE_GPF 5
1387
1381
1388
-
/* CXL 3.2 8.1.9: Register Locator DVSEC */
1389
-
#define CXL_DVSEC_REG_LOCATOR 8
1390
-
#define CXL_DVSEC_REG_LOCATOR_BLOCK1_OFFSET 0xC
1391
-
#define CXL_DVSEC_REG_LOCATOR_BIR_MASK __GENMASK(2, 0)
1392
-
#define CXL_DVSEC_REG_LOCATOR_BLOCK_ID_MASK __GENMASK(15, 8)
1393
-
#define CXL_DVSEC_REG_LOCATOR_BLOCK_OFF_LOW_MASK __GENMASK(31, 16)
1382
+
/* CXL r4.0, 8.1.9: Register Locator DVSEC */
1383
+
#define PCI_DVSEC_CXL_REG_LOCATOR 8
1384
+
#define PCI_DVSEC_CXL_REG_LOCATOR_BLOCK1 0xC
1385
+
#define PCI_DVSEC_CXL_REG_LOCATOR_BIR __GENMASK(2, 0)
1386
+
#define PCI_DVSEC_CXL_REG_LOCATOR_BLOCK_ID __GENMASK(15, 8)
1387
+
#define PCI_DVSEC_CXL_REG_LOCATOR_BLOCK_OFF_LOW __GENMASK(31, 16)
1394
1388
1395
1389
#endif /* LINUX_PCI_REGS_H */