Linux kernel mirror (for testing)
git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git
kernel
os
linux
Merge branch 'net-phy-mediatek-add-token-ring-helper-functions'
Sky Huang says:
====================
net: phy: mediatek: Add token-ring helper functions
This patchset add token-ring helper functions and moves some macros from
mtk-ge.c into mtk-phy-lib.c.
v2: https://lore.kernel.org/20250116012159.3816135-2-SkyLake.Huang@mediatek.com
====================
Link: https://patch.msgid.link/20250213080553.921434-1-SkyLake.Huang@mediatek.com
Signed-off-by: Jakub Kicinski <kuba@kernel.org>
+327
-111
+179
-91
drivers/net/phy/mediatek/mtk-ge-soc.c
+179
-91
drivers/net/phy/mediatek/mtk-ge-soc.c
···
24
24
#define MTK_PHY_SMI_DET_ON_THRESH_MASK GENMASK(13, 8)
25
25
26
26
#define MTK_PHY_PAGE_EXTENDED_2A30 0x2a30
27
-
#define MTK_PHY_PAGE_EXTENDED_52B5 0x52b5
27
+
28
+
/* Registers on Token Ring debug nodes */
29
+
/* ch_addr = 0x0, node_addr = 0x7, data_addr = 0x15 */
30
+
/* NormMseLoThresh */
31
+
#define NORMAL_MSE_LO_THRESH_MASK GENMASK(15, 8)
32
+
33
+
/* ch_addr = 0x0, node_addr = 0xf, data_addr = 0x3c */
34
+
/* RemAckCntLimitCtrl */
35
+
#define REMOTE_ACK_COUNT_LIMIT_CTRL_MASK GENMASK(2, 1)
36
+
37
+
/* ch_addr = 0x1, node_addr = 0xd, data_addr = 0x20 */
38
+
/* VcoSlicerThreshBitsHigh */
39
+
#define VCO_SLICER_THRESH_HIGH_MASK GENMASK(23, 0)
40
+
41
+
/* ch_addr = 0x1, node_addr = 0xf, data_addr = 0x0 */
42
+
/* DfeTailEnableVgaThresh1000 */
43
+
#define DFE_TAIL_EANBLE_VGA_TRHESH_1000 GENMASK(5, 1)
44
+
45
+
/* ch_addr = 0x1, node_addr = 0xf, data_addr = 0x1 */
46
+
/* MrvlTrFix100Kp */
47
+
#define MRVL_TR_FIX_100KP_MASK GENMASK(22, 20)
48
+
/* MrvlTrFix100Kf */
49
+
#define MRVL_TR_FIX_100KF_MASK GENMASK(19, 17)
50
+
/* MrvlTrFix1000Kp */
51
+
#define MRVL_TR_FIX_1000KP_MASK GENMASK(16, 14)
52
+
/* MrvlTrFix1000Kf */
53
+
#define MRVL_TR_FIX_1000KF_MASK GENMASK(13, 11)
54
+
55
+
/* ch_addr = 0x1, node_addr = 0xf, data_addr = 0x12 */
56
+
/* VgaDecRate */
57
+
#define VGA_DECIMATION_RATE_MASK GENMASK(8, 5)
58
+
59
+
/* ch_addr = 0x1, node_addr = 0xf, data_addr = 0x17 */
60
+
/* SlvDSPreadyTime */
61
+
#define SLAVE_DSP_READY_TIME_MASK GENMASK(22, 15)
62
+
/* MasDSPreadyTime */
63
+
#define MASTER_DSP_READY_TIME_MASK GENMASK(14, 7)
64
+
65
+
/* ch_addr = 0x1, node_addr = 0xf, data_addr = 0x18 */
66
+
/* EnabRandUpdTrig */
67
+
#define ENABLE_RANDOM_UPDOWN_COUNTER_TRIGGER BIT(8)
68
+
69
+
/* ch_addr = 0x1, node_addr = 0xf, data_addr = 0x20 */
70
+
/* ResetSyncOffset */
71
+
#define RESET_SYNC_OFFSET_MASK GENMASK(11, 8)
72
+
73
+
/* ch_addr = 0x2, node_addr = 0xd, data_addr = 0x0 */
74
+
/* FfeUpdGainForceVal */
75
+
#define FFE_UPDATE_GAIN_FORCE_VAL_MASK GENMASK(9, 7)
76
+
/* FfeUpdGainForce */
77
+
#define FFE_UPDATE_GAIN_FORCE BIT(6)
78
+
79
+
/* ch_addr = 0x2, node_addr = 0xd, data_addr = 0x3 */
80
+
/* TrFreeze */
81
+
#define TR_FREEZE_MASK GENMASK(11, 0)
82
+
83
+
/* ch_addr = 0x2, node_addr = 0xd, data_addr = 0x6 */
84
+
/* SS: Steady-state, KP: Proportional Gain */
85
+
/* SSTrKp100 */
86
+
#define SS_TR_KP100_MASK GENMASK(21, 19)
87
+
/* SSTrKf100 */
88
+
#define SS_TR_KF100_MASK GENMASK(18, 16)
89
+
/* SSTrKp1000Mas */
90
+
#define SS_TR_KP1000_MASTER_MASK GENMASK(15, 13)
91
+
/* SSTrKf1000Mas */
92
+
#define SS_TR_KF1000_MASTER_MASK GENMASK(12, 10)
93
+
/* SSTrKp1000Slv */
94
+
#define SS_TR_KP1000_SLAVE_MASK GENMASK(9, 7)
95
+
/* SSTrKf1000Slv */
96
+
#define SS_TR_KF1000_SLAVE_MASK GENMASK(6, 4)
97
+
98
+
/* ch_addr = 0x2, node_addr = 0xd, data_addr = 0x8 */
99
+
/* clear this bit if wanna select from AFE */
100
+
/* Regsigdet_sel_1000 */
101
+
#define EEE1000_SELECT_SIGNAL_DETECTION_FROM_DFE BIT(4)
102
+
103
+
/* ch_addr = 0x2, node_addr = 0xd, data_addr = 0xd */
104
+
/* RegEEE_st2TrKf1000 */
105
+
#define EEE1000_STAGE2_TR_KF_MASK GENMASK(13, 11)
106
+
107
+
/* ch_addr = 0x2, node_addr = 0xd, data_addr = 0xf */
108
+
/* RegEEE_slv_waketr_timer_tar */
109
+
#define SLAVE_WAKETR_TIMER_MASK GENMASK(20, 11)
110
+
/* RegEEE_slv_remtx_timer_tar */
111
+
#define SLAVE_REMTX_TIMER_MASK GENMASK(10, 1)
112
+
113
+
/* ch_addr = 0x2, node_addr = 0xd, data_addr = 0x10 */
114
+
/* RegEEE_slv_wake_int_timer_tar */
115
+
#define SLAVE_WAKEINT_TIMER_MASK GENMASK(10, 1)
116
+
117
+
/* ch_addr = 0x2, node_addr = 0xd, data_addr = 0x14 */
118
+
/* RegEEE_trfreeze_timer2 */
119
+
#define TR_FREEZE_TIMER2_MASK GENMASK(9, 0)
120
+
121
+
/* ch_addr = 0x2, node_addr = 0xd, data_addr = 0x1c */
122
+
/* RegEEE100Stg1_tar */
123
+
#define EEE100_LPSYNC_STAGE1_UPDATE_TIMER_MASK GENMASK(8, 0)
124
+
125
+
/* ch_addr = 0x2, node_addr = 0xd, data_addr = 0x25 */
126
+
/* REGEEE_wake_slv_tr_wait_dfesigdet_en */
127
+
#define WAKE_SLAVE_TR_WAIT_DFE_DETECTION_EN BIT(11)
28
128
29
129
#define ANALOG_INTERNAL_OPERATION_MAX_US 20
30
130
#define TXRESERVE_MIN 0
···
801
701
static void mt798x_phy_common_finetune(struct phy_device *phydev)
802
702
{
803
703
phy_select_page(phydev, MTK_PHY_PAGE_EXTENDED_52B5);
804
-
/* SlvDSPreadyTime = 24, MasDSPreadyTime = 24 */
805
-
__phy_write(phydev, 0x11, 0xc71);
806
-
__phy_write(phydev, 0x12, 0xc);
807
-
__phy_write(phydev, 0x10, 0x8fae);
704
+
__mtk_tr_modify(phydev, 0x1, 0xf, 0x17,
705
+
SLAVE_DSP_READY_TIME_MASK | MASTER_DSP_READY_TIME_MASK,
706
+
FIELD_PREP(SLAVE_DSP_READY_TIME_MASK, 0x18) |
707
+
FIELD_PREP(MASTER_DSP_READY_TIME_MASK, 0x18));
808
708
809
-
/* EnabRandUpdTrig = 1 */
810
-
__phy_write(phydev, 0x11, 0x2f00);
811
-
__phy_write(phydev, 0x12, 0xe);
812
-
__phy_write(phydev, 0x10, 0x8fb0);
709
+
__mtk_tr_set_bits(phydev, 0x1, 0xf, 0x18,
710
+
ENABLE_RANDOM_UPDOWN_COUNTER_TRIGGER);
813
711
814
-
/* NormMseLoThresh = 85 */
815
-
__phy_write(phydev, 0x11, 0x55a0);
816
-
__phy_write(phydev, 0x12, 0x0);
817
-
__phy_write(phydev, 0x10, 0x83aa);
712
+
__mtk_tr_modify(phydev, 0x0, 0x7, 0x15,
713
+
NORMAL_MSE_LO_THRESH_MASK,
714
+
FIELD_PREP(NORMAL_MSE_LO_THRESH_MASK, 0x55));
818
715
819
-
/* FfeUpdGainForce = 1(Enable), FfeUpdGainForceVal = 4 */
820
-
__phy_write(phydev, 0x11, 0x240);
821
-
__phy_write(phydev, 0x12, 0x0);
822
-
__phy_write(phydev, 0x10, 0x9680);
716
+
__mtk_tr_modify(phydev, 0x2, 0xd, 0x0,
717
+
FFE_UPDATE_GAIN_FORCE_VAL_MASK,
718
+
FIELD_PREP(FFE_UPDATE_GAIN_FORCE_VAL_MASK, 0x4) |
719
+
FFE_UPDATE_GAIN_FORCE);
823
720
824
-
/* TrFreeze = 0 (mt7988 default) */
825
-
__phy_write(phydev, 0x11, 0x0);
826
-
__phy_write(phydev, 0x12, 0x0);
827
-
__phy_write(phydev, 0x10, 0x9686);
721
+
__mtk_tr_clr_bits(phydev, 0x2, 0xd, 0x3, TR_FREEZE_MASK);
828
722
829
-
/* SSTrKp100 = 5 */
830
-
/* SSTrKf100 = 6 */
831
-
/* SSTrKp1000Mas = 5 */
832
-
/* SSTrKf1000Mas = 6 */
833
-
/* SSTrKp1000Slv = 5 */
834
-
/* SSTrKf1000Slv = 6 */
835
-
__phy_write(phydev, 0x11, 0xbaef);
836
-
__phy_write(phydev, 0x12, 0x2e);
837
-
__phy_write(phydev, 0x10, 0x968c);
723
+
__mtk_tr_modify(phydev, 0x2, 0xd, 0x6,
724
+
SS_TR_KP100_MASK | SS_TR_KF100_MASK |
725
+
SS_TR_KP1000_MASTER_MASK | SS_TR_KF1000_MASTER_MASK |
726
+
SS_TR_KP1000_SLAVE_MASK | SS_TR_KF1000_SLAVE_MASK,
727
+
FIELD_PREP(SS_TR_KP100_MASK, 0x5) |
728
+
FIELD_PREP(SS_TR_KF100_MASK, 0x6) |
729
+
FIELD_PREP(SS_TR_KP1000_MASTER_MASK, 0x5) |
730
+
FIELD_PREP(SS_TR_KF1000_MASTER_MASK, 0x6) |
731
+
FIELD_PREP(SS_TR_KP1000_SLAVE_MASK, 0x5) |
732
+
FIELD_PREP(SS_TR_KF1000_SLAVE_MASK, 0x6));
733
+
838
734
phy_restore_page(phydev, MTK_PHY_PAGE_STANDARD, 0);
839
735
}
840
736
···
853
757
}
854
758
855
759
phy_select_page(phydev, MTK_PHY_PAGE_EXTENDED_52B5);
856
-
/* ResetSyncOffset = 6 */
857
-
__phy_write(phydev, 0x11, 0x600);
858
-
__phy_write(phydev, 0x12, 0x0);
859
-
__phy_write(phydev, 0x10, 0x8fc0);
760
+
__mtk_tr_modify(phydev, 0x1, 0xf, 0x20,
761
+
RESET_SYNC_OFFSET_MASK,
762
+
FIELD_PREP(RESET_SYNC_OFFSET_MASK, 0x6));
860
763
861
-
/* VgaDecRate = 1 */
862
-
__phy_write(phydev, 0x11, 0x4c2a);
863
-
__phy_write(phydev, 0x12, 0x3e);
864
-
__phy_write(phydev, 0x10, 0x8fa4);
764
+
__mtk_tr_modify(phydev, 0x1, 0xf, 0x12,
765
+
VGA_DECIMATION_RATE_MASK,
766
+
FIELD_PREP(VGA_DECIMATION_RATE_MASK, 0x1));
865
767
866
768
/* MrvlTrFix100Kp = 3, MrvlTrFix100Kf = 2,
867
769
* MrvlTrFix1000Kp = 3, MrvlTrFix1000Kf = 2
868
770
*/
869
-
__phy_write(phydev, 0x11, 0xd10a);
870
-
__phy_write(phydev, 0x12, 0x34);
871
-
__phy_write(phydev, 0x10, 0x8f82);
771
+
__mtk_tr_modify(phydev, 0x1, 0xf, 0x1,
772
+
MRVL_TR_FIX_100KP_MASK | MRVL_TR_FIX_100KF_MASK |
773
+
MRVL_TR_FIX_1000KP_MASK | MRVL_TR_FIX_1000KF_MASK,
774
+
FIELD_PREP(MRVL_TR_FIX_100KP_MASK, 0x3) |
775
+
FIELD_PREP(MRVL_TR_FIX_100KF_MASK, 0x2) |
776
+
FIELD_PREP(MRVL_TR_FIX_1000KP_MASK, 0x3) |
777
+
FIELD_PREP(MRVL_TR_FIX_1000KF_MASK, 0x2));
872
778
873
779
/* VcoSlicerThreshBitsHigh */
874
-
__phy_write(phydev, 0x11, 0x5555);
875
-
__phy_write(phydev, 0x12, 0x55);
876
-
__phy_write(phydev, 0x10, 0x8ec0);
780
+
__mtk_tr_modify(phydev, 0x1, 0xd, 0x20,
781
+
VCO_SLICER_THRESH_HIGH_MASK,
782
+
FIELD_PREP(VCO_SLICER_THRESH_HIGH_MASK, 0x555555));
877
783
phy_restore_page(phydev, MTK_PHY_PAGE_STANDARD, 0);
878
784
879
785
/* TR_OPEN_LOOP_EN = 1, lpf_x_average = 9 */
···
927
829
phy_write_mmd(phydev, MDIO_MMD_VEND1, MTK_PHY_RG_TX_FILTER, 0x5);
928
830
929
831
phy_select_page(phydev, MTK_PHY_PAGE_EXTENDED_52B5);
930
-
/* ResetSyncOffset = 5 */
931
-
__phy_write(phydev, 0x11, 0x500);
932
-
__phy_write(phydev, 0x12, 0x0);
933
-
__phy_write(phydev, 0x10, 0x8fc0);
832
+
__mtk_tr_modify(phydev, 0x1, 0xf, 0x20,
833
+
RESET_SYNC_OFFSET_MASK,
834
+
FIELD_PREP(RESET_SYNC_OFFSET_MASK, 0x5));
934
835
935
836
/* VgaDecRate is 1 at default on mt7988 */
936
837
937
-
/* MrvlTrFix100Kp = 6, MrvlTrFix100Kf = 7,
938
-
* MrvlTrFix1000Kp = 6, MrvlTrFix1000Kf = 7
939
-
*/
940
-
__phy_write(phydev, 0x11, 0xb90a);
941
-
__phy_write(phydev, 0x12, 0x6f);
942
-
__phy_write(phydev, 0x10, 0x8f82);
838
+
__mtk_tr_modify(phydev, 0x1, 0xf, 0x1,
839
+
MRVL_TR_FIX_100KP_MASK | MRVL_TR_FIX_100KF_MASK |
840
+
MRVL_TR_FIX_1000KP_MASK | MRVL_TR_FIX_1000KF_MASK,
841
+
FIELD_PREP(MRVL_TR_FIX_100KP_MASK, 0x6) |
842
+
FIELD_PREP(MRVL_TR_FIX_100KF_MASK, 0x7) |
843
+
FIELD_PREP(MRVL_TR_FIX_1000KP_MASK, 0x6) |
844
+
FIELD_PREP(MRVL_TR_FIX_1000KF_MASK, 0x7));
943
845
944
-
/* RemAckCntLimitCtrl = 1 */
945
-
__phy_write(phydev, 0x11, 0xfbba);
946
-
__phy_write(phydev, 0x12, 0xc3);
947
-
__phy_write(phydev, 0x10, 0x87f8);
948
-
846
+
__mtk_tr_modify(phydev, 0x0, 0xf, 0x3c,
847
+
REMOTE_ACK_COUNT_LIMIT_CTRL_MASK,
848
+
FIELD_PREP(REMOTE_ACK_COUNT_LIMIT_CTRL_MASK, 0x1));
949
849
phy_restore_page(phydev, MTK_PHY_PAGE_STANDARD, 0);
950
850
951
851
/* TR_OPEN_LOOP_EN = 1, lpf_x_average = 10 */
···
1019
923
MTK_PHY_TR_READY_SKIP_AFE_WAKEUP);
1020
924
1021
925
phy_select_page(phydev, MTK_PHY_PAGE_EXTENDED_52B5);
1022
-
/* Regsigdet_sel_1000 = 0 */
1023
-
__phy_write(phydev, 0x11, 0xb);
1024
-
__phy_write(phydev, 0x12, 0x0);
1025
-
__phy_write(phydev, 0x10, 0x9690);
926
+
__mtk_tr_clr_bits(phydev, 0x2, 0xd, 0x8,
927
+
EEE1000_SELECT_SIGNAL_DETECTION_FROM_DFE);
1026
928
1027
-
/* REG_EEE_st2TrKf1000 = 2 */
1028
-
__phy_write(phydev, 0x11, 0x114f);
1029
-
__phy_write(phydev, 0x12, 0x2);
1030
-
__phy_write(phydev, 0x10, 0x969a);
929
+
__mtk_tr_modify(phydev, 0x2, 0xd, 0xd,
930
+
EEE1000_STAGE2_TR_KF_MASK,
931
+
FIELD_PREP(EEE1000_STAGE2_TR_KF_MASK, 0x2));
1031
932
1032
-
/* RegEEE_slv_wake_tr_timer_tar = 6, RegEEE_slv_remtx_timer_tar = 20 */
1033
-
__phy_write(phydev, 0x11, 0x3028);
1034
-
__phy_write(phydev, 0x12, 0x0);
1035
-
__phy_write(phydev, 0x10, 0x969e);
933
+
__mtk_tr_modify(phydev, 0x2, 0xd, 0xf,
934
+
SLAVE_WAKETR_TIMER_MASK | SLAVE_REMTX_TIMER_MASK,
935
+
FIELD_PREP(SLAVE_WAKETR_TIMER_MASK, 0x6) |
936
+
FIELD_PREP(SLAVE_REMTX_TIMER_MASK, 0x14));
1036
937
1037
-
/* RegEEE_slv_wake_int_timer_tar = 8 */
1038
-
__phy_write(phydev, 0x11, 0x5010);
1039
-
__phy_write(phydev, 0x12, 0x0);
1040
-
__phy_write(phydev, 0x10, 0x96a0);
938
+
__mtk_tr_modify(phydev, 0x2, 0xd, 0x10,
939
+
SLAVE_WAKEINT_TIMER_MASK,
940
+
FIELD_PREP(SLAVE_WAKEINT_TIMER_MASK, 0x8));
1041
941
1042
-
/* RegEEE_trfreeze_timer2 = 586 */
1043
-
__phy_write(phydev, 0x11, 0x24a);
1044
-
__phy_write(phydev, 0x12, 0x0);
1045
-
__phy_write(phydev, 0x10, 0x96a8);
942
+
__mtk_tr_modify(phydev, 0x2, 0xd, 0x14,
943
+
TR_FREEZE_TIMER2_MASK,
944
+
FIELD_PREP(TR_FREEZE_TIMER2_MASK, 0x24a));
1046
945
1047
-
/* RegEEE100Stg1_tar = 16 */
1048
-
__phy_write(phydev, 0x11, 0x3210);
1049
-
__phy_write(phydev, 0x12, 0x0);
1050
-
__phy_write(phydev, 0x10, 0x96b8);
946
+
__mtk_tr_modify(phydev, 0x2, 0xd, 0x1c,
947
+
EEE100_LPSYNC_STAGE1_UPDATE_TIMER_MASK,
948
+
FIELD_PREP(EEE100_LPSYNC_STAGE1_UPDATE_TIMER_MASK,
949
+
0x10));
1051
950
1052
-
/* REGEEE_wake_slv_tr_wait_dfesigdet_en = 0 */
1053
-
__phy_write(phydev, 0x11, 0x1463);
1054
-
__phy_write(phydev, 0x12, 0x0);
1055
-
__phy_write(phydev, 0x10, 0x96ca);
951
+
__mtk_tr_clr_bits(phydev, 0x2, 0xd, 0x25,
952
+
WAKE_SLAVE_TR_WAIT_DFE_DETECTION_EN);
1056
953
1057
-
/* DfeTailEnableVgaThresh1000 = 27 */
1058
-
__phy_write(phydev, 0x11, 0x36);
1059
-
__phy_write(phydev, 0x12, 0x0);
1060
-
__phy_write(phydev, 0x10, 0x8f80);
954
+
__mtk_tr_modify(phydev, 0x1, 0xf, 0x0,
955
+
DFE_TAIL_EANBLE_VGA_TRHESH_1000,
956
+
FIELD_PREP(DFE_TAIL_EANBLE_VGA_TRHESH_1000, 0x1b));
1061
957
phy_restore_page(phydev, MTK_PHY_PAGE_STANDARD, 0);
1062
958
1063
959
phy_select_page(phydev, MTK_PHY_PAGE_EXTENDED_3);
+56
-20
drivers/net/phy/mediatek/mtk-ge.c
+56
-20
drivers/net/phy/mediatek/mtk-ge.c
···
8
8
#define MTK_GPHY_ID_MT7530 0x03a29412
9
9
#define MTK_GPHY_ID_MT7531 0x03a29441
10
10
11
-
#define MTK_EXT_PAGE_ACCESS 0x1f
12
-
#define MTK_PHY_PAGE_STANDARD 0x0000
13
-
#define MTK_PHY_PAGE_EXTENDED 0x0001
14
-
#define MTK_PHY_PAGE_EXTENDED_2 0x0002
15
-
#define MTK_PHY_PAGE_EXTENDED_3 0x0003
16
-
#define MTK_PHY_PAGE_EXTENDED_2A30 0x2a30
17
-
#define MTK_PHY_PAGE_EXTENDED_52B5 0x52b5
11
+
#define MTK_PHY_PAGE_EXTENDED_2 0x0002
12
+
#define MTK_PHY_PAGE_EXTENDED_3 0x0003
13
+
#define MTK_PHY_RG_LPI_PCS_DSP_CTRL_REG11 0x11
14
+
15
+
#define MTK_PHY_PAGE_EXTENDED_2A30 0x2a30
16
+
17
+
/* Registers on Token Ring debug nodes */
18
+
/* ch_addr = 0x1, node_addr = 0xf, data_addr = 0x17 */
19
+
#define SLAVE_DSP_READY_TIME_MASK GENMASK(22, 15)
20
+
21
+
/* Registers on MDIO_MMD_VEND1 */
22
+
#define MTK_PHY_GBE_MODE_TX_DELAY_SEL 0x13
23
+
#define MTK_PHY_TEST_MODE_TX_DELAY_SEL 0x14
24
+
#define MTK_TX_DELAY_PAIR_B_MASK GENMASK(10, 8)
25
+
#define MTK_TX_DELAY_PAIR_D_MASK GENMASK(2, 0)
26
+
27
+
#define MTK_PHY_MCC_CTRL_AND_TX_POWER_CTRL 0xa6
28
+
#define MTK_MCC_NEARECHO_OFFSET_MASK GENMASK(15, 8)
29
+
30
+
#define MTK_PHY_RXADC_CTRL_RG7 0xc6
31
+
#define MTK_PHY_DA_AD_BUF_BIAS_LP_MASK GENMASK(9, 8)
32
+
33
+
#define MTK_PHY_RG_LPI_PCS_DSP_CTRL_REG123 0x123
34
+
#define MTK_PHY_LPI_NORM_MSE_LO_THRESH100_MASK GENMASK(15, 8)
35
+
#define MTK_PHY_LPI_NORM_MSE_HI_THRESH100_MASK GENMASK(7, 0)
18
36
19
37
static void mtk_gephy_config_init(struct phy_device *phydev)
20
38
{
21
39
/* Enable HW auto downshift */
22
-
phy_modify_paged(phydev, MTK_PHY_PAGE_EXTENDED, 0x14, 0, BIT(4));
40
+
phy_modify_paged(phydev, MTK_PHY_PAGE_EXTENDED_1,
41
+
MTK_PHY_AUX_CTRL_AND_STATUS,
42
+
0, MTK_PHY_ENABLE_DOWNSHIFT);
23
43
24
44
/* Increase SlvDPSready time */
25
-
phy_select_page(phydev, MTK_PHY_PAGE_EXTENDED_52B5);
26
-
__phy_write(phydev, 0x10, 0xafae);
27
-
__phy_write(phydev, 0x12, 0x2f);
28
-
__phy_write(phydev, 0x10, 0x8fae);
29
-
phy_restore_page(phydev, MTK_PHY_PAGE_STANDARD, 0);
45
+
mtk_tr_modify(phydev, 0x1, 0xf, 0x17, SLAVE_DSP_READY_TIME_MASK,
46
+
FIELD_PREP(SLAVE_DSP_READY_TIME_MASK, 0x5e));
30
47
31
48
/* Adjust 100_mse_threshold */
32
-
phy_write_mmd(phydev, MDIO_MMD_VEND1, 0x123, 0xffff);
49
+
phy_modify_mmd(phydev, MDIO_MMD_VEND1,
50
+
MTK_PHY_RG_LPI_PCS_DSP_CTRL_REG123,
51
+
MTK_PHY_LPI_NORM_MSE_LO_THRESH100_MASK |
52
+
MTK_PHY_LPI_NORM_MSE_HI_THRESH100_MASK,
53
+
FIELD_PREP(MTK_PHY_LPI_NORM_MSE_LO_THRESH100_MASK,
54
+
0xff) |
55
+
FIELD_PREP(MTK_PHY_LPI_NORM_MSE_HI_THRESH100_MASK,
56
+
0xff));
33
57
34
-
/* Disable mcc */
35
-
phy_write_mmd(phydev, MDIO_MMD_VEND1, 0xa6, 0x300);
58
+
/* If echo time is narrower than 0x3, it will be regarded as noise */
59
+
phy_modify_mmd(phydev, MDIO_MMD_VEND1,
60
+
MTK_PHY_MCC_CTRL_AND_TX_POWER_CTRL,
61
+
MTK_MCC_NEARECHO_OFFSET_MASK,
62
+
FIELD_PREP(MTK_MCC_NEARECHO_OFFSET_MASK, 0x3));
36
63
}
37
64
38
65
static int mt7530_phy_config_init(struct phy_device *phydev)
···
67
40
mtk_gephy_config_init(phydev);
68
41
69
42
/* Increase post_update_timer */
70
-
phy_write_paged(phydev, MTK_PHY_PAGE_EXTENDED_3, 0x11, 0x4b);
43
+
phy_write_paged(phydev, MTK_PHY_PAGE_EXTENDED_3,
44
+
MTK_PHY_RG_LPI_PCS_DSP_CTRL_REG11, 0x4b);
71
45
72
46
return 0;
73
47
}
···
79
51
80
52
/* PHY link down power saving enable */
81
53
phy_set_bits(phydev, 0x17, BIT(4));
82
-
phy_clear_bits_mmd(phydev, MDIO_MMD_VEND1, 0xc6, 0x300);
54
+
phy_modify_mmd(phydev, MDIO_MMD_VEND1, MTK_PHY_RXADC_CTRL_RG7,
55
+
MTK_PHY_DA_AD_BUF_BIAS_LP_MASK,
56
+
FIELD_PREP(MTK_PHY_DA_AD_BUF_BIAS_LP_MASK, 0x3));
83
57
84
58
/* Set TX Pair delay selection */
85
-
phy_write_mmd(phydev, MDIO_MMD_VEND1, 0x13, 0x404);
86
-
phy_write_mmd(phydev, MDIO_MMD_VEND1, 0x14, 0x404);
59
+
phy_modify_mmd(phydev, MDIO_MMD_VEND1, MTK_PHY_GBE_MODE_TX_DELAY_SEL,
60
+
MTK_TX_DELAY_PAIR_B_MASK | MTK_TX_DELAY_PAIR_D_MASK,
61
+
FIELD_PREP(MTK_TX_DELAY_PAIR_B_MASK, 0x4) |
62
+
FIELD_PREP(MTK_TX_DELAY_PAIR_D_MASK, 0x4));
63
+
phy_modify_mmd(phydev, MDIO_MMD_VEND1, MTK_PHY_TEST_MODE_TX_DELAY_SEL,
64
+
MTK_TX_DELAY_PAIR_B_MASK | MTK_TX_DELAY_PAIR_D_MASK,
65
+
FIELD_PREP(MTK_TX_DELAY_PAIR_B_MASK, 0x4) |
66
+
FIELD_PREP(MTK_TX_DELAY_PAIR_D_MASK, 0x4));
87
67
88
68
return 0;
89
69
}
+77
drivers/net/phy/mediatek/mtk-phy-lib.c
+77
drivers/net/phy/mediatek/mtk-phy-lib.c
···
6
6
7
7
#include "mtk.h"
8
8
9
+
/* Difference between functions with mtk_tr* and __mtk_tr* prefixes is
10
+
* mtk_tr* functions: wrapped by page switching operations
11
+
* __mtk_tr* functions: no page switching operations
12
+
*/
13
+
14
+
static void __mtk_tr_access(struct phy_device *phydev, bool read, u8 ch_addr,
15
+
u8 node_addr, u8 data_addr)
16
+
{
17
+
u16 tr_cmd = BIT(15); /* bit 14 & 0 are reserved */
18
+
19
+
if (read)
20
+
tr_cmd |= BIT(13);
21
+
22
+
tr_cmd |= (((ch_addr & 0x3) << 11) |
23
+
((node_addr & 0xf) << 7) |
24
+
((data_addr & 0x3f) << 1));
25
+
dev_dbg(&phydev->mdio.dev, "tr_cmd: 0x%x\n", tr_cmd);
26
+
__phy_write(phydev, 0x10, tr_cmd);
27
+
}
28
+
29
+
static void __mtk_tr_read(struct phy_device *phydev, u8 ch_addr, u8 node_addr,
30
+
u8 data_addr, u16 *tr_high, u16 *tr_low)
31
+
{
32
+
__mtk_tr_access(phydev, true, ch_addr, node_addr, data_addr);
33
+
*tr_low = __phy_read(phydev, 0x11);
34
+
*tr_high = __phy_read(phydev, 0x12);
35
+
dev_dbg(&phydev->mdio.dev, "tr_high read: 0x%x, tr_low read: 0x%x\n",
36
+
*tr_high, *tr_low);
37
+
}
38
+
39
+
static void __mtk_tr_write(struct phy_device *phydev, u8 ch_addr, u8 node_addr,
40
+
u8 data_addr, u32 tr_data)
41
+
{
42
+
__phy_write(phydev, 0x11, tr_data & 0xffff);
43
+
__phy_write(phydev, 0x12, tr_data >> 16);
44
+
dev_dbg(&phydev->mdio.dev, "tr_high write: 0x%x, tr_low write: 0x%x\n",
45
+
tr_data >> 16, tr_data & 0xffff);
46
+
__mtk_tr_access(phydev, false, ch_addr, node_addr, data_addr);
47
+
}
48
+
49
+
void __mtk_tr_modify(struct phy_device *phydev, u8 ch_addr, u8 node_addr,
50
+
u8 data_addr, u32 mask, u32 set)
51
+
{
52
+
u32 tr_data;
53
+
u16 tr_high;
54
+
u16 tr_low;
55
+
56
+
__mtk_tr_read(phydev, ch_addr, node_addr, data_addr, &tr_high, &tr_low);
57
+
tr_data = (tr_high << 16) | tr_low;
58
+
tr_data = (tr_data & ~mask) | set;
59
+
__mtk_tr_write(phydev, ch_addr, node_addr, data_addr, tr_data);
60
+
}
61
+
EXPORT_SYMBOL_GPL(__mtk_tr_modify);
62
+
63
+
void mtk_tr_modify(struct phy_device *phydev, u8 ch_addr, u8 node_addr,
64
+
u8 data_addr, u32 mask, u32 set)
65
+
{
66
+
phy_select_page(phydev, MTK_PHY_PAGE_EXTENDED_52B5);
67
+
__mtk_tr_modify(phydev, ch_addr, node_addr, data_addr, mask, set);
68
+
phy_restore_page(phydev, MTK_PHY_PAGE_STANDARD, 0);
69
+
}
70
+
EXPORT_SYMBOL_GPL(mtk_tr_modify);
71
+
72
+
void __mtk_tr_set_bits(struct phy_device *phydev, u8 ch_addr, u8 node_addr,
73
+
u8 data_addr, u32 set)
74
+
{
75
+
__mtk_tr_modify(phydev, ch_addr, node_addr, data_addr, 0, set);
76
+
}
77
+
EXPORT_SYMBOL_GPL(__mtk_tr_set_bits);
78
+
79
+
void __mtk_tr_clr_bits(struct phy_device *phydev, u8 ch_addr, u8 node_addr,
80
+
u8 data_addr, u32 clr)
81
+
{
82
+
__mtk_tr_modify(phydev, ch_addr, node_addr, data_addr, clr, 0);
83
+
}
84
+
EXPORT_SYMBOL_GPL(__mtk_tr_clr_bits);
85
+
9
86
int mtk_phy_read_page(struct phy_device *phydev)
10
87
{
11
88
return __phy_read(phydev, MTK_EXT_PAGE_ACCESS);
+15
drivers/net/phy/mediatek/mtk.h
+15
drivers/net/phy/mediatek/mtk.h
···
8
8
#ifndef _MTK_EPHY_H_
9
9
#define _MTK_EPHY_H_
10
10
11
+
#define MTK_PHY_AUX_CTRL_AND_STATUS 0x14
12
+
#define MTK_PHY_ENABLE_DOWNSHIFT BIT(4)
13
+
11
14
#define MTK_EXT_PAGE_ACCESS 0x1f
15
+
#define MTK_PHY_PAGE_EXTENDED_1 0x0001
16
+
#define MTK_PHY_PAGE_STANDARD 0x0000
17
+
#define MTK_PHY_PAGE_EXTENDED_52B5 0x52b5
12
18
13
19
/* Registers on MDIO_MMD_VEND2 */
14
20
#define MTK_PHY_LED0_ON_CTRL 0x24
···
71
65
struct mtk_socphy_priv {
72
66
unsigned long led_state;
73
67
};
68
+
69
+
void __mtk_tr_modify(struct phy_device *phydev, u8 ch_addr, u8 node_addr,
70
+
u8 data_addr, u32 mask, u32 set);
71
+
void mtk_tr_modify(struct phy_device *phydev, u8 ch_addr, u8 node_addr,
72
+
u8 data_addr, u32 mask, u32 set);
73
+
void __mtk_tr_set_bits(struct phy_device *phydev, u8 ch_addr, u8 node_addr,
74
+
u8 data_addr, u32 set);
75
+
void __mtk_tr_clr_bits(struct phy_device *phydev, u8 ch_addr, u8 node_addr,
76
+
u8 data_addr, u32 clr);
74
77
75
78
int mtk_phy_read_page(struct phy_device *phydev);
76
79
int mtk_phy_write_page(struct phy_device *phydev, int page);