Linux kernel mirror (for testing)
git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git
kernel
os
linux
ASoC: rsnd: use array for 44.1kHz/48kHz rate handling
ADG need to know output rate of 44.1kHz/48kHz.
It is using single variable for each, but this patch changes
it to array. Nothing is changed by this patch.
This is prepare for R-Car Gen4 support.
Signed-off-by: Kuninori Morimoto <kuninori.morimoto.gx@renesas.com>
Link: https://lore.kernel.org/r/87tu065em3.wl-kuninori.morimoto.gx@renesas.com
Signed-off-by: Mark Brown <broonie@kernel.org>
authored by
Kuninori Morimoto
and committed by
Mark Brown
662721ec
efaab615
+30
-30
+30
-30
sound/soc/sh/rcar/adg.c
+30
-30
sound/soc/sh/rcar/adg.c
···
25
25
.name = "adg",
26
26
};
27
27
28
+
#define ADG_HZ_441 0
29
+
#define ADG_HZ_48 1
30
+
#define ADG_HZ_SIZE 2
31
+
28
32
struct rsnd_adg {
29
33
struct clk *clkin[CLKINMAX];
30
34
struct clk *clkout[CLKOUTMAX];
···
42
38
u32 rbga;
43
39
u32 rbgb;
44
40
45
-
int rbga_rate_for_441khz; /* RBGA */
46
-
int rbgb_rate_for_48khz; /* RBGB */
41
+
int rbg_rate[ADG_HZ_SIZE]; /* RBGA / RBGB */
47
42
};
48
43
49
44
#define for_each_rsnd_clkin(pos, adg, i) \
···
127
124
adg->clkin_rate[CLKA], /* 0000: CLKA */
128
125
adg->clkin_rate[CLKB], /* 0001: CLKB */
129
126
adg->clkin_rate[CLKC], /* 0010: CLKC */
130
-
adg->rbga_rate_for_441khz, /* 0011: RBGA */
131
-
adg->rbgb_rate_for_48khz, /* 0100: RBGB */
127
+
adg->rbg_rate[ADG_HZ_441], /* 0011: RBGA */
128
+
adg->rbg_rate[ADG_HZ_48], /* 0100: RBGB */
132
129
};
133
130
134
131
min = ~0;
···
319
316
/*
320
317
* find divided clock from BRGA/BRGB
321
318
*/
322
-
if (rate == adg->rbga_rate_for_441khz)
319
+
if (rate == adg->rbg_rate[ADG_HZ_441])
323
320
return 0x10;
324
321
325
-
if (rate == adg->rbgb_rate_for_48khz)
322
+
if (rate == adg->rbg_rate[ADG_HZ_48])
326
323
return 0x20;
327
324
328
325
return -EIO;
···
359
356
360
357
dev_dbg(dev, "CLKOUT is based on BRG%c (= %dHz)\n",
361
358
(ckr) ? 'B' : 'A',
362
-
(ckr) ? adg->rbgb_rate_for_48khz :
363
-
adg->rbga_rate_for_441khz);
359
+
(ckr) ? adg->rbg_rate[ADG_HZ_48] :
360
+
adg->rbg_rate[ADG_HZ_441]);
364
361
365
362
return 0;
366
363
}
···
478
475
struct property *prop;
479
476
u32 ckr, rbgx, rbga, rbgb;
480
477
u32 rate, div;
481
-
#define REQ_SIZE 2
482
-
u32 req_rate[REQ_SIZE] = {};
478
+
u32 req_rate[ADG_HZ_SIZE] = {};
483
479
uint32_t count = 0;
484
-
unsigned long req_48kHz_rate, req_441kHz_rate;
480
+
unsigned long req_Hz[ADG_HZ_SIZE];
485
481
int clkout_size;
486
482
int i, req_size;
487
483
const char *parent_clk_name = NULL;
···
505
503
goto rsnd_adg_get_clkout_end;
506
504
507
505
req_size = prop->length / sizeof(u32);
508
-
if (req_size > REQ_SIZE) {
506
+
if (req_size > ADG_HZ_SIZE) {
509
507
dev_err(dev, "too many clock-frequency\n");
510
508
return -EINVAL;
511
509
}
512
510
513
511
of_property_read_u32_array(np, "clock-frequency", req_rate, req_size);
514
-
req_48kHz_rate = 0;
515
-
req_441kHz_rate = 0;
512
+
req_Hz[ADG_HZ_48] = 0;
513
+
req_Hz[ADG_HZ_441] = 0;
516
514
for (i = 0; i < req_size; i++) {
517
515
if (0 == (req_rate[i] % 44100))
518
-
req_441kHz_rate = req_rate[i];
516
+
req_Hz[ADG_HZ_441] = req_rate[i];
519
517
if (0 == (req_rate[i] % 48000))
520
-
req_48kHz_rate = req_rate[i];
518
+
req_Hz[ADG_HZ_48] = req_rate[i];
521
519
}
522
520
523
521
/*
···
529
527
* rsnd_adg_ssi_clk_try_start()
530
528
* rsnd_ssi_master_clk_start()
531
529
*/
532
-
adg->rbga_rate_for_441khz = 0;
533
-
adg->rbgb_rate_for_48khz = 0;
534
530
for_each_rsnd_clkin(clk, adg, i) {
535
531
rate = clk_get_rate(clk);
536
532
···
536
536
continue;
537
537
538
538
/* RBGA */
539
-
if (!adg->rbga_rate_for_441khz && (0 == rate % 44100)) {
539
+
if (!adg->rbg_rate[ADG_HZ_441] && (0 == rate % 44100)) {
540
540
div = 6;
541
-
if (req_441kHz_rate)
542
-
div = rate / req_441kHz_rate;
541
+
if (req_Hz[ADG_HZ_441])
542
+
div = rate / req_Hz[ADG_HZ_441];
543
543
rbgx = rsnd_adg_calculate_rbgx(div);
544
544
if (BRRx_MASK(rbgx) == rbgx) {
545
545
rbga = rbgx;
546
-
adg->rbga_rate_for_441khz = rate / div;
546
+
adg->rbg_rate[ADG_HZ_441] = rate / div;
547
547
ckr |= brg_table[i] << 20;
548
-
if (req_441kHz_rate)
548
+
if (req_Hz[ADG_HZ_441])
549
549
parent_clk_name = __clk_get_name(clk);
550
550
}
551
551
}
552
552
553
553
/* RBGB */
554
-
if (!adg->rbgb_rate_for_48khz && (0 == rate % 48000)) {
554
+
if (!adg->rbg_rate[ADG_HZ_48] && (0 == rate % 48000)) {
555
555
div = 6;
556
-
if (req_48kHz_rate)
557
-
div = rate / req_48kHz_rate;
556
+
if (req_Hz[ADG_HZ_48])
557
+
div = rate / req_Hz[ADG_HZ_48];
558
558
rbgx = rsnd_adg_calculate_rbgx(div);
559
559
if (BRRx_MASK(rbgx) == rbgx) {
560
560
rbgb = rbgx;
561
-
adg->rbgb_rate_for_48khz = rate / div;
561
+
adg->rbg_rate[ADG_HZ_48] = rate / div;
562
562
ckr |= brg_table[i] << 16;
563
-
if (req_48kHz_rate)
563
+
if (req_Hz[ADG_HZ_48])
564
564
parent_clk_name = __clk_get_name(clk);
565
565
}
566
566
}
···
654
654
655
655
dbg_msg(dev, m, "BRGCKR = 0x%08x, BRRA/BRRB = 0x%x/0x%x\n",
656
656
adg->ckr, adg->rbga, adg->rbgb);
657
-
dbg_msg(dev, m, "BRGA (for 44100 base) = %d\n", adg->rbga_rate_for_441khz);
658
-
dbg_msg(dev, m, "BRGB (for 48000 base) = %d\n", adg->rbgb_rate_for_48khz);
657
+
dbg_msg(dev, m, "BRGA (for 44100 base) = %d\n", adg->rbg_rate[ADG_HZ_441]);
658
+
dbg_msg(dev, m, "BRGB (for 48000 base) = %d\n", adg->rbg_rate[ADG_HZ_48]);
659
659
660
660
/*
661
661
* Actual CLKOUT will be exchanged in rsnd_adg_ssi_clk_try_start()