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git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git
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linux
arm64: dts: apm: Clean-up clock bindings
Clean-up a couple of clock binding related issues in the the X-Gene DTS.
CPU and I2C nodes aren't clock providers and shouldn't have
"#clock-cells" properties.
A fixed-clock only provides 1 clock, so "#clock-cells" must be 0. The
preferred node name is "clock-<freq>" as well.
The "type" property is undocumented and unused, so drop it.
Signed-off-by: Rob Herring (Arm) <robh@kernel.org>
Link: https://lore.kernel.org/r/20250910223020.612244-2-robh@kernel.org
Signed-off-by: Arnd Bergmann <arnd@arndb.de>
authored by
Rob Herring (Arm)
and committed by
Arnd Bergmann
668cf076
7a0e28e5
+29
-41
+4
-12
arch/arm64/boot/dts/apm/apm-shadowcat.dtsi
+4
-12
arch/arm64/boot/dts/apm/apm-shadowcat.dtsi
···
22
22
enable-method = "spin-table";
23
23
cpu-release-addr = <0x1 0x0000fff8>;
24
24
next-level-cache = <&xgene_L2_0>;
25
-
#clock-cells = <1>;
26
25
clocks = <&pmd0clk 0>;
27
26
};
28
27
cpu@1 {
···
31
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enable-method = "spin-table";
32
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cpu-release-addr = <0x1 0x0000fff8>;
33
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next-level-cache = <&xgene_L2_0>;
34
-
#clock-cells = <1>;
35
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clocks = <&pmd0clk 0>;
36
36
};
37
37
cpu@100 {
···
40
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enable-method = "spin-table";
41
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cpu-release-addr = <0x1 0x0000fff8>;
42
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next-level-cache = <&xgene_L2_1>;
43
-
#clock-cells = <1>;
44
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clocks = <&pmd1clk 0>;
45
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};
46
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cpu@101 {
···
49
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enable-method = "spin-table";
50
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cpu-release-addr = <0x1 0x0000fff8>;
51
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next-level-cache = <&xgene_L2_1>;
52
-
#clock-cells = <1>;
53
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clocks = <&pmd1clk 0>;
54
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};
55
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cpu@200 {
···
58
62
enable-method = "spin-table";
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cpu-release-addr = <0x1 0x0000fff8>;
60
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next-level-cache = <&xgene_L2_2>;
61
-
#clock-cells = <1>;
62
65
clocks = <&pmd2clk 0>;
63
66
};
64
67
cpu@201 {
···
67
72
enable-method = "spin-table";
68
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cpu-release-addr = <0x1 0x0000fff8>;
69
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next-level-cache = <&xgene_L2_2>;
70
-
#clock-cells = <1>;
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clocks = <&pmd2clk 0>;
72
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};
73
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cpu@300 {
···
76
82
enable-method = "spin-table";
77
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cpu-release-addr = <0x1 0x0000fff8>;
78
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next-level-cache = <&xgene_L2_3>;
79
-
#clock-cells = <1>;
80
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clocks = <&pmd3clk 0>;
81
86
};
82
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cpu@301 {
···
85
92
enable-method = "spin-table";
86
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cpu-release-addr = <0x1 0x0000fff8>;
87
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next-level-cache = <&xgene_L2_3>;
88
-
#clock-cells = <1>;
89
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clocks = <&pmd3clk 0>;
90
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};
91
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xgene_L2_0: l2-cache-0 {
···
203
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};
204
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};
205
213
206
-
refclk: refclk {
214
+
refclk: clock-100000000 {
207
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compatible = "fixed-clock";
208
-
#clock-cells = <1>;
216
+
#clock-cells = <0>;
209
217
clock-frequency = <100000000>;
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clock-output-names = "refclk";
211
219
};
···
238
246
pmdpll: pmdpll@170000f0 {
239
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compatible = "apm,xgene-pcppll-v2-clock";
240
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#clock-cells = <1>;
241
-
clocks = <&refclk 0>;
249
+
clocks = <&refclk>;
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reg = <0x0 0x170000f0 0x0 0x10>;
243
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clock-output-names = "pmdpll";
244
252
};
···
278
286
socpll: socpll@17000120 {
279
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compatible = "apm,xgene-socpll-v2-clock";
280
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#clock-cells = <1>;
281
-
clocks = <&refclk 0>;
289
+
clocks = <&refclk>;
282
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reg = <0x0 0x17000120 0x0 0x1000>;
283
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clock-output-names = "socpll";
284
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};
+25
-29
arch/arm64/boot/dts/apm/apm-storm.dtsi
+25
-29
arch/arm64/boot/dts/apm/apm-storm.dtsi
···
113
113
interrupts = <1 9 0xf04>; /* GIC Maintenence IRQ */
114
114
};
115
115
116
-
refclk: refclk {
116
+
refclk: clock-100000000 {
117
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compatible = "fixed-clock";
118
-
#clock-cells = <1>;
118
+
#clock-cells = <0>;
119
119
clock-frequency = <100000000>;
120
120
clock-output-names = "refclk";
121
121
};
···
159
159
pcppll: pcppll@17000100 {
160
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compatible = "apm,xgene-pcppll-clock";
161
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#clock-cells = <1>;
162
-
clocks = <&refclk 0>;
162
+
clocks = <&refclk>;
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clock-names = "pcppll";
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164
reg = <0x0 0x17000100 0x0 0x1000>;
165
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clock-output-names = "pcppll";
166
-
type = <0>;
167
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};
168
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169
168
socpll: socpll@17000120 {
170
169
compatible = "apm,xgene-socpll-clock";
171
170
#clock-cells = <1>;
172
-
clocks = <&refclk 0>;
171
+
clocks = <&refclk>;
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clock-names = "socpll";
174
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reg = <0x0 0x17000120 0x0 0x1000>;
175
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clock-output-names = "socpll";
176
-
type = <1>;
177
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};
178
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179
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socplldiv2: socplldiv2 {
180
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compatible = "fixed-factor-clock";
181
-
#clock-cells = <1>;
179
+
#clock-cells = <0>;
182
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clocks = <&socpll 0>;
183
-
clock-names = "socplldiv2";
184
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clock-mult = <1>;
185
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clock-div = <2>;
186
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clock-output-names = "socplldiv2";
···
186
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ahbclk: ahbclk@17000000 {
187
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compatible = "apm,xgene-device-clock";
188
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#clock-cells = <1>;
189
-
clocks = <&socplldiv2 0>;
192
+
clocks = <&socplldiv2>;
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reg = <0x0 0x17000000 0x0 0x2000>;
191
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reg-names = "div-reg";
192
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divider-offset = <0x164>;
···
198
201
sdioclk: sdioclk@1f2ac000 {
199
202
compatible = "apm,xgene-device-clock";
200
203
#clock-cells = <1>;
201
-
clocks = <&socplldiv2 0>;
204
+
clocks = <&socplldiv2>;
202
205
reg = <0x0 0x1f2ac000 0x0 0x1000
203
206
0x0 0x17000000 0x0 0x2000>;
204
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reg-names = "csr-reg", "div-reg";
···
215
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ethclk: ethclk {
216
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compatible = "apm,xgene-device-clock";
217
220
#clock-cells = <1>;
218
-
clocks = <&socplldiv2 0>;
221
+
clocks = <&socplldiv2>;
219
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clock-names = "ethclk";
220
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reg = <0x0 0x17000000 0x0 0x1000>;
221
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reg-names = "div-reg";
···
237
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sge0clk: sge0clk@1f21c000 {
238
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compatible = "apm,xgene-device-clock";
239
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#clock-cells = <1>;
240
-
clocks = <&socplldiv2 0>;
243
+
clocks = <&socplldiv2>;
241
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reg = <0x0 0x1f21c000 0x0 0x1000>;
242
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reg-names = "csr-reg";
243
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csr-mask = <0xa>;
···
248
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xge0clk: xge0clk@1f61c000 {
249
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compatible = "apm,xgene-device-clock";
250
253
#clock-cells = <1>;
251
-
clocks = <&socplldiv2 0>;
254
+
clocks = <&socplldiv2>;
252
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reg = <0x0 0x1f61c000 0x0 0x1000>;
253
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reg-names = "csr-reg";
254
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csr-mask = <0x3>;
···
259
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compatible = "apm,xgene-device-clock";
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status = "disabled";
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#clock-cells = <1>;
262
-
clocks = <&socplldiv2 0>;
265
+
clocks = <&socplldiv2>;
263
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reg = <0x0 0x1f62c000 0x0 0x1000>;
264
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reg-names = "csr-reg";
265
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csr-mask = <0x3>;
···
269
272
sataphy1clk: sataphy1clk@1f21c000 {
270
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compatible = "apm,xgene-device-clock";
271
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#clock-cells = <1>;
272
-
clocks = <&socplldiv2 0>;
275
+
clocks = <&socplldiv2>;
273
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reg = <0x0 0x1f21c000 0x0 0x1000>;
274
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reg-names = "csr-reg";
275
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clock-output-names = "sataphy1clk";
···
283
286
sataphy2clk: sataphy1clk@1f22c000 {
284
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compatible = "apm,xgene-device-clock";
285
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#clock-cells = <1>;
286
-
clocks = <&socplldiv2 0>;
289
+
clocks = <&socplldiv2>;
287
290
reg = <0x0 0x1f22c000 0x0 0x1000>;
288
291
reg-names = "csr-reg";
289
292
clock-output-names = "sataphy2clk";
···
297
300
sataphy3clk: sataphy1clk@1f23c000 {
298
301
compatible = "apm,xgene-device-clock";
299
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#clock-cells = <1>;
300
-
clocks = <&socplldiv2 0>;
303
+
clocks = <&socplldiv2>;
301
304
reg = <0x0 0x1f23c000 0x0 0x1000>;
302
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reg-names = "csr-reg";
303
306
clock-output-names = "sataphy3clk";
···
311
314
sata01clk: sata01clk@1f21c000 {
312
315
compatible = "apm,xgene-device-clock";
313
316
#clock-cells = <1>;
314
-
clocks = <&socplldiv2 0>;
317
+
clocks = <&socplldiv2>;
315
318
reg = <0x0 0x1f21c000 0x0 0x1000>;
316
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reg-names = "csr-reg";
317
320
clock-output-names = "sata01clk";
···
324
327
sata23clk: sata23clk@1f22c000 {
325
328
compatible = "apm,xgene-device-clock";
326
329
#clock-cells = <1>;
327
-
clocks = <&socplldiv2 0>;
330
+
clocks = <&socplldiv2>;
328
331
reg = <0x0 0x1f22c000 0x0 0x1000>;
329
332
reg-names = "csr-reg";
330
333
clock-output-names = "sata23clk";
···
337
340
sata45clk: sata45clk@1f23c000 {
338
341
compatible = "apm,xgene-device-clock";
339
342
#clock-cells = <1>;
340
-
clocks = <&socplldiv2 0>;
343
+
clocks = <&socplldiv2>;
341
344
reg = <0x0 0x1f23c000 0x0 0x1000>;
342
345
reg-names = "csr-reg";
343
346
clock-output-names = "sata45clk";
···
350
353
rtcclk: rtcclk@17000000 {
351
354
compatible = "apm,xgene-device-clock";
352
355
#clock-cells = <1>;
353
-
clocks = <&socplldiv2 0>;
356
+
clocks = <&socplldiv2>;
354
357
reg = <0x0 0x17000000 0x0 0x2000>;
355
358
reg-names = "csr-reg";
356
359
csr-offset = <0xc>;
···
363
366
rngpkaclk: rngpkaclk@17000000 {
364
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compatible = "apm,xgene-device-clock";
365
368
#clock-cells = <1>;
366
-
clocks = <&socplldiv2 0>;
369
+
clocks = <&socplldiv2>;
367
370
reg = <0x0 0x17000000 0x0 0x2000>;
368
371
reg-names = "csr-reg";
369
372
csr-offset = <0xc>;
···
377
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status = "disabled";
378
381
compatible = "apm,xgene-device-clock";
379
382
#clock-cells = <1>;
380
-
clocks = <&socplldiv2 0>;
383
+
clocks = <&socplldiv2>;
381
384
reg = <0x0 0x1f2bc000 0x0 0x1000>;
382
385
reg-names = "csr-reg";
383
386
clock-output-names = "pcie0clk";
···
387
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status = "disabled";
388
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compatible = "apm,xgene-device-clock";
389
392
#clock-cells = <1>;
390
-
clocks = <&socplldiv2 0>;
393
+
clocks = <&socplldiv2>;
391
394
reg = <0x0 0x1f2cc000 0x0 0x1000>;
392
395
reg-names = "csr-reg";
393
396
clock-output-names = "pcie1clk";
···
397
400
status = "disabled";
398
401
compatible = "apm,xgene-device-clock";
399
402
#clock-cells = <1>;
400
-
clocks = <&socplldiv2 0>;
403
+
clocks = <&socplldiv2>;
401
404
reg = <0x0 0x1f2dc000 0x0 0x1000>;
402
405
reg-names = "csr-reg";
403
406
clock-output-names = "pcie2clk";
···
407
410
status = "disabled";
408
411
compatible = "apm,xgene-device-clock";
409
412
#clock-cells = <1>;
410
-
clocks = <&socplldiv2 0>;
413
+
clocks = <&socplldiv2>;
411
414
reg = <0x0 0x1f50c000 0x0 0x1000>;
412
415
reg-names = "csr-reg";
413
416
clock-output-names = "pcie3clk";
···
417
420
status = "disabled";
418
421
compatible = "apm,xgene-device-clock";
419
422
#clock-cells = <1>;
420
-
clocks = <&socplldiv2 0>;
423
+
clocks = <&socplldiv2>;
421
424
reg = <0x0 0x1f51c000 0x0 0x1000>;
422
425
reg-names = "csr-reg";
423
426
clock-output-names = "pcie4clk";
···
426
429
dmaclk: dmaclk@1f27c000 {
427
430
compatible = "apm,xgene-device-clock";
428
431
#clock-cells = <1>;
429
-
clocks = <&socplldiv2 0>;
432
+
clocks = <&socplldiv2>;
430
433
reg = <0x0 0x1f27c000 0x0 0x1000>;
431
434
reg-names = "csr-reg";
432
435
clock-output-names = "dmaclk";
···
847
850
compatible = "snps,designware-i2c";
848
851
reg = <0x0 0x10512000 0x0 0x1000>;
849
852
interrupts = <0 0x44 0x4>;
850
-
#clock-cells = <1>;
851
853
clocks = <&ahbclk 0>;
852
854
};
853
855