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Merge tag 'soc-newsoc-6.19' of git://git.kernel.org/pub/scm/linux/kernel/git/soc/soc

Pull new SoC families update from Arnd Bergmann:
"These three new families of SoC are split out into a separate branch
because they touch multiple parts of the source tree and are better
left separate for the initial merge.

- Black Sesame Technologies C1200 is an automotive SoC using
Cortex-A78 CPU cores

- Anlogic dr1v90 (not to be confused with Amlogic) is an FPGA
platform using a single nuclei ux900 RISC-V core

- Tenstorrent Blackhole is a Neural Processing Unit using custom
"Tensix" cores for computation offload managed by Linux running on
SiFive X280 RISC-V cores.

Support for all three is rather rudimentary at the moment and will get
improved as device drivers are merged through other tree"

* tag 'soc-newsoc-6.19' of git://git.kernel.org/pub/scm/linux/kernel/git/soc/soc: (24 commits)
MAINTAINERS: add Black Sesame Technologies (BST) ARM SoC support
arm64: defconfig: enable BST platform support
arm64: dts: bst: add support for Black Sesame Technologies C1200 CDCU1.0 board
arm64: Kconfig: add ARCH_BST for Black Sesame Technologies SoCs
dt-bindings: arm: add Black Sesame Technologies (bst) SoC
dt-bindings: vendor-prefixes: Add Black Sesame Technologies Co., Ltd.
MAINTAINERS: Setup support for Anlogic tree
riscv: defconfig: Enable Anlogic SoC
riscv: dts: anlogic: Add Milianke MLKPAI FS01 board
riscv: dts: Add initial Anlogic DR1V90 SoC device tree
riscv: Add Anlogic SoC famly Kconfig support
dt-bindings: serial: snps-dw-apb-uart: Add Anlogic DR1V90 uart
dt-bindings: timer: Add Anlogic DR1V90 ACLINT MTIMER
dt-bindings: riscv: Add Anlogic DR1V90
dt-bindings: riscv: Add Nuclei UX900 compatibles
dt-bindings: vendor-prefixes: Add Anlogic, Milianke and Nuclei
riscv: defconfig: Enable Tenstorrent SoCs
riscv: Kconfig.socs: Add ARCH_TENSTORRENT for Tenstorrent SoCs
riscv: dts: Add Tenstorrent Blackhole SoC PCIe cards
dt-bindings: interrupt-controller: Add Tenstorrent Blackhole compatible
...

+541 -6
+31
Documentation/devicetree/bindings/arm/bst.yaml
··· 1 + # SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause 2 + %YAML 1.2 3 + --- 4 + $id: http://devicetree.org/schemas/arm/bst.yaml# 5 + $schema: http://devicetree.org/meta-schemas/core.yaml# 6 + 7 + title: BST platforms 8 + 9 + description: 10 + Black Sesame Technologies (BST) is a semiconductor company that produces 11 + automotive-grade system-on-chips (SoCs) for intelligent driving, focusing 12 + on computer vision and AI capabilities. The BST C1200 family includes SoCs 13 + for ADAS (Advanced Driver Assistance Systems) and autonomous driving 14 + applications. 15 + 16 + maintainers: 17 + - Ge Gordon <gordon.ge@bst.ai> 18 + 19 + properties: 20 + $nodename: 21 + const: '/' 22 + compatible: 23 + oneOf: 24 + - description: BST C1200 CDCU1.0 ADAS 4C2G board 25 + items: 26 + - const: bst,c1200-cdcu1.0-adas-4c2g 27 + - const: bst,c1200 28 + 29 + additionalProperties: true 30 + 31 + ...
+1
Documentation/devicetree/bindings/interrupt-controller/sifive,plic-1.0.0.yaml
··· 66 66 - spacemit,k1-plic 67 67 - starfive,jh7100-plic 68 68 - starfive,jh7110-plic 69 + - tenstorrent,blackhole-plic 69 70 - const: sifive,plic-1.0.0 70 71 - items: 71 72 - enum:
+27
Documentation/devicetree/bindings/riscv/anlogic.yaml
··· 1 + # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) 2 + %YAML 1.2 3 + --- 4 + $id: http://devicetree.org/schemas/riscv/anlogic.yaml# 5 + $schema: http://devicetree.org/meta-schemas/core.yaml# 6 + 7 + title: Anlogic SoC-based boards 8 + 9 + maintainers: 10 + - Junhui Liu <junhui.liu@pigmoral.tech> 11 + 12 + description: 13 + Anlogic SoC-based boards 14 + 15 + properties: 16 + $nodename: 17 + const: '/' 18 + compatible: 19 + oneOf: 20 + - items: 21 + - enum: 22 + - milianke,mlkpai-fs01 23 + - const: anlogic,dr1v90 24 + 25 + additionalProperties: true 26 + 27 + ...
+2
Documentation/devicetree/bindings/riscv/cpus.yaml
··· 48 48 - amd,mbv64 49 49 - andestech,ax45mp 50 50 - canaan,k210 51 + - nuclei,ux900 51 52 - sifive,bullet0 52 53 - sifive,e5 53 54 - sifive,e7 ··· 71 70 - enum: 72 71 - sifive,e51 73 72 - sifive,u54-mc 73 + - sifive,x280 74 74 - const: sifive,rocket0 75 75 - const: riscv 76 76 - const: riscv # Simulator only
+28
Documentation/devicetree/bindings/riscv/tenstorrent.yaml
··· 1 + # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) 2 + %YAML 1.2 3 + --- 4 + $id: http://devicetree.org/schemas/riscv/tenstorrent.yaml# 5 + $schema: http://devicetree.org/meta-schemas/core.yaml# 6 + 7 + title: Tenstorrent SoC-based boards 8 + 9 + maintainers: 10 + - Drew Fustini <dfustini@oss.tenstorrent.com> 11 + - Joel Stanley <jms@oss.tenstorrent.com> 12 + 13 + description: 14 + Tenstorrent SoC-based boards 15 + 16 + properties: 17 + $nodename: 18 + const: '/' 19 + compatible: 20 + oneOf: 21 + - description: Tenstorrent Blackhole PCIe card 22 + items: 23 + - const: tenstorrent,blackhole-card 24 + - const: tenstorrent,blackhole 25 + 26 + additionalProperties: true 27 + 28 + ...
+1
Documentation/devicetree/bindings/serial/snps-dw-apb-uart.yaml
··· 51 51 - const: renesas,rzn1-uart 52 52 - items: 53 53 - enum: 54 + - anlogic,dr1v90-uart 54 55 - brcm,bcm11351-dw-apb-uart 55 56 - brcm,bcm21664-dw-apb-uart 56 57 - rockchip,px30-uart
+1
Documentation/devicetree/bindings/timer/sifive,clint.yaml
··· 36 36 - starfive,jh7100-clint # StarFive JH7100 37 37 - starfive,jh7110-clint # StarFive JH7110 38 38 - starfive,jh8100-clint # StarFive JH8100 39 + - tenstorrent,blackhole-clint # Tenstorrent Blackhole 39 40 - const: sifive,clint0 # SiFive CLINT v0 IP block 40 41 - items: 41 42 - {}
+11 -6
Documentation/devicetree/bindings/timer/thead,c900-aclint-mtimer.yaml
··· 4 4 $id: http://devicetree.org/schemas/timer/thead,c900-aclint-mtimer.yaml# 5 5 $schema: http://devicetree.org/meta-schemas/core.yaml# 6 6 7 - title: Sophgo CLINT Timer 7 + title: ACLINT Machine-level Timer Device 8 8 9 9 maintainers: 10 10 - Inochi Amaoto <inochiama@outlook.com> 11 11 12 12 properties: 13 13 compatible: 14 - items: 15 - - enum: 16 - - sophgo,sg2042-aclint-mtimer 17 - - sophgo,sg2044-aclint-mtimer 18 - - const: thead,c900-aclint-mtimer 14 + oneOf: 15 + - items: 16 + - enum: 17 + - sophgo,sg2042-aclint-mtimer 18 + - sophgo,sg2044-aclint-mtimer 19 + - const: thead,c900-aclint-mtimer 20 + - items: 21 + - enum: 22 + - anlogic,dr1v90-aclint-mtimer 23 + - const: nuclei,ux900-aclint-mtimer 19 24 20 25 reg: 21 26 items:
+10
Documentation/devicetree/bindings/vendor-prefixes.yaml
··· 134 134 description: Anbernic 135 135 "^andestech,.*": 136 136 description: Andes Technology Corporation 137 + "^anlogic,.*": 138 + description: Shanghai Anlogic Infotech Co., Ltd. 137 139 "^anvo,.*": 138 140 description: Anvo-Systems Dresden GmbH 139 141 "^aoly,.*": ··· 257 255 description: Shanghai Broadmobi Communication Technology Co.,Ltd. 258 256 "^bsh,.*": 259 257 description: BSH Hausgeraete GmbH 258 + "^bst,.*": 259 + description: Black Sesame Technologies Co., Ltd. 260 260 "^bticino,.*": 261 261 description: Bticino International 262 262 "^buffalo,.*": ··· 1037 1033 description: MikroElektronika d.o.o. 1038 1034 "^mikrotik,.*": 1039 1035 description: MikroTik 1036 + "^milianke,.*": 1037 + description: Changzhou Milianke Electronic Technology Co., Ltd 1040 1038 "^milkv,.*": 1041 1039 description: MilkV Technology Co., Ltd 1042 1040 "^miniand,.*": ··· 1156 1150 description: Novatek 1157 1151 "^novtech,.*": 1158 1152 description: NovTech, Inc. 1153 + "^nuclei,.*": 1154 + description: Nuclei System Technology 1159 1155 "^numonyx,.*": 1160 1156 description: Numonyx (deprecated, use micron) 1161 1157 deprecated: true ··· 1630 1622 description: Tempo Semiconductor 1631 1623 "^tenda,.*": 1632 1624 description: Shenzhen Tenda Technology Co., Ltd. 1625 + "^tenstorrent,.*": 1626 + description: Tenstorrent AI ULC 1633 1627 "^terasic,.*": 1634 1628 description: Terasic Inc. 1635 1629 "^tesla,.*":
+25
MAINTAINERS
··· 2575 2575 F: Documentation/devicetree/bindings/arm/blaize.yaml 2576 2576 F: arch/arm64/boot/dts/blaize/ 2577 2577 2578 + ARM/BST SOC SUPPORT 2579 + M: Ge Gordon <gordon.ge@bst.ai> 2580 + R: BST Linux Kernel Upstream Group <bst-upstream@bstai.top> 2581 + L: linux-arm-kernel@lists.infradead.org (moderated for non-subscribers) 2582 + S: Supported 2583 + F: Documentation/devicetree/bindings/arm/bst.yaml 2584 + F: arch/arm64/boot/dts/bst/ 2585 + 2578 2586 ARM/CALXEDA HIGHBANK ARCHITECTURE 2579 2587 M: Andre Przywara <andre.przywara@arm.com> 2580 2588 L: linux-arm-kernel@lists.infradead.org (moderated for non-subscribers) ··· 22283 22275 F: Documentation/devicetree/bindings/timer/andestech,plmt0.yaml 22284 22276 F: arch/riscv/boot/dts/andes/ 22285 22277 22278 + RISC-V ANLOGIC SoC SUPPORT 22279 + M: Conor Dooley <conor@kernel.org> 22280 + T: git https://git.kernel.org/pub/scm/linux/kernel/git/conor/linux.git/ 22281 + L: linux-riscv@lists.infradead.org 22282 + S: Odd Fixes 22283 + F: Documentation/devicetree/bindings/riscv/anlogic.yaml 22284 + F: arch/riscv/boot/dts/anlogic/ 22285 + 22286 22286 RISC-V ARCHITECTURE 22287 22287 M: Paul Walmsley <pjw@kernel.org> 22288 22288 M: Palmer Dabbelt <palmer@dabbelt.com> ··· 22391 22375 F: arch/riscv/boot/dts/spacemit/ 22392 22376 N: spacemit 22393 22377 K: spacemit 22378 + 22379 + RISC-V TENSTORRENT SoC SUPPORT 22380 + M: Drew Fustini <dfustini@oss.tenstorrent.com> 22381 + M: Joel Stanley <jms@oss.tenstorrent.com> 22382 + L: linux-riscv@lists.infradead.org 22383 + S: Maintained 22384 + T: git https://github.com/tenstorrent/linux.git 22385 + F: Documentation/devicetree/bindings/riscv/tenstorrent.yaml 22386 + F: arch/riscv/boot/dts/tenstorrent/ 22394 22387 22395 22388 RISC-V THEAD SoC SUPPORT 22396 22389 M: Drew Fustini <fustini@kernel.org>
+8
arch/arm64/Kconfig.platforms
··· 119 119 help 120 120 This enables support for the Blaize SoC family 121 121 122 + config ARCH_BST 123 + bool "Black Sesame Technologies SoC Family" 124 + help 125 + This enables support for Black Sesame Technologies (BST) SoC family. 126 + BST produces automotive-grade system-on-chips for intelligent driving, 127 + focusing on computer vision and AI capabilities. The BST C1200 family 128 + includes SoCs for ADAS and autonomous driving applications. 129 + 122 130 config ARCH_CIX 123 131 bool "Cixtech SoC family" 124 132 help
+1
arch/arm64/boot/dts/Makefile
··· 13 13 subdir-y += bitmain 14 14 subdir-y += blaize 15 15 subdir-y += broadcom 16 + subdir-y += bst 16 17 subdir-y += cavium 17 18 subdir-y += cix 18 19 subdir-y += exynos
+2
arch/arm64/boot/dts/bst/Makefile
··· 1 + # SPDX-License-Identifier: GPL-2.0 2 + dtb-$(CONFIG_ARCH_BST) += bstc1200-cdcu1.0-adas_4c2g.dtb
+24
arch/arm64/boot/dts/bst/bstc1200-cdcu1.0-adas_4c2g.dts
··· 1 + // SPDX-License-Identifier: GPL-2.0 2 + /dts-v1/; 3 + 4 + #include "bstc1200.dtsi" 5 + 6 + / { 7 + model = "BST C1200-96 CDCU1.0 4C2G"; 8 + compatible = "bst,c1200-cdcu1.0-adas-4c2g", "bst,c1200"; 9 + 10 + chosen { 11 + stdout-path = "serial0:115200n8"; 12 + }; 13 + 14 + memory@810000000 { 15 + device_type = "memory"; 16 + reg = <0x8 0x10000000 0x0 0x30000000>, 17 + <0x8 0xc0000000 0x1 0x0>, 18 + <0xc 0x00000000 0x0 0x40000000>; 19 + }; 20 + }; 21 + 22 + &uart0 { 23 + status = "okay"; 24 + };
+97
arch/arm64/boot/dts/bst/bstc1200.dtsi
··· 1 + // SPDX-License-Identifier: GPL-2.0 2 + #include <dt-bindings/interrupt-controller/arm-gic.h> 3 + #include <dt-bindings/interrupt-controller/irq.h> 4 + 5 + / { 6 + compatible = "bst,c1200"; 7 + #address-cells = <2>; 8 + #size-cells = <2>; 9 + 10 + cpus { 11 + #address-cells = <1>; 12 + #size-cells = <0>; 13 + 14 + cpu@0 { 15 + device_type = "cpu"; 16 + compatible = "arm,cortex-a78"; 17 + reg = <0x0>; 18 + enable-method = "psci"; 19 + next-level-cache = <&l2_cache>; 20 + }; 21 + 22 + cpu@1 { 23 + device_type = "cpu"; 24 + compatible = "arm,cortex-a78"; 25 + reg = <0x100>; 26 + enable-method = "psci"; 27 + next-level-cache = <&l2_cache>; 28 + }; 29 + 30 + cpu@2 { 31 + device_type = "cpu"; 32 + compatible = "arm,cortex-a78"; 33 + reg = <0x200>; 34 + enable-method = "psci"; 35 + next-level-cache = <&l2_cache>; 36 + }; 37 + 38 + cpu@3 { 39 + device_type = "cpu"; 40 + compatible = "arm,cortex-a78"; 41 + reg = <0x300>; 42 + enable-method = "psci"; 43 + next-level-cache = <&l2_cache>; 44 + }; 45 + 46 + l2_cache: l2-cache { 47 + compatible = "cache"; 48 + cache-level = <2>; 49 + cache-unified; 50 + }; 51 + }; 52 + 53 + psci { 54 + compatible = "arm,psci-1.0"; 55 + method = "smc"; 56 + }; 57 + 58 + soc { 59 + compatible = "simple-bus"; 60 + ranges; 61 + #address-cells = <2>; 62 + #size-cells = <2>; 63 + interrupt-parent = <&gic>; 64 + 65 + uart0: serial@20008000 { 66 + compatible = "snps,dw-apb-uart"; 67 + reg = <0x0 0x20008000 0x0 0x1000>; 68 + clock-frequency = <25000000>; 69 + interrupts = <GIC_SPI 211 IRQ_TYPE_LEVEL_HIGH>; 70 + reg-shift = <2>; 71 + reg-io-width = <4>; 72 + status = "disabled"; 73 + }; 74 + 75 + gic: interrupt-controller@32800000 { 76 + compatible = "arm,gic-v3"; 77 + reg = <0x0 0x32800000 0x0 0x10000>, 78 + <0x0 0x32880000 0x0 0x100000>; 79 + ranges; 80 + #address-cells = <2>; 81 + #size-cells = <2>; 82 + #interrupt-cells = <3>; 83 + interrupt-controller; 84 + interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_LOW>; 85 + }; 86 + }; 87 + 88 + timer { 89 + compatible = "arm,armv8-timer"; 90 + always-on; 91 + interrupt-parent = <&gic>; 92 + interrupts = <GIC_PPI 13 IRQ_TYPE_LEVEL_LOW>, 93 + <GIC_PPI 14 IRQ_TYPE_LEVEL_LOW>, 94 + <GIC_PPI 11 IRQ_TYPE_LEVEL_LOW>, 95 + <GIC_PPI 10 IRQ_TYPE_LEVEL_LOW>; 96 + }; 97 + };
+1
arch/arm64/configs/defconfig
··· 47 47 CONFIG_ARCH_BRCMSTB=y 48 48 CONFIG_ARCH_BERLIN=y 49 49 CONFIG_ARCH_BLAIZE=y 50 + CONFIG_ARCH_BST=y 50 51 CONFIG_ARCH_CIX=y 51 52 CONFIG_ARCH_EXYNOS=y 52 53 CONFIG_ARCH_SPARX5=y
+13
arch/riscv/Kconfig.socs
··· 7 7 help 8 8 This enables support for Andes SoC platform hardware. 9 9 10 + config ARCH_ANLOGIC 11 + bool "Anlogic SoCs" 12 + help 13 + This enables support for Anlogic SoC platform hardware. 14 + 10 15 config ARCH_ESWIN 11 16 bool "ESWIN SoCs" 12 17 help ··· 67 62 help 68 63 This enables support for Allwinner sun20i platform hardware, 69 64 including boards based on the D1 and D1s SoCs. 65 + 66 + config ARCH_TENSTORRENT 67 + bool "Tenstorrent SoCs" 68 + help 69 + This enables support for Tenstorrent SoC platforms. 70 + Current support is for Blackhole P100 and P150 PCIe cards. 71 + The Blackhole SoC contains four RISC-V CPU tiles each 72 + consisting of 4x SiFive X280 cores. 70 73 71 74 config ARCH_THEAD 72 75 bool "T-HEAD RISC-V SoCs"
+2
arch/riscv/boot/dts/Makefile
··· 1 1 # SPDX-License-Identifier: GPL-2.0 2 2 subdir-y += allwinner 3 3 subdir-y += andes 4 + subdir-y += anlogic 4 5 subdir-y += canaan 5 6 subdir-y += eswin 6 7 subdir-y += microchip ··· 10 9 subdir-y += sophgo 11 10 subdir-y += spacemit 12 11 subdir-y += starfive 12 + subdir-y += tenstorrent 13 13 subdir-y += thead
+2
arch/riscv/boot/dts/anlogic/Makefile
··· 1 + # SPDX-License-Identifier: GPL-2.0 2 + dtb-$(CONFIG_ARCH_ANLOGIC) += dr1v90-mlkpai-fs01.dtb
+28
arch/riscv/boot/dts/anlogic/dr1v90-mlkpai-fs01.dts
··· 1 + // SPDX-License-Identifier: GPL-2.0 OR MIT 2 + /* 3 + * Copyright (C) 2025 Junhui Liu <junhui.liu@pigmoral.tech> 4 + */ 5 + 6 + #include "dr1v90.dtsi" 7 + 8 + / { 9 + model = "Milianke MLKPAI-FS01"; 10 + compatible = "milianke,mlkpai-fs01", "anlogic,dr1v90"; 11 + 12 + aliases { 13 + serial0 = &uart1; 14 + }; 15 + 16 + chosen { 17 + stdout-path = "serial0:115200n8"; 18 + }; 19 + 20 + memory@0 { 21 + device_type = "memory"; 22 + reg = <0x0 0x0 0x0 0x20000000>; 23 + }; 24 + }; 25 + 26 + &uart1 { 27 + status = "okay"; 28 + };
+100
arch/riscv/boot/dts/anlogic/dr1v90.dtsi
··· 1 + // SPDX-License-Identifier: GPL-2.0 OR MIT 2 + /* 3 + * Copyright (C) 2025 Junhui Liu <junhui.liu@pigmoral.tech> 4 + */ 5 + 6 + /dts-v1/; 7 + / { 8 + #address-cells = <2>; 9 + #size-cells = <2>; 10 + model = "Anlogic DR1V90"; 11 + compatible = "anlogic,dr1v90"; 12 + 13 + cpus { 14 + #address-cells = <1>; 15 + #size-cells = <0>; 16 + timebase-frequency = <800000000>; 17 + 18 + cpu@0 { 19 + compatible = "nuclei,ux900", "riscv"; 20 + d-cache-block-size = <64>; 21 + d-cache-sets = <256>; 22 + d-cache-size = <32768>; 23 + device_type = "cpu"; 24 + i-cache-block-size = <64>; 25 + i-cache-sets = <256>; 26 + i-cache-size = <32768>; 27 + mmu-type = "riscv,sv39"; 28 + reg = <0>; 29 + riscv,isa-base = "rv64i"; 30 + riscv,isa-extensions = "i", "m", "a", "f", "d", "c", "zba", "zbb", "zbc", 31 + "zbkc", "zbs", "zicntr", "zicsr", "zifencei", 32 + "zihintpause", "zihpm"; 33 + 34 + cpu0_intc: interrupt-controller { 35 + compatible = "riscv,cpu-intc"; 36 + #interrupt-cells = <1>; 37 + interrupt-controller; 38 + }; 39 + }; 40 + }; 41 + 42 + soc { 43 + compatible = "simple-bus"; 44 + interrupt-parent = <&plic>; 45 + #address-cells = <2>; 46 + #size-cells = <2>; 47 + ranges; 48 + 49 + aclint_mswi: interrupt-controller@68031000 { 50 + compatible = "anlogic,dr1v90-aclint-mswi", "nuclei,ux900-aclint-mswi"; 51 + reg = <0x0 0x68031000 0x0 0x4000>; 52 + interrupts-extended = <&cpu0_intc 3>; 53 + }; 54 + 55 + aclint_mtimer: timer@68035000 { 56 + compatible = "anlogic,dr1v90-aclint-mtimer", "nuclei,ux900-aclint-mtimer"; 57 + reg = <0x0 0x68035000 0x0 0x8000>; 58 + reg-names = "mtimecmp"; 59 + interrupts-extended = <&cpu0_intc 7>; 60 + }; 61 + 62 + aclint_sswi: interrupt-controller@6803d000 { 63 + compatible = "anlogic,dr1v90-aclint-sswi", "nuclei,ux900-aclint-sswi"; 64 + reg = <0x0 0x6803d000 0x0 0x3000>; 65 + #interrupt-cells = <0>; 66 + interrupt-controller; 67 + interrupts-extended = <&cpu0_intc 1>; 68 + }; 69 + 70 + plic: interrupt-controller@6c000000 { 71 + compatible = "anlogic,dr1v90-plic", "sifive,plic-1.0.0"; 72 + reg = <0x0 0x6c000000 0x0 0x4000000>; 73 + #address-cells = <0>; 74 + #interrupt-cells = <1>; 75 + interrupt-controller; 76 + interrupts-extended = <&cpu0_intc 11>, <&cpu0_intc 9>; 77 + riscv,ndev = <150>; 78 + }; 79 + 80 + uart0: serial@f8400000 { 81 + compatible = "anlogic,dr1v90-uart", "snps,dw-apb-uart"; 82 + reg = <0x0 0xf8400000 0x0 0x1000>; 83 + clock-frequency = <50000000>; 84 + interrupts = <71>; 85 + reg-io-width = <4>; 86 + reg-shift = <2>; 87 + status = "disabled"; 88 + }; 89 + 90 + uart1: serial@f8401000 { 91 + compatible = "anlogic,dr1v90-uart", "snps,dw-apb-uart"; 92 + reg = <0x0 0xf8401000 0x0 0x1000>; 93 + clock-frequency = <50000000>; 94 + interrupts = <72>; 95 + reg-io-width = <4>; 96 + reg-shift = <2>; 97 + status = "disabled"; 98 + }; 99 + }; 100 + };
+2
arch/riscv/boot/dts/tenstorrent/Makefile
··· 1 + # SPDX-License-Identifier: GPL-2.0 2 + dtb-$(CONFIG_ARCH_TENSTORRENT) += blackhole-card.dtb
+14
arch/riscv/boot/dts/tenstorrent/blackhole-card.dts
··· 1 + // SPDX-License-Identifier: (GPL-2.0 OR MIT) 2 + /dts-v1/; 3 + 4 + #include "blackhole.dtsi" 5 + 6 + / { 7 + model = "Tenstorrent Blackhole"; 8 + compatible = "tenstorrent,blackhole-card", "tenstorrent,blackhole"; 9 + 10 + memory@400030000000 { 11 + device_type = "memory"; 12 + reg = <0x4000 0x30000000 0x1 0x00000000>; 13 + }; 14 + };
+108
arch/riscv/boot/dts/tenstorrent/blackhole.dtsi
··· 1 + // SPDX-License-Identifier: (GPL-2.0 OR MIT) 2 + // Copyright 2025 Tenstorrent AI ULC 3 + /dts-v1/; 4 + 5 + / { 6 + compatible = "tenstorrent,blackhole"; 7 + #address-cells = <2>; 8 + #size-cells = <2>; 9 + 10 + cpus { 11 + #address-cells = <1>; 12 + #size-cells = <0>; 13 + timebase-frequency = <50000000>; 14 + 15 + cpu@0 { 16 + compatible = "sifive,x280", "sifive,rocket0", "riscv"; 17 + device_type = "cpu"; 18 + reg = <0>; 19 + mmu-type = "riscv,sv57"; 20 + riscv,isa-base = "rv64i"; 21 + riscv,isa-extensions = "i", "m", "a", "f", "d", "c", "v", "zicsr", 22 + "zifencei", "zfh", "zba", "zbb", "sscofpmf"; 23 + 24 + cpu0_intc: interrupt-controller { 25 + compatible = "riscv,cpu-intc"; 26 + #interrupt-cells = <1>; 27 + interrupt-controller; 28 + }; 29 + }; 30 + 31 + cpu@1 { 32 + compatible = "sifive,x280", "sifive,rocket0", "riscv"; 33 + device_type = "cpu"; 34 + reg = <1>; 35 + mmu-type = "riscv,sv57"; 36 + riscv,isa-base = "rv64i"; 37 + riscv,isa-extensions = "i", "m", "a", "f", "d", "c", "v", "zicsr", 38 + "zifencei", "zfh", "zba", "zbb", "sscofpmf"; 39 + 40 + cpu1_intc: interrupt-controller { 41 + compatible = "riscv,cpu-intc"; 42 + #interrupt-cells = <1>; 43 + interrupt-controller; 44 + }; 45 + }; 46 + 47 + cpu@2 { 48 + compatible = "sifive,x280", "sifive,rocket0", "riscv"; 49 + device_type = "cpu"; 50 + reg = <2>; 51 + mmu-type = "riscv,sv57"; 52 + riscv,isa-base = "rv64i"; 53 + riscv,isa-extensions = "i", "m", "a", "f", "d", "c", "v", "zicsr", 54 + "zifencei", "zfh", "zba", "zbb", "sscofpmf"; 55 + 56 + cpu2_intc: interrupt-controller { 57 + compatible = "riscv,cpu-intc"; 58 + #interrupt-cells = <1>; 59 + interrupt-controller; 60 + }; 61 + }; 62 + 63 + cpu@3 { 64 + compatible = "sifive,x280", "sifive,rocket0", "riscv"; 65 + device_type = "cpu"; 66 + reg = <3>; 67 + mmu-type = "riscv,sv57"; 68 + riscv,isa-base = "rv64i"; 69 + riscv,isa-extensions = "i", "m", "a", "f", "d", "c", "v", "zicsr", 70 + "zifencei", "zfh", "zba", "zbb", "sscofpmf"; 71 + 72 + cpu3_intc: interrupt-controller { 73 + compatible = "riscv,cpu-intc"; 74 + #interrupt-cells = <1>; 75 + interrupt-controller; 76 + }; 77 + }; 78 + }; 79 + 80 + soc { 81 + #address-cells = <2>; 82 + #size-cells = <2>; 83 + compatible = "simple-bus"; 84 + ranges; 85 + 86 + clint0: timer@2000000 { 87 + compatible = "tenstorrent,blackhole-clint", "sifive,clint0"; 88 + reg = <0x0 0x2000000 0x0 0x10000>; 89 + interrupts-extended = <&cpu0_intc 0x3>, <&cpu0_intc 0x7>, 90 + <&cpu1_intc 0x3>, <&cpu1_intc 0x7>, 91 + <&cpu2_intc 0x3>, <&cpu2_intc 0x7>, 92 + <&cpu3_intc 0x3>, <&cpu3_intc 0x7>; 93 + }; 94 + 95 + plic0: interrupt-controller@c000000 { 96 + compatible = "tenstorrent,blackhole-plic", "sifive,plic-1.0.0"; 97 + reg = <0x0 0x0c000000 0x0 0x04000000>; 98 + interrupts-extended = <&cpu0_intc 11>, <&cpu0_intc 9>, 99 + <&cpu1_intc 11>, <&cpu1_intc 9>, 100 + <&cpu2_intc 11>, <&cpu2_intc 9>, 101 + <&cpu3_intc 11>, <&cpu3_intc 9>; 102 + interrupt-controller; 103 + #interrupt-cells = <1>; 104 + #address-cells = <0>; 105 + riscv,ndev = <128>; 106 + }; 107 + }; 108 + };
+2
arch/riscv/configs/defconfig
··· 23 23 CONFIG_BLK_DEV_INITRD=y 24 24 CONFIG_PROFILING=y 25 25 CONFIG_ARCH_ANDES=y 26 + CONFIG_ARCH_ANLOGIC=y 26 27 CONFIG_ARCH_MICROCHIP=y 27 28 CONFIG_ARCH_SIFIVE=y 28 29 CONFIG_ARCH_SOPHGO=y 29 30 CONFIG_ARCH_SPACEMIT=y 30 31 CONFIG_SOC_STARFIVE=y 31 32 CONFIG_ARCH_SUNXI=y 33 + CONFIG_ARCH_TENSTORRENT=y 32 34 CONFIG_ARCH_THEAD=y 33 35 CONFIG_ARCH_VIRT=y 34 36 CONFIG_ARCH_CANAAN=y