Linux kernel mirror (for testing)
git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git
kernel
os
linux
clk: renesas: r9a09g057: Add clock and reset entries for DSI and LCDC
Add clock and reset entries for the DSI and LCDC peripherals.
Co-developed-by: Fabrizio Castro <fabrizio.castro.jz@renesas.com>
Signed-off-by: Fabrizio Castro <fabrizio.castro.jz@renesas.com>
Signed-off-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
Reviewed-by: Biju Das <biju.das.jz@bp.renesas.com>
Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be>
Link: https://patch.msgid.link/20251015192611.241920-5-prabhakar.mahadev-lad.rj@bp.renesas.com
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
authored by
Lad Prabhakar
and committed by
Geert Uytterhoeven
66a470ab
d67c39be
+65
+62
drivers/clk/renesas/r9a09g057-cpg.c
+62
drivers/clk/renesas/r9a09g057-cpg.c
···
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*/
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#include <linux/clk-provider.h>
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+
#include <linux/clk/renesas.h>
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#include <linux/device.h>
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#include <linux/init.h>
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#include <linux/kernel.h>
···
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CLK_PLLCA55,
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CLK_PLLVDO,
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CLK_PLLETH,
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CLK_PLLDSI,
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CLK_PLLGPU,
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/* Internal Core Clocks */
···
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CLK_SMUX2_GBE0_RXCLK,
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CLK_SMUX2_GBE1_TXCLK,
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CLK_SMUX2_GBE1_RXCLK,
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CLK_CDIV4_PLLETH_LPCLK,
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CLK_PLLETH_LPCLK_GEAR,
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CLK_PLLDSI_GEAR,
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CLK_PLLGPU_GEAR,
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/* Module Clocks */
···
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{0, 0},
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};
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static const struct clk_div_table dtable_2_32[] = {
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{0, 2},
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{1, 4},
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{2, 6},
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{3, 8},
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{4, 10},
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{5, 12},
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{6, 14},
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{7, 16},
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{8, 18},
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{9, 20},
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{10, 22},
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{11, 24},
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{12, 26},
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{13, 28},
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{14, 30},
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{15, 32},
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{0, 0},
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};
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static const struct clk_div_table dtable_2_64[] = {
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{0, 2},
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{1, 4},
···
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{2, 100},
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{0, 0},
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};
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+
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static const struct clk_div_table dtable_16_128[] = {
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{0, 16},
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{1, 32},
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{2, 64},
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{3, 128},
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{0, 0},
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};
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RZV2H_CPG_PLL_DSI_LIMITS(rzv2h_cpg_pll_dsi_limits);
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#define PLLDSI PLL_PACK_LIMITS(0xc0, 1, 0, &rzv2h_cpg_pll_dsi_limits)
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/* Mux clock tables */
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static const char * const smux2_gbe0_rxclk[] = { ".plleth_gbe0", "et0_rxclk" };
···
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DEF_PLL(".pllca55", CLK_PLLCA55, CLK_QEXTAL, PLLCA55),
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DEF_FIXED(".pllvdo", CLK_PLLVDO, CLK_QEXTAL, 105, 2),
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DEF_FIXED(".plleth", CLK_PLLETH, CLK_QEXTAL, 125, 3),
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DEF_PLLDSI(".plldsi", CLK_PLLDSI, CLK_QEXTAL, PLLDSI),
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DEF_PLL(".pllgpu", CLK_PLLGPU, CLK_QEXTAL, PLLGPU),
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/* Internal Core Clocks */
···
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DEF_SMUX(".smux2_gbe0_rxclk", CLK_SMUX2_GBE0_RXCLK, SSEL0_SELCTL3, smux2_gbe0_rxclk),
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DEF_SMUX(".smux2_gbe1_txclk", CLK_SMUX2_GBE1_TXCLK, SSEL1_SELCTL0, smux2_gbe1_txclk),
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DEF_SMUX(".smux2_gbe1_rxclk", CLK_SMUX2_GBE1_RXCLK, SSEL1_SELCTL1, smux2_gbe1_rxclk),
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DEF_FIXED(".cdiv4_plleth_lpclk", CLK_CDIV4_PLLETH_LPCLK, CLK_PLLETH, 1, 4),
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DEF_CSDIV(".plleth_lpclk_gear", CLK_PLLETH_LPCLK_GEAR, CLK_CDIV4_PLLETH_LPCLK,
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CSDIV0_DIVCTL2, dtable_16_128),
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DEF_PLLDSI_DIV(".plldsi_gear", CLK_PLLDSI_GEAR, CLK_PLLDSI,
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CSDIV1_DIVCTL2, dtable_2_32),
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DEF_DDIV(".pllgpu_gear", CLK_PLLGPU_GEAR, CLK_PLLGPU, CDDIV3_DIVCTL1, dtable_2_64),
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···
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383
BUS_MSTOP(9, BIT(9))),
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384
DEF_MOD("isp_0_isp_sclk", CLK_PLLVDO_ISP, 14, 5, 7, 5,
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BUS_MSTOP(9, BIT(9))),
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DEF_MOD("dsi_0_pclk", CLK_PLLDTY_DIV16, 14, 8, 7, 8,
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BUS_MSTOP(9, BIT(14) | BIT(15))),
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DEF_MOD("dsi_0_aclk", CLK_PLLDTY_ACPU_DIV2, 14, 9, 7, 9,
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BUS_MSTOP(9, BIT(14) | BIT(15))),
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DEF_MOD("dsi_0_vclk1", CLK_PLLDSI_GEAR, 14, 10, 7, 10,
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BUS_MSTOP(9, BIT(14) | BIT(15))),
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DEF_MOD("dsi_0_lpclk", CLK_PLLETH_LPCLK_GEAR, 14, 11, 7, 11,
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BUS_MSTOP(9, BIT(14) | BIT(15))),
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DEF_MOD("dsi_0_pllref_clk", CLK_QEXTAL, 14, 12, 7, 12,
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BUS_MSTOP(9, BIT(14) | BIT(15))),
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DEF_MOD("lcdc_0_clk_a", CLK_PLLDTY_ACPU_DIV2, 14, 13, 7, 13,
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BUS_MSTOP(10, BIT(1) | BIT(2) | BIT(3))),
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DEF_MOD("lcdc_0_clk_p", CLK_PLLDTY_DIV16, 14, 14, 7, 14,
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BUS_MSTOP(10, BIT(1) | BIT(2) | BIT(3))),
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DEF_MOD("lcdc_0_clk_d", CLK_PLLDSI_GEAR, 14, 15, 7, 15,
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BUS_MSTOP(10, BIT(1) | BIT(2) | BIT(3))),
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DEF_MOD("gpu_0_clk", CLK_PLLGPU_GEAR, 15, 0, 7, 16,
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BUS_MSTOP(3, BIT(4))),
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DEF_MOD("gpu_0_axi_clk", CLK_PLLDTY_ACPU_DIV2, 15, 1, 7, 17,
···
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464
DEF_RST(13, 2, 6, 3), /* ISP_0_REG_ARESETN */
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DEF_RST(13, 3, 6, 4), /* ISP_0_ISP_SRESETN */
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DEF_RST(13, 4, 6, 5), /* ISP_0_PRESETN */
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DEF_RST(13, 7, 6, 8), /* DSI_0_PRESETN */
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DEF_RST(13, 8, 6, 9), /* DSI_0_ARESETN */
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DEF_RST(13, 12, 6, 13), /* LCDC_0_RESET_N */
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DEF_RST(13, 13, 6, 14), /* GPU_0_RESETN */
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DEF_RST(13, 14, 6, 15), /* GPU_0_AXI_RESETN */
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DEF_RST(13, 15, 6, 16), /* GPU_0_ACE_RESETN */
+3
drivers/clk/renesas/rzv2h-cpg.h
+3
drivers/clk/renesas/rzv2h-cpg.h
···
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#define CPG_CDDIV3 (0x40C)
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#define CPG_CDDIV4 (0x410)
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#define CPG_CSDIV0 (0x500)
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#define CPG_CSDIV1 (0x504)
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#define CDDIV0_DIVCTL1 DDIV_PACK(CPG_CDDIV0, 4, 3, 1)
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#define CDDIV0_DIVCTL2 DDIV_PACK(CPG_CDDIV0, 8, 3, 2)
···
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#define CSDIV0_DIVCTL0 DDIV_PACK(CPG_CSDIV0, 0, 2, CSDIV_NO_MON)
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#define CSDIV0_DIVCTL1 DDIV_PACK(CPG_CSDIV0, 4, 2, CSDIV_NO_MON)
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#define CSDIV0_DIVCTL2 DDIV_PACK(CPG_CSDIV0, 8, 2, CSDIV_NO_MON)
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#define CSDIV0_DIVCTL3 DDIV_PACK_NO_RMW(CPG_CSDIV0, 12, 2, CSDIV_NO_MON)
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#define CSDIV1_DIVCTL2 DDIV_PACK(CPG_CSDIV1, 8, 4, CSDIV_NO_MON)
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#define SSEL0_SELCTL2 SMUX_PACK(CPG_SSEL0, 8, 1)
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#define SSEL0_SELCTL3 SMUX_PACK(CPG_SSEL0, 12, 1)