Merge tag 'drm/tegra/for-5.18-rc1' of https://gitlab.freedesktop.org/drm/tegra into drm-next

+32 -18

drivers/gpu/drm/tegra/dc.c

··· 345 345 { 346 346 unsigned h_offset, v_offset, h_size, v_size, h_dda, v_dda, bpp; 347 347 struct tegra_dc *dc = plane->dc; 348 - bool yuv, planar; 348 + unsigned int planes; 349 349 u32 value; 350 + bool yuv; 350 351 351 352 /* 352 353 * For YUV planar modes, the number of bytes per pixel takes into 353 354 * account only the luma component and therefore is 1. 354 355 */ 355 - yuv = tegra_plane_format_is_yuv(window->format, &planar, NULL); 356 + yuv = tegra_plane_format_is_yuv(window->format, &planes, NULL); 356 357 if (!yuv) 357 358 bpp = window->bits_per_pixel / 8; 358 359 else 359 - bpp = planar ? 1 : 2; 360 + bpp = (planes > 1) ? 1 : 2; 360 361 361 362 tegra_plane_writel(plane, window->format, DC_WIN_COLOR_DEPTH); 362 363 tegra_plane_writel(plane, window->swap, DC_WIN_BYTE_SWAP); ··· 386 385 * For DDA computations the number of bytes per pixel for YUV planar 387 386 * modes needs to take into account all Y, U and V components. 388 387 */ 389 - if (yuv && planar) 388 + if (yuv && planes > 1) 390 389 bpp = 2; 391 390 392 391 h_dda = compute_dda_inc(window->src.w, window->dst.w, false, bpp); ··· 406 405 407 406 tegra_plane_writel(plane, window->base[0], DC_WINBUF_START_ADDR); 408 407 409 - if (yuv && planar) { 408 + if (yuv && planes > 1) { 410 409 tegra_plane_writel(plane, window->base[1], DC_WINBUF_START_ADDR_U); 411 - tegra_plane_writel(plane, window->base[2], DC_WINBUF_START_ADDR_V); 410 + 411 + if (planes > 2) 412 + tegra_plane_writel(plane, window->base[2], DC_WINBUF_START_ADDR_V); 413 + 412 414 value = window->stride[1] << 16 | window->stride[0]; 413 415 tegra_plane_writel(plane, value, DC_WIN_LINE_STRIDE); 414 416 } else { ··· 1197 1193 DRM_FORMAT_YUYV, 1198 1194 DRM_FORMAT_YUV420, 1199 1195 DRM_FORMAT_YUV422, 1196 + /* semi-planar formats */ 1197 + DRM_FORMAT_NV12, 1198 + DRM_FORMAT_NV21, 1199 + DRM_FORMAT_NV16, 1200 + DRM_FORMAT_NV61, 1201 + DRM_FORMAT_NV24, 1202 + DRM_FORMAT_NV42, 1200 1203 }; 1201 1204 1202 1205 static const u32 tegra124_overlay_formats[] = { ··· 1232 1221 /* planar formats */ 1233 1222 DRM_FORMAT_UYVY, 1234 1223 DRM_FORMAT_YUYV, 1235 - DRM_FORMAT_YUV420, 1236 - DRM_FORMAT_YUV422, 1224 + DRM_FORMAT_YVYU, 1225 + DRM_FORMAT_VYUY, 1226 + DRM_FORMAT_YUV420, /* YU12 */ 1227 + DRM_FORMAT_YUV422, /* YU16 */ 1228 + DRM_FORMAT_YUV444, /* YU24 */ 1229 + /* semi-planar formats */ 1230 + DRM_FORMAT_NV12, 1231 + DRM_FORMAT_NV21, 1232 + DRM_FORMAT_NV16, 1233 + DRM_FORMAT_NV61, 1234 + DRM_FORMAT_NV24, 1235 + DRM_FORMAT_NV42, 1237 1236 }; 1238 1237 1239 1238 static struct drm_plane *tegra_dc_overlay_plane_create(struct drm_device *drm, ··· 3232 3211 return -ENXIO; 3233 3212 3234 3213 err = tegra_dc_rgb_probe(dc); 3235 - if (err < 0 && err != -ENODEV) { 3236 - const char *level = KERN_ERR; 3237 - 3238 - if (err == -EPROBE_DEFER) 3239 - level = KERN_DEBUG; 3240 - 3241 - dev_printk(level, dc->dev, "failed to probe RGB output: %d\n", 3242 - err); 3243 - return err; 3244 - } 3214 + if (err < 0 && err != -ENODEV) 3215 + return dev_err_probe(&pdev->dev, err, 3216 + "failed to probe RGB output\n"); 3245 3217 3246 3218 platform_set_drvdata(pdev, dc); 3247 3219 pm_runtime_enable(&pdev->dev);

+7

drivers/gpu/drm/tegra/dc.h

··· 637 637 #define WIN_COLOR_DEPTH_A8B8G8R8 36 638 638 #define WIN_COLOR_DEPTH_B8G8R8X8 37 639 639 #define WIN_COLOR_DEPTH_R8G8B8X8 38 640 + #define WIN_COLOR_DEPTH_YCbCr444P 41 641 + #define WIN_COLOR_DEPTH_YCrCb420SP 42 642 + #define WIN_COLOR_DEPTH_YCbCr420SP 43 643 + #define WIN_COLOR_DEPTH_YCrCb422SP 44 644 + #define WIN_COLOR_DEPTH_YCbCr422SP 45 645 + #define WIN_COLOR_DEPTH_YCrCb444SP 48 646 + #define WIN_COLOR_DEPTH_YCbCr444SP 49 640 647 #define WIN_COLOR_DEPTH_X8B8G8R8 65 641 648 #define WIN_COLOR_DEPTH_X8R8G8B8 66 642 649

+1 -2

drivers/gpu/drm/tegra/dpaux.c

··· 280 280 static irqreturn_t tegra_dpaux_irq(int irq, void *data) 281 281 { 282 282 struct tegra_dpaux *dpaux = data; 283 - irqreturn_t ret = IRQ_HANDLED; 284 283 u32 value; 285 284 286 285 /* clear interrupts */ ··· 296 297 if (value & DPAUX_INTR_AUX_DONE) 297 298 complete(&dpaux->complete); 298 299 299 - return ret; 300 + return IRQ_HANDLED; 300 301 } 301 302 302 303 enum tegra_dpaux_functions {

+3 -1

drivers/gpu/drm/tegra/dsi.c

··· 1538 1538 dsi->slave = platform_get_drvdata(gangster); 1539 1539 of_node_put(np); 1540 1540 1541 - if (!dsi->slave) 1541 + if (!dsi->slave) { 1542 + put_device(&gangster->dev); 1542 1543 return -EPROBE_DEFER; 1544 + } 1543 1545 1544 1546 dsi->slave->master = dsi; 1545 1547 }

+9 -25

drivers/gpu/drm/tegra/hdmi.c

··· 1775 1775 1776 1776 static int tegra_hdmi_probe(struct platform_device *pdev) 1777 1777 { 1778 - const char *level = KERN_ERR; 1779 1778 struct tegra_hdmi *hdmi; 1780 1779 struct resource *regs; 1781 1780 int err; ··· 1816 1817 1817 1818 hdmi->hdmi = devm_regulator_get(&pdev->dev, "hdmi"); 1818 1819 err = PTR_ERR_OR_ZERO(hdmi->hdmi); 1819 - if (err) { 1820 - if (err == -EPROBE_DEFER) 1821 - level = KERN_DEBUG; 1822 - 1823 - dev_printk(level, &pdev->dev, 1824 - "failed to get HDMI regulator: %d\n", err); 1825 - return err; 1826 - } 1820 + if (err) 1821 + return dev_err_probe(&pdev->dev, err, 1822 + "failed to get HDMI regulator\n"); 1827 1823 1828 1824 hdmi->pll = devm_regulator_get(&pdev->dev, "pll"); 1829 1825 err = PTR_ERR_OR_ZERO(hdmi->pll); 1830 - if (err) { 1831 - if (err == -EPROBE_DEFER) 1832 - level = KERN_DEBUG; 1833 - 1834 - dev_printk(level, &pdev->dev, 1835 - "failed to get PLL regulator: %d\n", err); 1836 - return err; 1837 - } 1826 + if (err) 1827 + return dev_err_probe(&pdev->dev, err, 1828 + "failed to get PLL regulator\n"); 1838 1829 1839 1830 hdmi->vdd = devm_regulator_get(&pdev->dev, "vdd"); 1840 1831 err = PTR_ERR_OR_ZERO(hdmi->vdd); 1841 - if (err) { 1842 - if (err == -EPROBE_DEFER) 1843 - level = KERN_DEBUG; 1844 - 1845 - dev_printk(level, &pdev->dev, 1846 - "failed to get VDD regulator: %d\n", err); 1847 - return err; 1848 - } 1832 + if (err) 1833 + return dev_err_probe(&pdev->dev, err, 1834 + "failed to get VDD regulator\n"); 1849 1835 1850 1836 hdmi->output.dev = &pdev->dev; 1851 1837

+15 -9

drivers/gpu/drm/tegra/hub.c

··· 540 540 struct tegra_plane *p = to_tegra_plane(plane); 541 541 u32 value, min_width, bypass = 0; 542 542 dma_addr_t base, addr_flag = 0; 543 - unsigned int bpc; 544 - bool yuv, planar; 543 + unsigned int bpc, planes; 544 + bool yuv; 545 545 int err; 546 546 547 547 /* rien ne va plus */ ··· 559 559 return; 560 560 } 561 561 562 - yuv = tegra_plane_format_is_yuv(tegra_plane_state->format, &planar, &bpc); 562 + yuv = tegra_plane_format_is_yuv(tegra_plane_state->format, &planes, &bpc); 563 563 564 564 tegra_dc_assign_shared_plane(dc, p); 565 565 ··· 660 660 value = PITCH(fb->pitches[0]); 661 661 tegra_plane_writel(p, value, DC_WIN_PLANAR_STORAGE); 662 662 663 - if (yuv && planar) { 663 + if (yuv && planes > 1) { 664 664 base = tegra_plane_state->iova[1] + fb->offsets[1]; 665 665 base |= addr_flag; 666 666 667 667 tegra_plane_writel(p, upper_32_bits(base), DC_WINBUF_START_ADDR_HI_U); 668 668 tegra_plane_writel(p, lower_32_bits(base), DC_WINBUF_START_ADDR_U); 669 669 670 - base = tegra_plane_state->iova[2] + fb->offsets[2]; 671 - base |= addr_flag; 670 + if (planes > 2) { 671 + base = tegra_plane_state->iova[2] + fb->offsets[2]; 672 + base |= addr_flag; 672 673 673 - tegra_plane_writel(p, upper_32_bits(base), DC_WINBUF_START_ADDR_HI_V); 674 - tegra_plane_writel(p, lower_32_bits(base), DC_WINBUF_START_ADDR_V); 674 + tegra_plane_writel(p, upper_32_bits(base), DC_WINBUF_START_ADDR_HI_V); 675 + tegra_plane_writel(p, lower_32_bits(base), DC_WINBUF_START_ADDR_V); 676 + } 675 677 676 - value = PITCH_U(fb->pitches[2]) | PITCH_V(fb->pitches[2]); 678 + value = PITCH_U(fb->pitches[1]); 679 + 680 + if (planes > 2) 681 + value |= PITCH_V(fb->pitches[2]); 682 + 677 683 tegra_plane_writel(p, value, DC_WIN_PLANAR_STORAGE_UV); 678 684 } else { 679 685 tegra_plane_writel(p, 0, DC_WINBUF_START_ADDR_U);

+66 -7

drivers/gpu/drm/tegra/plane.c

··· 413 413 *swap = BYTE_SWAP_SWAP2; 414 414 break; 415 415 416 + case DRM_FORMAT_YVYU: 417 + if (!swap) 418 + return -EINVAL; 419 + 420 + *format = WIN_COLOR_DEPTH_YCbCr422; 421 + *swap = BYTE_SWAP_SWAP4; 422 + break; 423 + 424 + case DRM_FORMAT_VYUY: 425 + if (!swap) 426 + return -EINVAL; 427 + 428 + *format = WIN_COLOR_DEPTH_YCbCr422; 429 + *swap = BYTE_SWAP_SWAP4HW; 430 + break; 431 + 416 432 case DRM_FORMAT_YUV420: 417 433 *format = WIN_COLOR_DEPTH_YCbCr420P; 418 434 break; 419 435 420 436 case DRM_FORMAT_YUV422: 421 437 *format = WIN_COLOR_DEPTH_YCbCr422P; 438 + break; 439 + 440 + case DRM_FORMAT_YUV444: 441 + *format = WIN_COLOR_DEPTH_YCbCr444P; 442 + break; 443 + 444 + case DRM_FORMAT_NV12: 445 + *format = WIN_COLOR_DEPTH_YCbCr420SP; 446 + break; 447 + 448 + case DRM_FORMAT_NV21: 449 + *format = WIN_COLOR_DEPTH_YCrCb420SP; 450 + break; 451 + 452 + case DRM_FORMAT_NV16: 453 + *format = WIN_COLOR_DEPTH_YCbCr422SP; 454 + break; 455 + 456 + case DRM_FORMAT_NV61: 457 + *format = WIN_COLOR_DEPTH_YCrCb422SP; 458 + break; 459 + 460 + case DRM_FORMAT_NV24: 461 + *format = WIN_COLOR_DEPTH_YCbCr444SP; 462 + break; 463 + 464 + case DRM_FORMAT_NV42: 465 + *format = WIN_COLOR_DEPTH_YCrCb444SP; 422 466 break; 423 467 424 468 default: ··· 485 441 return false; 486 442 } 487 443 488 - bool tegra_plane_format_is_yuv(unsigned int format, bool *planar, unsigned int *bpc) 444 + bool tegra_plane_format_is_yuv(unsigned int format, unsigned int *planes, unsigned int *bpc) 489 445 { 490 446 switch (format) { 491 447 case WIN_COLOR_DEPTH_YCbCr422: 492 448 case WIN_COLOR_DEPTH_YUV422: 493 - if (planar) 494 - *planar = false; 449 + if (planes) 450 + *planes = 1; 495 451 496 452 if (bpc) 497 453 *bpc = 8; ··· 506 462 case WIN_COLOR_DEPTH_YUV422R: 507 463 case WIN_COLOR_DEPTH_YCbCr422RA: 508 464 case WIN_COLOR_DEPTH_YUV422RA: 509 - if (planar) 510 - *planar = true; 465 + case WIN_COLOR_DEPTH_YCbCr444P: 466 + if (planes) 467 + *planes = 3; 468 + 469 + if (bpc) 470 + *bpc = 8; 471 + 472 + return true; 473 + 474 + case WIN_COLOR_DEPTH_YCrCb420SP: 475 + case WIN_COLOR_DEPTH_YCbCr420SP: 476 + case WIN_COLOR_DEPTH_YCrCb422SP: 477 + case WIN_COLOR_DEPTH_YCbCr422SP: 478 + case WIN_COLOR_DEPTH_YCrCb444SP: 479 + case WIN_COLOR_DEPTH_YCbCr444SP: 480 + if (planes) 481 + *planes = 2; 511 482 512 483 if (bpc) 513 484 *bpc = 8; ··· 530 471 return true; 531 472 } 532 473 533 - if (planar) 534 - *planar = false; 474 + if (planes) 475 + *planes = 1; 535 476 536 477 return false; 537 478 }

+1 -1

drivers/gpu/drm/tegra/plane.h

··· 90 90 91 91 int tegra_plane_format(u32 fourcc, u32 *format, u32 *swap); 92 92 bool tegra_plane_format_is_indexed(unsigned int format); 93 - bool tegra_plane_format_is_yuv(unsigned int format, bool *planar, unsigned int *bpc); 93 + bool tegra_plane_format_is_yuv(unsigned int format, unsigned int *planes, unsigned int *bpc); 94 94 int tegra_plane_setup_legacy_state(struct tegra_plane *tegra, 95 95 struct tegra_plane_state *state); 96 96 int tegra_plane_interconnect_init(struct tegra_plane *plane);

+6 -2

drivers/gpu/host1x/dev.c

··· 447 447 if (syncpt_irq < 0) 448 448 return syncpt_irq; 449 449 450 - host1x_bo_cache_init(&host->cache); 451 450 mutex_init(&host->devices_lock); 452 451 INIT_LIST_HEAD(&host->devices); 453 452 INIT_LIST_HEAD(&host->list); ··· 488 489 if (err) 489 490 return err; 490 491 492 + host1x_bo_cache_init(&host->cache); 493 + 491 494 err = host1x_iommu_init(host); 492 495 if (err < 0) { 493 496 dev_err(&pdev->dev, "failed to setup IOMMU: %d\n", err); 494 - return err; 497 + goto destroy_cache; 495 498 } 496 499 497 500 err = host1x_channel_list_init(&host->channel_list, ··· 554 553 host1x_channel_list_free(&host->channel_list); 555 554 iommu_exit: 556 555 host1x_iommu_exit(host); 556 + destroy_cache: 557 + host1x_bo_cache_destroy(&host->cache); 557 558 558 559 return err; 559 560 } ··· 571 568 572 569 host1x_intr_deinit(host); 573 570 host1x_syncpt_deinit(host); 571 + host1x_channel_list_free(&host->channel_list); 574 572 host1x_iommu_exit(host); 575 573 host1x_bo_cache_destroy(&host->cache); 576 574

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