Linux kernel mirror (for testing)
git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git
kernel
os
linux
arm64: dts: qcom: sm8550: add display port nodes
Add the Display Port controller subnode to the MDSS node.
Reviewed-by: Konrad Dybcio <konrad.dybcio@linaro.org>
Signed-off-by: Neil Armstrong <neil.armstrong@linaro.org>
Signed-off-by: Bjorn Andersson <andersson@kernel.org>
Link: https://lore.kernel.org/r/20230601-topic-sm8550-upstream-dp-v4-2-ac2c6899d22c@linaro.org
authored by
Neil Armstrong
and committed by
Bjorn Andersson
66adfbc4
bbde65f9
+87
-2
+87
-2
arch/arm64/boot/dts/qcom/sm8550.dtsi
+87
-2
arch/arm64/boot/dts/qcom/sm8550.dtsi
···
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remote-endpoint = <&mdss_dsi1_in>;
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};
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};
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+
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+
port@2 {
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+
reg = <2>;
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+
dpu_intf0_out: endpoint {
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+
remote-endpoint = <&mdss_dp0_in>;
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+
};
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+
};
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};
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mdp_opp_table: opp-table {
···
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opp-514000000 {
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opp-hz = /bits/ 64 <514000000>;
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+
required-opps = <&rpmhpd_opp_nom>;
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+
};
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+
};
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+
};
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+
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+
mdss_dp0: displayport-controller@ae90000 {
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+
compatible = "qcom,sm8550-dp", "qcom,sm8350-dp";
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+
reg = <0 0xae90000 0 0x200>,
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+
<0 0xae90200 0 0x200>,
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+
<0 0xae90400 0 0xc00>,
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+
<0 0xae91000 0 0x400>,
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+
<0 0xae91400 0 0x400>;
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+
interrupt-parent = <&mdss>;
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+
interrupts = <12>;
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+
clocks = <&dispcc DISP_CC_MDSS_AHB_CLK>,
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+
<&dispcc DISP_CC_MDSS_DPTX0_AUX_CLK>,
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+
<&dispcc DISP_CC_MDSS_DPTX0_LINK_CLK>,
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+
<&dispcc DISP_CC_MDSS_DPTX0_LINK_INTF_CLK>,
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+
<&dispcc DISP_CC_MDSS_DPTX0_PIXEL0_CLK>;
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+
clock-names = "core_iface",
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+
"core_aux",
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+
"ctrl_link",
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+
"ctrl_link_iface",
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+
"stream_pixel";
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+
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+
assigned-clocks = <&dispcc DISP_CC_MDSS_DPTX0_LINK_CLK_SRC>,
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+
<&dispcc DISP_CC_MDSS_DPTX0_PIXEL0_CLK_SRC>;
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+
assigned-clock-parents = <&usb_dp_qmpphy QMP_USB43DP_DP_LINK_CLK>,
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+
<&usb_dp_qmpphy QMP_USB43DP_DP_VCO_DIV_CLK>;
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+
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+
phys = <&usb_dp_qmpphy QMP_USB43DP_DP_PHY>;
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+
phy-names = "dp";
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+
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+
#sound-dai-cells = <0>;
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+
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+
operating-points-v2 = <&dp_opp_table>;
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+
power-domains = <&rpmhpd SM8550_MMCX>;
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+
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+
status = "disabled";
2550
+
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+
ports {
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+
#address-cells = <1>;
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+
#size-cells = <0>;
2554
+
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+
port@0 {
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+
reg = <0>;
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+
mdss_dp0_in: endpoint {
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+
remote-endpoint = <&dpu_intf0_out>;
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+
};
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+
};
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+
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+
port@1 {
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+
reg = <1>;
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+
mdss_dp0_out: endpoint {
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+
};
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+
};
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+
};
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+
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+
dp_opp_table: opp-table {
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+
compatible = "operating-points-v2";
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+
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+
opp-162000000 {
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+
opp-hz = /bits/ 64 <162000000>;
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+
required-opps = <&rpmhpd_opp_low_svs_d1>;
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+
};
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+
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+
opp-270000000 {
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+
opp-hz = /bits/ 64 <270000000>;
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+
required-opps = <&rpmhpd_opp_low_svs>;
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+
};
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+
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+
opp-540000000 {
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+
opp-hz = /bits/ 64 <540000000>;
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+
required-opps = <&rpmhpd_opp_svs_l1>;
2585
+
};
2586
+
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+
opp-810000000 {
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+
opp-hz = /bits/ 64 <810000000>;
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required-opps = <&rpmhpd_opp_nom>;
2519
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};
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};
···
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<&mdss_dsi0_phy 1>,
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<&mdss_dsi1_phy 0>,
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<&mdss_dsi1_phy 1>,
2784
-
<0>, /* dp0 */
2785
-
<0>,
2699
+
<&usb_dp_qmpphy QMP_USB43DP_DP_LINK_CLK>,
2700
+
<&usb_dp_qmpphy QMP_USB43DP_DP_VCO_DIV_CLK>,
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<0>, /* dp1 */
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<0>,
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<0>, /* dp2 */