Linux kernel mirror (for testing)
git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git
kernel
os
linux
Merge tag 'dmaengine-fix-5.2-rc4' of git://git.infradead.org/users/vkoul/slave-dma
Pull dmaengine fixes from Vinod Koul:
- jz4780 transfer fix for acking descriptors early
- fsl-qdma: clean registers on error
- dw-axi-dmac: null pointer dereference fix
- mediatek-cqdma: fix sleeping in atomic context
- tegra210-adma: fix bunch os issues like crashing in driver probe,
channel FIFO configuration etc.
- sprd: Fixes for possible crash on descriptor status, block length
overflow. For 2-stage transfer fix incorrect start, configuration and
interrupt handling.
* tag 'dmaengine-fix-5.2-rc4' of git://git.infradead.org/users/vkoul/slave-dma:
dmaengine: sprd: Add interrupt support for 2-stage transfer
dmaengine: sprd: Fix the right place to configure 2-stage transfer
dmaengine: sprd: Fix block length overflow
dmaengine: sprd: Fix the incorrect start for 2-stage destination channels
dmaengine: sprd: Add validation of current descriptor in irq handler
dmaengine: sprd: Fix the possible crash when getting descriptor status
dmaengine: tegra210-adma: Fix spelling
dmaengine: tegra210-adma: Fix channel FIFO configuration
dmaengine: tegra210-adma: Fix crash during probe
dmaengine: mediatek-cqdma: sleeping in atomic context
dmaengine: dw-axi-dmac: fix null dereference when pointer first is null
dmaengine: fsl-qdma: Add improvement
dmaengine: jz4780: Fix transfers being ACKed too soon
+100
-49
+21
-11
drivers/dma/dma-jz4780.c
+21
-11
drivers/dma/dma-jz4780.c
···
662
662
return status;
663
663
}
664
664
665
-
static void jz4780_dma_chan_irq(struct jz4780_dma_dev *jzdma,
666
-
struct jz4780_dma_chan *jzchan)
665
+
static bool jz4780_dma_chan_irq(struct jz4780_dma_dev *jzdma,
666
+
struct jz4780_dma_chan *jzchan)
667
667
{
668
668
uint32_t dcs;
669
+
bool ack = true;
669
670
670
671
spin_lock(&jzchan->vchan.lock);
671
672
···
689
688
if ((dcs & (JZ_DMA_DCS_AR | JZ_DMA_DCS_HLT)) == 0) {
690
689
if (jzchan->desc->type == DMA_CYCLIC) {
691
690
vchan_cyclic_callback(&jzchan->desc->vdesc);
692
-
} else {
691
+
692
+
jz4780_dma_begin(jzchan);
693
+
} else if (dcs & JZ_DMA_DCS_TT) {
693
694
vchan_cookie_complete(&jzchan->desc->vdesc);
694
695
jzchan->desc = NULL;
695
-
}
696
696
697
-
jz4780_dma_begin(jzchan);
697
+
jz4780_dma_begin(jzchan);
698
+
} else {
699
+
/* False positive - continue the transfer */
700
+
ack = false;
701
+
jz4780_dma_chn_writel(jzdma, jzchan->id,
702
+
JZ_DMA_REG_DCS,
703
+
JZ_DMA_DCS_CTE);
704
+
}
698
705
}
699
706
} else {
700
707
dev_err(&jzchan->vchan.chan.dev->device,
···
710
701
}
711
702
712
703
spin_unlock(&jzchan->vchan.lock);
704
+
705
+
return ack;
713
706
}
714
707
715
708
static irqreturn_t jz4780_dma_irq_handler(int irq, void *data)
716
709
{
717
710
struct jz4780_dma_dev *jzdma = data;
711
+
unsigned int nb_channels = jzdma->soc_data->nb_channels;
718
712
uint32_t pending, dmac;
719
713
int i;
720
714
721
715
pending = jz4780_dma_ctrl_readl(jzdma, JZ_DMA_REG_DIRQP);
722
716
723
-
for (i = 0; i < jzdma->soc_data->nb_channels; i++) {
724
-
if (!(pending & (1<<i)))
725
-
continue;
726
-
727
-
jz4780_dma_chan_irq(jzdma, &jzdma->chan[i]);
717
+
for_each_set_bit(i, (unsigned long *)&pending, nb_channels) {
718
+
if (jz4780_dma_chan_irq(jzdma, &jzdma->chan[i]))
719
+
pending &= ~BIT(i);
728
720
}
729
721
730
722
/* Clear halt and address error status of all channels. */
···
734
724
jz4780_dma_ctrl_writel(jzdma, JZ_DMA_REG_DMAC, dmac);
735
725
736
726
/* Clear interrupt pending status. */
737
-
jz4780_dma_ctrl_writel(jzdma, JZ_DMA_REG_DIRQP, 0);
727
+
jz4780_dma_ctrl_writel(jzdma, JZ_DMA_REG_DIRQP, pending);
738
728
739
729
return IRQ_HANDLED;
740
730
}
+2
-1
drivers/dma/dw-axi-dmac/dw-axi-dmac-platform.c
+2
-1
drivers/dma/dw-axi-dmac/dw-axi-dmac-platform.c
+1
-3
drivers/dma/fsl-qdma.c
+1
-3
drivers/dma/fsl-qdma.c
···
701
701
702
702
intr = qdma_readl(fsl_qdma, status + FSL_QDMA_DEDR);
703
703
704
-
if (intr) {
704
+
if (intr)
705
705
dev_err(fsl_qdma->dma_dev.dev, "DMA transaction error!\n");
706
-
return IRQ_NONE;
707
-
}
708
706
709
707
qdma_writel(fsl_qdma, FSL_QDMA_DEDR_CLEAR, status + FSL_QDMA_DEDR);
710
708
return IRQ_HANDLED;
+2
-2
drivers/dma/mediatek/mtk-cqdma.c
+2
-2
drivers/dma/mediatek/mtk-cqdma.c
···
225
225
mtk_dma_set(pc, MTK_CQDMA_RESET, MTK_CQDMA_HARD_RST_BIT);
226
226
mtk_dma_clr(pc, MTK_CQDMA_RESET, MTK_CQDMA_HARD_RST_BIT);
227
227
228
-
return mtk_cqdma_poll_engine_done(pc, false);
228
+
return mtk_cqdma_poll_engine_done(pc, true);
229
229
}
230
230
231
231
static void mtk_cqdma_start(struct mtk_cqdma_pchan *pc,
···
671
671
mtk_dma_set(cvc->pc, MTK_CQDMA_FLUSH, MTK_CQDMA_FLUSH_BIT);
672
672
673
673
/* wait for the completion of flush operation */
674
-
if (mtk_cqdma_poll_engine_done(cvc->pc, false) < 0)
674
+
if (mtk_cqdma_poll_engine_done(cvc->pc, true) < 0)
675
675
dev_err(cqdma2dev(to_cqdma_dev(c)), "cqdma flush timeout\n");
676
676
677
677
/* clear the flush bit and interrupt flag */
+38
-11
drivers/dma/sprd-dma.c
+38
-11
drivers/dma/sprd-dma.c
···
62
62
/* SPRD_DMA_GLB_2STAGE_GRP register definition */
63
63
#define SPRD_DMA_GLB_2STAGE_EN BIT(24)
64
64
#define SPRD_DMA_GLB_CHN_INT_MASK GENMASK(23, 20)
65
+
#define SPRD_DMA_GLB_DEST_INT BIT(22)
66
+
#define SPRD_DMA_GLB_SRC_INT BIT(20)
65
67
#define SPRD_DMA_GLB_LIST_DONE_TRG BIT(19)
66
68
#define SPRD_DMA_GLB_TRANS_DONE_TRG BIT(18)
67
69
#define SPRD_DMA_GLB_BLOCK_DONE_TRG BIT(17)
···
137
135
/* define DMA channel mode & trigger mode mask */
138
136
#define SPRD_DMA_CHN_MODE_MASK GENMASK(7, 0)
139
137
#define SPRD_DMA_TRG_MODE_MASK GENMASK(7, 0)
138
+
#define SPRD_DMA_INT_TYPE_MASK GENMASK(7, 0)
140
139
141
140
/* define the DMA transfer step type */
142
141
#define SPRD_DMA_NONE_STEP 0
···
193
190
u32 dev_id;
194
191
enum sprd_dma_chn_mode chn_mode;
195
192
enum sprd_dma_trg_mode trg_mode;
193
+
enum sprd_dma_int_type int_type;
196
194
struct sprd_dma_desc *cur_desc;
197
195
};
198
196
···
433
429
val = chn & SPRD_DMA_GLB_SRC_CHN_MASK;
434
430
val |= BIT(schan->trg_mode - 1) << SPRD_DMA_GLB_TRG_OFFSET;
435
431
val |= SPRD_DMA_GLB_2STAGE_EN;
432
+
if (schan->int_type != SPRD_DMA_NO_INT)
433
+
val |= SPRD_DMA_GLB_SRC_INT;
434
+
436
435
sprd_dma_glb_update(sdev, SPRD_DMA_GLB_2STAGE_GRP1, val, val);
437
436
break;
438
437
···
443
436
val = chn & SPRD_DMA_GLB_SRC_CHN_MASK;
444
437
val |= BIT(schan->trg_mode - 1) << SPRD_DMA_GLB_TRG_OFFSET;
445
438
val |= SPRD_DMA_GLB_2STAGE_EN;
439
+
if (schan->int_type != SPRD_DMA_NO_INT)
440
+
val |= SPRD_DMA_GLB_SRC_INT;
441
+
446
442
sprd_dma_glb_update(sdev, SPRD_DMA_GLB_2STAGE_GRP2, val, val);
447
443
break;
448
444
···
453
443
val = (chn << SPRD_DMA_GLB_DEST_CHN_OFFSET) &
454
444
SPRD_DMA_GLB_DEST_CHN_MASK;
455
445
val |= SPRD_DMA_GLB_2STAGE_EN;
446
+
if (schan->int_type != SPRD_DMA_NO_INT)
447
+
val |= SPRD_DMA_GLB_DEST_INT;
448
+
456
449
sprd_dma_glb_update(sdev, SPRD_DMA_GLB_2STAGE_GRP1, val, val);
457
450
break;
458
451
···
463
450
val = (chn << SPRD_DMA_GLB_DEST_CHN_OFFSET) &
464
451
SPRD_DMA_GLB_DEST_CHN_MASK;
465
452
val |= SPRD_DMA_GLB_2STAGE_EN;
453
+
if (schan->int_type != SPRD_DMA_NO_INT)
454
+
val |= SPRD_DMA_GLB_DEST_INT;
455
+
466
456
sprd_dma_glb_update(sdev, SPRD_DMA_GLB_2STAGE_GRP2, val, val);
467
457
break;
468
458
···
526
510
sprd_dma_set_uid(schan);
527
511
sprd_dma_enable_chn(schan);
528
512
529
-
if (schan->dev_id == SPRD_DMA_SOFTWARE_UID)
513
+
if (schan->dev_id == SPRD_DMA_SOFTWARE_UID &&
514
+
schan->chn_mode != SPRD_DMA_DST_CHN0 &&
515
+
schan->chn_mode != SPRD_DMA_DST_CHN1)
530
516
sprd_dma_soft_request(schan);
531
517
}
532
518
···
570
552
schan = &sdev->channels[i];
571
553
572
554
spin_lock(&schan->vc.lock);
555
+
556
+
sdesc = schan->cur_desc;
557
+
if (!sdesc) {
558
+
spin_unlock(&schan->vc.lock);
559
+
return IRQ_HANDLED;
560
+
}
561
+
573
562
int_type = sprd_dma_get_int_type(schan);
574
563
req_type = sprd_dma_get_req_type(schan);
575
564
sprd_dma_clear_int(schan);
576
-
577
-
sdesc = schan->cur_desc;
578
565
579
566
/* cyclic mode schedule callback */
580
567
cyclic = schan->linklist.phy_addr ? true : false;
···
648
625
else
649
626
pos = 0;
650
627
} else if (schan->cur_desc && schan->cur_desc->vd.tx.cookie == cookie) {
651
-
struct sprd_dma_desc *sdesc = to_sprd_dma_desc(vd);
628
+
struct sprd_dma_desc *sdesc = schan->cur_desc;
652
629
653
630
if (sdesc->dir == DMA_DEV_TO_MEM)
654
631
pos = sprd_dma_get_dst_addr(schan);
···
794
771
temp |= slave_cfg->src_maxburst & SPRD_DMA_FRG_LEN_MASK;
795
772
hw->frg_len = temp;
796
773
797
-
hw->blk_len = len & SPRD_DMA_BLK_LEN_MASK;
774
+
hw->blk_len = slave_cfg->src_maxburst & SPRD_DMA_BLK_LEN_MASK;
798
775
hw->trsc_len = len & SPRD_DMA_TRSC_LEN_MASK;
799
776
800
777
temp = (dst_step & SPRD_DMA_TRSF_STEP_MASK) << SPRD_DMA_DEST_TRSF_STEP_OFFSET;
···
927
904
schan->linklist.virt_addr = 0;
928
905
}
929
906
907
+
/*
908
+
* Set channel mode, interrupt mode and trigger mode for 2-stage
909
+
* transfer.
910
+
*/
911
+
schan->chn_mode =
912
+
(flags >> SPRD_DMA_CHN_MODE_SHIFT) & SPRD_DMA_CHN_MODE_MASK;
913
+
schan->trg_mode =
914
+
(flags >> SPRD_DMA_TRG_MODE_SHIFT) & SPRD_DMA_TRG_MODE_MASK;
915
+
schan->int_type = flags & SPRD_DMA_INT_TYPE_MASK;
916
+
930
917
sdesc = kzalloc(sizeof(*sdesc), GFP_NOWAIT);
931
918
if (!sdesc)
932
919
return NULL;
···
969
936
return NULL;
970
937
}
971
938
}
972
-
973
-
/* Set channel mode and trigger mode for 2-stage transfer */
974
-
schan->chn_mode =
975
-
(flags >> SPRD_DMA_CHN_MODE_SHIFT) & SPRD_DMA_CHN_MODE_MASK;
976
-
schan->trg_mode =
977
-
(flags >> SPRD_DMA_TRG_MODE_SHIFT) & SPRD_DMA_TRG_MODE_MASK;
978
939
979
940
ret = sprd_dma_fill_desc(chan, &sdesc->chn_hw, 0, 0, src, dst, len,
980
941
dir, flags, slave_cfg);
+36
-21
drivers/dma/tegra210-adma.c
+36
-21
drivers/dma/tegra210-adma.c
···
42
42
#define ADMA_CH_CONFIG_MAX_BUFS 8
43
43
44
44
#define ADMA_CH_FIFO_CTRL 0x2c
45
-
#define ADMA_CH_FIFO_CTRL_OVRFW_THRES(val) (((val) & 0xf) << 24)
46
-
#define ADMA_CH_FIFO_CTRL_STARV_THRES(val) (((val) & 0xf) << 16)
47
-
#define ADMA_CH_FIFO_CTRL_TX_FIFO_SIZE_SHIFT 8
48
-
#define ADMA_CH_FIFO_CTRL_RX_FIFO_SIZE_SHIFT 0
45
+
#define TEGRA210_ADMA_CH_FIFO_CTRL_OFLWTHRES(val) (((val) & 0xf) << 24)
46
+
#define TEGRA210_ADMA_CH_FIFO_CTRL_STRVTHRES(val) (((val) & 0xf) << 16)
47
+
#define TEGRA210_ADMA_CH_FIFO_CTRL_TXSIZE(val) (((val) & 0xf) << 8)
48
+
#define TEGRA210_ADMA_CH_FIFO_CTRL_RXSIZE(val) ((val) & 0xf)
49
+
#define TEGRA186_ADMA_CH_FIFO_CTRL_OFLWTHRES(val) (((val) & 0x1f) << 24)
50
+
#define TEGRA186_ADMA_CH_FIFO_CTRL_STRVTHRES(val) (((val) & 0x1f) << 16)
51
+
#define TEGRA186_ADMA_CH_FIFO_CTRL_TXSIZE(val) (((val) & 0x1f) << 8)
52
+
#define TEGRA186_ADMA_CH_FIFO_CTRL_RXSIZE(val) ((val) & 0x1f)
49
53
50
54
#define ADMA_CH_LOWER_SRC_ADDR 0x34
51
55
#define ADMA_CH_LOWER_TRG_ADDR 0x3c
···
64
60
65
61
#define TEGRA_ADMA_BURST_COMPLETE_TIME 20
66
62
67
-
#define ADMA_CH_FIFO_CTRL_DEFAULT (ADMA_CH_FIFO_CTRL_OVRFW_THRES(1) | \
68
-
ADMA_CH_FIFO_CTRL_STARV_THRES(1))
63
+
#define TEGRA210_FIFO_CTRL_DEFAULT (TEGRA210_ADMA_CH_FIFO_CTRL_OFLWTHRES(1) | \
64
+
TEGRA210_ADMA_CH_FIFO_CTRL_STRVTHRES(1) | \
65
+
TEGRA210_ADMA_CH_FIFO_CTRL_TXSIZE(3) | \
66
+
TEGRA210_ADMA_CH_FIFO_CTRL_RXSIZE(3))
67
+
68
+
#define TEGRA186_FIFO_CTRL_DEFAULT (TEGRA186_ADMA_CH_FIFO_CTRL_OFLWTHRES(1) | \
69
+
TEGRA186_ADMA_CH_FIFO_CTRL_STRVTHRES(1) | \
70
+
TEGRA186_ADMA_CH_FIFO_CTRL_TXSIZE(3) | \
71
+
TEGRA186_ADMA_CH_FIFO_CTRL_RXSIZE(3))
69
72
70
73
#define ADMA_CH_REG_FIELD_VAL(val, mask, shift) (((val) & mask) << shift)
71
74
···
84
73
* @global_int_clear: Register offset of DMA global interrupt clear.
85
74
* @ch_req_tx_shift: Register offset for AHUB transmit channel select.
86
75
* @ch_req_rx_shift: Register offset for AHUB receive channel select.
87
-
* @ch_base_offset: Reister offset of DMA channel registers.
76
+
* @ch_base_offset: Register offset of DMA channel registers.
77
+
* @ch_fifo_ctrl: Default value for channel FIFO CTRL register.
88
78
* @ch_req_mask: Mask for Tx or Rx channel select.
89
79
* @ch_req_max: Maximum number of Tx or Rx channels available.
90
80
* @ch_reg_size: Size of DMA channel register space.
···
98
86
unsigned int ch_req_tx_shift;
99
87
unsigned int ch_req_rx_shift;
100
88
unsigned int ch_base_offset;
89
+
unsigned int ch_fifo_ctrl;
101
90
unsigned int ch_req_mask;
102
91
unsigned int ch_req_max;
103
92
unsigned int ch_reg_size;
···
602
589
ADMA_CH_CTRL_FLOWCTRL_EN;
603
590
ch_regs->config |= cdata->adma_get_burst_config(burst_size);
604
591
ch_regs->config |= ADMA_CH_CONFIG_WEIGHT_FOR_WRR(1);
605
-
ch_regs->fifo_ctrl = ADMA_CH_FIFO_CTRL_DEFAULT;
592
+
ch_regs->fifo_ctrl = cdata->ch_fifo_ctrl;
606
593
ch_regs->tc = desc->period_len & ADMA_CH_TC_COUNT_MASK;
607
594
608
595
return tegra_adma_request_alloc(tdc, direction);
···
786
773
.ch_req_tx_shift = 28,
787
774
.ch_req_rx_shift = 24,
788
775
.ch_base_offset = 0,
776
+
.ch_fifo_ctrl = TEGRA210_FIFO_CTRL_DEFAULT,
789
777
.ch_req_mask = 0xf,
790
778
.ch_req_max = 10,
791
779
.ch_reg_size = 0x80,
···
800
786
.ch_req_tx_shift = 27,
801
787
.ch_req_rx_shift = 22,
802
788
.ch_base_offset = 0x10000,
789
+
.ch_fifo_ctrl = TEGRA186_FIFO_CTRL_DEFAULT,
803
790
.ch_req_mask = 0x1f,
804
791
.ch_req_max = 20,
805
792
.ch_reg_size = 0x100,
···
849
834
return PTR_ERR(tdma->ahub_clk);
850
835
}
851
836
852
-
pm_runtime_enable(&pdev->dev);
853
-
854
-
ret = pm_runtime_get_sync(&pdev->dev);
855
-
if (ret < 0)
856
-
goto rpm_disable;
857
-
858
-
ret = tegra_adma_init(tdma);
859
-
if (ret)
860
-
goto rpm_put;
861
-
862
837
INIT_LIST_HEAD(&tdma->dma_dev.channels);
863
838
for (i = 0; i < tdma->nr_channels; i++) {
864
839
struct tegra_adma_chan *tdc = &tdma->channels[i];
···
866
861
tdc->vc.desc_free = tegra_adma_desc_free;
867
862
tdc->tdma = tdma;
868
863
}
864
+
865
+
pm_runtime_enable(&pdev->dev);
866
+
867
+
ret = pm_runtime_get_sync(&pdev->dev);
868
+
if (ret < 0)
869
+
goto rpm_disable;
870
+
871
+
ret = tegra_adma_init(tdma);
872
+
if (ret)
873
+
goto rpm_put;
869
874
870
875
dma_cap_set(DMA_SLAVE, tdma->dma_dev.cap_mask);
871
876
dma_cap_set(DMA_PRIVATE, tdma->dma_dev.cap_mask);
···
920
905
921
906
dma_remove:
922
907
dma_async_device_unregister(&tdma->dma_dev);
923
-
irq_dispose:
924
-
while (--i >= 0)
925
-
irq_dispose_mapping(tdma->channels[i].irq);
926
908
rpm_put:
927
909
pm_runtime_put_sync(&pdev->dev);
928
910
rpm_disable:
929
911
pm_runtime_disable(&pdev->dev);
912
+
irq_dispose:
913
+
while (--i >= 0)
914
+
irq_dispose_mapping(tdma->channels[i].irq);
930
915
931
916
return ret;
932
917
}